WO2018133424A1 - 阵列基板以及显示装置 - Google Patents

阵列基板以及显示装置 Download PDF

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Publication number
WO2018133424A1
WO2018133424A1 PCT/CN2017/100143 CN2017100143W WO2018133424A1 WO 2018133424 A1 WO2018133424 A1 WO 2018133424A1 CN 2017100143 W CN2017100143 W CN 2017100143W WO 2018133424 A1 WO2018133424 A1 WO 2018133424A1
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WIPO (PCT)
Prior art keywords
pixel
sub
light
rows
aligned
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PCT/CN2017/100143
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English (en)
French (fr)
Inventor
廖峰
董学
吕敬
林允植
Original Assignee
京东方科技集团股份有限公司
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Priority to EP17842313.3A priority Critical patent/EP3572867A4/en
Priority to US15/755,874 priority patent/US10510307B2/en
Publication of WO2018133424A1 publication Critical patent/WO2018133424A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
    • G09G3/364—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals with use of subpixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/52—RGB geometrical arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate and a display device.
  • array substrates are widely used in display panels.
  • the embodiments described herein provide a novel array substrate and display device that can avoid the difference in brightness of pixel display at low gray levels without reducing the aperture ratio.
  • an array substrate includes a plurality of pixel groups arranged in a column direction.
  • Each of the plurality of pixel groups includes a plurality of sub-pixel rows.
  • Each of the sub-pixel rows includes a plurality of sub-pixels, and a first light-shielding strip or a second light-shielding strip is disposed between the adjacent two sub-pixels, and the first light-shielding strip and the second light-shielding strip are alternately disposed.
  • the first light bar has a first width and the second light bar has a second width. For each pixel group, the first light bar on at least one of the sub-pixel rows is aligned with the second light bar on at least one different sub-pixel row.
  • the first width is different from the second width.
  • sub-pixels having the same color on different sub-pixel rows are aligned for each pixel group.
  • each pixel group includes two sub-pixel rows, a first light-shielding strip on one sub-pixel row is aligned with a second light-shielding strip on another sub-pixel row, and a second light-shielding on one sub-pixel row The bar aligns with the first shade on another sub-pixel row.
  • each pixel group is divided into two pixel groups in the column direction.
  • the first light-shielding strips on different sub-pixel rows are aligned with each other
  • the second light-shielding strips on different sub-pixel rows are aligned with each other.
  • a first light bar on each of the two pixel groups of the two pixel groups is aligned with a second light bar on each of the other pixel groups, on each of the one pixel rows
  • the second light bar is aligned with the first light bar on each of the other pixel groups.
  • the number of sub-pixel rows in a pixel group is 1, 2, 3, or 4.
  • sub-pixel rows adjacent to each other are arranged to be offset from each other by half of the width of the sub-pixels, and sub-pixels having the same color are aligned on the sub-pixel rows arranged one row apart.
  • each pixel group includes four sub-pixel rows, the sub-pixel rows of the odd rows constitute the first pixel group, and the sub-pixel rows of the even rows constitute the second pixel group.
  • the first light bar on one sub-pixel row is aligned with the second light bar on the other sub-pixel row, and the second light bar on one sub-pixel row Align the first light bar on the other sub-pixel row.
  • the first light-shielding strips on different sub-pixel rows are aligned with each other, and the second light-shielding strips on different sub-pixel row lines are aligned with each other.
  • each pixel group includes six sub-pixel rows.
  • the sub-pixel rows of the odd rows constitute the first pixel group, and the sub-pixel rows of the even rows constitute the second pixel group.
  • the first light bar on the middle sub-pixel row is aligned with the second light bar on the upper and lower sub-pixel rows, on the middle sub-pixel row
  • the second light bar is aligned with the first light bar on the upper and lower sub-pixel rows.
  • the first light bar on the middle sub-pixel row is aligned with the second light bar on one of the upper and lower sub-pixel rows and Aligning the first light bar on the other sub-pixel row in the upper and lower sub-pixel rows, the second light bar on the middle sub-pixel row is aligned on the first sub-pixel row in the upper and lower sub-pixel rows a light-shielding strip and aligning the second light-shielding strip on the other of the sub-pixel rows in the upper and lower sub-pixel rows.
  • the array substrate further includes a direction along a direction parallel to the sub-pixel row A plurality of gate lines and a plurality of data lines perpendicular to the gate lines.
  • a gate line dedicated to the sub-pixel row is disposed on each side of each sub-pixel row. In each sub-pixel row, one data line is set every two sub-pixels.
  • the first light shielding strip is configured to cover the data line
  • the second light shielding strip is configured to cover the common electrode between the two sub-pixels
  • the second width is smaller than the first width
  • a display panel comprising the array substrate as described above.
  • a display device comprising the display panel as described above.
  • the display panel, and the display device of the embodiments of the present disclosure by changing the arrangement manner of the first light-shielding strip and the second light-shielding strip, it is possible to avoid the difference in brightness of the pixel display at the low gray level without lowering the aperture ratio. That is to avoid the phenomenon of periodic vertical lines (such as light and dark stripes under a white screen) when the screen is viewed at different distances and angles from the display screen.
  • Figure 1 is a schematic view schematically illustrating a difference of a black matrix
  • FIG. 2 is a schematic structural view of an array substrate employing a basic pixel structure
  • FIG. 3 is a schematic structural view of an array substrate using a brightness display (Bright View 3, BV3 for short) pixel structure;
  • FIG. 4 is a schematic structural view of an array substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of an array substrate employing a basic pixel structure according to a first exemplary embodiment of the present disclosure
  • FIG. 6 is a schematic structural view of an array substrate employing a basic pixel structure in accordance with a second exemplary embodiment of the present disclosure
  • FIG. 7 is a schematic structural view of an array substrate employing a BV3 pixel structure in accordance with a third exemplary embodiment of the present disclosure
  • FIG. 8 is a schematic view for explaining the design of the array substrate shown in FIG. 7;
  • FIG. 9 is a schematic view for explaining a design of an array substrate employing a BV3 pixel structure according to a fourth exemplary embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • An array substrate for a display device includes a plurality of gate lines disposed in a direction parallel to a row of sub-pixels and a plurality of data lines perpendicular to the gate lines.
  • a gate line dedicated to the sub-pixel row is disposed on each side of each sub-pixel row.
  • every second sub-pixel is set Set a data line.
  • the width of the black matrix between adjacent sub-pixels is different, and this phenomenon is called a black matrix difference.
  • the embodiment of the present disclosure is described by taking the array substrate as described above as an example, but the protection range of the present disclosure is not limited to the array substrate, and may also include other types of array substrates.
  • FIG. 1 is a schematic diagram schematically illustrating a difference in a black matrix.
  • the black matrix width on the left side of the sub-pixel R is AA'
  • the black matrix width on the right side of the sub-pixel R is BB'.
  • a black matrix of width AA' is used to cover the data lines, so its width is set according to the design rules of the black matrix.
  • a black matrix of width BB' is used to cover the common electrode, and its width can be adjusted within a certain range. The narrower the black matrix having the width BB' is set, the larger the black matrix difference (i.e., (AA'-BB') / the width of the two sub-pixels).
  • the aperture ratio increases, but the difference in luminance distribution between the two pixels also increases, causing a difference in brightness between the pixels displayed at low gray levels. That is to say, in the case of observing the screen at different distances and angles from the display screen, there will be a phenomenon of periodic vertical lines (such as light and dark stripes under a white screen).
  • Fig. 2 shows a schematic structural view of an array substrate employing a basic pixel structure.
  • pixel structures having sub-pixel alignments of the same color on different sub-pixel rows are hereinafter referred to as "basic pixel structures.”
  • the array substrate shown in FIG. 2 includes a plurality of gate lines 220 disposed in a direction parallel to the sub-pixel rows, and a plurality of data lines 230 and a plurality of common electrodes (not shown) perpendicular to the gate lines.
  • a gate line 220 dedicated to the sub-pixel row is disposed on each side of each sub-pixel row. In each sub-pixel row, one data line 230 is placed every two sub-pixels.
  • the first light-shielding strip 211 i.e., the black matrix of width AA' in Fig. 1 is used to cover the data line 230, and thus its width is set according to the design rule of the black matrix.
  • the second light-shielding strip 212 i.e., the black matrix having a width of BB' in Fig. 1 is used to cover the common electrode, and its width can be adjusted within a certain range. As shown in FIG. 2, the first light-shielding strips 211 on different sub-pixel rows are aligned with each other, and the second light-shielding strips 212 on different sub-pixel rows are aligned with each other.
  • FIG. 3 shows a schematic structural diagram of an array substrate using a Bright View 3 (BV3) pixel structure.
  • the array substrate includes a plurality of gate lines 320 disposed in a direction parallel to the sub-pixel rows, and a plurality of data lines 330 and a plurality of common electrodes 350 perpendicular to the gate lines.
  • On the array substrate one side of each sub-pixel row is respectively provided for the sub-pixel row.
  • Grid line 320 In each sub-pixel row, one data line 330 is placed every two sub-pixels.
  • the common electrode 350 is located between the two sub-pixels.
  • each pixel group 3000 includes two sub-pixel rows 3100, and because the sub-pixel rows adjacent to each other are misaligned, the first light-shielding strip on the different sub-pixel row 3100 The 311 and the second light blocking strip 312 are not aligned.
  • each pixel group 3000 is identical in structure and aligned, the first light bar 311 on the first sub-pixel row 3100 of one pixel group 3000 is aligned with the first one on the first sub-pixel row 3100 of the other pixel group 3000.
  • the second light bar 312 on the first sub-pixel row 3100 of one pixel group 3000 is aligned with the second light bar 312 on the first sub-pixel row 3100 of the other pixel group 3000.
  • the first light-shielding strip 311 on the second sub-pixel row 3100 of one pixel group 3000 is aligned with the first light-shielding strip 311 on the second sub-pixel row 3100 of the other pixel group 3000.
  • the second light bar 312 on the second sub-pixel row 3100 of one pixel group 3000 is aligned with the second light bar 312 on the second sub-pixel row 3100 of the other pixel group 3000.
  • the array substrate using the above two pixel structures has a problem of difference in brightness between pixels displayed at low gray levels.
  • One solution is to increase the width of the second shading strip, thereby reducing the black matrix difference. But this will sacrifice the aperture ratio.
  • FIG. 4 illustrates a schematic structural diagram of an array substrate according to an exemplary embodiment of the present disclosure.
  • the array substrate includes a plurality of gate lines 420 disposed in a direction parallel to the sub-pixel rows, and a plurality of data lines 430 and a plurality of common electrodes (not shown) perpendicular to the gate lines.
  • a gate line 420 dedicated to the sub-pixel row is disposed on each side of each sub-pixel row.
  • one data line 430 is disposed every two sub-pixels 440.
  • the array substrate is composed of a plurality of pixel groups 4000 arranged in the column direction.
  • Each pixel group 4000 is identical in structure and aligned.
  • Each pixel group 4000 includes a plurality of sub-pixel rows 4100. Two adjacent in each sub-pixel row 4100 A first light bar 411 or a second light bar 412 is disposed between the sub-pixels 440, and the first light bar 411 and the second light bar 412 are alternately disposed.
  • the first light strip 411 on at least one of the sub-pixel rows 4100 is aligned with the second light strip 412 on at least one different sub-pixel row 4100.
  • the first light blocking strip 411 has a first width and the second light blocking strip 412 has a second width.
  • the first light strip 411 is used to cover the data line 430
  • the second light strip 412 is used to cover the common electrode (not shown). Since the width of the common electrode is smaller than the width of the data line 430, the width of the second light blocking strip 412 is smaller than the width of the first light blocking strip 411.
  • the array substrate according to the embodiment of the present disclosure is changed in the column direction by changing the arrangement manner of the first light-shielding strip 411 and the second light-shielding strip 412.
  • the difference in luminance distribution between the upper pixels is reduced, so that the difference in brightness of the pixel display at the low gray level can be avoided without lowering the aperture ratio.
  • FIG. 5 illustrates a schematic structural diagram of an array substrate employing a basic pixel structure according to a first exemplary embodiment of the present disclosure.
  • the array substrate includes a plurality of gate lines 520 disposed in a direction parallel to the sub-pixel rows, and a plurality of data lines 530 and a plurality of common electrodes (not shown) perpendicular to the gate lines.
  • a gate line 520 dedicated to the sub-pixel row is disposed on each side of each sub-pixel row.
  • one data line 530 is placed every two sub-pixels.
  • Each pixel group 5000 includes two sub-pixel rows 5100.
  • a first light blocking strip 511 or a second light blocking strip 512 is disposed between two adjacent sub-pixels 540 in each sub-pixel row 5100, and the first light blocking strip 511 and the second light blocking strip 512 are alternately disposed.
  • the first light blocking strip 511 has a first width
  • the second light blocking strip 512 has a second width.
  • the first light-shielding strip 511 on one sub-pixel row 5100 is aligned with the second light-shielding strip 512 on the other sub-pixel row 5100
  • the second light-shielding strip 512 on the sub-pixel row 5100 is aligned with the other The first light bar 511 on the sub-pixel row 5100.
  • the first light-shielding strip 511 and the second light-shielding strip 512 are also alternately arranged in the column direction, so the first light-shielding strip 511 and the second light-shielding on each column of the light-shielding strips
  • the number of bars 512 is equal such that the luminance distribution between the sub-pixel columns is uniform. Therefore, the embodiment can avoid low gray scale images without reducing the aperture ratio. The difference between light and dark displayed by the prime.
  • the first light blocking strip 511 is used to cover the data line 530. Since the first light blocking strip 511 and the second light blocking strip 512 are alternately arranged in the column direction, on the array substrate according to the present embodiment, as shown in FIG. 5, the wiring pattern of the data line 530 has a zigzag shape.
  • the zigzag routing method increases the line resistance and may therefore affect the voltage of the data signal transmitted on the data line 530.
  • FIG. 6 illustrates a schematic structural diagram of an array substrate employing a basic pixel structure according to a second exemplary embodiment of the present disclosure.
  • the array substrate includes a plurality of gate lines 620 disposed in a direction parallel to the sub-pixel row 6100 and a plurality of data lines 630 and a plurality of common electrodes (not shown) perpendicular to the gate lines.
  • a gate line 620 dedicated to the sub-pixel row 6100 is disposed on each side of each sub-pixel row 6100.
  • each pixel group 6000 can include more than two sub-pixel rows 6100.
  • Each pixel group 6000 is divided into a first pixel group 600A and a second pixel group 600B in the column direction.
  • the first pixel group 600A may include N sub-pixel rows 6100
  • the second pixel group 600B may include M sub-pixel rows 6100.
  • the first light strips 611 on different sub-pixel rows 6100 are aligned with each other, and the second light strips 612 on different sub-pixel rows 6100 are aligned with each other.
  • the first light bar 611 on each of the sub-pixel rows 6100 in the first pixel group 600A is aligned with the second light bar 612 on each of the second pixel groups 600B.
  • the second light bar 612 on each of the sub-pixel rows 6100 in the first pixel group 600A is aligned with the first light bar 611 on each of the second pixel groups 600B.
  • N and M can be any of 1 to 4, and N and M can be equal.
  • each pixel group 6000 including four sub-pixel rows 6100 as an example.
  • Each pixel group 6000 is divided into a first pixel group 600A and a second pixel group 600B in the column direction.
  • the first pixel group 600A includes a first sub-pixel row 6100 and a second sub-pixel row 6100.
  • the second pixel group 600B includes a third sub-pixel row 6100 and a fourth sub-pixel row 6100.
  • the first light bar 611 on the first and second sub-pixel rows 6100 are aligned with each other, and the first and second sub-pixel rows 6100
  • the second light blocking strips 612 are aligned with each other.
  • the first light-shielding bars 611 on the third and fourth sub-pixel rows 6100 are aligned with each other, and the second light-shielding bars 612 on the third and fourth sub-pixel rows 6100 are aligned with each other. Furthermore, the first visor 611 on the first and second sub-pixel rows 6100 is aligned with the second visor 612 on the third and fourth sub-pixel rows 6100. The second light bar 612 on the first and second sub-pixel rows 6100 is aligned with the first light bar 611 on the third and fourth sub-pixel rows 6100.
  • the luminance distribution between the sub-pixel columns can be made uniform. Therefore, the present embodiment can avoid the difference in brightness between pixels displayed at low gray levels without reducing the aperture ratio. Due to the reduction of the zigzag trace of the data line, the present embodiment can also reduce the line resistance of the data line as compared with the first exemplary embodiment.
  • FIG. 7 illustrates a schematic structural diagram of an array substrate employing a BV3 pixel structure according to a third exemplary embodiment of the present disclosure.
  • the array substrate includes a plurality of gate lines 720 disposed in a direction parallel to the sub-pixel rows, and a plurality of data lines 730 and a plurality of common electrodes 750 perpendicular to the gate lines.
  • a gate line 720 dedicated to the sub-pixel row is disposed on each side of each sub-pixel row.
  • one data line 730 is placed every two sub-pixels.
  • the common electrode 750 is located between the two sub-pixels.
  • Each pixel group 7000 includes four sub-pixel rows 7100.
  • Each pixel group 7000 is divided into a first pixel group 700A and a second pixel group 700B in the column direction.
  • the first pixel grouping 700A includes an odd number of rows of sub-pixel rows 7100.
  • the second pixel group 700B includes sub-pixel rows 7100 of even rows.
  • the first light-shielding strip 711 on one sub-pixel row 7100 and the other on the other sub-pixel row 7100 The second light blocking strips 712 are aligned, and the second light blocking strips 712 on one sub-pixel row 7100 are aligned with the first light blocking strips 711 on the other sub-pixel row 7100.
  • the first light-shielding bars 711 on different sub-pixel rows 7100 are aligned with each other, on different sub-pixel rows 7100
  • the second light blocking strips 712 are aligned with each other.
  • Fig. 8 is a schematic view for explaining the design of the array substrate shown in Fig. 7.
  • the same reference numerals denote the same elements, components or combinations.
  • FIG. 9 is a schematic diagram for explaining a design of an array substrate employing a BV3 pixel structure according to a fourth exemplary embodiment of the present disclosure.
  • Each pixel group 9000 includes six sub-pixel rows 9100.
  • Each pixel group 9000 is divided into a first pixel grouping 900A and a second pixel grouping 900B in the column direction.
  • the first pixel grouping 900A includes odd-numbered rows of sub-pixel rows 9100.
  • the second pixel grouping 900B includes sub-pixel rows 9100 of even rows.
  • the first light bar 911 on the middle sub-pixel row 9100 is aligned with the upper and lower sub-pixel rows 9100
  • the second light-shielding strip 912 on the middle sub-pixel row 9100 is aligned with the first light-shielding strip 911 on the upper and lower sub-pixel rows 9100.
  • the first light-shielding strip 911 on the middle sub-pixel row 9100 is aligned with the upper and lower sub-pixel rows a second light bar 912 on one of the sub-pixel rows 9100 in 9100 and aligned with the first light bar 911 on the other of the upper and lower sub-pixel rows 9100, the first sub-pixel row 9100
  • the second light blocking strip 912 aligns the first light blocking strip 911 on one of the sub-pixel rows 9100 in the upper and lower sub-pixel rows 9100 and aligns the second light blocking on the other sub-pixel row 9100 in the upper and lower sub-pixel rows 9100 Article 912.
  • This design of the fourth exemplary embodiment changes the first light bar 911 and the second light bar 912 in both the first pixel grouping 900A and the second pixel grouping 900B with respect to the design of the third exemplary embodiment.
  • the arrangement is such that the difference in brightness of the pixel display at low gray levels can be better avoided without reducing the aperture ratio.
  • each pixel group may include more sub-pixel rows than Six.
  • Variations or modifications to the arrangement of the first light-shielding strip and the second light-shielding strip based on the idea of the present disclosure are intended to fall within the scope of the present disclosure.
  • FIG. 10 shows a schematic structural diagram of a display device D100 according to an embodiment of the present disclosure.
  • the display device D100 includes a display panel D110, which includes the array substrate provided by any of the above embodiments. Therefore, the description of the structure, function, and effect of the array substrate in the above embodiment is also suitable for the display panel D110 and the display device D100 in the present embodiment.
  • the array substrate, the display panel, and the display device according to the embodiments of the present disclosure can avoid the difference in brightness of the pixel display at the time of low gray scale without lowering the aperture ratio.
  • the display device provided by the embodiment of the present disclosure can be applied to any product having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, or a navigator.
  • a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, or a navigator.

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  • Nonlinear Science (AREA)
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Abstract

一种阵列基板，包括沿列方向排列的多个像素组（4000，5000，6000，7000，9000）。多个像素组（4000，5000，6000，7000，9000）中的每一个包括多个子像素行（4100，5100，6100，7100，9100）。每一个子像素行（4100，5100，6100，7100，9100）包括多个子像素（440，540，640），在相邻的两个子像素（440，540，640）之间设置有第一遮光条（411，511，611，711，911）或者第二遮光条（412，512，612，712，912），并且第一遮光条（411，511，611，711，911）和第二遮光条（412，512，612，712，912）交替设置。第一遮光条（411，511，611，711，911）具有第一宽度，第二遮光条（412，512，612，712，912）具有第二宽度。对于每一个像素组（4000，5000，6000，7000，9000），至少一个子像素行（4100，5100，6100，7100，9100）上的第一遮光条（411，511，611，711，911）对齐至少一个不同的子像素行（4100，5100，6100，7100，9100）上的第二遮光条（412，512，612，712，912）。该阵列基板能够在不降低开口率的同时，避免低灰阶时像素显示的明暗差异。

Description

阵列基板以及显示装置
相关申请的交叉引用
本申请要求于2017年01月20日递交的中国专利申请第201710051837.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，具体地，涉及阵列基板以及显示装置。
背景技术
随着显示技术的不断发展，阵列基板被广泛应用于显示面板中。
发明内容
本文中描述的实施例提供了一种新型的阵列基板以及显示装置，其能够在不降低开口率的同时，避免低灰阶时像素显示的明暗差异。
根据本公开的第一个方面，提供了一种阵列基板。该阵列基板包括沿列方向排列的多个像素组。多个像素组中的每一个包括多个子像素行。每一个子像素行包括多个子像素，在相邻的两个子像素之间设置有第一遮光条或者第二遮光条，并且第一遮光条和第二遮光条交替设置。第一遮光条具有第一宽度，第二遮光条具有第二宽度。对于每一个像素组，至少一个子像素行上的第一遮光条对齐至少一个不同的子像素行上的第二遮光条。
在本公开的实施例中，第一宽度与第二宽度不同。
在本公开的实施例中，对于每个像素组，不同子像素行上的具有相同颜色的子像素对齐。
在本公开的实施例中，每个像素组包括两个子像素行，一个子像素行上的第一遮光条对齐另一个子像素行上的第二遮光条，一个子像素行上的第二遮光条对齐另一个子像素行上的第一遮光条。
在本公开的实施例中，每个像素组在列方向上被分为两个像素分组。在每一个像素分组中，不同子像素行上的第一遮光条彼此对齐，不同子像素行上的第二遮光条彼此对齐。两个像素分组中的一个像素分组中的每个子像素行上的第一遮光条与另一个像素分组中的每个子像素行上的第二遮光条对齐，一个像素分组中的每个子像素行上的第二遮光条与另一个像素分组中的每个子像素行上的第一遮光条对齐。
在本公开的实施例中，像素分组中的子像素行的数量为1、2、3或4。
在本公开的实施例中，彼此相邻的子像素行被排列成相互偏移子像素的宽度的一半，间隔一行排列的子像素行上的具有相同颜色的子像素对齐。
在本公开的实施例中，每个像素组包括四个子像素行，奇数行的子像素行构成第一像素分组，偶数行的子像素行构成第二像素分组。在第一像素分组和第二像素分组中的一个像素分组中，一个子像素行上的第一遮光条对齐另一个子像素行上的第二遮光条，一个子像素行上的第二遮光条对齐另一个子像素行上的第一遮光条。在第一像素分组和第二像素分组中的另一个像素分组中，不同子像素行上的第一遮光条彼此对齐，不同子像素行上的第二遮光条彼此对齐。
在本公开的实施例中，每个像素组包括六个子像素行。奇数行的子像素行构成第一像素分组，偶数行的子像素行构成第二像素分组。在第一像素分组和第二像素分组中的一个像素分组中，中间的子像素行上的第一遮光条对齐上方和下方的子像素行上的第二遮光条，中间的子像素行上的第二遮光条对齐上方和下方的子像素行上的第一遮光条。在第一像素分组和第二像素分组中的另一个像素分组中，中间的子像素行上的第一遮光条对齐上方和下方的子像素行中的一个子像素行上的第二遮光条并且对齐上方和下方的子像素行中的另一个子像素行上的第一遮光条，中间的子像素行上的第二遮光条对齐上方和下方的子像素行中的一个子像素行上的第一遮光条并且对齐上方和下方的子像素行中的另一个子像素行上的第二遮光条。
在本公开的实施例中，阵列基板还包括沿着平行于子像素行的方向设 置的多条栅线和与栅线垂直的多条数据线。在每一个子像素行的两侧分别设置一条专用于该子像素行的栅线。在每一个子像素行中，每隔两个子像素设置一条数据线。
在本公开的实施例中，第一遮光条被配置为遮住数据线，第二遮光条被配置为遮住该两个子像素之间的公共电极，并且第二宽度小于第一宽度。
根据本公开的第二个方面，提供了一种显示面板，其包括如上所述的阵列基板。
根据本公开的第三个方面，提供了一种显示装置，其包括如上所述的显示面板。
根据本公开实施例的阵列基板、显示面板以及显示装置，通过改变第一遮光条与第二遮光条的排列方式，能够在不降低开口率的同时，避免低灰阶时像素显示的明暗差异，即避免在距离显示画面不同距离和角度来观察屏幕的情况下，看到有周期性的竖线条的现象(如白色画面下的明暗条纹等)。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图进行简要说明。应当知道，以下描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制，其中：
图1是示意性说明黑矩阵差异的示意图；
图2是一种采用基本像素结构的阵列基板的示意性结构图；
图3是一种采用高亮屏(Bright View 3，简称BV3)像素结构的阵列基板的示意性结构图；
图4是根据本公开的示例性实施例的阵列基板的示意性结构图；
图5是根据本公开的第一示例性实施例的采用基本像素结构的阵列基板的示意性结构图；
图6是根据本公开的第二示例性实施例的采用基本像素结构的阵列基板的示意性结构图；
图7是根据本公开的第三示例性实施例的采用BV3像素结构的阵列基板的示意性结构图；
图8是用于说明图7所示的阵列基板的设计的示意图；
图9是用于说明根据本公开的第四示例性实施例的采用BV3像素结构的阵列基板的设计的示意图；
图10是根据本公开的实施例的显示装置的示意性结构图。
在附图中，最后两位数字相同的标记对应于相同的元素。需要注意的是，附图中的元素是示意性的，没有按比例绘制。
具体实施方式
为了使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本公开保护的范围。
除非另外定义，否则在此使用的所有术语(包括技术和科学术语)具有与本公开主题所属的领域的技术人员所通常理解的相同含义。进一步将理解的是，诸如在通常使用的词典中定义的那些的术语应解释为具有与说明书上下文和相关技术中它们的含义一致的含义，并且将不以理想化或过于正式的形式来解释，除非在此另外明确定义。如在此所使用的，将两个或更多部分“连接”或“耦接”到一起的陈述应指该部分直接结合到一起或通过一个或多个中间部件结合。另外，诸如“第一”和“第二”的术语仅用于将一个部件(或部件的一部分)与另一个部件(或部件的另一部分)区分开。
一种用于显示装置的阵列基板包括沿着平行于子像素行的方向设置的多条栅线和与栅线垂直的多条数据线。在每一个子像素行的两侧分别设置一条专用于该子像素行的栅线。在每一个子像素行中，每隔两个子像素设 置一条数据线。在这种阵列基板上，相邻子像素之间的黑矩阵的宽度不同，这种现象被称为黑矩阵差异。本公开的实施例以上述这种阵列基板为例进行说明，但是本公开的保护范围并不限于该阵列基板，还可以包括其它类型的阵列基板。
图1是示意性说明黑矩阵差异的示意图。如图1所示，在行方向上，例如子像素R左边的黑矩阵宽度为AA’，子像素R右边的黑矩阵宽度为BB’。宽度为AA’的黑矩阵用于遮住数据线，因此其宽度根据黑矩阵的设计规则来设定。宽度为BB’的黑矩阵用于遮住公共电极，其宽度可在一定的范围内调整。将宽度为BB’的黑矩阵设置得越窄，则黑矩阵差异(即(AA’-BB’)/两个子像素的宽度)越大。这样，开口率增加，但是两个像素之间的亮度分布差异也会增加，从而引起低灰阶时像素显示的明暗差异。也就是说，在距离显示画面不同距离和角度来观察屏幕的情况下，会看到有周期性的竖线条的现象(如白色画面下的明暗条纹等)。
图2示出一种采用基本像素结构的阵列基板的示意性结构图。如图2所示，不同的子像素行上的具有相同颜色的子像素对齐的像素结构在下文中被称为“基本像素结构”。图2所示的阵列基板包括沿着平行于子像素行的方向设置的多条栅线220和与栅线垂直的多条数据线230和多个公共电极(未示出)。在图2所示的阵列基板上，在每一个子像素行的两侧分别设置一条专用于该子像素行的栅线220。在每一个子像素行中，每隔两个子像素设置一条数据线230。第一遮光条211(即在图1中宽度为AA’的黑矩阵)用于遮住数据线230，因此其宽度根据黑矩阵的设计规则来设定。而第二遮光条212(即在图1中宽度为BB’的黑矩阵)用于遮住公共电极，其宽度可在一定的范围内调整。如图2所示，不同的子像素行上的第一遮光条211彼此对齐，不同的子像素行上的第二遮光条212彼此对齐。
图3示出一种采用高亮屏(Bright View 3，简称BV3)像素结构的阵列基板的示意性结构图。该阵列基板包括沿着平行于子像素行的方向设置的多条栅线320和与栅线垂直的多条数据线330和多个公共电极350。在该阵列基板上，在每一个子像素行的两侧分别设置一条专用于该子像素行 的栅线320。在每一个子像素行中，每隔两个子像素设置一条数据线330。而公共电极350位于该两个子像素之间。如图3所示的彼此相邻的子像素行被排列成相互偏移子像素的宽度的一半，间隔一行排列的子像素行上的具有相同颜色的子像素对齐的像素结构在下文中被称为“BV3像素结构”。这种结构的阵列基板由沿列方向排列的多个像素组3000组成。如图3所示，在一种BV3像素结构中，每个像素组3000包括两个子像素行3100，并且因为彼此相邻的子像素行错位排列，所以不同子像素行3100上的第一遮光条311和第二遮光条312不对齐。然而由于每个像素组3000结构相同并且对齐设置，因此一个像素组3000的第一个子像素行3100上的第一遮光条311对齐其它像素组3000的第一个子像素行3100上的第一遮光条311。一个像素组3000的第一个子像素行3100上的第二遮光条312对齐其它像素组3000的第一个子像素行3100上的第二遮光条312。一个像素组3000的第二个子像素行3100上的第一遮光条311对齐其它像素组3000的第二个子像素行3100上的第一遮光条311。一个像素组3000的第二个子像素行3100上的第二遮光条312对齐其它像素组3000的第二个子像素行3100上的第二遮光条312。
采用上述这两种像素结构(基本像素结构和BV3像素结构)的阵列基板都存在低灰阶时像素显示的明暗差异的问题。一种解决方案是增加第二遮光条的宽度，从而减少黑矩阵差异。但是这样会牺牲开口率。
本公开的实施例提供一种新型的阵列基板，其能够在不降低开口率的同时避免低灰阶时像素显示的明暗差异。图4示出根据本公开的示例性实施例的阵列基板的示意性结构图。该阵列基板包括沿着平行于子像素行的方向设置的多条栅线420和与栅线垂直的多条数据线430和多个公共电极(未示出)。在该阵列基板上，在每一个子像素行的两侧分别设置一条专用于该子像素行的栅线420。在每一个子像素行中，每隔两个子像素440设置一条数据线430。根据本公开示例性实施例的阵列基板由沿列方向排列的多个像素组4000组成。每个像素组4000结构相同并且对齐设置。每个像素组4000包括多个子像素行4100。在每一个子像素行4100中相邻的两 个子像素440之间设置有第一遮光条411或者第二遮光条412，并且第一遮光条411和第二遮光条412交替设置。对于每一个像素组4000，至少一个子像素行4100上的第一遮光条411对齐至少一个不同的子像素行4100上的第二遮光条412。第一遮光条411具有第一宽度，第二遮光条412具有第二宽度。
在一个示例中，第一遮光条411用于遮住数据线430，第二遮光条412用于遮住公共电极(未示出)。因为公共电极的宽度小于数据线430的宽度，所以第二遮光条412的宽度小于第一遮光条411的宽度。
根据本公开实施例的阵列基板在第一遮光条411的宽度与第二遮光条412的宽度不同的情况下，通过改变第一遮光条411与第二遮光条412的排列方式，使得在列方向上像素之间的亮度分布差异性减小，从而能够在不降低开口率的同时，避免低灰阶时像素显示的明暗差异。
下面将针对不同的像素结构来描述本公开的示例性实施例。
图5示出根据本公开的第一示例性实施例的采用基本像素结构的阵列基板的示意性结构图。该阵列基板包括沿着平行于子像素行的方向设置的多条栅线520和与栅线垂直的多条数据线530和多个公共电极(未示出)。在该阵列基板上，在每一个子像素行的两侧分别设置一条专用于该子像素行的栅线520。在每一个子像素行中，每隔两个子像素设置一条数据线530。每个像素组5000包括两个子像素行5100。在每一个子像素行5100中相邻的两个子像素540之间设置有第一遮光条511或者第二遮光条512，并且第一遮光条511和第二遮光条512交替设置。第一遮光条511具有第一宽度，第二遮光条512具有第二宽度。在本实施例中，一个子像素行5100上的第一遮光条511对齐另一个子像素行5100上的第二遮光条512，并且该子像素行5100上的第二遮光条512对齐该另一个子像素行5100上的第一遮光条511。也就是说，在根据本实施例的阵列基板上，第一遮光条511和第二遮光条512在列方向上也交替设置，因此在每一列遮光条上的第一遮光条511和第二遮光条512的数量相等，从而使得在子像素列之间的亮度分布均匀。因此本实施例能够在不降低开口率的同时，避免低灰阶时像 素显示的明暗差异。
在本实施例中，第一遮光条511用于遮住数据线530。因为第一遮光条511和第二遮光条512在列方向上交替设置，所以在根据本实施例的阵列基板上，如图5所示，数据线530的走线方式呈Z字形。Z字形的走线方式会增加线电阻，因此可能会影响数据线530上传输的数据信号的电压。
在本公开的第二示例性实施例中，提供另一种采用基本像素结构的阵列基板。在该阵列基板中，每个像素组包括多于两个的子像素行。图6示出根据本公开的第二示例性实施例的采用基本像素结构的阵列基板的示意性结构图。该阵列基板包括沿着平行于子像素行6100的方向设置的多条栅线620和与栅线垂直的多条数据线630和多个公共电极(未示出)。在该阵列基板上，在每一个子像素行6100的两侧分别设置一条专用于该子像素行6100的栅线620。在每一个子像素行6100中，每隔两个子像素640设置一条数据线630。每个像素组6000可包括多于两个的子像素行6100。每个像素组6000在列方向上被分为第一像素分组600A与第二像素分组600B。第一像素分组600A可包括N个子像素行6100，而第二像素分组600B可包括M个子像素行6100。在每一个像素分组中，不同子像素行6100上的第一遮光条611彼此对齐，不同子像素行6100上的第二遮光条612彼此对齐。第一像素分组600A中的每个子像素行6100上的第一遮光条611与第二像素分组600B中的每个子像素行6100上的第二遮光条612对齐。第一像素分组600A中的每个子像素行6100上的第二遮光条612与第二像素分组600B中的每个子像素行6100上的第一遮光条611对齐。在一个示例中，N和M可以是1至4中的任一值，并且N与M可以相等。
下面以每个像素组6000包括四个子像素行6100为例来更详细的描述第二示例性实施例。每个像素组6000在列方向上被分为第一像素分组600A与第二像素分组600B。第一像素分组600A包括第一个子像素行6100和第二个子像素行6100。第二像素分组600B包括第三个子像素行6100和第四个子像素行6100。在第一像素分组600A中，第一个和第二个子像素行6100上的第一遮光条611彼此对齐，第一个和第二个子像素行6100上的 第二遮光条612彼此对齐。在第二像素分组600B中，第三个和第四个子像素行6100上的第一遮光条611彼此对齐，第三个和第四个子像素行6100上的第二遮光条612彼此对齐。此外，第一个和第二个子像素行6100上的第一遮光条611与第三个和第四个子像素行6100上的第二遮光条612对齐。第一个和第二个子像素行6100上的第二遮光条612与第三个和第四个子像素行6100上的第一遮光条611对齐。
采用根据第二示例性实施例的布置，可以使得在子像素列之间的亮度分布均匀。因此本实施例能够在不降低开口率的同时，避免低灰阶时像素显示的明暗差异。由于数据线的Z字形走线的减少，与第一示例性实施例相比，本实施例还能够减少数据线的线电阻。
图7示出根据本公开的第三示例性实施例的采用BV3像素结构的阵列基板的示意性结构图。该阵列基板包括沿着平行于子像素行的方向设置的多条栅线720和与栅线垂直的多条数据线730和多个公共电极750。在该阵列基板上，在每一个子像素行的两侧分别设置一条专用于该子像素行的栅线720。在每一个子像素行中，每隔两个子像素设置一条数据线730。而公共电极750位于该两个子像素之间。每个像素组7000包括四个子像素行7100。每个像素组7000在列方向上被分为第一像素分组700A与第二像素分组700B。第一像素分组700A包括奇数行的子像素行7100。第二像素分组700B包括偶数行的子像素行7100。在第一像素分组700A与第二像素分组700B中的一个像素分组(例如，第一像素分组700A)中，一个子像素行7100上的第一遮光条711与另一个子像素行7100上的第二遮光条712对齐，一个子像素行7100上的第二遮光条712与另一个子像素行7100上的第一遮光条711对齐。在第一像素分组700A与第二像素分组700B中的另一个像素分组(例如，第二像素分组700B)中，不同子像素行7100上的第一遮光条711彼此对齐，不同子像素行7100上的第二遮光条712彼此对齐。采用这种布置，能够在不降低开口率的同时避免低灰阶时像素显示的明暗差异。
图8是用于说明图7所示的阵列基板的设计的示意图。为方便理解， 在图7和图8中，相同的标号表示相同的元件、部件或组合。
图9是用于说明根据本公开的第四示例性实施例的采用BV3像素结构的阵列基板的设计的示意图。每个像素组9000包括六个子像素行9100。每个像素组9000在列方向上被分为第一像素分组900A与第二像素分组900B。第一像素分组900A包括奇数行的子像素行9100。第二像素分组900B包括偶数行的子像素行9100。在第一像素分组900A与第二像素分组900B中的一个像素分组(例如，第二像素分组900B)中，中间的子像素行9100上的第一遮光条911对齐上方和下方的子像素行9100上的第二遮光条912，中间的子像素行9100上的第二遮光条912对齐上方和下方的子像素行9100上的第一遮光条911。在第一像素分组900A与第二像素分组900B中的另一个像素分组(例如，第一像素分组900A)中，中间的子像素行9100上的第一遮光条911对齐上方和下方的子像素行9100中的一个子像素行9100上的第二遮光条912并且对齐上方和下方的子像素行9100中的另一个子像素行9100上的第一遮光条911，中间的子像素行9100上的第二遮光条912对齐上方和下方的子像素行9100中的一个子像素行9100上的第一遮光条911并且对齐上方和下方的子像素行9100中的另一个子像素行9100上的第二遮光条912。相对于第三示例性实施例的设计，第四示例性实施例的这种设计在第一像素分组900A与第二像素分组900B二者中均改变了第一遮光条911与第二遮光条912的排列方式，因此能够在不降低开口率的同时更好地避免低灰阶时像素显示的明暗差异。
本领域的技术人员应理解，对于采用BV3像素结构的阵列基板，在本公开的第三和第四示例性实施例的变型或者修改中，每个像素组包括的子像素行的数量可以多于六个。基于本公开的思想对第一遮光条和第二遮光条的排列方式的变型或者修改都应落入本公开的保护范围之内。
图10示出根据本公开的实施例的显示装置D100的示意性结构图。显示装置D100包括显示面板D110，该显示面板D110包括上述任一实施例提供的阵列基板。因此在上述实施例中对阵列基板的结构、功能和效果的描述同样适于本实施例中的显示面板D110和显示装置D100。
从以上描述可以看出，根据本公开实施例的阵列基板、显示面板以及显示装置，能够在不降低开口率的同时，避免低灰阶时像素显示的明暗差异。
本公开实施例提供的显示装置可以应用于任何具有显示功能的产品，例如，电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框或导航仪等。
除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。相似地，措辞“包含”和“包括”将解释为包含在内而不是独占性地。同样地，术语“包括”和“或”应当解释为包括在内的，除非本文中明确禁止这样的解释。在本文中使用术语“示例”之处，特别是当其位于一组术语之后时，所述“示例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解，本申请的各个方面可以单独或者与一个或多个其它方面组合实施。还应当理解，本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本申请的范围。
以上对本公开的若干实施例进行了详细描述，但显然，本领域技术人员可以在不脱离本公开的精神和范围的情况下对本公开的实施例进行各种修改和变型。本公开的保护范围由所附的权利要求限定。

Claims (13)

  1. 一种阵列基板，包括沿列方向排列的多个像素组，
    其中，所述多个像素组中的每一个包括多个子像素行；
    其中，每一个子像素行包括多个子像素，在相邻的两个所述子像素之间设置有第一遮光条或者第二遮光条，并且所述第一遮光条和所述第二遮光条交替设置；
    其中，所述第一遮光条具有第一宽度，所述第二遮光条具有第二宽度；
    其中，对于每一个像素组，至少一个所述子像素行上的所述第一遮光条对齐至少一个不同的子像素行上的所述第二遮光条。
  2. 根据权利要求1所述的阵列基板，其中，所述第一宽度与所述第二宽度不同。
  3. 根据权利要求1或2所述的阵列基板，其中，对于每个像素组，不同子像素行上的具有相同颜色的子像素对齐。
  4. 根据权利要求3所述的阵列基板，其中，每个像素组包括两个所述子像素行，一个子像素行上的所述第一遮光条对齐另一个子像素行上的所述第二遮光条，所述一个子像素行上的所述第二遮光条对齐所述另一个子像素行上的所述第一遮光条。
  5. 根据权利要求3所述的阵列基板，其中，每个像素组在列方向上被分为两个像素分组，
    其中，在每一个像素分组中，不同子像素行上的所述第一遮光条彼此对齐，不同子像素行上的所述第二遮光条彼此对齐；以及
    所述两个像素分组中的一个像素分组中的每个子像素行上的所述第一遮光条与另一个像素分组中的每个子像素行上的所述第二遮光条对齐，所述一个像素分组中的每个子像素行上的所述第二遮光条与所述另一个像素分组中的每个子像素行上的所述第一遮光条对齐。
  6. 根据权利要求5所述的阵列基板，其中，所述像素分组中的所述子像素行的数量为1、2、3或4。
  7. 根据权利要求1或2所述的阵列基板，其中，彼此相邻的所述子像 素行被排列成相互偏移子像素的宽度的一半，间隔一行排列的所述子像素行上的具有相同颜色的子像素对齐。
  8. 根据权利要求7所述的阵列基板，其中，每个像素组包括四个所述子像素行，奇数行的所述子像素行构成第一像素分组，偶数行的所述子像素行构成第二像素分组，
    其中，在所述第一像素分组和所述第二像素分组中的一个像素分组中，一个子像素行上的所述第一遮光条对齐另一个子像素行上的所述第二遮光条，所述一个子像素行上的所述第二遮光条对齐所述另一个子像素行上的所述第一遮光条；以及
    在所述第一像素分组和所述第二像素分组中的另一个像素分组中，不同子像素行上的所述第一遮光条彼此对齐，不同子像素行上的所述第二遮光条彼此对齐。
  9. 根据权利要求7所述的阵列基板，其中，每个像素组包括六个所述子像素行，
    其中，奇数行的所述子像素行构成第一像素分组，偶数行的所述子像素行构成第二像素分组，
    其中，在所述第一像素分组和所述第二像素分组中的一个像素分组中，中间的所述子像素行上的所述第一遮光条对齐上方和下方的所述子像素行上的所述第二遮光条，所述中间的子像素行上的所述第二遮光条对齐所述上方和下方的子像素行上的所述第一遮光条；以及
    在所述第一像素分组和所述第二像素分组中的另一个像素分组中，中间的所述子像素行上的所述第一遮光条对齐上方和下方的所述子像素行中的一个子像素行上的所述第二遮光条并且对齐所述上方和下方的子像素行中的另一个子像素行上的所述第一遮光条，所述中间的子像素行上的所述第二遮光条对齐所述上方和下方的子像素行中的一个子像素行上的所述第一遮光条并且对齐所述上方和下方的子像素行中的另一个子像素行上的所述第二遮光条。
  10. 根据权利要求1至9中任一项所述的阵列基板，还包括沿着平行 于所述子像素行的方向设置的多条栅线和与所述栅线垂直的多条数据线，
    其中，在每一个子像素行的两侧分别设置一条专用于该子像素行的栅线；
    在每一个子像素行中，每隔两个子像素设置一条数据线。
  11. 根据权利要求10所述的阵列基板，其中，第一遮光条被配置为遮住所述数据线，第二遮光条被配置为遮住所述两个子像素之间的公共电极，并且所述第二宽度小于所述第一宽度。
  12. 一种显示面板，包括如权利要求1至11中任一项所述的阵列基板。
  13. 一种显示装置，包括如权利要求12所述的显示面板。
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