WO2018126723A1 - 移位寄存器单元电路及其驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元电路及其驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2018126723A1
WO2018126723A1 PCT/CN2017/100367 CN2017100367W WO2018126723A1 WO 2018126723 A1 WO2018126723 A1 WO 2018126723A1 CN 2017100367 W CN2017100367 W CN 2017100367W WO 2018126723 A1 WO2018126723 A1 WO 2018126723A1
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Prior art keywords
node
terminal
potential
shift register
register unit
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Ceased
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PCT/CN2017/100367
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English (en)
French (fr)
Inventor
樊君
张洁
王继国
李付强
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US15/752,790 priority Critical patent/US10950322B2/en
Publication of WO2018126723A1 publication Critical patent/WO2018126723A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to generation of gate drive signals, and more particularly to a shift register unit circuit, a method of driving the shift register unit circuit, a gate drive circuit, and a display device.
  • a shift register comprising a plurality of cascaded shift register cell circuits can operate as a gate drive circuit to provide a gate drive signal for a pixel array in a display panel.
  • display devices eg, cell phones, tablets, etc.
  • a shift register unit circuit can only generate one gate drive signal to drive a row of pixels. Therefore, there is a need to provide a large number of shift register unit circuits for display panels, especially those having high resolution, thereby occupying a bezel area. This is not conducive to achieving a narrow border.
  • a shift register unit circuit comprising: a first node control circuit configured to supply an effective potential from a first scan level terminal to an responsive to an input pulse from an input terminal a node that supplies an inactive potential from the second scan level terminal to the first node in response to the reset pulse from the reset terminal being active, and inverting the potential from the first reference level terminal in response to the second node being at an active potential Supplying to the first node; the second node control circuit configured to supply an invalid potential from the first reference level terminal to the second node in response to the first node being at an active potential, and responsive The first node is at an inactive potential and the reset sustain signal from the reset sustain terminal is active to set the second node at an active potential; and N output circuits, each connected to a corresponding internal node, a corresponding clock terminal, and corresponding Output, the corresponding internal node is electrically connected to the first node, and N is greater than or equal to 2 .
  • Each of the N output circuits is configured to supply a clock signal from the respective clock terminal to the respective output in response to the respective internal node being at an active potential, in response to the second The node is at an effective potential and will be in the future An ineffective potential from the first reference level terminal is supplied to the respective output terminal, and a change in potential of the corresponding internal node is caused in response to a change in potential of the corresponding output terminal.
  • each of the N output circuits includes a first pass transistor having a gate coupled to the respective internal node, a first electrode coupled to the respective output, and a connection a second electrode to the corresponding clock terminal; a second transfer transistor having a gate connected to the second node, a first electrode connected to the first reference level terminal, and a connection to the corresponding output a second electrode of the terminal; and an output capacitor coupled between the respective internal node and the corresponding output.
  • the first node control circuit includes: a first transistor having a gate connected to the input, a first electrode connected to the first node, and a first scan a second terminal having a flat end; a second transistor having a gate connected to the reset terminal, a first electrode connected to the second scan level terminal, and a second electrode connected to the first node; and a third A transistor having a gate connected to the second node, a first electrode connected to the first node, and a second electrode connected to the first reference level terminal.
  • the second node control circuit includes: a fourth transistor having a gate connected to the first node, a first electrode connected to the first reference level terminal, and connected to the a second electrode of the second node; a fifth transistor having a gate connected to the reset sustaining terminal, a first electrode connected to the reset sustaining end, and a second electrode connected to the second node; and a first And a capacitor connected between the second node and the first reference level terminal.
  • the internal node of each of the N output circuits is directly connected to the first node.
  • the shift register unit circuit further includes N third transfer transistors each having a gate connected to a second reference level terminal for supplying an effective potential, connected to the first node a first electrode, and a second electrode connected to the internal node of a respective one of the N output circuits.
  • a method of driving a shift register unit circuit as described above includes supplying an effective potential from the first scan level terminal to the first node in response to an input pulse from the input being active such that each respective internal node is at an active potential; Corresponding internal node A clock signal from each respective clock terminal is supplied to each respective output terminal at an effective potential, wherein a change in potential of each respective internal node is caused in response to a change in potential of each respective output terminal; responsive to said reset a reset pulse of the terminal is enabled to supply an inactive potential from the second scan level terminal to the first node; in response to the first node being at an inactive potential and a reset sustain signal from the reset sustain terminal being active
  • the second node is set to be at an active potential; and the inactive potential from the first reference level terminal is supplied to each respective output in response to the second node being at an active potential.
  • the method further includes supplying N different clock signals having the same period and a duty cycle of 1/2 N to respective ones of the N output circuits.
  • the nth of the N clock signals is delayed by 1/2N cycles with respect to the n-1th of the N clock signals, n is an integer and 1 ⁇ n ⁇ N.
  • the method further includes supplying identical clock signals to respective ones of the N output circuits.
  • a gate driving circuit including a plurality of cascaded shift register unit circuits as described above.
  • An input of each of the plurality of shift register unit circuits is coupled to N outputs of an adjacent one of the shift register unit circuits, except for the first one of the plurality of shift register unit circuits The last one in the middle.
  • a reset terminal of each of the plurality of shift register unit circuits is connected to N outputs of adjacent ones of the shift register unit circuits First.
  • the 2k-1th of the plurality of shift register unit circuits are configured to receive respective clock signals from a first group of clock lines including N clock lines, k being a positive integer.
  • the 2kth of the plurality of shift register unit circuits are configured to receive respective clock signals from the second group of clock lines including N clock lines, the first and second sets of clock lines are supplied Each of the clock signals has the same period, and each of the clock signals supplied by the second group of clock lines is delayed by 1/N cycles with respect to a corresponding one of the clock signals supplied by the first group of clock lines.
  • a display device comprising the gate drive circuit as described above.
  • FIG. 1 is a block diagram of a shift register unit circuit in accordance with an embodiment of the present disclosure
  • FIG. 2 is a circuit diagram of an example circuit of the shift register unit circuit shown in FIG. 1;
  • FIG. 3 is a circuit diagram of another example circuit of the shift register unit circuit shown in FIG. 1;
  • FIG. 4 is a timing diagram of the example circuit shown in FIG. 3 in a first mode of operation
  • Figure 5 is a timing diagram of the example circuit shown in Figure 3 in a second mode of operation
  • FIG. 6 is a block diagram of a gate drive circuit in accordance with an embodiment of the present disclosure.
  • Figure 7 is a timing diagram of the gate driving circuit shown in Figure 6 in a first mode of operation
  • Figure 8 is a timing diagram of the gate driving circuit shown in Figure 6 in a second mode of operation
  • FIG. 9 is a block diagram of a display device in accordance with an embodiment of the present disclosure.
  • FIG. 1 is a block diagram of a shift register unit circuit 100 in accordance with an embodiment of the present disclosure.
  • the shift register unit circuit 100 includes a first node control circuit 110, a second node control circuit 120, and at least two output circuits. For convenience of illustration and description, only the first output circuit 130 and the second output circuit 140 are shown in FIG.
  • the first node control circuit 110 is configured to supply an effective potential from the first scan level terminal CN to the first node N1 in response to the input pulse from the input terminal IN being active.
  • the first node control circuit 110 is further configured to supply an inactive potential from the second scan level terminal CNB to the first node N1 in response to the reset pulse from the reset terminal RST being active.
  • the first node control circuit 110 is further configured to supply an inactive potential from the first reference level terminal VGL to the first node N1 in response to the second node N2 being at an active potential.
  • the second node control circuit 120 is configured to supply an inactive potential from the first reference level terminal VGL to the second node N2 in response to the first node N1 being at an active potential.
  • the second node control circuit 120 is further configured to set the second node N2 to an active potential in response to the first node N1 being at an inactive potential and the reset sustain signal from the reset sustain terminal CKB being active.
  • the first output circuit 130 is connected to the internal node ND1 (not shown in FIG. 1), the clock terminal CLK1, and the output terminal OUT1.
  • the internal node ND1 is electrically connected to the first node N1.
  • the first output circuit 130 is configured to supply a clock signal from the clock terminal CLK1 to the output terminal OUT1 in response to the internal node ND1 being at an active potential.
  • the first output circuit 130 is further configured to supply an inactive potential from the first reference level terminal VGL to the output terminal OUT1 in response to the second node N2 being at an active potential.
  • the first output circuit 130 is also configured to cause a change in the potential of the internal node ND1 in response to a change in the potential of the output terminal OUT1.
  • the second output circuit 140 is connected to the internal node ND2 (not shown in FIG. 1), the clock terminal CLK2, and the output terminal OUT2.
  • the second output circuit 140 is configured to operate similarly to the first output circuit 130, the description of which is omitted herein for the sake of brevity.
  • the term "effective potential” as used herein refers to the circuit components involved (eg, crystals) Tube) is the potential at which it is activated. In contrast, the term “invalid potential” refers to the potential at which the circuit components involved are disabled. For an n-type transistor, the effective potential is high and the inactive potential is low. For a p-type transistor, the effective potential is low and the inactive potential is high.
  • FIG. 2 is a circuit diagram of an example circuit 100A of shift register unit circuit 100 as shown in FIG. An example configuration of the shift register unit circuit 100 will be described below with reference to FIG.
  • the first node control circuit 110 includes a first transistor M1, a second transistor M2, and a third transistor M3.
  • the first transistor M1 has a gate connected to the input terminal IN, a first electrode connected to the first node N1, and a second electrode connected to the first scan level terminal CN.
  • the second transistor M2 has a gate connected to the reset terminal RST, a first electrode connected to the second scan level terminal CNB, and a second electrode connected to the first node N1.
  • the third transistor M3 has a gate connected to the second node N2, a first electrode connected to the first node N1, and a second electrode connected to the first reference level terminal VGL.
  • the second node control circuit 120 includes a fourth transistor M4, a fifth transistor M5, and a first capacitor C1.
  • the fourth transistor M4 has a gate connected to the first node N1, a first electrode connected to the first reference level terminal VGL, and a second electrode connected to the second node N2.
  • the fifth transistor M5 has a gate connected to the reset sustaining terminal CKB, a first electrode connected to the reset sustaining terminal CKB, and a second electrode connected to the second node N2.
  • the first capacitor C1 is connected between the second node N2 and the first reference level terminal VGL.
  • the first output circuit 130 includes its own first transfer transistor MT11, second transfer transistor MT12, and output capacitor OC1.
  • the first transfer transistor MT11 has a gate connected to the internal node ND1, a first electrode connected to the output terminal OUT1, and a second electrode connected to the clock terminal CLK1.
  • the second transfer transistor MT12 has a gate connected to the second node N2, a first electrode connected to the first reference level terminal VGL, and a second electrode connected to the output terminal OUT1.
  • An output capacitor OC1 is connected between the internal node ND1 and the output terminal OUT1.
  • the second output circuit 140 has the same configuration as the first output circuit 130. Specifically, as shown in FIG. 2, the first output circuit 130 includes its own first transfer transistor MT21, second transfer transistor MT22, and output capacitor OC2.
  • FIG. 3 is a circuit diagram of another example circuit 100B of shift register unit circuit 100 as shown in FIG. 1.
  • the configurations of the first node control circuit 110, the second node control circuit 120, the first output circuit 130, and the second output circuit 140 are the same as those described above with respect to FIG. 2, and are here for the sake of simplicity. Omitted.
  • the example circuit 100B differs from the example circuit 100A of FIG. 2 in that the internal nodes ND1 and ND2 of the first and second output circuits 130 and 140 are now connected to the first node N1 through respective third transfer transistors MT13 and MT23.
  • the third transfer transistor MT13 has a gate connected to a second reference level terminal VGH for supplying an effective potential, a first electrode connected to the first node N1, and a connection to the internal node ND1. Second electrode.
  • the third transfer transistor MT23 has a gate connected to a second reference level terminal VGH for supplying an effective potential, a first electrode connected to the first node N1, and a second electrode connected to the internal node ND2. .
  • the addition of the third transfer transistors MT13 and MT23 may be advantageous. Specifically, when the potentials of the output terminals OUT1 and OUT2 are changed from the inactive potential (low level in the example of FIG. 3) to the effective potential (in the example of FIG. 3, the high level), the internal nodes ND1 and ND2 The potential rises due to the bootstrap effect of the output capacitors OC1 and OC2, and the potential of the first node N1 also rises correspondingly due to the reason why the third transfer transistors MT13 and MT23 are initially turned on.
  • the third transfer transistors MT13 and MT23 are turned off, so that the rise of the potential of the first node N1 is limited. This can avoid a potential increase in leakage current flowing from the first node N1 through the second transistor M2 to the second scan level terminal CNB. Further, since the first node N1 and the internal nodes ND1 and ND2 are not turned on, the drop of the potential of the first node N1 due to the leakage current does not affect the potentials of the internal nodes ND1 and ND2, thereby ensuring the output terminal OUT1.
  • the gate drive signal outputted with OUT2 does not deteriorate. This is particularly advantageous in high temperature scenarios where leakage current is significantly increased.
  • FIG. 4 is a timing diagram of the example circuit 100B shown in FIG. 3 in a first mode of operation. The operation of the example circuit 100B of FIG. 3 is described below with reference to FIG. Hereinafter, a high level is indicated by 1 and a low level is indicated by 0. It is also assumed that the first scan level terminal CN and the second reference level terminal supply a high level voltage, and the second scan level terminal CNB and the first reference level terminal VGL supply a low level voltage.
  • the clock signals of the N clock terminals CLK1 and CLK2 supplied to the N output circuits have the same period and a duty of 1/2N. Ratio, and the nth clock signal is delayed by 1/2N cycles with respect to the n-1th clock signal, where n is an integer and 1 ⁇ n ⁇ N.
  • the first transistor M1 is turned on, and a high level voltage from the first scan level terminal CN is transferred to the first node N1 such that the first node N1 is set to an effective potential (high level in this example).
  • the turned-on third transfer transistors MT13 and MT23 transfer the effective potential of the first node N1 to the internal nodes ND1 and ND2, causing the first transfer transistors MT11 and MT21 to be turned on.
  • the invalid clock signals are transmitted to the output terminals OUT1 and OUT2 through the first transfer transistors MT11 and MT21, respectively, such that the output terminals OUT1 and OUT2 are at an inactive potential (low level in this example).
  • the output capacitors OC1 and OC2 keep the internal nodes ND1 and ND2 at an effective potential, so that the first transfer transistors MT11 and MT21 remain turned on.
  • the valid clock signal is transmitted from the clock terminal CLK1 to the output terminal OUT1 such that the output terminal OUT1 is at an effective potential.
  • the invalid clock signal is transmitted from the clock terminal CLK2 to the output terminal OUT2, so that the output terminal OUT2 is at an inactive potential. Due to the bootstrap effect of the output capacitor OC1, the potentials of the internal node ND1 and the first node N1 are further pulled high.
  • the third transfer transistor MT13 is turned off, so that the first node N1 and the internal node ND1 are not turned on.
  • the invalid clock signal is transmitted from the clock terminal CLK1 to the output terminal OUT1 through the turned-on first transfer transistor MT11, so that the output terminal OUT1 is at an inactive potential. Due to the bootstrap effect of the output capacitor OC1, the potential of the internal node ND1 is pulled low but still at the effective potential.
  • the valid clock signal is transmitted from the clock terminal CLK2 through the turned-on first transfer transistor MT21 to the output terminal OUT2, so that the output terminal OUT2 is at an effective potential. Due to the bootstrap effect of the output capacitor OC2, the potentials of the internal node ND2 and the first node N1 are further pulled high.
  • the third transfer transistor MT23 is turned off, so that the first node N1 and the internal node ND2 are not turned on.
  • Second crystal The body tube T2 is turned on, and the low level voltage from the second scan level terminal CNB is transmitted to the first node N1 such that the first node N1 is set to the inactive potential.
  • the fifth transistor M5 is turned on, and the effective potential from the reset sustain terminal CKB is transferred to the second node N2, so that the second transfer transistors MT12 and MT22 are turned on and the first capacitor C1 is charged.
  • the low level voltage from the first reference level terminal VGL is transferred to the output terminals OUT1 and OUT2 such that the output terminals OUT1 and OUT2 are at an inactive potential.
  • the reset sustain signal from the reset sustain terminal CKB periodically charges the first capacitor C1, thereby keeping the second node N2 at an effective potential.
  • the second transfer transistors MT12 and MT22 are kept turned on, and the inactive potential from the first reference level terminal VGL is transferred to the output terminals OUT1 and OUT2. Therefore, the output terminals OUT1 and OUT2 remain at an inactive potential.
  • FIG. 5 is a timing diagram of the example circuit 100B shown in FIG. 3 in the second mode of operation. The operation of the example circuit 100B of FIG. 3 is described below with reference to FIG.
  • the clock signals of the N clock terminals CLK1 and CLK2 supplied to the N output circuits are identical.
  • the first transistor M1 is turned on, and a high level voltage from the first scan level terminal CN is transferred to the first node N1 such that the first node N1 is set to an effective potential.
  • the turned-on third transfer transistors MT13 and MT23 transfer the effective potential of the first node N1 to the internal nodes ND1 and ND2, causing the first transfer transistors MT11 and MT21 to be turned on.
  • the invalid clock signals are transmitted to the output terminals OUT1 and OUT2 through the first transfer transistors MT11 and MT21, respectively, so that the output terminals OUT1 and OUT2 are at an inactive potential.
  • the output capacitors OC1 and OC2 keep the internal nodes ND1 and ND2 at an effective potential, so that the first transfer transistors MT11 and MT21 remain turned on.
  • the valid clock signal is transmitted from the clock terminal CLK1 to the output terminal OUT1 such that the output terminal OUT1 is at an effective potential.
  • the valid clock signal is transferred from the clock terminal CLK2 to the output terminal OUT2 such that the output terminal OUT2 is at an effective potential. Due to the bootstrap effect of the output capacitors OC1 and OC2, the potentials of the internal nodes ND1 and ND2 (and the first node N1) are further pulled high.
  • the third transfer transistors MT13 and MT23 are turned off, so that the first node N1 and the internal node ND1 and ND2 are not conductive.
  • the second transistor T2 is turned on, and the low level voltage from the second scan level terminal CNB is transferred to the first node N1 such that the first node N1 is set to an inactive potential.
  • the fifth transistor M5 is turned on, and the effective potential from the reset sustain terminal CKB is transferred to the second node N2, so that the second transfer transistors MT12 and MT22 are turned on and the first capacitor C1 is charged.
  • the low level voltage from the first reference level terminal VGL is transferred to the output terminals OUT1 and OUT2 such that the output terminals OUT1 and OUT2 are at an inactive potential.
  • the reset sustain signal from the reset sustain terminal CKB periodically charges the first capacitor C1, thereby keeping the second node N2 at an effective potential.
  • the second transfer transistors MT12 and MT22 are kept turned on, and the inactive potential from the first reference level terminal VGL is transferred to the output terminals OUT1 and OUT2. Therefore, the output terminals OUT1 and OUT2 remain at an inactive potential.
  • FIG. 6 is a block diagram of a gate drive circuit 600 in accordance with an embodiment of the present disclosure.
  • the gate driving circuit 600 includes a plurality of cascaded shift register unit circuits S1, S2, S3, S4, ..., S4K-1, S4K (K is a positive integer), and each shift register unit circuit It is illustrated as having two clock terminals CLK1 and CLK2 and two output terminals OUT1 and OUT2.
  • the shift register unit circuits S1, S2, S3, S4, ..., S4K-1, S4K work together to the gate lines G[1], G[2], G[3], G[4], G[5] , G[6], G[7], G[8]...G[8K-3], G[8K-2], G[8K-1], G[8K] provide respective gate drive signals .
  • Each of these shift register unit circuits may be the shift register unit circuit 100 as described above. More generally, each shift register unit circuit can be described as having N clock terminals and N outputs (N is an integer greater than or equal to 2).
  • Nth clock terminals of the 2k-1th (k is a positive integer) of the plurality of shift register unit circuits are configured to be from a first group of clock lines including N clock lines (in the example of FIG. 6, Clk3 and clk4) receive their respective clock signals.
  • the 2kth N clock terminals of the plurality of shift register unit circuits are configured to A respective clock signal is received from a second set of clock lines including N clock lines (in the example of FIG. 6, clk1 and clk2). Further, the reset sustaining terminals CKB of the 4k-3th, 4k-2th, 4k-1th, and 4kth shift register unit circuits receive the reset sustain signals from the reset sustain signal lines clkr1, clk11, clkr2, and clk12, respectively. .
  • the gate driving circuit 600 is configured to operate in a forward scan mode in which a start pulse STV is applied to the first shift register unit circuit S1.
  • the gate drive circuit 600 can also be configured to operate in a reverse scan mode in which a start pulse is applied to the last shift register cell circuit S4K.
  • the input terminal IN and the reset terminal RST of the shift register unit circuit are used interchangeably, and the first scan level terminal CN and the second scan level terminal CNB are used interchangeably.
  • the first scan level terminal CN supplies the active level voltage
  • the second scan level terminal CNB supplies the inactive level voltage
  • the input terminal IN and the reset terminal RST are normally used.
  • the first scan level terminal CN supplies an inactive level voltage
  • the second scan level terminal CNB supplies an active level voltage
  • the input terminal IN acts as a "reset terminal”
  • the reset terminal RST acts as an "input terminal”.
  • gate driving circuit 600 is illustrated as including an integer multiple of shift register unit circuits of 4, and each shift register unit circuit is illustrated as having two clock terminals and two outputs, the present disclosure Not limited to this.
  • FIG. 7 is a timing diagram of the gate driving circuit 600 shown in FIG. 6 in the first operation mode.
  • the first set of clock signals (clk3 and clk4) and the second set of clock signals (clk1 and clk2) have the same period, and each of the second set of clock signals is relative to the first set of clock signals.
  • the corresponding one is delayed by 1/N cycles.
  • clk1 is delayed by 1/N cycles with clk3, and clk2 is delayed by 1/N cycles with clk4.
  • the operation of the respective shift register unit circuits is the same as those described above with respect to FIG. 4, and is omitted herein for the sake of simplicity.
  • the resulting gate drive signal is shown in FIG.
  • the resulting gate drive signal is shown in FIG.
  • FIG. 5] For convenience of illustration, only the gate drive signals G[1], G[2], G[3], G[4], G generated by the first four shift register unit circuits are shown in FIG. 5], G[6], G[7], G[8].
  • FIG. 8 is a timing diagram of the gate driving circuit 600 shown in FIG. 6 in the second operation mode.
  • the N are identical in N clock signals.
  • the first set of clock signals (clk3 and clk4) and the second set of clock signals (clk1 and clk2) have the same period, and each of the second set of clock signals is relative to the first set of clock signals.
  • the corresponding one is delayed by 1/N cycles.
  • clk1 is delayed by 1/N cycles with clk3, and clk2 is delayed by 1/N cycles with clk4.
  • the operation of the respective shift register unit circuits is the same as those described above with respect to FIG. 5, and is omitted herein for the sake of simplicity.
  • the resulting gate drive signal is shown in FIG.
  • the resulting gate drive signal is shown in FIG.
  • only the gate drive signals G[1], G[2], G[3], G[4], G[[] generated by the first four shift register unit circuits are shown in FIG. 5], G[6], G[7], G[8].
  • the second mode of operation may be advantageous because the N gate drive signals generated by each shift register unit circuit are synchronized, as shown in Figure 8, which means that N rows of pixels can be scanned simultaneously (by The data signal is supplied) and thus provides a higher refresh rate. This can result in an improved display.
  • FIG. 9 is a block diagram of a display device 900 in accordance with an embodiment of the present disclosure.
  • the display device 900 includes a display panel 910, a timing controller 920, a gate driving circuit 930, and a data driving circuit 940.
  • the gate drive circuit 930 can be the gate drive circuit 600 described above with respect to FIG.
  • the display panel 910 is connected to the plurality of gate lines GL and the plurality of data lines DL.
  • the display panel 910 displays an image having a plurality of gradations based on the output image data RGBD'.
  • the gate line GL may extend in the first direction D1
  • the data line DL may extend in the second direction D2 crossing (eg, substantially perpendicular) to the first direction D1.
  • the display panel 910 may include a plurality of pixels (not shown) arranged in a matrix form. Each of the pixels may be electrically connected to a corresponding one of the gate lines GL and one corresponding one of the data lines DL.
  • Display panel 910 can be a liquid crystal display panel, an organic light emitting diode (OLED) display panel, or other suitable type of display panel.
  • OLED organic light emitting diode
  • the timing controller 920 controls the operations of the display panel 910, the gate drive circuit 930, and the data drive circuit 940.
  • the timing controller 920 receives input image data RGBD and an input control signal CONT from an external device (eg, a host).
  • the input image data RGBD may include a plurality of input pixel data for a plurality of pixels. Each of the input pixel data may include red gradation data R, green gradation data G, and blue gradation data B for a corresponding one of the plurality of pixels.
  • the input control signal CONT may include a main clock signal, a data enable signal, Vertical sync signal, horizontal sync signal, etc.
  • the timing controller 920 generates output image data RGBD', a first control signal CONT1, and a second control signal CONT2 based on the input image data RGBD and the input control signal CONT.
  • the gate drive circuit 930 receives the first control signal CONT1 from the timing controller 920.
  • the gate driving circuit 930 generates a plurality of gate signals for driving the gate lines GL based on the first control signal CONT1.
  • the gate driving circuit 930 can sequentially apply a plurality of gate signals to the gate lines GL.
  • the data driving circuit 940 receives the second control signal CONT2 and the output image data RGBD' from the timing controller 920.
  • the data driving circuit 940 generates a plurality of data voltages (e.g., analog data voltages) based on the second control signal CONT2 and the output image data RGBD' (e.g., digital image data).
  • the data driving circuit 940 can apply a plurality of data voltages to the data lines DL.
  • gate drive circuit 930 and/or data drive circuit 940 may be disposed (eg, directly mounted) on display panel 910, or may be by, for example, a Tape Carrier Package (TCP). Connected to the display panel 910. In some embodiments, gate drive circuit 930 and/or data drive circuit 940 can be integrated in display panel 910.
  • TCP Tape Carrier Package
  • Examples of display device 900 include, but are not limited to, cell phones, tablets, televisions, displays, notebook computers, digital photo frames, navigators.
  • each transistor is illustrated and described as an n-type transistor, a p-type transistor is possible.
  • the gate-on voltage has a low level
  • the gate-off voltage has a high level.
  • each transistor can be, for example, a thin film transistor that is typically fabricated such that their first and second electrodes are used interchangeably. Other embodiments are also contemplated.

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Abstract

一种移位寄存器单元电路（100），其包括第一节点控制电路（110）、第二节点控制电路（120）、以及多个输出电路（130，140）；多个输出电路（130，140）中每一个连接到相应的输出端，并且向该相应的输出端提供栅极驱动信号。还提供了一种驱动该移位寄存器单元电路（100）的方法、栅极驱动电路（930）和显示装置（900）。

Description

移位寄存器单元电路及其驱动方法、栅极驱动电路和显示装置 技术领域
本公开涉及栅极驱动信号的生成，尤其涉及一种移位寄存器单元电路、驱动该移位寄存器单元电路的方法、栅极驱动电路和显示装置。
背景技术
包括级联的多个移位寄存器单元电路的移位寄存器可以作为栅极驱动电路操作以便为显示面板中的像素阵列提供栅极驱动信号。随着显示设备(例如手机、平板电脑等)越来越轻薄化，存在对于越来越窄的屏幕边框的需求。利用传统的栅极驱动电路，一个移位寄存器单元电路只能生成一个栅极驱动信号来驱动一行像素。因此，需要为显示面板、尤其是对于具有高分辨率的那些显示面板提供大量的移位寄存器单元电路，从而占用边框面积。这不利于实现窄边框。
发明内容
提供一种可以缓解、减轻或消除上述问题中的一个或多个的移位寄存器单元电路将是有利的。
根据本公开的一个方面，提供了一种移位寄存器单元电路，包括：第一节点控制电路，被配置成响应于来自输入端的输入脉冲有效而将来自第一扫描电平端的有效电位供应到第一节点，响应于来自复位端的复位脉冲有效而将来自第二扫描电平端的无效电位供应到所述第一节点，并且响应于第二节点处于有效电位而将来自第一参考电平端的无效电位供应到所述第一节点；第二节点控制电路，被配置成响应于所述第一节点处于有效电位而将来自所述第一参考电平端的无效电位供应到所述第二节点，并且响应于所述第一节点处于无效电位且来自复位维持端的复位维持信号有效而将第二节点设定处于有效电位；以及N个输出电路，每一个连接到相应的内部节点、相应的时钟端和相应的输出端，所述相应的内部节点电连接到所述第一节点，N为大于或等于2的整数。所述N个输出电路中的每一个被配置成响应于所述相应的内部节点处于有效电位而将来自所述相应的时钟端的时钟信号供应到所述相应的输出端，响应于所述第二节点处于有效电位而将来 自所述第一参考电平端的无效电位供应到所述相应的输出端，并且响应于所述相应的输出端的电位的变化而引起所述相应的内部节点的电位的变化。
在一些实施例中，所述N个输出电路中的每一个包括：第一传送晶体管，具有连接到所述相应的内部节点的栅极、连接到所述相应的输出端的第一电极、以及连接到所述相应的时钟端的第二电极；第二传送晶体管，具有连接到所述第二节点的栅极、连接到所述第一参考电平端的第一电极、以及连接到所述相应的输出端的第二电极；以及输出电容器，连接在所述相应的内部节点与所述相应的输出端之间。
在一些实施例中，所述第一节点控制电路包括：第一晶体管，具有连接到所述输入端的栅极、连接到所述第一节点的第一电极、以及连接到所述第一扫描电平端的第二电极；第二晶体管，具有连接到所述复位端的栅极、连接到所述第二扫描电平端的第一电极、以及连接到所述第一节点的第二电极；以及第三晶体管，具有连接到所述第二节点的栅极、连接到所述第一节点的第一电极、以及连接到所述第一参考电平端的第二电极。
在一些实施例中，所述第二节点控制电路包括：第四晶体管，具有连接到所述第一节点的栅极、连接到所述第一参考电平端的第一电极、以及连接到所述第二节点的第二电极；第五晶体管，具有连接到所述复位维持端的栅极、连接到所述复位维持端的第一电极、以及连接到所述第二节点的第二电极；以及第一电容器，连接在所述第二节点与所述第一参考电平端之间。
在一些实施例中，所述N个输出电路中的每一个的所述内部节点直接连接到所述第一节点。
在一些实施例中，所述移位寄存器单元电路还包括N个第三传送晶体管，每一个具有连接到用于供应有效电位的第二参考电平端的栅极、连接到所述第一节点的第一电极、以及连接到所述N个输出电路中的相应一个的所述内部节点的第二电极。
根据本公开的另一方面，提供了一种驱动如上所述的移位寄存器单元电路的方法。所述方法包括：响应于来自所述输入端的输入脉冲有效而将来自所述第一扫描电平端的有效电位供应到所述第一节点，以使得各相应的内部节点处于有效电位；响应于各相应的内部节点处 于有效电位而将来自各相应的时钟端的时钟信号供应到各相应的输出端，其中响应于各相应的输出端的电位的变化而引起各相应的内部节点的电位的变化；响应于来自所述复位端的复位脉冲有效而将来自所述第二扫描电平端的无效电位供应到所述第一节点；响应于所述第一节点处于无效电位且来自所述复位维持端的复位维持信号有效而将所述第二节点设定处于有效电位；以及响应于所述第二节点处于有效电位而将来自所述第一参考电平端的无效电位供应到各相应的输出端。
在一些实施例中，所述方法还包括向所述N个输出电路的各相应时钟端分别供应具有相同周期和1/2N的占空比的N个不同的时钟信号。该N个时钟信号中的第n个相对于该N个时钟信号中的第n-1个被延迟1/2N个周期，n为整数且1＜n≤N。
在一些实施例中，所述方法还包括向所述N个输出电路的各相应时钟端供应完全相同的时钟信号。
根据本公开的又另一方面，提供了一种栅极驱动电路，包括多个级联的如上所述的移位寄存器单元电路。除所述多个移位寄存器单元电路中的第一个之外，所述多个移位寄存器单元电路中的每一个的输入端连接到相邻上一个移位寄存器单元电路的N个输出端中的最后一个。除所述多个移位寄存器单元电路中的最后一个之外，所述多个移位寄存器单元电路中每一个的复位端连接到相邻下一个移位寄存器单元电路的N个输出端中的第一个。所述多个移位寄存器单元电路中的第2k-1个的N个时钟端被配置成从包括N条时钟线的第一组时钟线接收各自的时钟信号，k为正整数。所述多个移位寄存器单元电路中的第2k个的N个时钟端被配置成从包括N条时钟线的第二组时钟线接收各自的时钟信号，第一和第二组时钟线供应的各时钟信号具有相同的周期，所述第二组时钟线供应的各时钟信号中的每一个相对于所述第一组时钟线供应的各时钟信号中的对应一个被延迟1/N个周期。
根据本公开的再另一方面，提供了一种显示装置，包括如上所述的栅极驱动电路。
根据在下文中所描述的实施例，本公开的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
图1是根据本公开实施例的移位寄存器单元电路的框图；
图2是如图1所示的移位寄存器单元电路的示例电路的电路图；
图3是如图1所示的移位寄存器单元电路的另一示例电路的电路图；
图4是如图3所示的示例电路在第一工作模式下的时序图；
图5是如图3所示的示例电路在第二工作模式下的时序图；
图6是根据本公开实施例的栅极驱动电路的框图；
图7是如图6所示的栅极驱动电路在第一工作模式下的时序图；
图8是如图6所示的栅极驱动电路在第二工作模式下的时序图；并且
图9是根据本公开实施例的显示装置的框图。
具体实施方式
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件和/或部分，但是这些元件、部件和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件或部分与另一个元件、部件或部分相区分。因此，下面讨论的第一元件、部件或部分可以被称为第二元件、部件或部分而不偏离本公开的教导。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件被称为“连接到另一个元件”或“耦合到另一个元件”时，其可以直接连接到另一个元件或直接耦合到另一个元件，或者可以存在中间元件。相反，当元件被称为“直接连接到另一个元件”或“直接耦合到另一个元件”时，没有中间元件存在。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。 将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
下面将结合附图详细描述本公开的实施例。
图1是根据本公开实施例的移位寄存器单元电路100的框图。参考图1，移位寄存器单元电路100包括第一节点控制电路110、第二节点控制电路120、和至少两个输出电路。为了图示和描述的方便，在图1中仅示出了第一输出电路130和第二输出电路140。
第一节点控制电路110被配置成响应于来自输入端IN的输入脉冲有效而将来自第一扫描电平端CN的有效电位供应到第一节点N1。第一节点控制电路110还被配置成响应于来自复位端RST的复位脉冲有效而将来自第二扫描电平端CNB的无效电位供应到所述第一节点N1。第一节点控制电路110还被配置成响应于第二节点N2处于有效电位而将来自第一参考电平端VGL的无效电位供应到所述第一节点N1。
第二节点控制电路120被配置成响应于所述第一节点N1处于有效电位而将来自所述第一参考电平端VGL的无效电位供应到所述第二节点N2。第二节点控制电路120还被配置成响应于所述第一节点N1处于无效电位且来自复位维持端CKB的复位维持信号有效而将第二节点N2设定处于有效电位。
第一输出电路130连接到内部节点ND1(图1中未示出)、时钟端CLK1和输出端OUT1。内部节点ND1电连接到所述第一节点N1。第一输出电路130被配置成响应于内部节点ND1处于有效电位而将来自所述时钟端CLK1的时钟信号供应到所述输出端OUT1。第一输出电路130还被配置成响应于所述第二节点N2处于有效电位而将来自所述第一参考电平端VGL的无效电位供应到所述输出端OUT1。第一输出电路130还被配置成响应于所述输出端OUT1的电位的变化而引起所述内部节点ND1的电位的变化。
第二输出电路140连接到内部节点ND2(图1中未示出)、时钟端CLK2和输出端OUT2。第二输出电路140被配置成与第一输出电路130类似地工作，其描述为了简单起见在此被省略。
如本文使用的术语“有效电位”是指所涉及的电路元件(例如，晶体 管)被启用所处的电位。相反，术语“无效电位”是指所涉及的电路元件被禁用所处的电位。对于n型晶体管而言，有效电位是高电位，并且无效电位是低电位。对于p型晶体管而言，有效电位是低电位，并且无效电位是高电位。
图2是如图1所示的移位寄存器单元电路100的示例电路100A的电路图。下面结合图2描述移位寄存器单元电路100的示例配置。
第一节点控制电路110包括第一晶体管M1、第二晶体管M2以及第三晶体管M3。第一晶体管M1具有连接到所述输入端IN的栅极、连接到所述第一节点N1的第一电极、以及连接到所述第一扫描电平端CN的第二电极。第二晶体管M2具有连接到所述复位端RST的栅极、连接到所述第二扫描电平端CNB的第一电极、以及连接到所述第一节点N1的第二电极。第三晶体管M3具有连接到所述第二节点N2的栅极、连接到所述第一节点N1的第一电极、以及连接到所述第一参考电平端VGL的第二电极。
第二节点控制电路120包括第四晶体管M4、第五晶体管M5以及第一电容器C1。第四晶体管M4具有连接到所述第一节点N1的栅极、连接到所述第一参考电平端VGL的第一电极、以及连接到所述第二节点N2的第二电极。第五晶体管M5具有连接到所述复位维持端CKB的栅极、连接到所述复位维持端CKB的第一电极、以及连接到所述第二节点N2的第二电极。第一电容器C1连接在所述第二节点N2与所述第一参考电平端VGL之间。
第一输出电路130包括其自己的第一传送晶体管MT11、第二传送晶体管MT12和输出电容器OC1。第一传送晶体管MT11具有连接到内部节点ND1的栅极、连接到输出端OUT1的第一电极、以及连接到时钟端CLK1的第二电极。第二传送晶体管MT12具有连接到所述第二节点N2的栅极、连接到所述第一参考电平端VGL的第一电极、以及连接到所述输出端OUT1的第二电极。输出电容器OC1连接在所述内部节点ND1与所述输出端OUT1之间。
第二输出电路140具有与第一输出电路130相同的配置。具体地，如图2所示，第一输出电路130包括其自己的第一传送晶体管MT21、第二传送晶体管MT22和输出电容器OC2。
在示例电路100A中，第一和第二输出电路130和140的内部节点 ND1和ND2直接连接到第一节点N1。因此，各内部节点ND1和ND2的电位在任何时候都等于第一节点N1的电位。
图3是如图1所示的移位寄存器单元电路100的另一示例电路100B的电路图。在示例电路100B中，第一节点控制电路110、第二节点控制电路120、第一输出电路130和第二输出电路140的配置与上面关于图2描述的那些相同，并且为了简单起见在此被省略。
示例电路100B与图2的示例电路100A的不同之处在于，第一和第二输出电路130和140的内部节点ND1和ND2现在通过各自的第三传送晶体管MT13和MT23连接到第一节点N1。如图3所示，第三传送晶体管MT13具有连接到用于供应有效电位的第二参考电平端VGH的栅极、连接到所述第一节点N1的第一电极、以及连接到内部节点ND1的第二电极。类似地，第三传送晶体管MT23具有连接到用于供应有效电位的第二参考电平端VGH的栅极、连接到所述第一节点N1的第一电极、以及连接到内部节点ND2的第二电极。
第三传送晶体管MT13和MT23的添加可以是有利的。具体地，当输出端OUT1和OUT2的电位从无效电位(在图3的示例中，低电平)被改变到有效电位(在图3的示例中，高电平)时，内部节点ND1和ND2的电位由于输出电容器OC1和OC2的自举效应而升高，并且第一节点N1的电位由于最初开启的第三传送晶体管MT13和MT23的原因也相应地升高。当第一节点N1的电位升高到等于第二参考电平端VGH所供应的有效电位时，第三传送晶体管MT13和MT23被关断，使得第一节点N1的电位的升高被限制。这可以避免从第一节点N1通过第二晶体管M2流到第二扫描电平端CNB的漏电流的潜在的增大。进一步地，由于使得第一节点N1与内部节点ND1和ND2不导通，由于漏电流所致的第一节点N1的电位的下降不会影响内部节点ND1和ND2的电位，从而保证从输出端OUT1和OUT2输出的栅极驱动信号不会恶化。这在其中漏电流显著增大的高温场景下尤为有利。
图4是如图3所示的示例电路100B在第一工作模式下的时序图。下面参考图4描述图3的示例电路100B的操作。在下文中，以1表示高电平，并且以0表示低电平。还假定：第一扫描电平端CN和第二参考电平端供应高电平电压，并且第二扫描电平端CNB和第一参考电平端VGL供应低电平电压。
如图4所示，在第一工作模式下，供应到N个输出电路(在该示例中，N＝2)的N个时钟端CLK1和CLK2的时钟信号具有相同周期和1/2N的占空比，并且第n个时钟信号相对于第n-1个时钟信号被延迟1/2N个周期，其中n为整数且1＜n≤N。
在阶段P1，IN＝1，CLK1＝0，CLK2＝0，CKB＝0，RST＝0。第一晶体管M1开启，并且将来自第一扫描电平端CN的高电平电压传送到第一节点N1，使得第一节点N1被设定处于有效电位(在该示例中，高电平)。开启的第三传送晶体管MT13和MT23将第一节点N1的有效电位传送到内部节点ND1和ND2，使得第一传送晶体管MT11和MT21开启。无效的时钟信号分别通过第一传送晶体管MT11和MT21被传送到输出端OUT1和OUT2，使得输出端OUT1和OUT2处于无效电位(在该示例中，低电平)。
在阶段P2，IN＝0，CLK1＝1，CLK2＝0，CKB＝0，RST＝0。输出电容器OC1和OC2保持内部节点ND1和ND2处于有效电位，使得第一传送晶体管MT11和MT21保持开启。有效的时钟信号从时钟端CLK1被传送到输出端OUT1，使得输出端OUT1处于有效电位。无效的时钟信号从时钟端CLK2被传送到输出端OUT2，使得输出端OUT2处于无效电位。由于输出电容器OC1的自举效应，内部节点ND1和第一节点N1的电位被进一步拉高。如上所述，当第一节点N1的电位升高到等于第三传送晶体管MT13的栅极电压VGH时，第三传送晶体管MT13被关断，使得第一节点N1和内部节点ND1不导通。
在阶段P3，IN＝0，CLK1＝0，CLK2＝1，CKB＝0，RST＝0。无效的时钟信号通过开启的第一传送晶体管MT11从时钟端CLK1被传送到输出端OUT1，使得输出端OUT1处于无效电位。由于输出电容器OC1的自举效应，内部节点ND1的电位被拉低但是仍然处于有效电位。有效的时钟信号从时钟端CLK2通过开启的第一传送晶体管MT21被传送到输出端OUT2，使得输出端OUT2处于有效电位。由于输出电容器OC2的自举效应，内部节点ND2和第一节点N1的电位被进一步拉高。如上所述，当第一节点N1的电位升高到等于第三传送晶体管MT23的栅极电压VGH时，第三传送晶体管MT23被关断，使得第一节点N1和内部节点ND2不导通。
在阶段P4，IN＝0，CLK1＝0，CLK2＝0，CKB＝1，RST＝1。第二晶 体管T2被开启，并且将来自第二扫描电平端CNB的低电平电压传送到第一节点N1，使得第一节点N1被设定处于无效电位。第五晶体管M5被开启，并且将来自复位维持端CKB的有效电位传送到第二节点N2，使得第二传送晶体管MT12和MT22被开启并且第一电容器C1被充电。来自第一参考电平端VGL的低电平电压被传送到输出端OUT1和OUT2，使得输出端OUT1和OUT2处于无效电位。
此后，来自复位维持端CKB的复位维持信号周期性地对第一电容器C1充电，从而保持第二节点N2处于有效电位。第二传送晶体管MT12和MT22被保持开启，并且将来自第一参考电平端VGL的无效电位传送到输出端OUT1和OUT2。因此，输出端OUT1和OUT2保持处于无效电位。
图5是如图3所示的示例电路100B在第二工作模式下的时序图。下面参考图5描述图3的示例电路100B的操作。
如图5所示，在第二工作模式下，供应到N个输出电路(在该示例中，N＝2)的N个时钟端CLK1和CLK2的时钟信号完全相同(identical)。
在阶段P1′，IN＝1，CLK1＝0，CLK2＝0，CKB＝0，RST＝0。第一晶体管M1开启，并且将来自第一扫描电平端CN的高电平电压传送到第一节点N1，使得第一节点N1被设定处于有效电位。开启的第三传送晶体管MT13和MT23将第一节点N1的有效电位传送到内部节点ND1和ND2，使得第一传送晶体管MT11和MT21开启。无效的时钟信号分别通过第一传送晶体管MT11和MT21被传送到输出端OUT1和OUT2，使得输出端OUT1和OUT2处于无效电位。
在阶段P2′，IN＝0，CLK1＝1，CLK2＝1，CKB＝0，RST＝0。输出电容器OC1和OC2保持内部节点ND1和ND2处于有效电位，使得第一传送晶体管MT11和MT21保持开启。有效的时钟信号从时钟端CLK1被传送到输出端OUT1，使得输出端OUT1处于有效电位。有效的时钟信号从时钟端CLK2被传送到输出端OUT2，使得输出端OUT2处于有效电位。由于输出电容器OC1和OC2的自举效应，内部节点ND1和ND2(以及第一节点N1)的电位被进一步拉高。当第一节点N1的电位升高到等于第三传送晶体管MT13和MT23的栅极电压VGH时，第三传送晶体管MT13和MT23被关断，使得第一节点N1和内部节点 ND1和ND2不导通。
在阶段P3′，IN＝0，CLK1＝0，CLK2＝0，CKB＝1，RST＝1。第二晶体管T2被开启，并且将来自第二扫描电平端CNB的低电平电压传送到第一节点N1，使得第一节点N1被设定处于无效电位。第五晶体管M5被开启，并且将来自复位维持端CKB的有效电位传送到第二节点N2，使得第二传送晶体管MT12和MT22被开启并且第一电容器C1被充电。来自第一参考电平端VGL的低电平电压被传送到输出端OUT1和OUT2，使得输出端OUT1和OUT2处于无效电位。
此后，来自复位维持端CKB的复位维持信号周期性地对第一电容器C1充电，从而保持第二节点N2处于有效电位。第二传送晶体管MT12和MT22被保持开启，并且将来自第一参考电平端VGL的无效电位传送到输出端OUT1和OUT2。因此，输出端OUT1和OUT2保持处于无效电位。
图6是根据本公开实施例的栅极驱动电路600的框图。参考图6，栅极驱动电路600包括多个级联的移位寄存器单元电路S1、S2、S3、S4...S4K-1、S4K(K为正整数)，并且每个移位寄存器单元电路被图示为具有两个时钟端CLK1和CLK2和两个输出端OUT1和OUT2。移位寄存器单元电路S1、S2、S3、S4...S4K-1、S4K一起工作以便向栅线G[1]、G[2]、G[3]、G[4]、G[5]、G[6]、G[7]、G[8]...G[8K-3]、G[8K-2]、G[8K-1]、G[8K]提供各自的栅极驱动信号。这些移位寄存器单元电路中的每一个可以是如上所述的移位寄存器单元电路100。更一般地，每个移位寄存器单元电路可以被描述为具有N个时钟端和N个输出端(N为大于或等于2的整数)。
如图6所示，除移位寄存器单元电路S1之外，所述多个移位寄存器单元电路中的每一个的输入端IN连接到相邻上一个移位寄存器单元电路的N个输出端中的最后一个(在图6的示例中，OUT2)。除移位寄存器单元电路S4K之外，所述多个移位寄存器单元电路中每一个的复位端RST连接到相邻下一个移位寄存器单元电路的N个输出端中的第一个(在图6的示例中，OUT1)。所述多个移位寄存器单元电路中的第2k-1个(k为正整数)的N个时钟端被配置成从包括N条时钟线的第一组时钟线(在图6的示例中，clk3和clk4)接收各自的时钟信号。所述多个移位寄存器单元电路中的第2k个的N个时钟端被配置成 从包括N条时钟线的第二组时钟线(在图6的示例中，clk1和clk2)接收各自的时钟信号。另外，第4k-3个、第4k-2个、第4k-1个和第4k个移位寄存器单元电路的复位维持端CKB分别从复位维持信号线clkr1、clkl1、clkr2和clkl2接收复位维持信号。
在图6的示例中，栅极驱动电路600被配置为工作在正向扫描模式下，其中起始脉冲STV被施加到第一个移位寄存器单元电路S1。虽然未图示，栅极驱动电路600也可以被配置为工作在反向扫描模式下，其中起始脉冲被施加到最后一个移位寄存器单元电路S4K。将理解的是，取决于扫描方向，移位寄存器单元电路的输入端IN和复位端RST可互换地使用，并且第一扫描电平端CN和第二扫描电平端CNB可互换地使用。在正向扫描模式下，第一扫描电平端CN供应有效电平电压，第二扫描电平端CNB供应无效电平电压，并且输入端IN和复位端RST被正常地使用。在反向扫描模式下，第一扫描电平端CN供应无效电平电压，并且第二扫描电平端CNB供应有效电平电压。在这种情况下，输入端IN充当“复位端”，并且复位端RST充当“输入端”。
另外，虽然栅极驱动电路600被图示为包括4的整数倍个移位寄存器单元电路，并且每个移位寄存器单元电路被图示为具有两个时钟端和两个输出端，但是本公开不限于此。
图7是如图6所示的栅极驱动电路600在第一工作模式下的时序图。在第一工作模式下，施加到每一个移位寄存器单元电路的N个时钟端接收的N个时钟信号具有1/2N的占空比(在该示例中，N＝2)，并且该N个时钟信号中的第n个(例如，clk4或clk2)相对于该N个时钟信号中的第n-1个(例如，clk3或clk1)被延迟1/2N个周期(n为整数且1＜n≤N)。
如图7所示，第一组时钟信号(clk3和clk4)和第二组时钟信号(clk1和clk2)具有相同的周期，并且第二组时钟信号中的每一个相对于第一组时钟信号中的对应一个被延迟1/N个周期。例如，clk1相对于clk3被延迟1/N个周期，并且clk2相对于clk4被延迟1/N个周期。各个移位寄存器单元电路的操作与上面关于图4描述的那些相同，并且为了简单起见在此被省略。结果得到的栅极驱动信号如图7所示。为了图示的方便，在图7中仅示出了前四个移位寄存器单元电路生成的栅极驱动信号G[1]、G[2]、G[3]、G[4]、G[5]、G[6]、G[7]、G[8]。
图8是如图6所示的栅极驱动电路600在第二工作模式下的时序图。在第二工作模式下，施加到每一个移位寄存器单元电路的N个(在该示例中，N＝2)时钟端接收的N个时钟信号完全相同。
如图8所示，第一组时钟信号(clk3和clk4)和第二组时钟信号(clk1和clk2)具有相同的周期，并且第二组时钟信号中的每一个相对于第一组时钟信号中的对应一个被延迟1/N个周期。例如，clk1相对于clk3被延迟1/N个周期，并且clk2相对于clk4被延迟1/N个周期。各个移位寄存器单元电路的操作与上面关于图5描述的那些相同，并且为了简单起见在此被省略。结果得到的栅极驱动信号如图8所示。为了图示的方便，在图8中仅示出了前四个移位寄存器单元电路生成的栅极驱动信号G[1]、G[2]、G[3]、G[4]、G[5]、G[6]、G[7]、G[8]。
第二工作模式可以是有利的，因为每个移位寄存器单元电路生成的N个栅极驱动信号是同步的，如图8中所示的，这意味着N行像素可以被同时扫描到(被供应数据信号)，并且因此提供更高的刷新速率。这可以导致改进的显示效果。
图9是根据本公开实施例的显示装置900的框图。参考图9，显示装置900包括显示面板910、时序控制器920、栅极驱动电路930和数据驱动电路940。栅极驱动电路930可以是上面关于图6所述的栅极驱动电路600。
显示面板910连接至多个栅极线GL和多个数据线DL。显示面板910基于输出图像数据RGBD’显示具有多个灰度的图像。栅极线GL可在第一方向D1延伸，并且数据线DL可在与第一方向D1交叉(例如，基本垂直)的第二方向D2延伸。显示面板910可包括以矩阵形式排列的多个像素(未示出)。每个像素可电连接至栅极线GL的对应一个栅极线和数据线DL的对应一个数据线。显示面板910可以是液晶显示面板、有机发光二极管(OLED)显示面板或其他合适类型的显示面板。
时序控制器920控制显示面板910、栅极驱动电路930和数据驱动电路940的操作。时序控制器920从外部设备(例如，主机)接收输入图像数据RGBD和输入控制信号CONT。输入图像数据RGBD可包括用于多个像素的多个输入像素数据。每个输入像素数据可包括用于多个像素中的对应一个的红色灰度数据R、绿色灰度数据G和蓝色灰度数据B。输入控制信号CONT可包括主时钟信号、数据使能信号、 垂直同步信号、水平同步信号等。时序控制器920基于输入图像数据RGBD和输入控制信号CONT生成输出图像数据RGBD’、第一控制信号CONT1和第二控制信号CONT2。
栅极驱动电路930从时序控制器920接收第一控制信号CONT1。栅极驱动电路930基于第一控制信号CONT1生成用于驱动栅极线GL的多个栅极信号。栅极驱动电路930可顺序地将多个栅极信号施加至栅极线GL。
数据驱动电路940从时序控制器920接收第二控制信号CONT2和输出图像数据RGBD’。数据驱动电路940基于第二控制信号CONT2和输出图像数据RGBD’(例如，数字图像数据)生成多个数据电压(例如，模拟数据电压)。数据驱动电路940可将多个数据电压施加至数据线DL。
在一些示例性实施例中，栅极驱动电路930和/或数据驱动电路940可被设置(例如，直接安装)在显示面板910上，或者可以借助例如带式载体封装(Tape Carrier Package，TCP)连接至显示面板910。在一些实施例中，栅极驱动电路930和/或数据驱动电路940可被集成在显示面板910中。
显示装置900的示例包括但不限于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪。
将理解的是，在各实施例中，虽然各晶体管被图示和描述为n型晶体管，但是p型晶体管是可能的。在p型晶体管的情况下，栅极开启电压具有低电平，并且栅极关闭电压具有高电平。在各实施例中，各晶体管可以例如是薄膜晶体管，其典型地被制作使得它们的第一电极和第二电极可互换地使用。还设想了其他实施例。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (13)

  1. 一种移位寄存器单元电路，包括：
    第一节点控制电路，被配置成响应于来自输入端的输入脉冲有效而将来自第一扫描电平端的有效电位供应到第一节点，响应于来自复位端的复位脉冲有效而将来自第二扫描电平端的无效电位供应到所述第一节点，并且响应于第二节点处于有效电位而将来自第一参考电平端的无效电位供应到所述第一节点；
    第二节点控制电路，被配置成响应于所述第一节点处于有效电位而将来自所述第一参考电平端的无效电位供应到所述第二节点，并且响应于所述第一节点处于无效电位且来自复位维持端的复位维持信号有效而将第二节点设定处于有效电位；以及
    N个输出电路，每一个连接到相应的内部节点、相应的时钟端和相应的输出端，所述相应的内部节点电连接到所述第一节点，N为大于或等于2的整数，
    其中所述N个输出电路中的每一个被配置成响应于所述相应的内部节点处于有效电位而将来自所述相应的时钟端的时钟信号供应到所述相应的输出端，响应于所述第二节点处于有效电位而将来自所述第一参考电平端的无效电位供应到所述相应的输出端，并且响应于所述相应的输出端的电位的变化而引起所述相应的内部节点的电位的变化。
  2. 如权利要求1所述的移位寄存器单元电路，其中所述N个输出电路中的每一个包括：
    第一传送晶体管，具有连接到所述相应的内部节点的栅极、连接到所述相应的输出端的第一电极、以及连接到所述相应的时钟端的第二电极；
    第二传送晶体管，具有连接到所述第二节点的栅极、连接到所述第一参考电平端的第一电极、以及连接到所述相应的输出端的第二电极；以及
    输出电容器，连接在所述相应的内部节点与所述相应的输出端之间。
  3. 如权利要求1所述的移位寄存器单元电路，其中所述第一节点控制电路包括：
    第一晶体管，具有连接到所述输入端的栅极、连接到所述第一节 点的第一电极、以及连接到所述第一扫描电平端的第二电极；
    第二晶体管，具有连接到所述复位端的栅极、连接到所述第二扫描电平端的第一电极、以及连接到所述第一节点的第二电极；以及
    第三晶体管，具有连接到所述第二节点的栅极、连接到所述第一节点的第一电极、以及连接到所述第一参考电平端的第二电极。
  4. 如权利要求1所述的移位寄存器单元电路，其中所述第二节点控制电路包括：
    第四晶体管，具有连接到所述第一节点的栅极、连接到所述第一参考电平端的第一电极、以及连接到所述第二节点的第二电极；
    第五晶体管，具有连接到所述复位维持端的栅极、连接到所述复位维持端的第一电极、以及连接到所述第二节点的第二电极；以及
    第一电容器，连接在所述第二节点与所述第一参考电平端之间。
  5. 如权利要求1所述的移位寄存器单元电路，其中所述N个输出电路中的每一个的所述内部节点直接连接到所述第一节点。
  6. 如权利要求1所述的移位寄存器单元电路，还包括N个第三传送晶体管，每一个具有连接到用于供应有效电位的第二参考电平端的栅极、连接到所述第一节点的第一电极、以及连接到所述N个输出电路中的相应一个的所述内部节点的第二电极。
  7. 一种驱动如权利要求1至6中任一项所述的移位寄存器单元电路的方法，所述方法包括：
    响应于来自所述输入端的输入脉冲有效而将来自所述第一扫描电平端的有效电位供应到所述第一节点，以使得各相应的内部节点处于有效电位；
    响应于各相应的内部节点处于有效电位而将来自各相应的时钟端的时钟信号供应到各相应的输出端，其中响应于各相应的输出端的电位的变化而引起各相应的内部节点的电位的变化；
    响应于来自所述复位端的复位脉冲有效而将来自所述第二扫描电平端的无效电位供应到所述第一节点；
    响应于所述第一节点处于无效电位且来自所述复位维持端的复位维持信号有效而将所述第二节点设定处于有效电位；以及
    响应于所述第二节点处于有效电位而将来自所述第一参考电平端的无效电位供应到各相应的输出端。
  8. 如权利要求7所述的方法，还包括向所述N个输出电路的各相应时钟端分别供应具有相同周期和1/2N的占空比的N个不同的时钟信号，其中该N个时钟信号中的第n个相对于该N个时钟信号中的第n-1个被延迟1/2N个周期，n为整数且1＜n≤N。
  9. 如权利要求7所述的方法，还包括向所述N个输出电路的各相应时钟端供应完全相同的时钟信号。
  10. 一种栅极驱动电路，包括多个级联的如权利要求1至6中任一项所述的移位寄存器单元电路，其中
    除所述多个移位寄存器单元电路中的第一个之外，所述多个移位寄存器单元电路中的每一个的输入端连接到相邻上一个移位寄存器单元电路的N个输出端中的最后一个；
    除所述多个移位寄存器单元电路中的最后一个之外，所述多个移位寄存器单元电路中每一个的复位端连接到相邻下一个移位寄存器单元电路的N个输出端中的第一个；
    所述多个移位寄存器单元电路中的第2k-1个的N个时钟端被配置成从包括N条时钟线的第一组时钟线接收各自的时钟信号，k为正整数；并且
    所述多个移位寄存器单元电路中的第2k个的N个时钟端被配置成从包括N条时钟线的第二组时钟线接收各自的时钟信号，第一和第二组时钟线供应的各时钟信号具有相同的周期，所述第二组时钟线供应的各时钟信号中的每一个相对于所述第一组时钟线供应的各时钟信号中的对应一个被延迟1/N个周期。
  11. 如权利要求10所述的栅极驱动电路，其中所述栅极驱动电路被配置有第一工作模式，其中所述多个移位寄存器单元电路中的每一个的N个时钟端接收的N个时钟信号具有1/2N的占空比并且该N个时钟信号中的第n个相对于该N个时钟信号中的第n-1个被延迟1/2N个周期，n为整数且1＜n≤N。
  12. 如权利要求10所述的栅极驱动电路，其中所述栅极驱动电路被配置有第二工作模式下，其中所述多个移位寄存器单元电路中的每一个的N个时钟端接收的N个时钟信号完全相同。
  13. 一种显示装置，包括如权利要求10至12中任一项所述的栅极驱动电路。
PCT/CN2017/100367 2017-01-09 2017-09-04 移位寄存器单元电路及其驱动方法、栅极驱动电路和显示装置 Ceased WO2018126723A1 (zh)

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