WO2018126706A1 - 频率可调的频率源和相关的系统、方法和电子设备 - Google Patents

频率可调的频率源和相关的系统、方法和电子设备 Download PDF

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Publication number
WO2018126706A1
WO2018126706A1 PCT/CN2017/098825 CN2017098825W WO2018126706A1 WO 2018126706 A1 WO2018126706 A1 WO 2018126706A1 CN 2017098825 W CN2017098825 W CN 2017098825W WO 2018126706 A1 WO2018126706 A1 WO 2018126706A1
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frequency
signal
taf
dps
input
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PCT/CN2017/098825
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English (en)
French (fr)
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修黎明
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京东方科技集团股份有限公司
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Priority to US15/751,615 priority Critical patent/US10558238B2/en
Priority to EP17838113.3A priority patent/EP3567726A4/en
Publication of WO2018126706A1 publication Critical patent/WO2018126706A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop

Definitions

  • the present disclosure relates to a frequency adjustable frequency source for identifying the frequency of an input voltage signal.
  • the present disclosure also relates to a system including the frequency source, a method of identifying a frequency of a voltage signal, and an electronic device including the frequency source.
  • Capacitive sensing is an important technology for modern consumer electronics, devices, home control and the Internet of Things (IoT). Among them, the change in capacitance value is used for proximity/posture detection, material analysis, liquid level measurement, and the like.
  • Temperature sensing is also important in modern electronics. There are two widely used temperature sensing methods, thermistors and resistive temperature detectors (RTDs). They measure temperature (resistance sensing) by correlating the resistance of the sensing element with temperature.
  • the time for RC charging and discharging is an object of interest.
  • the change is first converted (by an analog-to-digital converter ADC) to a voltage level or (by a time-to-digital converter TDC) to a time, followed by Is converted to a numeric value.
  • the time for RC charge and discharge is an object of interest.
  • This duration can be measured directly with a clock signal of known frequency.
  • the observed capacitance/resistance may be part of a relaxation oscillator (also referred to as an unsteady oscillating resonator) whose resonant frequency is related to R and C.
  • the frequency of the relaxation oscillator is measured with a frequency-fixed frequency source to measure R and C variations.
  • a frequency adjustable frequency source In an embodiment of the present disclosure, a frequency adjustable frequency source, a system including the frequency source, a method of identifying a frequency of a voltage signal, and an electronic device including the frequency source are provided.
  • a frequency adjustable frequency source having an input for receiving an input voltage signal, the frequency source identifying a frequency of the input voltage signal.
  • the input voltage signal of the frequency source is received from the resistive and capacitive sensing device, wherein the resistive and capacitive sensing device converts the resistance value and the capacitance value into a voltage signal, the voltage The signal is input to the frequency source.
  • the frequency source comprises a time averaged frequency direct cycle synthesis TAF-DPS clock generator, wherein the TAF-DPS clock generator has:
  • An output terminal for outputting a clock signal wherein the clock signal is a pulse having a first period T A and a pulse having a second period T B is interleaved, wherein the first period T A and the second period T B
  • the probability of occurrence is controlled by the value of r
  • the control word has a one-to-one correspondence with the measured capacitance value or the resistance value of the resistive and capacitive sensing device, thereby obtaining the capacitance value and The change in resistance value.
  • the TAF-DPS clock generator can generate almost any frequency when the resources used are large enough, so the sensing of the frequency, and thus the sensing of changes in resistance and capacitance values, can be more sensitive.
  • the base time unit ⁇ is generated by a multi-stage voltage controlled oscillator, wherein the multi-stage voltage controlled oscillator is locked to the reference frequency by the phase locked loop, thereby the frequency of the multi-stage voltage controlled oscillator f vco is a known value, and the multi-stage voltage controlled oscillator outputs K phase uniform signals, where K is an integer greater than 1, so that the base time unit ⁇ can be calculated as:
  • T VCO represents the period of the multi-stage voltage controlled oscillator.
  • I and r are input by a user, wherein TAF-DPS
  • the accuracy of the frequency of the clock generator is related to the number of bits assigned to r.
  • the frequency source includes a TAF-DPS vernier caliper
  • the TAF-DPS vernier caliper includes:
  • the first TAF-DPS clock generator is used as a slow TAF-DPS clock generator, and the first TAF-DPS clock generator has a second input for receiving the slow control word Fslow , the first TAF-DPS clock generator A third input terminal is further configured to receive the input voltage signal, that is, a start signal of a pulse period of the measured voltage signal, and the first TAF-DPS clock generator outputs a slow clock signal at the output end,
  • the second TAF-DPS clock generator is used as a fast TAF-DPS clock generator, and the second TAF-DPS clock generator has a second input for receiving the fast control word F fast , the second TAF-DPS clock generator And a third input end, configured to receive the input voltage signal, that is, the end signal of the pulse period of the measured voltage signal, and the second TAF-DPS clock generator outputs a fast clock signal at the output end,
  • phase detector for detecting a coincidence point of the slow clock signal and the fast clock signal, wherein the slow clock signal is aligned with the edge of the fast clock signal at the coincidence point, wherein the phase detector has a first input for receiving the slow clock a signal, a second input for receiving a fast clock signal, and an output for outputting a reset signal when a coincident point is detected,
  • a first digital counter having a clock input for receiving a slow clock signal, a reset input for receiving a reset signal from the phase detector, and an output for outputting a first digital counter storage upon receiving the reset signal a slow clock signal, wherein the number of cycles of the output slow clock signal is stored as a first digital value, and after outputting the stored slow clock signal, the first digital counter is reset.
  • a second digital counter having a clock input for receiving a fast clock signal, a reset input for receiving a reset signal from the phase detector, and an output for outputting a second digital counter storage upon receiving the reset signal a fast clock signal, wherein the number of cycles of the output fast clock signal is stored as a second digital value, and after outputting the stored fast clock signal, the second digital counter is reset.
  • a calculating module configured to calculate a time of flight (TOF) between the start signal and the end signal according to the first digital value and the second digital value, thereby obtaining a frequency change of the input voltage signal, that is, the measured voltage signal.
  • TOF time of flight
  • the capacitance value and the resistance value change can be obtained.
  • the first TAF-DPS clock generator includes:
  • a first digitally controlled oscillator for generating a slow base time unit ⁇ slow ,
  • a first TAF-DPS frequency synthesizer that outputs a slow TAF clock signal based on F slow and a slow base time unit ⁇ slow from the first digitally controlled oscillator.
  • the second TAF-DPS clock generator includes:
  • a second digitally controlled oscillator for generating a fast base time unit ⁇ fast
  • a second TAF-DPS frequency synthesizer that outputs a fast TAF clock signal according to the fast control word F fast and the fast base time unit ⁇ fast from the second digitally controlled oscillator
  • 1 ⁇ PLL phase-locked loop with a division ratio of 1
  • PLL phase-locked loop with a division ratio of 1
  • the frequency source includes a frequency-locked loop constructed based on a TAF-DPS clock generator, wherein the input voltage signal, such as an output voltage signal of a resistive and capacitive sensing device, is input to the The frequency-locked loop is used as a reference signal, the reference signal is compared with the clock signal generated by the TAF-DPS clock generator in terms of frequency, and the control word F of the TAF-DPS clock generator is iteratively adjusted according to the comparison result until the generated The frequency of the clock signal coincides with the frequency of the reference signal, so that the frequency of the reference signal is obtained from the control word F, and the frequency variation of the input voltage signal is obtained.
  • the capacitance value and the resistance value change of the resistive and capacitive sensing device can be obtained from the frequency change.
  • the frequency locked loop includes:
  • a frequency detector is coupled to the low pass filter downstream of the frequency detector and to a TAF-DPS digitally controlled oscillator coupled downstream of the low pass filter.
  • the frequency detector is configured to detect a difference between a frequency f r of the reference signal input to the frequency detector and a frequency f o of the output signal of the frequency-locked loop, and Outputting a difference variable;
  • the low pass filter is configured to low pass filter the difference variable to remove the high frequency component, generating a control variable for the downstream TAF-DPS digitally controlled oscillator, wherein the control variable includes the control word F;
  • TAF-DPS digital controlled oscillator is configured to generate an output signal of a frequency f o in accordance with the control variable, wherein the output signal is transmitted to a frequency detector.
  • the number of rising edges of the reference signal detected during each period of the output signal whose frequency f o is known to be output from the frequency-locked loop is determined. Wherein the frequency f r of the reference signal is unknown,
  • the half cycle includes a rising edge and a falling edge of the output signal, the rising edge and the falling edge in a half cycle of the output signal
  • the frequency locked loop further includes a frequency divider connected between the TAF-DPS digitally controlled oscillator and the frequency detector.
  • the frequency detector is configured to detect a difference between a frequency f r of the reference signal input to the frequency detector and a signal frequency f o ' from the frequency divider, and output the difference a variable;
  • the low pass filter is configured to low pass filter the difference variable to remove the high frequency component, and generate a control variable for the downstream TAF-DPS digitally controlled oscillator, wherein the control variable includes the control word F;
  • TAF- DPS digital controlled oscillator is configured to generate a frequency f o of the output signal of the control variable;
  • divider is configured by a factor of 1 / N dividing the output signal to generate a frequency f o 'signal and The signal of frequency f o ' is transmitted to the frequency detector, where N is an integer greater than or equal to one.
  • the number of rising edges of the reference signal detected during each period of the frequency f o ' from the frequency divider is determined, wherein the reference signal The frequency f r is unknown,
  • the half cycle includes a rising edge and a falling edge of the output signal, the rising edge and the falling edge in a half cycle of the output signal
  • the difference variable and the control variable are both digital values.
  • the present disclosure also provides a system for detecting changes in resistance and capacitance values of resistive and capacitive sensing devices.
  • the system includes a frequency adjustable frequency according to the present disclosure a source, resistive and capacitive sensing device and a comparison unit, wherein the resistive and capacitive sensing device converts the resistance value and the capacitance value into a voltage signal, the frequency source identifying the frequency of the voltage signal, wherein the comparison unit will identify The frequency of the output is compared with the frequency of the voltage signal of the resistive and capacitive sensing device previously stored, and in the case where the frequency of the voltage signal is determined to be changed, the resistance value of the resistive and capacitive sensing device is determined. The capacitance value has changed.
  • the resistive and capacitive sensing device is a relaxation oscillator, wherein the relaxation oscillator comprises an operational amplifier and a sensing capacitor connected to one input of the operational amplifier, wherein the operational amplifier output A voltage signal having a frequency associated with a resistance value and a capacitance value in the relaxation oscillator.
  • the present disclosure also provides a method of identifying a frequency of a voltage signal, wherein a voltage signal is input to a frequency-adjustable frequency source according to the present disclosure, the frequency source identifying the input voltage signal frequency.
  • the method of identifying the frequency of the voltage signal includes the following steps:
  • an output signal of the resistive and capacitive sensing device is input to the frequency-locked loop constructed based on the TAF-DPS clock generator as a reference signal
  • control word F of the TAF-DPS clock generator is iteratively adjusted according to the comparison result until the frequency of the generated clock signal coincides with the frequency of the reference signal, thereby obtaining the reference signal according to the control word F Frequency, and
  • the capacitance value and the resistance value change of the resistive and capacitive sensing device are obtained.
  • the frequency locked loop includes:
  • a frequency detector connected downstream of the frequency detector, and a TAF-DPS DCO connected downstream of the low pass filter.
  • the difference between the frequency f r of the reference signal input to the frequency detector and the frequency f o of the output signal of the frequency-locked loop is detected by the frequency detector, and the difference is output variable
  • a control variable for the downstream TAF-DPS digitally controlled oscillator is generated, and the control variable includes the control word F,
  • the output signal is transmitted to a frequency detector.
  • the frequency detector in the frequency detector, determining a number of rising edges of the reference signal detected in each period of the output signal of the frequency-locked loop whose frequency f o is known, wherein The frequency f r of the reference signal is unknown,
  • the half cycle includes a rising edge and a falling edge of the output signal, the rising edge and the falling edge in a half cycle of the output signal
  • the frequency locked loop further includes a frequency divider connected between the TAF-DPS digitally controlled oscillator and the frequency detector.
  • the difference between the frequency f r of the reference signal input to the frequency detector and the signal frequency f o ' from the frequency divider is detected by the frequency detector, and the difference variable is output,
  • a control variable for the downstream TAF-DPS digitally controlled oscillator is generated, and the control variable includes the control word F,
  • the output signal is divided by a frequency divider by a factor of 1/N to obtain a signal of frequency f o ', and
  • the signal of frequency f o ' is transmitted to the frequency detector, where N is an integer greater than or equal to one.
  • the number of rising edges of the reference signal detected during each period of the frequency f o ' from the frequency divider is determined, wherein the reference signal The frequency f r is unknown,
  • the half cycle of the output signal includes a rising edge and a falling edge, the rising edge and the falling edge in a half cycle of the output signal
  • the difference variable and the control variable are both digital values.
  • the present disclosure also provides an electronic device including a frequency source according to the present disclosure.
  • the frequency programmability of the TAF-DPS is used according to the present disclosure to provide a frequency-variable frequency source for detecting resistance and capacitance value changes of the resistive and capacitive sensing devices, and any frequency can be provided under sufficient computing resources. Thereby providing measurement accuracy.
  • FIG. 1 schematically illustrates measurement of resistance values and capacitance values for detecting resistive and capacitive sensing devices using a system in accordance with the present disclosure
  • FIG. 2 shows schematically the TAF-DPS clock generator and its working principle
  • FIG. 3 shows a voltage controlled oscillator VCO 300 generating a basic time unit ⁇ ;
  • Figure 4 is a schematic illustration of a vernier caliper based on a TAF-DPS clock generator and its operation
  • FIG. 5 schematically shows a frequency locked loop based on a TAF-DPS clock generator and its working principle
  • Figure 6 schematically shows a schematic diagram for frequency detection
  • FIG. 7 schematically illustrates one embodiment of a method for identifying a frequency of a voltage signal in accordance with the present disclosure.
  • FIG. 1 schematically illustrates the measurement of resistance values and capacitance values for detecting resistive and capacitive sensing devices using a system in accordance with the present disclosure.
  • the system includes a relaxation oscillator 100 and a frequency adjustable frequency source in accordance with the present disclosure.
  • the right diagram of Figure 1 shows a frequency source in accordance with the present disclosure, which in this embodiment is implemented as a time/frequency recovery circuit based on time averaged frequency direct cycle synthesis (TAF-DPS).
  • TAF-DPS time averaged frequency direct cycle synthesis
  • the left diagram of FIG. 1 shows a relaxation oscillator 100 including an operational amplifier 101 and a sensing capacitor C.
  • the output voltage terminal V of the operational amplifier 101 is grounded via the first resistor R and the sense capacitor C, and the junction between the first resistor R and the sense capacitor C is led to the negative input terminal of the operational amplifier 101.
  • the voltage output from the output voltage terminal V of the operational amplifier 101 is divided by a voltage dividing circuit composed of a resistor R2 and a resistor R3 and sent to the positive input terminal of the operational amplifier 101.
  • the operational amplifier 101 After oscillating, the operational amplifier 101 outputs a voltage signal having a frequency associated with the resistance value and the capacitance value in the relaxation oscillator 100.
  • the change of the resistance value and the capacitance value can be known by detecting the frequency.
  • the frequency of the relaxation oscillator is measured with a frequency-fixed frequency source to measure the resistance value and the capacitance value change.
  • the inventors of the present disclosure have noted that the resolution of known systems is limited, which is at most the period of the frequency source. Therefore, the inventors of the present application have proposed a frequency-variable frequency source based on a TAF-DPS clock generator.
  • FIG. 1 schematically shows the pulse sequence output by the relaxation oscillator 100. As the resistance or capacitance value in the relaxation oscillator 100 changes, the frequency or period of the pulse sequence will also change.
  • the pulse sequence is sent to a frequency-adjustable frequency source in accordance with the present disclosure to determine the change in resistance and capacitance values in the relaxation oscillator 100 by measuring the frequency variation of the pulse sequence.
  • the voltage signal output by the relaxation oscillator 100 in association with its resistance value and capacitance value is input to the frequency-adjustable frequency source according to the present disclosure shown in the right diagram of FIG. 1, the frequency source identification The frequency of the input voltage signal.
  • the frequency source tunable according to the present disclosure is a TAF-DPS based time/frequency recovery circuit that includes a TAF-DPS clock generator.
  • Time-Average-Frequency Direct Period Synthesis is an emerging frequency synthesis architecture based on the new time-averaged frequency concept. Notable features of TAF-DPS include small frequency granularity (also known as arbitrary frequency generation) and fast frequency switching (also known as instantaneous frequency switching). More importantly, its frequency switching speed is quantifiable. In other words, the response time from the time when the frequency control word is updated to the time when the frequency is switched can be calculated based on the clock period.
  • FIG. 2 shows schematically the TAF-DPS clock generator and its working principle.
  • the TAF-DPS clock generator has:
  • An output terminal for outputting a clock signal wherein the clock signal is a pulse having a first period T A and a pulse having a second period T B is interleaved, wherein the first period T A and the second period T B
  • the probability of occurrence is controlled by the value of r. Specifically, the probability of occurrence of the first period T A is (1-r)%, and the probability of occurrence of the second period T B is r%.
  • the capacitance value or the resistance value of the capacitance sensing device are in a one-to-one correspondence, thereby obtaining a change in the capacitance value and the resistance value.
  • I and r are input by the user, wherein the accuracy of the frequency of the TAF-DPS clock generator is related to the number of bits allocated to r.
  • the TAF-DPS clock generator can generate any frequency in the case where the memory capacity is sufficiently large, that is, given a sufficient number of bits in the control word F. This means that the TAF-DPS clock generator enables small-grained fine frequency measurements. Furthermore, since each individual pulse is constructed directly, the output frequency of the TAF-DPS clock generator can be changed instantaneously, that is, with rapid frequency switching. Ability to generate any frequency The rate and ability to perform frequency switching quickly is also a major advantage of the TAF-DPS clock generator over conventional frequency sources.
  • FIG. 3 shows a voltage controlled oscillator VCO 300 that generates a basic time unit ⁇ .
  • the value of the base time unit ⁇ is the time interval between two adjacent VCO outputs.
  • the base time unit ⁇ is generated by a multi-stage voltage controlled oscillator VCO in which the multi-stage voltage controlled oscillator VCO is locked to the reference frequency by a phase locked loop, so that the frequency f vco of the multistage voltage controlled oscillator VCO is a known value
  • the multi-stage voltage controlled oscillator VCO outputs K phase uniform signals, where K is an integer greater than 1, so that the base time unit ⁇ can be calculated as:
  • T VCO the period of the multi-stage voltage controlled oscillator VCO.
  • Fig. 4 schematically shows a vernier caliper based on a TAF-DPS clock generator and its operation.
  • the left diagram of Fig. 4 schematically shows a resonator to represent an object to be measured.
  • the pulse waveform diagram in the middle of Fig. 4 schematically shows the output signal of the resonator whose frequency is unknown.
  • the diagram on the right side of Figure 4 shows the TAF-DPS vernier caliper, which detects the frequency of the output signal.
  • the TAF-DPS vernier caliper includes:
  • a first TAF-DPS clock generator for use as a slow TAF-DPS clock generator, the first TAF-DPS clock generator receiving a slow control word Fslow at its second input, the first TAF-DPS clock generator also having a third input terminal for receiving a start signal of a pulse period of the input voltage signal, the first TAF-DPS clock generator outputting a slow clock signal at the output end,
  • a second TAF-DPS clock generator for use as a fast TAF-DPS clock generator, a second TAF-DPS clock generator receiving a fast control word F fast at its second input, and a second TAF-DPS clock generator having a third input terminal for receiving an end signal of one pulse period of the input voltage signal, and a second TAF-DPS clock generator outputting a fast clock signal at the output end,
  • phase detector for detecting a coincidence point of the slow clock signal and the fast clock signal, wherein the slow clock signal is aligned with the edge of the fast clock signal at the coincidence point, wherein the phase detector has a first input for receiving the slow clock a signal, a second input for receiving a fast clock signal, and an output for outputting a reset signal when a coincident point is detected,
  • a first digital counter having a clock input for receiving a slow clock signal, a reset input for receiving a reset signal from the phase detector, and an output for outputting a first digital counter storage upon receiving the reset signal a slow clock signal, wherein the number of cycles of the output slow clock signal is stored as a first digital value n 1 , and after outputting the stored slow clock signal, the first digital counter is reset.
  • a second digital counter having a clock input for receiving a fast clock signal, a reset input for receiving a reset signal from the phase detector, and an output for outputting a second digital counter storage upon receiving the reset signal a fast clock signal, wherein the number of cycles of the output fast clock signal is stored as a second digital value n 2 , and after outputting the stored fast clock signal, the second digital counter is reset.
  • a calculation module (not shown) is configured to calculate a time of flight (TOF) between the start signal and the end signal based on the first digital value n 1 and the second digital value n 2 to derive a period of the signal under test. For example, in the case of measuring the voltage signal output by the capacitive and inductive sensing device, the capacitance value and the resistance value change can be further derived.
  • TOF time of flight
  • F slow I, where I is an integer greater than or equal to 2
  • F fast (I-1) + r.
  • the accuracy of F can be arbitrary, that is, the output frequency of the associated TAF-DPS clock generator can be arbitrary.
  • the first TAF-DPS clock generator includes:
  • the first TAF-DPS digitally controlled oscillator DCO1 is used to generate a slow base time unit ⁇ slow ,
  • TAF-DPS first frequency synthesizer (not shown), which ⁇ slow clock output signal F slow slow TAF and from DCO1 based.
  • the input, output, and intermediate parameters of the first TAF-DPS DCO1 are digital values. Specifically, the first TAF-DPS DCO1 for the reception frequency f ref1 of the reference signal CK ref1 at its first input.
  • the time interval between every two signals is treated as the slow base time unit ⁇ slow .
  • TAF-DPS DCO1 receiving a first control word F slow at its second input terminal, and a first clock generator TAF-DPS contained in a first frequency synthesizer TAF-DPS
  • the output frequency is the signal of f DCO1 .
  • the second TAF-DPS clock generator includes:
  • the second TAF-DPS digitally controlled oscillator DCO2 is used to generate a fast base time unit ⁇ fast ,
  • TAF-DPS second frequency synthesizer (not shown), which in accordance with the fast clock signal ⁇ fast TAF F fast and output from the DCO2,
  • TAF-DPS frequency synthesizer 1 ⁇ PLL (phase-locked loop with a division ratio of 1) for connection from the second TAF-DPS frequency synthesizer
  • the TAF clock signal is received as an input signal of the phase locked loop, and a slow clock signal is outputted according to the input signal as an output signal of the phase locked loop, wherein a frequency ratio of the input signal to the output signal is 1.
  • the input, output, and intermediate parameters of the second TAF-DPS DCO2 are digital values.
  • the time interval between every two signals is treated as the fast base time unit ⁇ fast .
  • the output frequency is the signal of f DCO2 .
  • the frequency source can be implemented by software simulation. This saves space and cost.
  • Fig. 5 schematically shows a frequency-locked loop based on a TAF-DPS clock generator and its operation.
  • the left diagram of Fig. 5 schematically shows a resonator to represent the object to be measured.
  • the pulse waveform diagram in the middle of Fig. 5 schematically shows the output signal of the resonator whose frequency is unknown.
  • the right diagram of Figure 5 shows the TAF-DPS frequency-locked loop FLL, which detects the frequency of the output signal.
  • the reference signal is compared with a clock signal generated by the TAF-DPS clock generator in terms of frequency, and iterated according to the comparison result
  • the control word F of the TAF-DPS clock generator is adjusted until the frequency of the generated clock signal coincides with the frequency of the reference signal, thereby determining the frequency of the reference signal based on the control word F.
  • the capacitance values and resistance values of the resistive and capacitive sensing devices can be derived.
  • the frequency-locked loop FLL shown in FIG. 5 includes:
  • the frequency detector FD is connected to a low pass filter LPF downstream of the frequency detector FD, a TAF-DPS DCO connected downstream of the low pass filter LPF, and a frequency division connected between the TAF-DPS DCO and the frequency detector FD.
  • the frequency detector FD detects a difference between the frequency f r of the reference signal input to the frequency detector FD and the frequency f o ' of the signal from the frequency divider, and outputs a difference variable, the low pass filter LPF the difference variable low-pass filtered to remove high frequency components, generates the downstream TAF-DPS DCO control variable, the control variable comprises a control word F., and then, TAF-DPS DCO generates the control variable for the frequency according to the f o output signal, the output signal is a factor of the frequency divider 1 / N obtained after the frequency division of the frequency f o 'signal and the frequency f o' the signal is transferred to the FD frequency detector, where N is greater than or equal An integer of 1.
  • the output signal f o of the frequency-locked loop FLL is directly input to the frequency detector FD.
  • the frequency detector FD detects a difference between the frequency f r of the reference signal input to the frequency detector FD and the frequency f o of the output signal of the frequency-locked loop FLL, and outputs a difference variable, a low-pass filter LPF After low-pass filtering the difference variable to remove high-frequency components, a control variable for the downstream TAF-DPS DCO is generated, the control variable containing the control word F, and then the TAF-DPS DCO generates a frequency f according to the control variable.
  • the output signal of o is transmitted to the frequency detector FD.
  • the difference variable and the control variable are both digital values.
  • the advantages of the frequency-locked loop based on the TAF-DPS clock generator correspond to the advantages of the vernier caliper based on the TAF-DPS clock generator.
  • Fig. 6 schematically shows a schematic diagram for frequency detection.
  • the first signal and the second signal of two frequencies f in and f DCO are taken as driving clocks.
  • This second signal is for example derived from a TAF-DPS clock generator.
  • the period of the second signal is first determined by the detection of the rising edge and the falling edge.
  • the number of rising edges of the first signal detected during each cycle of the second signal is then determined. If two or more rising edges of the first signal are detected within one cycle of the second signal, the fact that f in >f DCO can be determined. Otherwise, based on a half cycle of the second signal, the half cycle includes a rising edge and a falling edge of the second signal.
  • the method for detecting the relationship between the frequencies of two input signals according to the present disclosure can be implemented simply, quickly, and at low cost.
  • the present disclosure also provides a method for identifying a frequency of a voltage signal, wherein the voltage signal is input to a frequency adjustable frequency source that identifies the frequency of the input voltage signal.
  • FIG. 7 schematically illustrates a method for identifying a frequency of a voltage signal in accordance with the present disclosure.
  • the frequency value and the capacitance value change of the resistive and capacitive sensing device are detected by using a frequency-adjustable frequency source, including the following steps:
  • Step 700 Converting a resistance value and a capacitance value into a voltage output signal by a resistive and capacitive sensing device
  • Step 710 transmitting the voltage output signal to a frequency source and identifying a frequency of the voltage output signal by the frequency source;
  • Step 720 confirm whether the frequency of the voltage output signal is different from the frequency of the voltage output signal previously stored in the resistive and capacitive sensing device, and if so,
  • Step 730 Determine that there is a change in the resistance value and the capacitance value.
  • a circuit including a TAF-DPS clock generator is used as the frequency source, wherein the TAF-DPS clock generator has:
  • An output terminal for outputting a clock signal wherein the clock signal is a pulse having a first period T A and a pulse having a second period T B is interleaved, wherein the first period T A and the second period T B
  • the probability of occurrence is controlled by the value of r. Specifically, the probability of occurrence of the first period T A is (1-r)%, and the probability of occurrence of the second period T B is r%.
  • an output signal of the resistive and capacitive sensing device is input to a frequency-locked loop FLL constructed based on the TAF-DPS clock generator as a reference signal,
  • control word F of the TAF-DPS clock generator is iteratively adjusted according to the comparison result until the frequency of the generated clock signal coincides with the frequency of the reference signal, thereby obtaining the reference signal according to the control word F Frequency, and
  • the capacitance value and the resistance value change of the resistive and capacitive sensing device are obtained.
  • the frequency-locked loop FLL includes:
  • the frequency detector FD is connected to a low pass filter LPF downstream of the frequency detector FD and a TAF-DPS DCO connected downstream of the low pass filter LPF.
  • the difference between the frequency f r of the reference signal input to the frequency detector FD and the frequency f o of the output signal of the frequency-locked loop FLL is detected by the frequency detector FD, And output the difference variable,
  • a control variable for the downstream TAF-DPS DCO is generated, the control variable including the control word F,
  • the output signal is transmitted to the frequency detector FD.
  • the frequency detector FD in the frequency detector FD, the number of rising edges of the reference signal detected in each period of the output signal of the frequency-locked loop FLL whose frequency f o is known is determined. Wherein the frequency f r of the reference signal is unknown,
  • the half cycle includes a rising edge and a falling edge of the output signal, the rising edge and the falling edge in a half cycle of the output signal
  • the frequency-locked loop FLL further includes a frequency divider connected between the TAF-DPS DCO and the frequency detector FD.
  • the difference between the frequency f r of the reference signal input to the frequency detector FD and the signal frequency f o ' from the frequency divider is detected by the frequency detector FD, and the difference is output.
  • a control variable for the downstream TAF-DPS DCO is generated, the control variable including the control word F,
  • An output signal of frequency f o is generated by the TAF-DPS DCO according to the control variable
  • the output signal is divided by a frequency divider by a factor of 1/N to obtain a signal of frequency f o ', and
  • the signal of frequency f o ' is transmitted to a frequency detector FD, where N is an integer greater than or equal to one.
  • the number of rising edges of the reference signal detected in each period of the frequency f o ' from the frequency divider is determined, wherein the reference The frequency f r of the signal is unknown.
  • the half cycle includes a rising edge and a falling edge of the output signal, the rising edge and the falling edge in a half cycle of the output signal
  • the difference variable and the control variable are both digital values.
  • the present disclosure also provides an electronic device including a frequency adjustable frequency source in accordance with the present disclosure.
  • the present disclosure proposes a frequency-variable frequency source of a TAF-DPS-based clock generator based on the problem that the detection accuracy is limited by the frequency of the frequency source when detecting the unknown reference frequency by using the frequency source in the prior art.
  • the vernier caliper of the TAF-DPS-based clock generator and the frequency-locked loop of the TAF-DPS-based clock generator are specifically given.
  • the accuracy of frequency detection can be adjusted by modifying the number of bits in the TAF-DPS clock generator.
  • a TAF-DPS-based digitally controlled oscillator DCO can be used as a clock generator in the vernier caliper of the TAF-DPS-based clock generator and the frequency-locked loop based on the TAF-DPS clock generator.

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Abstract

本公开涉及频率可调的频率源和相关的系统、方法和电子设备。尤其涉及一种频率可调的频率源，其具有输入端用于接收所输入的电压信号，所述频率源识别所输入的电压信号的频率。本公开还涉及一种包括该频率源的系统、一种识别电压信号的频率的方法和一种包括该频率源的电子设备。

Description

频率可调的频率源和相关的系统、方法和电子设备
本申请要求2017年01月04日提交的申请号为201710004754.8且发明名称为“频率可调的频率源和相关的系统、方法和电子设备”的中国优先申请的优先权，通过引用将其全部内容并入于此。
技术领域
本公开涉及一种频率可调的频率源，用于识别输入的电压信号的频率。本公开还涉及一种包括该频率源的系统、一种识别电压信号的频率的方法和一种包括该频率源的电子设备。
背景技术
电容性感测是用于现代消费者电子产品、设备、家庭控制和物联网(IoT)的重要技术。其中，将电容值的变化用于接近度/姿势探测、材料分析、液位测量等。
温度感测在现代电子产品中同样是很重要的。存在两种被广泛采用的温度感测方法，即热敏电阻和电阻性温度探测器(RTD)。它们通过将感测元件的电阻与温度相关联来测量温度(电阻性感测)。
在基于电容和电阻的感测中，需要将电阻值R或电容值C的变化转换为电压水平或时间，并且随后转换为数字值。在用时间代表电容/电阻变化的方法中，用于RC充电和放电的时间是感兴趣的目标。在将电阻值R或电容值C的变化转换为数字值的过程中，该变化首先(通过模数转换器ADC)被转换为电压水平或者(通过时间数字转换器TDC)被转换为时间，随后被转换为数字值。在用时间表示电容/电阻变化的方法中，用于RC充放电的时间是感兴趣的目标。该持续时间可以用频率已知的时钟信号来直接测量。或者，受观察的电容/电阻可以成为弛张振荡器(也称作非稳态复振器)的一部分，该弛张振荡器的谐振频率是与R和C有关的。
在现有技术中，用频率固定的频率源测量弛张振荡器的频率，从而测量R和C变化。
发明内容
在本公开的实施例中提供一种频率可调的频率源、一种包括该频率源的系统、一种识别电压信号的频率的方法和一种包括该频率源的电子设备。
根据本公开的一个方面，提供了一种频率可调的频率源，其具有输入端用于接收所输入的电压信号，所述频率源识别所输入的电压信号的频率。
在本公开的一个实施形式中，频率源的输入的电压信号是从电阻性和电容性感测装置接收的，其中，电阻性和电容性感测装置将电阻值和电容值转换为电压信号，该电压信号被输入至频率源。
在本公开的一个实施形式中，频率源包括时间平均频率直接周期合成TAF-DPS时钟发生器，其中，TAF-DPS时钟发生器具有：
第一输入端，用于接收基础时间单元△，
第二输入端，用于接收频率/周期控制字F＝I+r，其中，I是整数，0≦r<1，
直接周期合成单元，用于创建第一周期TA＝I*△和第二周期TB＝(I+1)*△，
输出端，用于输出时钟信号，该时钟信号是具有第一周期TA的脉冲和具有第二周期TB的脉冲以交织方式构成的，其中，第一周期TA和第二周期TB的出现可能性由r的值控制，
其中，TAF-DPS时钟发生器的频率和周期根据时钟信号的时间平均频率计算为1/fTAF＝TTAF＝F*△，控制字F与其输出周期呈线性关系。在测量电阻性和电容性感测装置输出的电压信号的频率的情况下，控制字与被测的电阻性和电容性感测装置的电容值或电阻值呈一一对应关系，从而得出电容值和电阻值的变化。在所使用的资源足够大的情况下，TAF-DPS时钟发生器几乎可以生成任何频率，所以对频率的感测，进而对例如电阻值和电容值变化的感测可以有更高的灵敏度。
在本公开的一个实施形式中，基础时间单元△是由多级压控振荡器产生的，其中通过锁相环将多级压控振荡器锁定至参考频率，从而多级压控振荡器的频率fvco是已知值，多级压控振荡器输出K个相位均匀信号，其中K是大于1的整数，从而基础时间单元△可以计算为：
Δ＝TVCO/K＝1/(K·fvco)，
其中，TVCO代表所述多级压控振荡器的周期。
在本公开的一个实施形式中，I和r是由用户输入的，其中，TAF-DPS 时钟发生器的频率的精度与分配给r的位数有关。
在本公开的一个实施形式中，频率源包括TAF-DPS游标卡尺，TAF-DPS游标卡尺包括：
第一TAF-DPS时钟发生器，用作慢TAF-DPS时钟发生器，第一TAF-DPS时钟发生器具有第二输入端，用于接收慢控制字Fslow，第一TAF-DPS时钟发生器还具有第三输入端，用于接收所述输入的电压信号、即被测电压信号的一个脉冲周期的开始信号，第一TAF-DPS时钟发生器在输出端输出慢时钟信号，
第二TAF-DPS时钟发生器，用作快TAF-DPS时钟发生器，第二TAF-DPS时钟发生器具有第二输入端，用于接收快控制字Ffast，第二TAF-DPS时钟发生器还具有第三输入端，用于接收所述输入的电压信号、即被测电压信号的上述脉冲周期的结束信号，第二TAF-DPS时钟发生器在输出端输出快时钟信号，
相位检测器，用于检测慢时钟信号和快时钟信号的重合点，其中，在重合点上慢时钟信号和快时钟信号的边沿对齐，其中，相位检测器具有第一输入端用于接收慢时钟信号，第二输入端用于接收快时钟信号，和输出端用于在检测到重合点时输出重置信号，
第一数字计数器，具有时钟输入端用于接收慢时钟信号，重置输入端用于接收来自相位检测器的重置信号，以及输出端用于在接收到重置信号时输出第一数字计数器存储的慢时钟信号，其中，所输出的慢时钟信号的循环个数被存储为第一数字值，并且在输出所存储的慢时钟信号后，第一数字计数器被重置，
第二数字计数器，具有时钟输入端用于接收快时钟信号，重置输入端用于接收来自相位检测器的重置信号，以及输出端用于在接收到重置信号时输出第二数字计数器存储的快时钟信号，其中，所输出的快时钟信号的循环个数被存储为第二数字值，并且在输出所存储的快时钟信号后，第二数字计数器被重置，
计算模块，用于根据第一数字值和第二数字值计算开始信号和结束信号之间的飞行时间(TOF)，从而得出所述输入的电压信号、即被测电压信号的频率变化。例如在测量电阻性和电容性感测装置、例如弛张振荡器输出的电压信号的周期的情况下，可以得出其电容值和电阻值变化。
在本公开的一个实施形式中，慢控制字Fslow＝I，其中I是大于等于2的整数，快控制字Ffast＝(I-1)+r。
在本公开的一个实施形式中，第一TAF-DPS时钟发生器包括：
第一数位控制振荡器，用于生成慢基础时间单元△slow，
第一TAF-DPS频率合成器，其根据Fslow和得自第一数位控制振荡器的慢基础时间单元△slow输出慢TAF时钟信号。
在本公开的一个实施形式中，第二TAF-DPS时钟发生器包括：
第二数位控制振荡器，用于生成快基础时间单元△fast，
第二TAF-DPS频率合成器，其根据快控制字Ffast和得自第二数位控制振荡器的快基础时间单元△fast输出快TAF时钟信号，
1×PLL(分频比为1的锁相环)，用于从第二TAF-DPS频率合成器接收快TAF时钟信号作为输入信号，并且根据输入信号输出慢时钟信号作为输出信号，其中，输入信号与输出信号的频率比是1。
在本公开的一个实施形式中，频率源包括基于TAF-DPS时钟发生器构建的锁频环，其中，将所述输入的电压信号、例如电阻性和电容性感测装置的输出电压信号输入至所述锁频环作为参考信号，将参考信号与由TAF-DPS时钟发生器生成的时钟信号在频率方面相比较，并且根据比较结果迭代地调整TAF-DPS时钟发生器的控制字F，直至所生成的时钟信号的频率与参考信号的频率一致，从而根据控制字F求出参考信号的频率，进而得出所输入的电压信号的频率变化。例如可以从频率变化求出电阻性和电容性感测装置的电容值和电阻值变化。
在本公开的一个实施形式中，锁频环包括：
频率检测器，连接在频率检测器下游的低通滤波器和连接在所述低通滤波器下游的TAF-DPS数位控制振荡器。
在本公开的一个实施形式中，频率检测器被配置为检测出输入至频率检测器的所述参考信号的频率fr与所述锁频环的输出信号的频率fo之间的差异，并且输出差异变量；低通滤波器被配置为对差异变量进行低通滤波以去除高频分量后，生成用于下游的TAF-DPS数位控制振荡器的控制变量，其中该控制变量包含控制字F；TAF-DPS数位控制振荡器被配置为根据该控制变量生成频率为fo的输出信号，其中该输出信号被传送到频率检测器。
在本公开的一个实施形式中，在频率检测器中，确定在从所述锁频环输 出的、频率fo已知的输出信号的每个周期内检测到的所述参考信号的上升沿数目，其中，所述参考信号的频率fr未知，
如果在所述输出信号的一个周期内检测到参考信号的两个或更多个上升沿，则可以确定fr>fo的事实，
否则，以所述输出信号的半个周期为基础，该半个周期包括所述输出信号的一个上升沿和一个下降沿，以所述输出信号的半个周期内的该上升沿和该下降沿为采样时间点对所述参考信号进行采样，如果采样到参考信号的一个上升沿和一个下降沿，则认为fr＝fo，否则，认为fr<fo。
在本公开的一个实施形式中，所述锁频环还包括连接在TAF-DPS数位控制振荡器与频率检测器之间的分频器。
在本公开的一个实施形式中，频率检测器被配置为检测出输入至频率检测器的所述参考信号的频率fr与来自分频器的信号频率fo’之间的差异，并且输出差异变量；低通滤波器被配置为对差异变量进行低通滤波以去除高频分量之后，生成用于下游的TAF-DPS数位控制振荡器的控制变量，其中该控制变量包含控制字F；TAF-DPS数位控制振荡器被配置为根据该控制变量生成频率为fo的输出信号；分频器被配置为以1/N的系数对该输出信号进行分频以产生频率为fo’的信号并且将该频率为fo’的信号传送到频率检测器，其中N为大于等于1的整数。
在本公开的一个实施形式中，在频率检测器中，确定在来自分频器的、频率fo’的每个周期内检测到的所述参考信号的上升沿数目，其中，所述参考信号的频率fr未知，
如果在所述输出信号的一个周期内检测到参考信号的两个或更多个上升沿，则确定fr>fo’的事实，
否则，以所述输出信号的半个周期为基础，该半个周期包括所述输出信号的一个上升沿和一个下降沿，以所述输出信号的半个周期内的该上升沿和该下降沿为采样时间点对所述参考信号进行采样，如果采样到参考信号的一个上升沿和一个下降沿，则认为fr＝fo’，否则，认为fr<fo’。
在本公开的一个实施形式中，所述差异变量和所述控制变量都是数字值。
根据本公开的另一方面，本公开还提供了一种探测电阻性和电容性感测装置的电阻值和电容值变化的系统。该系统包括根据本公开的频率可调的频 率源、电阻性和电容性感测装置和比较单元，其中，电阻性和电容性感测装置将电阻值和电容值转换为电压信号，频率源识别所述电压信号的频率，其中，比较单元将识别出的频率与之前存储的所述电阻性和电容性感测装置的电压信号的频率相比较，在确定电压信号的频率有变化的情况下，确定所述电阻性和电容性感测装置的电阻值和电容值有变化。
在根据本公开的一个实施形式中，电阻性和电容性感测装置是弛张振荡器，其中，弛张振荡器包括运算放大器和连接在运算放大器的一个输入端的感测电容，其中，运算放大器输出电压信号，该电压信号具有与所述弛张振荡器中的电阻值和电容值有关的频率。
根据本公开的另一方面，本公开还提供了一种识别电压信号的频率的方法，其中，将电压信号输入至根据本公开的频率可调的频率源，频率源识别所输入的电压信号的频率。
在本公开的一个实施形式中，识别电压信号的频率的方法包括如下步骤：
通过电阻性和电容性感测装置将电阻值和电容值转换为电压信号；
将所述电压信号传送至所述频率可调的频率源并且通过所述频率可调的频率源识别所述电压信号的频率；
确认所述电压信号的频率与之前存储的所述电阻性和电容性感测装置的电压信号的频率相比是否有变化，如果有，则确定电阻值和电容值有变化。
在本公开的一个实施形式中，将所述电阻性和电容性感测装置的输出信号输入所述基于所述TAF-DPS时钟发生器构建的锁频环作为参考信号，
将所述参考信号与由所述TAF-DPS时钟发生器生成的时钟信号在频率方面相比较，
根据比较结果迭代地调整所述TAF-DPS时钟发生器的控制字F，直至所生成的时钟信号的频率与所述参考信号的频率一致，从而根据所述控制字F求出所述参考信号的频率，以及
得出所述电阻性和电容性感测装置的电容值和电阻值变化。
在本公开的一个实施形式中，所述锁频环包括：
频率检测器，连接在所述频率检测器下游的低通滤波器、连接在所述低通滤波器下游的TAF-DPS DCO。
在本公开的一个实施形式中，通过频率检测器检测出输入至频率检测器 的所述参考信号的频率fr与所述锁频环的输出信号的频率fo之间的差异，并且输出差异变量，
通过低通滤波器对差异变量进行低通滤波以去除高频分量后，生成用于下游的TAF-DPS数位控制振荡器的控制变量，该控制变量包含控制字F，
通过TAF-DPS数位控制振荡器根据该控制变量生成频率为fo的输出信号，以及
将该输出信号传送到频率检测器。
在本公开的一个实施形式中，在频率检测器中，确定在所述锁频环的、频率fo已知的输出信号的每个周期内检测到的所述参考信号的上升沿数目，其中，所述参考信号的频率fr未知，
如果在所述输出信号的一个周期内检测到参考信号的两个或更多个上升沿，则确定fr>fo的事实，
否则，以所述输出信号的半个周期为基础，该半个周期包括所述输出信号的一个上升沿和一个下降沿，以所述输出信号的半个周期内的该上升沿和该下降沿为采样时间点对所述参考信号进行采样，如果采样到参考信号的一个上升沿和一个下降沿，则认为fr＝fo，否则，认为fr<fo。
在本公开的一个实施形式中，所述锁频环还包括连接在TAF-DPS数位控制振荡器与频率检测器之间的分频器。
在本公开的一个实施形式中，通过频率检测器检测出输入至频率检测器的所述参考信号的频率fr与来自分频器的信号频率fo’之间的差异，并且输出差异变量，
通过低通滤波器对差异变量进行低通滤波以去除高频分量后，生成用于下游的TAF-DPS数位控制振荡器的控制变量，该控制变量包含控制字F，
通过TAF-DPS数位控制振荡器根据该控制变量生成频率为fo的输出信号，
将该输出信号借助分频器以1/N的系数分频后得到频率为fo’的信号，以及
将该频率为fo’的信号传送到频率检测器，其中N为大于等于1的整数。
在本公开的一个实施形式中，在频率检测器中，确定在来自分频器的、频率fo’的每个周期内检测到的所述参考信号的上升沿数目，其中，所述参考信号的频率fr未知，
如果在所述输出信号的一个周期内检测到第一信号的两个或更多个上升沿，则确定fr>fo’的事实，
否则，以所述输出信号的半个周期为基础，该所述输出信号的半个周期包括一个上升沿和一个下降沿，以所述输出信号的半个周期内的该上升沿和该下降沿为采样时间点对所述参考信号进行采样，如果采样到参考信号的一个上升沿和一个下降沿，则认为fr＝fo’，否则，认为fr<fo’。
在本公开的一个实施形式中，所述差异变量和所述控制变量都是数字值。
根据本公开的另一方面，本公开还提供了一种包括根据本公开的频率源的电子设备。
根据本公开利用TAF-DPS的频率可编程性提供频率可变的频率源，用于探测电阻性和电容性感测装置的电阻值和电容值变化，在计算资源充足的条件下可以提供任何频率，从而提供了测量精度。
附图说明
通过结合附图对本公开的优选实施例进行详细描述，本公开的上述和其他目的、特性和优点将会变得更加清楚，其中相同的标号指定相同结构的单元，并且在其中：
图1示意性地示出了使用根据本公开的系统测量用于探测电阻性和电容性感测装置的电阻值和电容值变化；
图2示意性地示出了TAF-DPS时钟发生器和其工作原理；
图3示出了生成基本时间单元△的压控振荡器VCO 300；
图4示意性地示出了基于TAF-DPS时钟发生器的游标卡尺及其工作原理；
图5示意性地示出了基于TAF-DPS时钟发生器的锁频环及其工作原理；
图6示意性地示出了用于频率检测的原理图；
图7示意性地示出了根据本公开的用于识别电压信号的频率的方法的一个实施例。
为了纵览性，为相同或相当的元件贯穿所有附图地标以相同的附图标记。附图仅为示意性的，其中的元件无需合乎比例。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些实施例获得其他的实施例。
图1示意性地示出了使用根据本公开的系统测量用于探测电阻性和电容性感测装置的电阻值和电容值变化。该系统包括弛张振荡器100和根据本公开的频率可调的频率源。
图1的右图示出了根据本公开的频率源，其在该实施例中实现为基于时间平均频率直接周期合成(TAF-DPS)的时间/频率恢复电路。借助根据本公开的频率可调的频率源的输入端接收探测弛张振荡器100的输出电压信号，并且由该频率源探测该输出电压信号的频率。
图1左图示出了弛张振荡器100,其包括运算放大器101和感测电容器C。运算放大器101的输出电压端V经由第一电阻器R和感测电容器C接地，第一电阻器R与感测电容器C之间的结点被引至运算放大器101的负输入端。运算放大器101的输出电压端V所输出的电压在经由电阻器R2和电阻器R3组成的分压电路分压后送往运算放大器101的正输入端。起振后，运算放大器101输出电压信号，该电压信号具有与弛张振荡器100中的电阻值和电容值有关的频率。可见，可以通过检测频率而得知电阻值和电容值的变化。在现有技术中，用频率固定的频率源测量弛张振荡器的频率，从而测量电阻值和电容值变化。本公开的发明人注意到，已知系统的分辨率(resolution)受限，其至多为该频率源的周期。因此，本申请的发明人提出了基于TAF-DPS时钟发生器的、频率可变的频率源。
图1的中间下方图示意性地示出了弛张振荡器100输出的脉冲序列。在弛张振荡器100中的电阻或电容值变化时，该脉冲序列的频率或周期也将发生变化。图1的中间上方图示出了该脉冲序列的每个信号周期包括两个脉冲，在第一脉冲中包括上升沿tup，在第二脉冲中包括下降沿tdo。
该脉冲序列被送往根据本公开的频率可调的频率源以通过测得该脉冲序列的频率变化而得知弛张振荡器100中的电阻值和电容值变化。具体地，弛张振荡器100输出的、与其电阻值和电容值关联的电压信号被输入至图1右图示出的根据本公开的频率可调的频率源，该频率源识别 所输入的电压信号的频率。在本实施例中，根据本公开的频率可调的该频率源是基于TAF-DPS的时间/频率恢复电路，其包括TAF-DPS时钟发生器。
时间平均频率直接周期合成(TAF-DPS,Time-Average-Frequency Direct Period Synthesis)是一种新兴的频率合成架构，其基于新的时间平均频率概念。TAF-DPS的显著特征包括小频率粒度(也称为任意频率生成)和快速频率切换(也称为瞬时频率切换)。更重要的是，其频率切换速度是可量化的。换句话说，从接收频率控制字更新的时刻到频率切换的时刻的响应时间可以根据时钟周期来计算。
图2示意性地示出了TAF-DPS时钟发生器和其工作原理。
TAF-DPS时钟发生器具有：
第一输入端，用于接收基础时间单元△，
第二输入端，用于接收频率/周期控制字F＝I+r，其中，I是整数，0≦r<1，
直接周期合成单元，用于创建第一周期TA＝I*△和第二周期TB＝(I+1)*△，
输出端，用于输出时钟信号，该时钟信号是具有第一周期TA的脉冲和具有第二周期TB的脉冲以交织方式构成的，其中，第一周期TA和第二周期TB的出现可能性由r的值控制，具体地，第一周期TA出现可能性为(1-r)％，第二周期TB出现可能性为r％，
其中，TAF-DPS时钟发生器的频率和周期根据时钟信号的时间平均频率计算为1/fTAF＝TTAF＝F*△，控制字F与其输出周期呈线性关系,因此与被测的电阻性和电容性感测装置的电容值或电阻值呈一一对应关系，从而得出电容值和电阻值的变化。
在本公开的一个实施形式中，I和r是由用户输入的，其中，TAF-DPS时钟发生器的频率的精度与分配给r的位数有关。
从控制字F和时间平均频率的计算公式可以得知，在存储器容量足够大的情况下，即给予控制字F中的r足够的位数，则TAF-DPS时钟发生器可以生成任何频率。这也就是说，TAF-DPS时钟发生器能够实现小粒度的精细频率测量。此外，因为每个单个脉冲是直接构建的，所以TAF-DPS时钟发生器的输出频率可以瞬间改变，也即具有频率切换迅速性。能够生成任何频 率和能够迅速进行频率切换也是TAF-DPS时钟发生器相比于常规频率源的主要优点。
图3示出了生成基本时间单元△的压控振荡器VCO 300。基础时间单元△的值是两个相邻的VCO输出之间的时间间隔。基础时间单元△是由多级压控振荡器VCO产生的，其中通过锁相环将多级压控振荡器VCO锁定至参考频率，从而多级压控振荡器VCO的频率fvco是已知值，多级压控振荡器VCO输出K个相位均匀信号，其中K是大于1的整数，从而基础时间单元△可以计算为：
Δ＝TVCO/K＝1/(K·fvco)，其中，TVCO代表所述多级压控振荡器VCO的周期。
图4示意性地示出了基于TAF-DPS时钟发生器的游标卡尺及其工作原理。图4的左图示意性地示出了谐振器，以表示被测对象。图4中间的脉冲波形图示意性地示出了谐振器的频率未知的输出信号。图4右边的图示出了TAF-DPS游标卡尺，该TAF-DPS游标卡尺检测该输出信号的频率。
该TAF-DPS游标卡尺包括：
第一TAF-DPS时钟发生器，用作慢TAF-DPS时钟发生器，第一TAF-DPS时钟发生器在其第二输入端接收慢控制字Fslow，第一TAF-DPS时钟发生器还具有第三输入端，该第三输入端用于接收输入的电压信号的一个脉冲周期的开始信号，第一TAF-DPS时钟发生器在输出端输出慢时钟信号，
第二TAF-DPS时钟发生器，用作快TAF-DPS时钟发生器，第二TAF-DPS时钟发生器在其第二输入端接收快控制字Ffast，第二TAF-DPS时钟发生器还具有第三输入端，该第三输入端用于接收输入的电压信号的一个脉冲周期的结束信号，第二TAF-DPS时钟发生器在输出端输出快时钟信号，
相位检测器，用于检测慢时钟信号和快时钟信号的重合点，其中，在重合点上慢时钟信号和快时钟信号的边沿对齐，其中，相位检测器具有第一输入端用于接收慢时钟信号，第二输入端用于接收快时钟信号，和输出端用于在检测到重合点时输出重置信号，
第一数字计数器，具有时钟输入端用于接收慢时钟信号，重置输入端用于接收来自相位检测器的重置信号，以及输出端用于在接收到重置信号时输出第一数字计数器存储的慢时钟信号，其中，所输出的慢时钟信号的循环个数被存储为第一数字值n1，并且，在输出所存储的慢时钟信号后，第一数字 计数器被重置，
第二数字计数器，具有时钟输入端用于接收快时钟信号，重置输入端用于接收来自相位检测器的重置信号，以及输出端用于在接收到重置信号时输出第二数字计数器存储的快时钟信号，其中，所输出的快时钟信号的循环个数被存储为第二数字值n2，并且，在输出所存储的快时钟信号后，第二数字计数器被重置，
计算模块(未示出)，用于根据第一数字值n1和第二数字值n2计算开始信号和结束信号之间的飞行时间(TOF)，从而得出被测信号的周期。例如，在测量电容性和电感性感测装置输出的电压信号的情况下，可以进而得出其电容值和电阻值变化。
在该实施例中，Fslow＝I，其中I是大于等于2的整数，Ffast＝(I-1)+r。如之前已经阐述过的，r可以由用户自由输入。因此，F的精确度可以是任意的，也即相关的TAF-DPS时钟发生器的输出频率可以是任意的。
第一TAF-DPS时钟发生器包括：
第一TAF-DPS数位控制振荡器DCO1，用于生成慢基础时间单元△slow，
第一TAF-DPS频率合成器(未示出)，其根据Fslow和得自DCO1的△slow输出慢TAF时钟信号。
第一TAF-DPS DCO1的输入、输出以及中间参数均为数字值。具体地，第一TAF-DPS DCO1在其第一输入端接收频率为fref1的参考信号CKref1。第一TAF-DPS DCO1根据参考信号CKref1生成多个信号，例如16个信号，其为相位均匀地间隔的信号，这16个信号中的每两个信号之间间隔的频率为fdiv1＝fref1/16。每两个信号之间的时间间隔被当做慢基础时间单元△slow。第一TAF-DPS DCO1在其第二输入端接收控制字Fslow，然后由第一TAF-DPS时钟发生器中所包含的第一TAF-DPS频率合成器根据控制字Fslow和慢基础时间单元△slow输出频率为fDCO1的信号。其中，可以通过下式算出：
fDCO1＝1/(Fslow·△slow)＝fref 1/Fslow。
第二TAF-DPS时钟发生器包括：
第二TAF-DPS数位控制振荡器DCO2，用于生成快基础时间单元△fast，
第二TAF-DPS频率合成器(未示出)，其根据Ffast和得自DCO2的△fast输出快TAF时钟信号，
1×PLL(分频比为1的锁相环)，用于从第二TAF-DPS频率合成器接 收快TAF时钟信号作为该锁相环的输入信号，并且根据该输入信号输出慢时钟信号作为该锁相环的输出信号，其中，输入信号与输出信号的频率比是1。
第二TAF-DPS DCO2的输入、输出以及中间参数均为数字值。具体地，第二TAF-DPS DCO2在其第一输入端接收频率为fref2的参考信号CKref2。第二TAF-DPS DCO2根据参考信号CKref2生成多个信号，例如16个信号，其为相位均匀地间隔的信号，这16个信号中的每两个信号之间间隔的频率为fdiv2＝fref2/16。每两个信号之间的时间间隔被当做快基础时间单元△fast。第二TAF-DPS DCO2在其第二输入端接收控制字Ffast，然后由第二TAF-DPS时钟发生器中所包含的第二TAF-DPS频率合成器根据控制字Ffast和快基础时间单元△fast输出频率为fDCO2的信号。其中，可以通过下式算出：
fDCO2＝1/(Ffast·△fast)＝fref 2/Ffast。
从公式可以看出，只要为控制字Fslow和Ffast提供的位数资源足够大，则可以获得几乎任意的输出频率fDCO1和fDCO2。也即可以实现对参考频率fref1和fref 2的几乎任意粒度的检测精度。另外，由于第一TAF-DPS DCO1和第二TAF-DPS DCO2的输入、输出以及中间参数均为数字值，可以实现全数字化的频率源。例如，该频率源可以通过软件模拟来实现。这节省了空间和成本。
图5示意性地示出了基于TAF-DPS时钟发生器的锁频环及其工作原理。图5左图示意性地示出了谐振器，以表示被测对象。图5中间的脉冲波形图示意性地示出了谐振器的频率未知的输出信号。图5右图示出了TAF-DPS锁频环FLL，该TAF-DPS锁频环FLL检测该输出信号的频率。具体地，其中，将谐振器的频率未知的输出信号输入至锁频环FLL作为参考信号，将参考信号与由TAF-DPS时钟发生器生成的时钟信号在频率方面相比较，并且根据比较结果迭代地调整TAF-DPS时钟发生器的控制字F，直至所生成的时钟信号的频率与参考信号的频率一致，从而根据控制字F求出参考信号的频率。例如在测量电容性和电感性感测装置输出的电压信号的情况下，可以进而得出电阻性和电容性感测装置的电容值和电阻值变化。
图5示出的锁频环FLL包括：
频率检测器FD，连接在频率检测器FD下游的低通滤波器LPF、连接在低通滤波器LPF下游的TAF-DPS DCO，和连接在TAF-DPS DCO与频率检测器FD之间的分频器，
其中，频率检测器FD检测出输入至频率检测器FD的参考信号的频率fr与来自分频器的信号的频率fo’之间的差异，并且输出差异变量，低通滤波器LPF对该差异变量进行低通滤波以去除高频分量后，生成用于下游的TAF-DPS DCO的控制变量，该控制变量包含控制字F，随后，TAF-DPS DCO根据该控制变量生成频率为fo的输出信号，该输出信号被分频器以1/N的系数分频后得到频率为fo’的信号并且所述频率为fo’的信号被传送到频率检测器FD，其中N为大于等于1的整数。
其中分频器也可以被省略，则锁频环FLL的输出信号fo直接输入至频率检测器FD。频率检测器FD检测出输入至频率检测器FD的所述参考信号的频率fr与所述锁频环FLL的输出信号的频率fo之间的差异，并且输出差异变量，低通滤波器LPF对该差异变量进行低通滤波以去除高频分量后，生成用于下游的TAF-DPS DCO的控制变量，该控制变量包含控制字F，随后，TAF-DPS DCO根据该控制变量生成频率为fo的输出信号，该输出信号被传送到频率检测器FD。
在该实施例中，差异变量和控制变量都是数字值。
该基于TAF-DPS时钟发生器的锁频环的优点相应于基于TAF-DPS时钟发生器的游标卡尺的优点。
图6示意性地示出了用于频率检测的原理图。其中取两个频率分别为fin和fDCO的第一信号和第二信号作为驱动时钟。该第二信号例如得自TAF-DPS时钟发生器。先通过上升沿和下降沿的检测确定第二信号的周期。再确定在第二信号的每个周期内检测到的第一信号的上升沿数目。如果在第二信号的一个周期内检测到第一信号的两个或更多个上升沿，则可以确定fin>fDCO的事实。否则，以第二信号的半个周期为基础，该半个周期包括第二信号的一个上升沿和一个下降沿。以所述第二信号的半个周期内的上升沿和下降沿为采样时间点对第一信号进行采样，如果采样到第一信号的一个上升沿和一个下降沿，则认为fin＝fDCO。否则，认为fin<fDCO。根据本公开的用于检测两个输入信号的频率之间的关系的方法可以简单快速且低成本地实现。
本公开还提供了一种用于识别电压信号的频率的方法，其中，将电压信号输入至频率可调的频率源，该频率可调的频率源识别所输入的电压信号的频率。
图7示意性地示出了根据本公开的用于识别电压信号的频率的方法的 一个实施例，其中，利用频率可调的频率源探测电阻性和电容性感测装置的电阻值和电容值变化，包括如下步骤：
步骤700：通过电阻性和电容性感测装置将电阻值和电容值转换为电压输出信号；
步骤710：将所述电压输出信号传送至频率源并且通过所述频率源识别所述电压输出信号的频率；
步骤720：确认所述电压输出信号的频率与之前存储在所述电阻性和电容性感测装置中的电压输出信号的频率相比是否有变化，如果有，则
步骤730：确定电阻值和电容值有变化。
在本公开的一个实施形式中，将包括TAF-DPS时钟发生器的电路用作所述频率源，其中，所述TAF-DPS时钟发生器具有：
第一输入端，用于接收基础时间单元△，
第二输入端，用于接收频率/周期控制字F＝I+r，其中，I是整数，0≦r<1，
直接周期合成单元，用于创建第一周期TA＝I*△和第二周期TB＝(I+1)*△，
输出端，用于输出时钟信号，该时钟信号是具有第一周期TA的脉冲和具有第二周期TB的脉冲以交织方式构成的，其中，第一周期TA和第二周期TB的出现可能性由r的值控制，具体地，第一周期TA出现可能性为(1-r)％，第二周期TB出现可能性为r％，
其中，所述TAF-DPS时钟发生器的频率和周期根据所述时钟信号的时间平均频率计算为1/fTAF＝TTAF＝F*△，所述控制字F与其输出周期呈线性关系,因此与被测的电阻性和电容性感测装置的电容值或电阻值呈一一对应线性关系，从而得出电容值和电阻值的变化。
在本公开的一个实施形式中，将所述电阻性和电容性感测装置的输出信号输入至基于所述TAF-DPS时钟发生器构建的锁频环FLL作为参考信号，
将所述参考信号与由所述TAF-DPS时钟发生器生成的时钟信号在频率方面相比较，
根据比较结果迭代地调整所述TAF-DPS时钟发生器的控制字F，直至所生成的时钟信号的频率与所述参考信号的频率一致，从而根据所述控制字F求出所述参考信号的频率，以及
得出所述电阻性和电容性感测装置的电容值和电阻值变化。
在本公开的一个实施形式中，所述锁频环FLL包括：
频率检测器FD，连接在所述频率检测器FD下游的低通滤波器LPF、连接在所述低通滤波器LPF下游的TAF-DPS DCO。
在本公开的一个实施形式中，通过频率检测器FD检测出输入至频率检测器FD的所述参考信号的频率fr与所述锁频环FLL的输出信号的频率fo之间的差异，并且输出差异变量，
通过低通滤波器LPF对该差异变量进行低通滤波以去除高频分量后，生成用于下游的TAF-DPS DCO的控制变量，该控制变量包含控制字F，
通过TAF-DPS DCO根据该控制变量生成频率为fo的输出信号，以及
将该输出信号传送到频率检测器FD。
在本公开的一个实施形式中，在频率检测器FD中，确定在所述锁频环FLL的、频率fo已知的输出信号的每个周期内检测到的所述参考信号的上升沿数目，其中，所述参考信号的频率fr未知，
如果在所述输出信号的一个周期内检测到所述参考信号的两个或更多个上升沿，则可以确定fr>fo的事实，
否则，以所述输出信号的半个周期为基础，该半个周期包括所述输出信号的一个上升沿和一个下降沿，以所述输出信号的半个周期内的该上升沿和该下降沿为采样时间点对所述参考信号进行采样，如果采样到所述参考信号的一个上升沿和一个下降沿，则认为fr＝fo，否则，认为fr<fo。
在本公开的一个实施形式中，所述锁频环FLL还包括连接在TAF-DPS DCO与频率检测器FD之间的分频器。
在本公开的一个实施形式中，通过频率检测器FD检测出输入至频率检测器FD的所述参考信号的频率fr与来自分频器的信号频率fo’之间的差异，并且输出差异变量，
通过低通滤波器LPF对该差异变量进行低通滤波以去除高频分量后，生成用于下游的TAF-DPS DCO的控制变量，该控制变量包含控制字F，
通过TAF-DPS DCO根据该控制变量生成频率为fo的输出信号，
将该输出信号借助分频器以1/N的系数分频后得到频率为fo’的信号，以及
将所述频率为fo’的信号传送到频率检测器FD，其中N为大于等于1的 整数。
在本公开的一个实施形式中，在频率检测器FD中，确定在来自分频器的、频率fo’的每个周期内检测到的所述参考信号的上升沿数目，其中，所述参考信号的频率fr未知，
如果在所述输出信号的一个周期内检测到所述参考信号的两个或更多个上升沿，则可以确定fr>fo’的事实，
否则，以所述输出信号的半个周期为基础，该半个周期包括所述输出信号的一个上升沿和一个下降沿，以所述输出信号的半个周期内的该上升沿和该下降沿为采样时间点对所述参考信号进行采样，如果采样到所述参考信号的一个上升沿和一个下降沿，则认为fr＝fo’，否则，认为fr<fo’。
在本公开的一个实施形式中，所述差异变量和所述控制变量都是数字值。
本公开还提供了一种包括根据本公开的频率可调的频率源的电子设备。
本公开从现有技术中利用频率源检测未知的参考频率时检测精度受频率源的频率制约这一问题出发，提出了基于TAF-DPS的时钟发生器的频率可变的频率源。具体地给出了基于TAF-DPS的时钟发生器的游标卡尺以及基于TAF-DPS的时钟发生器的锁频环。通过修改TAF-DPS时钟发生器的位数，可以调节频率检测时的精度。另外，在基于TAF-DPS的时钟发生器的游标卡尺以及基于TAF-DPS时钟发生器的锁频环中都可以采用基于TAF-DPS的数位控制振荡器DCO来作为时钟发生器。其优点是可以全数字化地实现。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (17)

  1. 一种频率可调的频率源，其具有输入端用于接收所输入的电压信号，所述频率源识别所输入的电压信号的频率，并且所述频率源包括时间平均频率直接周期合成TAF-DPS时钟发生器，其中，所述TAF-DPS时钟发生器具有：
    第一输入端，用于接收基础时间单元△，
    第二输入端，用于接收频率/周期控制字F＝I+r，其中，I是整数，0≦r<1，
    直接周期合成单元，用于创建第一周期TA＝I*△和第二周期TB＝(I+1)*△，
    输出端，用于输出时钟信号，所述时钟信号是具有第一周期TA的脉冲和具有第二周期TB的脉冲以交织方式构成的，其中，第一周期TA和第二周期TB的出现可能性由r的值控制，
    其中，所述TAF-DPS时钟发生器的频率和周期根据所述时钟信号的时间平均频率计算为1/fTAF＝TTAF＝F*△，所述控制字F与其输出周期呈线性关系。
  2. 根据权利要求1所述的频率源，其特征在于，所述基础时间单元△是由多级压控振荡器产生的，其中通过锁相环将所述多级压控振荡器锁定至参考频率，从而所述多级压控振荡器的频率fvco是已知值，所述多级压控振荡器输出K个相位均匀信号，其中K是大于1的整数，从而所述基础时间单元△可以计算为：
    Δ＝TVCO/K＝1/(K·fvco)，
    其中，TVCO代表所述多级压控振荡器的周期。
  3. 根据权利要求1或2所述的频率源，其特征在于，I和r是由用户输入的，其中，所述TAF-DPS时钟发生器的频率的精度与分配给r的位数对应。
  4. 根据权利要求1或2所述的频率源，其特征在于，所述频率源包括TAF-DPS游标卡尺，所述TAF-DPS游标卡尺包括：
    第一TAF-DPS时钟发生器，用作慢TAF-DPS时钟发生器，所述第一TAF-DPS时钟发生器具有第二输入端，用于接收慢控制字Fslow，所述第一 TAF-DPS时钟发生器还具有第三输入端，用于接收所述输入的电压信号的一个脉冲周期的开始信号，所述第一TAF-DPS时钟发生器在输出端输出慢时钟信号，
    第二TAF-DPS时钟发生器，用作快TAF-DPS时钟发生器，所述第二TAF-DPS时钟发生器具有第二输入端，用于接收快控制字Ffast，所述第二TAF-DPS时钟发生器还具有第三输入端，用于接收所述输入的电压信号的所述脉冲周期的结束信号，所述第二TAF-DPS时钟发生器在输出端输出快时钟信号，
    相位检测器，用于检测所述慢时钟信号和所述快时钟信号的重合点，其中，在重合点上所述慢时钟信号和所述快时钟信号的边沿对齐，其中，所述相位检测器具有第一输入端用于接收所述慢时钟信号，第二输入端用于接收所述快时钟信号，和输出端用于在检测到所述重合点时输出重置信号，
    第一数字计数器，具有时钟输入端用于接收所述慢时钟信号，重置输入端用于接收来自所述相位检测器的重置信号，以及输出端用于在接收到重置信号时输出所述第一数字计数器存储的所述慢时钟信号，其中，所输出的慢时钟信号的循环个数被存储为第一数字值，并且在输出所存储的慢时钟信号后，所述第一数字计数器被重置，
    第二数字计数器，具有时钟输入端用于接收所述快时钟信号，重置输入端用于接收来自所述相位检测器的重置信号，以及输出端用于在接收到重置信号时输出所述第二数字计数器存储的所述快时钟信号，其中，所输出的快时钟信号的循环个数被存储为第二数字值，并且在输出所存储的快时钟信号后，所述第二数字计数器被重置，
    计算模块，用于根据第一数字值和第二数字值计算所述开始信号和所述结束信号之间的飞行时间(TOF)，从而得出所述输入的电压信号的周期。
  5. 根据权利要求4所述的频率源，其特征在于，慢控制字Fslow＝I，其中I是大于等于2的整数，快控制字Ffast＝(I-1)+r。
  6. 根据权利要求4所述的频率源，其特征在于，所述第一TAF-DPS时钟发生器包括：
    第一数位控制振荡器，用于生成慢基础时间单元△slow，
    第一TAF-DPS频率合成器，其根据所述慢控制字Fslow和得自所述第一数位控制振荡器的慢基础时间单元△slow输出慢TAF时钟信号。
  7. 根据权利要求4所述的频率源，其特征在于，所述第二TAF-DPS时钟发生器包括：
    第二数位控制振荡器，用于生成快基础时间单元△fast，
    第二TAF-DPS频率合成器，其根据所述快控制字Ffast和得自所述第二数位控制振荡器的快基础时间单元△fast输出快TAF时钟信号，
    1×PLL，其中1×PLL表示分频比为1的锁相环，用于从所述第二TAF-DPS频率合成器接收所述快TAF时钟信号作为所述锁相环的输入信号，并且根据所述输入信号输出慢时钟信号作为所述锁相环的输出信号，其中，所述输入信号与所述输出信号的频率比是1。
  8. 根据权利要求1或2所述的频率源，其特征在于，所述频率源包括基于所述TAF-DPS时钟发生器构建的锁频环，其中，将所述输入的电压信号输入至所述锁频环作为参考信号，将所述参考信号与由所述TAF-DPS时钟发生器生成的时钟信号在频率方面相比较，并且根据比较结果迭代地调整所述TAF-DPS时钟发生器的控制字F，直至所生成的时钟信号的频率与所述参考信号的频率一致，从而根据所述控制字F求出所述参考信号的频率。
  9. 根据权利要求8所述的频率源，其特征在于，所述锁频环包括：
    频率检测器，连接在所述频率检测器下游的低通滤波器、连接在所述低通滤波器下游的TAF-DPS数位控制振荡器。
  10. 根据权利要求9所述的频率源，其特征在于，所述频率检测器被配置为检测出输入至所述频率检测器的所述参考信号的频率fr与所述锁频环的输出信号的频率fo之间的差异，并且输出差异变量；所述低通滤波器被配置为对所述差异变量进行低通滤波以去除高频分量之后，生成用于下游的所述TAF-DPS数位控制振荡器的控制变量，其中所述控制变量包含控制字F；所述TAF-DPS数位控制振荡器被配置为根据所述控制变量生成频率为fo的输出信号，其中所述输出信号被传送到所述频率检测器。
  11. 根据权利要求9所述的频率源，其特征在于，所述锁频环还包括连接在所述TAF-DPS数位控制振荡器与所述频率检测器之间的分频器。
  12. 根据权利要求11所述的频率源，其特征在于，所述频率检测器被配置为检测出输入至所述频率检测器的所述参考信号的频率fr与来自分频器的信号频率fo’之间的差异，并且输出差异变量；所述低通滤波器被配置为对所述差异变量进行低通滤波以去除高频分量之后，生成用于下游的所述 TAF-DPS数位控制振荡器的控制变量，其中所述控制变量包含控制字F；所述TAF-DPS数位控制振荡器被配置为根据所述控制变量生成频率为fo的输出信号；所述分频器被配置为以1/N的系数对所述输出信号进行分频以产生频率为fo’的信号，并且将所述频率为fo’的信号传送到所述频率检测器，其中N为大于等于1的整数。
  13. 根据权利要求10或12所述的频率源，其特征在于，所述差异变量和所述控制变量都是数字值。
  14. 一种探测电阻性和电容性感测装置的电阻值和电容值变化的系统，其特征在于，所述系统包括根据权利要求1至13任一项所述的频率源、所述电阻性和电容性感测装置和比较单元，其中，所述电阻性和电容性感测装置将电阻值和电容值转换为电压信号，所述频率源识别所述电压信号的频率，其中，所述比较单元将识别出的频率与之前存储的所述电阻性和电容性感测装置的电压信号的频率相比较，在确定电压信号的频率有变化的情况下，确定所述电阻性和电容性感测装置的电阻值和电容值有变化。
  15. 根据权利要求14所述的系统，其特征在于，所述电阻性和电容性感测装置是弛张振荡器，其中，弛张振荡器包括运算放大器和连接在运算放大器的一个输入端的感测电容器，其中，运算放大器输出电压信号，所述电压信号具有与所述弛张振荡器中的电阻值和电容值有关的频率。
  16. 一种识别电压信号的频率的方法，其中，将电压信号输入至根据权利要求1至13任一项所述的频率可调的频率源，所述频率源识别所输入的电压信号的频率，所述方法包括如下步骤：
    通过电阻性和电容性感测装置将电阻值和电容值转换为电压信号；
    将所述电压信号传送至所述频率可调的频率源并且通过所述频率可调的频率源识别所述电压信号的频率；
    确认所述电压信号的频率与之前存储的所述电阻性和电容性感测装置的电压信号的频率相比是否有变化，如果有，则确定电阻值和电容值有变化。
  17. 一种包括根据权利要求1至13中任一项所述的频率源的电子设备。
PCT/CN2017/098825 2017-01-04 2017-08-24 频率可调的频率源和相关的系统、方法和电子设备 WO2018126706A1 (zh)

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