WO2018125105A1 - Mise en forme d'un gabarit d'oxydes complexes en vue d'une intégration ferroélectrique et magnétoélectrique - Google Patents

Mise en forme d'un gabarit d'oxydes complexes en vue d'une intégration ferroélectrique et magnétoélectrique Download PDF

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WO2018125105A1
WO2018125105A1 PCT/US2016/069023 US2016069023W WO2018125105A1 WO 2018125105 A1 WO2018125105 A1 WO 2018125105A1 US 2016069023 W US2016069023 W US 2016069023W WO 2018125105 A1 WO2018125105 A1 WO 2018125105A1
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layer
mgo
multiferroic
materials
layers
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PCT/US2016/069023
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Sasikanth Manipatruni
Chia-Ching Lin
Jasmeet S. Chawla
Dmitri E. Nikonov
Ian A. Young
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Intel Corporation
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/20—Spin-polarised current-controlled devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H10N50/85—Magnetic active materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F10/00—Thin magnetic films, e.g. of one-domain structure
    • H01F10/08—Thin magnetic films, e.g. of one-domain structure characterised by magnetic layers
    • H01F10/10—Thin magnetic films, e.g. of one-domain structure characterised by magnetic layers characterised by the composition
    • H01F10/18—Thin magnetic films, e.g. of one-domain structure characterised by magnetic layers characterised by the composition being compounds
    • H01F10/193—Magnetic semiconductor compounds
    • H01F10/1933—Perovskites

Definitions

  • Spintronics is the study of intrinsic spin of the electron and its associated magnetic moment in solid-state devices.
  • Spintronic logic are integrated circuit devices that use a physical variable of magnetization or spin as a computation variable. Such variables can be non-volatile (i.e., preserving a computation state when the power to an integrated circuit is switched off). Non-volatile logic can improve the power and computational efficiency by allowing architects to put a processor to un-powered sleep states more often and therefore reduce energy consumption.
  • Existing spintronic logic generally suffer from high energy and relatively long switching times.
  • large write current e.g., greater than 100 micro- Ampere per bit
  • MRAM Magnetic Random Access Memory
  • WER write error rate
  • MgO magnesium oxide
  • Ferroelectric and multiferroic materials can be used for building non-volatile logic. Ferroelectric and multiferroic materials are used for
  • ferroelectricity ferro-magnetism
  • multiferroic behavior ferroelectricity, ferro-magnetism, and/or multiferroic behavior. These materials require the use of crystalline and/or poly crystalline materials. However, developing consistent crystalline structures for these materials is a challenge.
  • Fig. 1A illustrates a magnetization response to applied magnetic field for a ferromagnet.
  • Fig. IB illustrates a magnetization response to applied magnetic field for a paramagnet.
  • Fig. 1C illustrates a magnetization response to applied voltage field for a paramagnet connected to a magnetoelectric layer.
  • Fig. 2A illustrates a perpendicular magnetoelectric spin orbit logic (SOL), according to some embodiments of the disclosure.
  • Fig. IB illustrates a spin orbit material stack of an interconnect, according to some embodiments of the disclosure.
  • Fig. 2C illustrates a material stack at the output of an interconnect, according to some embodiments of the disclosure.
  • Fig. 3 illustrates a material stack for multiferroic deposition on a backend of a semiconductor die, according to some embodiments of the disclosure.
  • Fig. 4 illustrates a cross-section of a templated multiferroic conductive via, according to some embodiments of the disclosure.
  • Fig. 5 illustrates a backend material stack for Bismuth Ferrite (BFO) with platinum (Pt) electrodes, according to some embodiments of the disclosure.
  • Fig. 6 illustrates a cross-section of a super lattice backend with a templating layer, according to some embodiments of the disclosure.
  • Figs. 7A-G illustrate cross-sections of a die showing fabrication of templated ferroelectric and/or ferromagnetic interconnect and vias, in accordance with some embodiments of the disclosure.
  • Figs. 8A-G illustrate cross-sections of a die showing fabrication of templated ferroelectric and/or ferromagnetic interconnect and vias, in accordance with some embodiments of the disclosure.
  • Figs. 9A-D illustrate cross-sections of ferroelectric and/or ferromagnetic interconnect or vias with various templating configurations, in accordance with some embodiments of the disclosure.
  • Fig. 10 illustrates a smart device or a computer system or a SoC (System-on-
  • Chip with templated ferroelectric, multiferroic, and/or ferromagnetic interconnects and/or vias, according to some embodiments.
  • the Magnetoelectric (ME) effect has the ability to manipulate the magnetization (and the associated spin of electrons in the material) by an applied electric field. Since an estimated energy dissipation per unit area per magnet switching event through the ME effect is an order of magnitude smaller than with spin-transfer torque (STT) effect, ME materials have the capability for next-generation memory and logic applications.
  • STT spin-transfer torque
  • perpendicular magnets Compared to in-plane magnets, perpendicular magnets generally allow for easier lithography constraints on the magnetic dots with reduced aspect ratio requirements for shape.
  • Perpendicular magnets exhibit higher retention since the magnetic energy barrier is proportional to anisotropy. Another benefit of perpendicular magnets is that they provide greater choice perpendicular anisotropy and super-lattices.
  • spin-to-charge conversion is achieved via a layer with the inverse Rashba-Bychkov effect (or spin Hall effect) wherein a spin current injected from an input magnet produces a charge current. The sign of the charge current is determined by the direction of the injected spin and thus by the direction of magnetization.
  • charge-to-spin conversion is achieved via magnetoelectric effect in which the charge current produces a voltage on a capacitor, comprising a layer with magnetoelectric effect, leading to switching magnetization of an output magnet.
  • magnetic response of a perpendicular magnet is via applied exchange bias from magnetoelectric effect.
  • a templated magnetoelectric oxide provides perpendicular exchange bias to the perpendicular magnet due to partially compensated anti-ferromagnetism.
  • high speed operation of the logic e.g., 100 picoseconds (ps)
  • ps picoseconds
  • switching energy is reduced (e.g., 1-10 attojoule (aJ)) because the current needs to be "on” for a shorter time (e.g., approximately 3 ps) in order to charge the capacitor.
  • charge current does not attenuate in the interconnect.
  • ferroelectric and ferromagnetic devices positioned in the backend of a device processing stack are templated using a templating material such as MgO.
  • a templating material such as MgO.
  • Some embodiments describe templated ferroelectric materials with Lutetium and Scandium iron oxides in the backend of the semiconductor chip.
  • Some embodiments describe templated ferroelectric materials with BFO (e.g., BiFeC ) and Nd, and La doped BiFeC in the backend of the semiconductor chip.
  • the templating material of various embodiments improves crystallinity for improving ferroelectric properties (e.g., high enough value of saturated ferroelectric polarization P s , and low value of coercive electric E c ).
  • the templating material of various embodiments improves crystallinity for improving multiferroic properties (e.g., high enough values of saturated ferroelectric polarization P s ,
  • the templating material of various embodiments can be used for forming vias for integrating ferroelectric and/or multiferroic materials.
  • the templating material of various embodiments is such that it allows the use of non-magnetic metal interconnects (e.g., Cu) to couple with the templated ferroelectric and/or multiferroic materials.
  • non-magnetic metal interconnects e.g., Cu
  • signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.
  • connection means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.
  • coupled means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.
  • circuit or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.
  • signal may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal.
  • the meaning of "a,” “an,” and “the” include plural references.
  • the meaning of "in” includes “in” and "on.”
  • phrases “A and/or B” and “A or B” mean (A), (B), or (A and B).
  • phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
  • Fig. 1A illustrates a magnetization hysteresis plot 100 for a perpendicular ferromagnet 101.
  • Plot 100 shows the magnetization response to applied magnetic field for ferromagnet 101.
  • the x-axis of plot 100 is magnetic field 'FT while the y-axis is
  • magnetization 'm' For ferromagnet (FM) 101, the relationship between 'FT and 'm' is not linear and results in a hysteresis loop as shown by curves 102 and 103.
  • the maximum and minimum magnetic field regions of the hysteresis loop correspond to saturated magnetization configurations 104 and 106, respectively.
  • saturation magnetization configurations 104 and 106 FM 101 has stable magnetizations.
  • FM 101 does not have a definite value of magnetizations, but rather depends on the history of applied magnetic fields.
  • the magnetization of perpendicular FM 101 in region 105 can be either in the +y direction or the -y direction.
  • Fig. IB illustrates magnetization plot 120 for paramagnet 121.
  • Plot 120 shows the magnetization response to applied magnetic field for paramagnet 121.
  • a paramagnet as opposed to a ferromagnet exhibits magnetization when a magnetic field is applied to it.
  • Fig. 1C illustrates a plot 130 showing magnetization response to applied voltage field for a paramagnet 131 connected to a magnetoelectric layer 132.
  • the x-axis is voltage 'V applied across ME layer 132 and y-axis is magnetization 'm'.
  • Ferroelectric polarization PFE is in ME layer 132 and is indicated by the arrow in the ME layer 132.
  • magnetization is driven by exchange bias exerted by a ME effect from ME layer 132.
  • paramagnet 131 establishes a deterministic magnetization (e.g., in the +y direction by voltage +V C ) as shown by configuration 136.
  • paramagnet 131 When negative voltage is applied to ME layer 132, paramagnet 131 establishes a deterministic magnetization (e.g., in the -y direction by voltage -V c ) as shown by configuration 134.
  • Plot 130 shows that magnetization functions 133a and 133b have hysteresis.
  • switching speeds of paramagnet as shown in Fig. IB are achieved.
  • the hysteresis behavior of FM 131 is associated with the driving force of switching rather than the intrinsic resistance of the magnet to switching.
  • Fig. 2A illustrates a perpendicular magnetoelectric spin orbit logic (SOL) 200 using templated multiferroic material, according to some embodiments of the disclosure.
  • Fig. 2B illustrates a material stack at the input from an interconnect, according to some embodiments of the disclosure.
  • Fig. 2C illustrates a perpendicular magnetoelectric material stack at the output to an interconnect, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 2A-C having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • SOL 200 comprises a first magnet 201 with perpendicular magnetic anisotropy (PMA), a stack of layers (e.g., layers 202, 203, and 204) adjacent to first magnet 201, interconnecting conductor 205 (e.g., a non-magnetic charge conductor), magnetoelectric (ME) layer 206, and second magnet 207 with PMA.
  • PMA perpendicular magnetic anisotropy
  • ME layer 206 is adjacent to second magnet 207.
  • conductor 205 is coupled to at least a portion of the stack of layers (201, 202, 203, 204) and ME layer 206.
  • conductor 205 is coupled to layer 204 of the stack.
  • a contact (not shown) is provided on top of first magnet 201, where the contact is used to connect to a transistor or any source that provides charge current.
  • the contact is formed of non-magnetic metal (e.g., Cu, Ag, etc.).
  • a non-magnetic metal layer e.g., Cu, Ag, etc. is sandwiched between first magnet 201 and the stack of layers.
  • the stack of layers is to provide an inverse Rashba-
  • the stack of layers provides spin-to-charge conversion where a spin current J s or is injected from first magnet 201 (also referred to as the input magnet) and charge current I c is generated by the stack of layers.
  • This charge current I c is provided to conductor 205 (e.g., charge interconnect).
  • charge current does not attenuate in conductor 205.
  • the direction of the charge current I c depends on the direction of magnetization of first magnet 201.
  • the charge current I c charges the capacitor around ME layer 206 and switches its polarization.
  • ME layer 206 exerts exchange bias on second magnet layer 207, and the direction of the exchange bias determines the magnetization of second magnet 207.
  • the length of first magnet is L m
  • the width of conductor 205 is
  • conductor 205 is formed of a material which includes one or more of: Cu, Ag, Al, or Au.
  • a transistor e.g., p-type transistor MPl
  • the source terminal of MPl is coupled to a supply Vdd
  • the gate terminal of MPl is coupled to a control voltage V c i (e.g., a switching clock signal that switches between Vdd and ground levels)
  • the drain terminal of MPl is coupled to first magnet 201.
  • the current Idrive from transistor MPl causes first magnet 201 to generate spin current the stack of layers (e.g., layers 202, 203, and 204).
  • ME layer 206 forms a magnetoelectric capacitor to switch PMA FM magnets.
  • the conductor 205 forms one plate of the capacitor
  • PMA FM magnet 207 forms the other plate of the capacitor
  • layer 206 is the magnetic- electric oxide that provides out-of-plane exchange bias to PMA FM magnet 207.
  • the magnetoelectric oxide comprises perpendicular exchange bias due to partially compensated anti-ferromagnetism.
  • the first magnet 201 injects a spin polarized current into the high spin-orbit coupling (SOC) material stack (e.g., layers 202, 203, and 204).
  • the spin polarization is determined by the magnetization of first magnet 201.
  • the injection stack comprises i) an interface 203 with a high density 2D (two dimensional) electron gas and with high SOC formed between materials 202 and 204 such as Ag or Bi, or ii) a bulk material 204 with high Spin Hall Effect (SHE) coefficient such as Ta, W, or Pt.
  • SHE Spin Hall Effect
  • a spacer (or template layer) is formed between first magnet 201 and the injection stack.
  • this spacer is a templating metal layer which provides a template for forming first magnet 201.
  • the metal of the spacer which is directly coupled to first magnet 201 is a noble metal (e.g., Ag, Cu, or Au) doped with other elements from Group 4d and/or 5d of the Periodic Table.
  • first magnet 201 are sufficiently lattice matched to Ag (e.g., a material which is engineered to have a lattice constant close (e.g., within 3%) to that of Ag).
  • sufficiently matched atomistic crystalline layers refer to matching of the lattice constant 'a' within a threshold level above which atoms exhibit dislocation which is harmful to the device (for instance, the number and character of dislocations lead to a significant (e.g., greater than 10%) probability of spin flip while an electron traverses the interface layer).
  • the threshold level is within 5% (i.e., threshold levels in the range of 0% to 5% of the relative difference of the lattice constants).
  • the matching improves (i.e., matching gets closer to perfect matching)
  • spin injection efficiency from spin transfer from first magnet 201 to first ISHE/ISOC stacked layer increases.
  • Poor matching e.g., matching worse than 5% implies dislocation of atoms that is harmful for the device.
  • Table 1 summarizes transduction mechanisms for converting magnetization to charge current and charge current to magnetization for bulk materials and interfaces.
  • Table 1 Transduction mechanisms for Spin to Charge and Charge to Spin Conversion
  • the spin-orbit mechanism responsible for spin-to-charge current conversion is described by the inverse Rashba-Bychkov effect in a 2D electron gases.
  • the Hamiltonian (energy) of spin-orbit coupling electrons in a 2D electron gas is:
  • IRYE is the IRYE constant (with units of length) proportional to a R .
  • IRBE effect produces spin-to-charge current conversion around 0.1 with existing materials at 10 nm (nanometers) magnet width.
  • the net conversion of the drive charge current Idrtve to magnetization dependent charge current is given as:
  • the charge current I c carried by interconnect 205, produces a voltage on the capacitor of ME layer 206 comprising templated magnetoelectric material dielectric (such as BiFeC (BFO) or CrcC ) in contact with second magnet 207 (which serves as one of the plates of the capacitor).
  • templated magnetoelectric materials are either intrinsic multiferroic or composite multiferroic structures.
  • a non-magnetic electrode e.g., Cu
  • a supply e.g., ground or Vdd
  • the sideways section of conducting interconnect 205 is aligned with the interface between layer 202 and 204 to capture sideways IRBE current.
  • materials for first and second magnets 201 and 207 have saturated magnetization M s and effecting anisotropy field Hk.
  • Saturated magnetization Ms is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material (i.e., total magnetic flux density B substantially levels off).
  • Anisotropy Hk generally refers to the material property which is directionally dependent. Materials with Hk are materials with material properties that are highly directionally dependent.
  • a top contact is attached to magnet 201.
  • materials for first and second magnets are paramagnets
  • Paramagnets are non-ferromagnetic elements with strong paramagnetism materials which have high number of unpaired spins but are not room temperature ferromagnets.
  • first and second paramagnets 201 and 207 comprise a material which includes one or more of: Platinum (Pt), Palladium (Pd), Tungsten (W), Cerium (Ce), Aluminum (Al), Lithium (Li), Magnesium (Mg), Sodium (Na), CnCb
  • Neodymium oxide KO2 (potassium superoxide), praseodymium (Pr), Samarium (Sm), Srri203 (samarium oxide), Terbium (Tb), Tb203 (Terbium oxide), Thulium (Tm), T1T12O3 (Thulium oxide), and V2O3 (Vanadium oxide).
  • the first and second paramagnets 201 and 207 comprise dopands which include one or more of: Ce, Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, and Yb.
  • the relaxation time of a paramagnet is enhanced (e.g., made shorter) by doping with materials with stronger dissipation elements to promote Spin-lattice relaxation time (Ti) and Spin-spin relaxation time (T2).
  • the term “Spin-lattice relaxation time (Ti)” generally refers to the mechanism by which the component of the magnetization vector along the direction of the static magnetic field reaches thermodynamic equilibrium with its surroundings.
  • the term “Spin-spin relaxation time (T 2 )” generally refers to a spin-spin relaxation is the mechanism by which, the transverse component of the magnetization vector, exponentially decays towards its equilibrium value.
  • first and second magnets 201 and 207 are free ferromagnets that are made from CFGG (i.e., Cobalt (Co), Iron (Fe), Germanium (Ge), or Gallium (Ga) or a combination of them).
  • first and second magnets 201 and 207 are free magnets that are formed from Heusler alloy (s).
  • Heusler alloy is ferromagnetic metal alloy based on a Heusler phase. Heusler phase is intermetallic with certain composition and face-centered cubic (FCC) crystal structure. The ferromagnetic property of the Heusler alloy is a result of a double-exchange mechanism between neighboring magnetic ions.
  • first and second magnets 201 and 207 are Heusler alloy lattices matched to Ag (i.e., the Heusler alloy is engineered to have a lattice constant close (e.g., within 3%) to that of Ag or to a rotated lattice).
  • the direction of the spin polarization is determined by the magnetization direction of first magnet 201.
  • the magnetization direction of second magnet 207 depends on the direction of the strain provided by ME layer 206, which in turn depends on the direction of an input charge current Icharge (IN).
  • first and second magnets 201 and 207 include one or more of: Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, or a combination of them.
  • Heusler alloys that form first and second magnets 201 and 207 include one or more of: Cu 2 MnAl, Cu 2 MnIn, Cu 2 MnSn, Ni 2 MnAl, Ni 2 MnIn, Ni 2 MnSn, Ni 2 MnSb, Ni 2 MnGa Co 2 MnAl, Co 2 MnSi, Co 2 MnGa, Co 2 MnGe, PdJVInAl, PdJVInln, Pd 2 MnSn, Pd 2 MnSb, Co 2 FeSi, Co 2 FeAl, Fe 2 VAl, Mn 2 VGa, Co 2 FeGe, MnGa, or MnGaRu.
  • first and second magnets 201 and 207 may determine its magnetization direction. For example, when the thickness of a ferromagnetic layer is above a certain threshold (depending on the material of the magnet, e.g., approximately 1.5 nm for CoFe), then the ferromagnetic layer exhibits magnetization direction which is in-plane. Likewise, when the thickness of the ferromagnetic layer is below a certain threshold (depending on the material of the magnet), then the ferromagnetic layer exhibits magnetization direction which is perpendicular to the plane of the magnetic layer. Other factors may also determine the direction of magnetization.
  • first and second magnets 201 and 207 have out-of-plane magnetization (e.g., pointing in the +/- z-direction).
  • factors such as surface anisotropy (depending on the adjacent layers or a multi-layer composition of the ferromagnetic layer) and/or crystalline anisotropy (depending on stress and the crystal lattice structure modification such as FCC (face centered cubic) lattice, BCC (body centered cubic) lattice, or Llo-type of crystals, where Llo is a type of crystal class which exhibits perpendicular magnetizations), can also determine the direction of magnetization.
  • FCC face centered cubic lattice
  • BCC body centered cubic lattice
  • Llo-type of crystals where Llo is a type of crystal class which exhibits perpendicular magnetizations
  • first and second magnets 201 and 207 are magnetized perpendicular to the plane of the chip having apparatus 200.
  • first and second magnets 201 and 207 with PMA are formed with multiple layers in a stack.
  • the multiple thin layers can be layers of Cobalt and Platinum (i.e., Co/Pt), for example.
  • the multiple thin layers include: Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, MgO; Mn x Ga y ; Materials with Llo crystal symmetry; or materials with tetragonal crystal structure.
  • the perpendicular magnetic layer is formed of a single layer of one or more materials.
  • the single layer is formed of MnGa.
  • the perpendicular magnetic layer includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, YIG (Yttrium iron garnet), or a combination of them.
  • the stack of layers comprises a first layer 202 comprising Ag, wherein first layer 202 is adjacent to first magnet 201; and a second layer 204 comprising a material or a hetero-structure which provided Rashba-Bychkov effect, wherein second layer 204 is adjacent to first layer 202 and to conductor 205.
  • layers 203 and 204 comprise two-dimensional materials (2D) with spin orbit interaction.
  • the 2D materials include one or more of: Mp, S, W, Se, Graphene, M0S2, ⁇ VSe2, WS2, or MoSe2.
  • the 2D materials include an absorbent which includes one or more of: Cu, Ag, Pt, Bi, Fr, or H absorbents.
  • a third layer 203 is sandwiched between first layer 202 and second layer 204 as shown.
  • the third layer 203 may be formed of special materials with the Rashba-Bychkov effect.
  • layer 203 comprises materials ROCI12, where 'R' includes one or more of: La, Ce, Pr, Nd, Sr, Sc, Ga, Al, or In, and where "Ch" is a chalcogenide includes one or more of: S, Se, or Te.
  • layer 202 and 204 are layers that form hetero-structure with Cu, Ag, Al, and/or Au.
  • the stack of layers comprises a material which includes one or more of: ⁇ -Ta, ⁇ -W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.
  • ME layer 206 is formed of a material includes one or more of: CnC or multiferroic material.
  • ME layer 206 comprises Cr and O.
  • the multiferroic material comprises BiFeC .
  • ME layer 206 comprises magnetoelectric perovskites having output out-of- plane remnant magnetization.
  • the magnetoelectric perovskites comprise a material which includes one or more of: BFO, La-BFO, or Ce-BFO.
  • ME layer 206 comprises magnetoelectric oxides having out-of-plane magnetism without ferroelectricity.
  • the magnetoelectric layer comprises a material which includes one or more of: CnO and B-CnC .
  • the material that forms ME layer 206 is a templated material.
  • templated ferroelectric materials with Lutetium and scandium iron oxides are used for forming ME layer 206.
  • templated ferroelectric materials with Nd doped BiFeCb or La doped BiFeC is used for forming ME layer 206.
  • templating material is part of the templated material.
  • Figs. 3-6 illustrate various material stacks for templated multiferroic materials that can be used for ME layer 206. The same templated material stacks can also be used for forming interconnects and via of those materials, in accordance with some embodiments. Fabrication of various ferroelectric and/or multiferroic material based interconnect and vias are described with reference to Figs. 7-8.
  • Fig. 3 illustrates a cross-section of material stack 300 for multiferroic deposition on a backend, according to some embodiments of the disclosure.
  • material stack 300 comprises templating material 301 and multiferroic or ferroelectric material 302.
  • material stack 300 may be also include backend 303 of the wafer.
  • templating material 301 is also include backend 303 of the wafer.
  • templating material 301 comprises one or more of:
  • multiferroic or ferroelectric material 302 comprises one or more of: LuFe204, LuFeC , LU2O3, h-LuFeCb (e.g., hexagonal LuFeC ), Fe203, Fe304, BiFeC (Bismuth Ferrite also referred to as BFO), Nd-BiFeC (e.g., Nd doped BFO material), layers of Pt and BiFe03, and layers of Pt and Nd-BiFe03.
  • MgO when deposited at appropriate conditions, MgO forms a crystalline substrate due to high stability of its crystalline phase. This highly stable crystalline substrate templates
  • Lutetium based multiferroic material in accordance with some embodiments.
  • templated ferroelectric materials i.e., 301 and 302 together
  • Lutetium and Scandium iron oxides in the backend of a semiconductor chip may comprise the following templating forming order: MgO and LuFe204, MgO and
  • LuFe03 MgO and LU2O3, and MgO and h-LuFe03, where MgO is templating material 301 and the material paired with MgO is the to-be templated material 302.
  • Table 1 illustrates a relationship of deposited MgO and ferroelectric (FE) material deposited on top.
  • MgO templates the FE material.
  • InSnO is a conductive oxide which is used for templating LuFeO class of FE materials because InSnO has a crystalline structure that matches the crystalline structure of LuFeO class of FE materials.
  • InSnO is templating layer 301 and the to-be templated material 302 are one or more of: LuFe204, LuFe03, Fe304, LU2O3, h-LuFe03, or Nd-BFO.
  • a conductive template is provided for the formation of conducting vias for FE and multiferroic materials inside a backend via.
  • Nd doped BFO Nd-BFO
  • MgO with 45 degree axial rotation is templating layer 301 and Nd doped BFO is to-be templated material 302.
  • templated ferroelectric materials i.e., 301 and 302 together
  • Lutetium and Scandium iron oxides in the backend of a semiconductor chip may comprise the following templating forming order: MgAlO and LuFe204, MgAlO and LuFe03, MgAlO and LU2O3, and MgAlO and h-LuFe03, where MgAlO is templating material 301 and the material paired with MgAlO is the to-be templated material 302.
  • templated ferroelectric materials i.e., 301 and 302 together
  • Lutetium and Scandium iron oxides in the backend of a semiconductor chip may comprise the following templating forming order: C-AI2O3 and LuFe204, C-AI2O3 and LuFeC , C-AI2O3 and LU2O3, and C-AI2O3 and h-LuFeC , where C-AI2O3 is templating material 301 and the material paired with C-AI2O3 is the to-be templated material 302.
  • templated ferroelectric materials i.e., 301 and 302 together
  • Fe and Co oxides in the backend of a semiconductor chip may comprise the following templating forming order: MgO and Fe203, MgAlO and Fe203, C-AI2O3 and Fe203, MgO and Fe304, MgAlO and Fe304, and C-AI2O3 and Fe304.
  • templated ferroelectric and multiferroic materials i.e., a thermoelectric and multiferroic materials
  • Nd doped BFO or La doped BFO may comprise the following templating forming order: MgO and BiFe03, MgAlO and BiFe03, C-AI2O3 and BiFe03, MgO and Nf-BiFe0 4 , MgAlO and Nd-BiFe0 4 , and C-AI2O3 and Nd-BiFe0 4 .
  • templated ferroelectric and multiferroic materials i.e., a thermoelectric and multiferroic materials
  • Nd doped BFO or La doped BFO with Pt insert may comprise the following templating forming order: MgO followed by Pt and BiFe03, MgAlO followed by Pt and BiFe0 3 , C-AI2O3 followed by Pt and BiFe0 3 , MgO followed by Pt and Nf-BiFe0 4 , MgAlO followed by Pt and Nd-BiFe0 4 , and C-AI2O3 followed by Pt and Nd-BiFe0 4 .
  • templating layer 301 is deposited using DC (direct current) deposition.
  • DC deposition of Mg is followed by oxygen flow.
  • RF (radio frequency) deposition of MgO is performed at cryogenic low temperature followed by annealing.
  • DC deposition Mg with oxygen flow is performed at cryogenic low temperature followed by annealing.
  • FIG. 4 illustrates cross-section 400 of a templated multiferroic conductive via, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 4 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • multiferroic conductive via 402 can be formed by using conductive templating materials 401a on top and bottom of via 402.
  • the InSnO is a conductive oxide 401a which is used for templating LuFeO class of FE materials 402 because InSnO has a crystalline structure that matches the crystalline structure of LuFeO class of FE materials.
  • the to-be templated material 402 can also be one of:
  • a conductive template is provided for the formation of conducting vias for FE and multiferroic materials inside a backend via.
  • via 402 can be templated by one of top or bottom templating layers 401a (e.g., both 401a layers may not be needed to template in some cases).
  • Fig. 5 illustrates a cross-section of a backend material stack 500 for BFO with platinum (Pt) electrodes, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 5 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • material stack 500 comprises a stack of templating materials 501a and 501b which are used to template a ferroelectric and/or multiferroic material.
  • templating material 501a comprises one of MgO, MgAlO, and C-AI2O3.
  • templating material 501b comprises Pt.
  • the to-be templated material 502 is BFO (e.g., BiFeC ) or Nd doped BFO.
  • Fig. 6 illustrates cross-section 600 of super lattice backend with a templating layer, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • templating layer 301 e.g., one of MgO, MgAlO, c-
  • AI2O3, InSnO, or Ag can be used to template a super lattice comprising layers 602a (e.g., LuFe20 4 ), 602b (e.g., LuFeOs), 602c (e.g., LuFe 2 0 4 ), and 602d (e.g., Fe 3 0 4 ).
  • layers 602a e.g., LuFe20 4
  • 602b e.g., LuFeOs
  • 602c e.g., LuFe 2 0 4
  • 602d e.g., Fe 3 0 4
  • Any combination of FE and/or multiferroic materials discussed with reference to Fig. 3 can be used with the templating material 301 to form a super lattice of FE and/or multiferroic materials.
  • These super lattice materials can be used in the backend of the die.
  • Figs. 7A-G illustrate cross-sections 700, 720, 730, 740, 750, 760, and 770, respectively, of a die showing fabrication of templated ferroelectric and/or ferromagnetic interconnect and vias, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 7A-G having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • embodiments can be performed in a different order, and some actions/fabrication processes may be performed in parallel.
  • Some of the fabrication processes listed in Figs. 2A-G are optional in accordance with certain embodiments.
  • the numbering of the fabrication processes presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.
  • Fig. 7A illustrates one example of a starting point.
  • Fig. 7B illustrates cross-section 720 of the die after deposition of ferroelectric and/or multiferroic layer 702a on layer 701.
  • This layer of ferroelectric and/or multiferroic 702a may initially have an unordered crystalline structure.
  • unordered crystalline structure generally refers to a crystalline structure in which the electron wave diffraction is not defined by Bragg' s law. Unordered materials may exhibit high directional and angular isotropy without long range
  • Unordered materials are characterized by a signature on a TEM (Transmission Electron Microscopy), STEM (Scanning Transmission Electron
  • Fig. 7C illustrates cross-section 730 of the die after deposition of a templating material 703 over ferroelectric and/or multiferroic layer 702a.
  • templating material 703 include MgO, MgAlO, C-AI2O3, InSnO, and Ag.
  • templating material 703 after increasing temperature, e.g., to 298K, templating material 703 causes ferroelectric and/or multiferroic layer 702a to transform to ferroelectric and/or multiferroic layer 702b, where ferroelectric and/or multiferroic layer 702b has an ordered crystalline structure while ferroelectric and/or multiferroic layer 702a has an unordered crystalline structure.
  • ferroelectric and/or multiferroic layer 702a is Metal 0 (M0) layer.
  • ferroelectric and/or multiferroic layer 702a can be any metal layer of a process technology node.
  • Fig. 7D illustrates cross-section 740 of the die after templating material 703 is removed and dielectric layer 704 (e.g., layer of oxide) is deposited over ordered ferroelectric and/or multiferroic layer 702b.
  • dielectric layer 704 e.g., layer of oxide
  • ordered generally refers to material condition that shows electron wave diffraction as defined by Bragg' s law. Ordered material may be characterized by one of the space groups combined with a unit cell. Ordered material exhibit long range periodicity both in direction and displacement. In Metrology tools such as XRD and RHEED, an interferometric signature is evident for ordered materials.
  • templating material 703 is a sacrificial layer which is removed after the crystalline structure of ferroelectric and/or multiferroic layer 702b is ordered to be ferroelectric and/or multiferroic layer 702a. In some embodiments, templating material 703 remains as is and further processing steps are performed above templating material 703.
  • templating material 703 and ferroelectric and/or multiferroic layer 702a/b together form a pair of layers MgO and LuFe204, MgO and LuFe03, MgO and LU2O3, and MgO and h-LuFe03, MgAlO and LuFe204, MgAlO and LuFeOs, MgAlO and Lu 2 0 3 , and MgAlO and h-LuFe0 3 , MgO followed by Pt and BiFeOs, MgAlO followed by Pt and BiFeOs, C-AI2O3 followed by Pt and BiFeOs, MgO followed by Pt and Nf-BiFe0 4 , MgAlO followed by Pt and Nd-BiFe0 4 , and C-AI2O3 followed by Pt and Nd-BiFe0 4 .
  • templating material 703 being MgO and ferroelectric and/or multiferroic layer 702a/b being Nd doped BFO a lattice of MgO is matched to a lattice of Co when rotated by 45°.
  • a crystalline axis of ferroelectric and/or multiferroic layer 702a/b is set by templating material 703.
  • Fig. 7E illustrates cross-section 750 of the die after trenches 705 are etched through dielectric layer 704. Any known suitable process of forming trenches 705 may be used.
  • two trenches are etched (e.g., the left and right trenches) and each trench is a future location of a via to couple to ferroelectric and/or multiferroic layer 702b and a future location of another metal layer.
  • the other ferroelectric and/or multiferroic layer extends orthogonal to ferroelectric and/or multiferroic layer 702b.
  • ferroelectric and/or multiferroic layer 702b is metal layer 1 (Ml) and the other metal layer (later shown as 707) is metal layer 2 (M2).
  • Fig. 7F illustrates cross-section 760 of the die after templating material 706 is deposited along the outer walls of trenches 705.
  • templating material 706 is any of the materials discussed with reference to templating material 703. Any known method for depositing templating material 706 along the outer walls may be used. In this example, templating material 706 behaves as a liner which separates the via and interconnect ferroelectric and/or multiferroic from dielectric 704.
  • Fig. 7G illustrates cross-section 770 of the die after ferroelectric and/or multiferroic 707 is deposited in trench 705.
  • material deposited for the via is different from the material deposited for the ferroelectric and/or multiferroic interconnect.
  • ferroelectric and/or multiferroic 707 is any of the materials discussed with reference to ferroelectric and/or multiferroic layer 702a/b.
  • templating material 706 causes ferroelectric and/or multiferroic 707 to transform from unordered crystalline structure to ordered crystalline structure.
  • damascene based processing method are used for creating templated interconnect 702b and 706.
  • subtractive processing methods are used for creating templating interconnect 702b and 706.
  • recess processing method are used to take advantage of the templated interconnect 702b and 706.
  • super-lattice stacks comprising of repeated patterns of template enhancing material (e.g., as those described with reference to Fig. 6) are used for ferroelectric and/or multiferroic 202b and ferroelectric and/or multiferroic 206.
  • Figs. 8A-G illustrate cross-sections 800, 820, 830, 840, 850, 860, and 870, respectively, of a die showing fabrication of templated ferroelectric and/or ferromagnetic interconnect and vias, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 8A-G having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • embodiments can be performed in a different order, and some actions/fabrication processes may be performed in parallel.
  • Some of the fabrication processes listed in Figs. 3A-G are optional in accordance with certain embodiments.
  • the numbering of the fabrication processes presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.
  • Figs. 8A-E are similar to Figs. 7A-E, and so they are not repeated again but a presented for completeness sake.
  • ferroelectric and/or multiferroic 707 is deposited into trenches 705 as illustrated with reference Fig. 8F.
  • material deposited for the via is different from the material deposited for the ferroelectric and/or multiferroic interconnect.
  • ferroelectric and/or multiferroic 807 is any of the materials discussed with reference to ferroelectric and/or multiferroic layer 802a/b.
  • templating material layer 808 is deposited over ferroelectric and/or multiferroic 807 to transfer unordered metal 807 to ordered metal 809. In some embodiments, after the crystalline structure of ferroelectric and/or multiferroic 807 is ordered, templating layer 808 may be removed. In some embodiments, after the crystalline structure of ferroelectric and/or multiferroic 807 is ordered, templating layer 808 is not removed and further processing continues. In some embodiments, templating layer 808 is formed of any of the materials of templating material 703.
  • damascene based processing method are used for creating templated interconnect 808.
  • subtractive processing methods are used for creating templating interconnect 808.
  • recess processing method are used to take advantage of the templated interconnect 808.
  • super-lattice stacks comprising of repeated patterns of template enhancing material (e.g., as those described with reference to Fig. 6) are used for ferroelectric and/or multiferroic 808.
  • Figs. 9A-D illustrate cross-sections 900, 920, and 930, respectively, of ferroelectric and/or ferromagnetic interconnect or vias with various templating
  • FIG. 9D illustrates cross-section 940 after templating layer is removed, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 9A-D having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • Cross-section 900 illustrates the case where templating material 901 is deposited on all four sides of interconnect ferroelectric and/or multiferroic 902.
  • templating material is any of the materials used for templating material 703.
  • ferroelectric and/or multiferroic 902 is any of the materials used for ferroelectric and/or multiferroic layer 702a/b.
  • the crystalline structure of templating material 901 is ordered while the crystalline structure of metal 902 is unordered.
  • the crystalline structure of templating material 901 is unordered while the crystalline structure of metal 902 is ordered.
  • Cross-section 930 illustrates the case where templating material 931 is deposited along one side of ferroelectric and/or multiferroic 902.
  • templating material 931 and ferroelectric and/or multiferroic 902 when the combination of templating material 931 and ferroelectric and/or multiferroic 902 is heated (e.g., to about 298K), unordered crystalline structure ferroelectric and/or multiferroic 902 becomes ordered.
  • Cross-section 940 illustrates the case where templating material 931 is removed after chemical processing (e.g., etching process) leaving behind an ordered ferroelectric and/or multiferroic 902 with improved resistivity.
  • Fig. 10 illustrates a smart device or a computer system or a SoC (System-on-
  • Fig. 10 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used.
  • computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.
  • the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals.
  • the transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices.
  • MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here.
  • a TFET device on the other hand, has asymmetric Source and Drain terminals.
  • BJT PNP/NPN Bi-polar junction transistors
  • BiCMOS BiCMOS
  • CMOS complementary metal-oxide-semiconductor
  • eFET eFET
  • MN indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.)
  • MP indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).
  • computing device 1600 includes first processor 1610 with templated ferroelectric, multiferroic, and/or ferromagnetic interconnects and/or vias, according to some embodiments discussed.
  • Other blocks of the computing device 1600 may also include templated ferroelectric, multiferroic, and/or ferromagnetic interconnects and/or vias, according to some embodiments.
  • the various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.
  • processor 1610 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means.
  • the processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed.
  • the processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device.
  • the processing operations may also include operations related to audio I/O and/or display I/O.
  • computing device 1600 includes audio subsystem
  • Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.
  • computing device 1600 comprises display subsystem
  • Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600.
  • Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user.
  • display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display.
  • display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.
  • computing device 1600 comprises I/O controller 1640.
  • I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.
  • I/O controller 1640 can interact with audio subsystem
  • display subsystem 1630 For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.
  • I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600.
  • the input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).
  • computing device 1600 includes power management
  • Memory subsystem 1660 includes memory devices for storing information in computing device 1600.
  • Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices.
  • Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.
  • Elements of embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein).
  • the machine-readable medium may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions.
  • a computer program e.g., BIOS
  • BIOS BIOS
  • a remote computer e.g., a server
  • a requesting computer e.g., a client
  • a communication link e.g., a modem or network connection
  • computing device 1600 comprises connectivity 1670.
  • Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices.
  • the computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.
  • Connectivity 1670 can include multiple different types of connectivity.
  • the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674.
  • Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards.
  • Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.
  • computing device 1600 comprises peripheral connections 1680.
  • Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections.
  • the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from” 1684) connected to it.
  • the computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600.
  • a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.
  • the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors.
  • Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.
  • USB Universal Serial Bus
  • MDP MiniDisplayPort
  • HDMI High Definition Multimedia Interface
  • Firewire or other types.
  • Example 1 is an apparatus which comprises: a first magnet with perpendicular magnetic anisotropy (PMA); a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse Rashba-Bychkov effect; a second magnet with PMA; a templated magnetoelectric layer adjacent to the second magnet, wherein the templated magnetoelectric layer has an ordered crystalline structure; and a conductor coupled to at least a portion of the stack of layers and the templated magnetoelectric layer.
  • PMA perpendicular magnetic anisotropy
  • Example 2 includes all features of example 1, wherein the templated magnetoelectric layer comprises a pair of materials including material A and material B, wherein material A includes one or more of: Mg, Al, In, O, Sn, MgO, MgAlO, C-AI2O3, or InSnO; and wherein material B includes one or more of: Lu, Fe, O, Nd, Bi, Pt, LuFe204, LuFeCb, LU2O3, h-LuFeCb, Fe2Cb, Fe304, BiFeCb, Nd-BiFeCb, layers of Pt and BiFeCb, or layers of Pt and Nd-BiFe0 3 .
  • material A includes one or more of: Mg, Al, In, O, Sn, MgO, MgAlO, C-AI2O3, or InSnO
  • material B includes one or more of: Lu, Fe, O, Nd, Bi, Pt, LuFe204, LuFeCb
  • Example 3 includes all features of example 3, wherein the templated magnetoelectric layer comprises magnetoelectric oxides having out-of-plane magnetism without ferroelectricity.
  • Example 4 is according to any one of examples 1 to 3, wherein the stack of materials comprise two-dimensional materials (2D) with spin orbit interaction, wherein the 2D materials include one or more of: Graphene, Mo, S, W, Se, M0S2, ⁇ VSe2, WS2, or MoSe2, and wherein the 2D materials include an absorbent which comprises one of: Cu, Ag, Pt, Bi, Fr, and H absorbents.
  • 2D materials include one or more of: Graphene, Mo, S, W, Se, M0S2, ⁇ VSe2, WS2, or MoSe2
  • the 2D materials include an absorbent which comprises one of: Cu, Ag, Pt, Bi, Fr, and H absorbents.
  • Example 5 is according to any one of examples 1 to 3, wherein the first and second magnets are magnets comprise dopants which comprise one or more of: W, Ce, Al, Li, Mg, Na, Cr 2 0 3 , CoO, Dy, Dy 2 0, Er. Er 2 0 3 , Eu, Eu 2 0 3 , Gd, Gd 2 0 3 , Fe, O, FeO, Fe 2 0 3 , Nd, Nd20 3 , K, KO2, Pr, Sm, SrmCb, Tb, Tb20 3 , Tm, TircCb, V, or V20 3 .
  • dopants comprise one or more of: W, Ce, Al, Li, Mg, Na, Cr 2 0 3 , CoO, Dy, Dy 2 0, Er. Er 2 0 3 , Eu, Eu 2 0 3 , Gd, Gd 2 0 3 , Fe, O, FeO, Fe 2 0 3 , Nd, Nd20 3 , K, KO2, Pr,
  • Example 6 is according to any one of examples 1 to 3, wherein the first and second magnets comprise one or a combination of materials: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG).
  • a Heusler alloy Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG).
  • Example 7 includes all features of example 6, wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Ga, Pd, Fe, Si, V, Ru, Cu 2 MnAl, Cu 2 MnIn, Cu 2 MnSn, Ni 2 MnAl, Ni 2 MnIn, Ni 2 MnSn, Ni 2 MnSb, Ni 2 MnGa Co 2 MnAl, Co 2 MnSi, Co 2 MnGa, Co 2 MnGe, PdJVInAl, PdJVInln, Pd 2 MnSn, Pd 2 MnSb, Co 2 FeSi, Co 2 FeAl, Fe 2 VAl, Mn 2 VGa, Co 2 FeGe, MnGa, MnGaRu, and Mn 3 X, where 'X' is one of Ga or Ge.
  • the Heusler alloy is a material which includes one or more of: Cu, M
  • Example 8 is according to any one of examples 1 to 3, wherein the first and second magnets are formed of a stack of materials, wherein the materials for the stack include one or more of: Co, Pt, Pd, Ni, Mg, O, Fe, B, Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn x Ga y ; Materials with Llo symmetry; or materials with tetragonal crystal structure.
  • the materials for the stack include one or more of: Co, Pt, Pd, Ni, Mg, O, Fe, B, Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO;
  • Example 9 is according to any one of examples 1 to 3, wherein the first and second magnets are formed of a single layer of one or more materials, and wherein the single layer comprises Mn and Ga.
  • Example 10 is according to any one of examples 1 to 3, wherein the conductor is formed of a material which includes one of: Cu, Ag, Al, or Au.
  • Example 11 is according to any one of examples 1 to 3 comprises a layer sandwiched between the stack of layers and the first magnet.
  • Example 12 includes all features of example 11 wherein the layer comprises
  • Example 13 is according to any one of claims 1 to 3 comprises a transistor coupled to the first paramagnet.
  • Example 14 is according to any one of claims 1 to 3, wherein a portion of the stack of the layers is coupled to ground, wherein the first paramagnet is coupled to a negative supply, and wherein the second paramagnet is coupled to ground.
  • Example 15 is according to any one of claims 1 to 3, wherein a portion of the stack of the layers is coupled to ground, wherein the first paramagnet is coupled to a positive supply, and wherein the second paramagnet is coupled to ground.
  • Example 16 is according to any one of claims 1 to 3, wherein the stack of layers comprise materials ROCh2, where R is a material which includes one of: La, Ce, Pr, Nd, Sr, Sc, Ga, Al, or In, and where Ch is a chalcogenide which includes one of: S, Se, or Te.
  • Example 17 is an apparatus which comprises: a multiferroic layer having an ordered crystalline structure; and a crystallinity templating layer adjacent to the multiferroic layer.
  • Example 18 includes all features of example 17, wherein the: crystallinity templating layer comprises a material which includes one or more of: Mg, Al, O, In, Sn, MgO, MgAlO, C-AI2O3, InSnO, or Ag; and multiferroic layer comprises a material which includes one or more of: Lu, Fe, O, Bi, Nd, Pt, LuFe204, LuFe03, LU2O3, h-LuFe03, Fe203, Fe 3 0 4 , BiFe0 3 , Nd-BiFe0 3 , layers of Pt and BiFe0 3 , or layers of Pt and Nd-BiFe0 3 .
  • the: crystallinity templating layer comprises a material which includes one or more of: Mg, Al, O, In, Sn, MgO, MgAlO, C-AI2O3, InSnO, or Ag
  • multiferroic layer comprises a material which includes one or
  • Example 19 includes all features of example 17, wherein when the multiferroic layer comprises BFO and the crystallinity templating layer is MgO, then a lattice of MgO is rotated by 45 degree relative to the lattice of BFO.
  • Example 20 is according to any one of examples 17 to 19, wherein a crystalline axis of the multiferroic layer is aligned with the crystallinity of templating layer.
  • Example 21 is according to any one of examples 17 to 19, wherein the crystallinity templating layer is adjacent to: three sides of the multiferroic layer; four sides of the multiferroic layer; or one side of the multiferroic layer.
  • Example 22 is an integrated circuit die which comprises: an interlay er dielectric layer; and an interconnect formed within the interlay er dielectric layer, the interconnect comprising a crystalline multiferroic or ferroelectric.
  • Example 23 includes all features of example 22, wherein the: interlayer dielectric layer comprises a material which includes one or more of: Mg, O, Mg, Al, In, Sn, MgO, MgAlO, C-AI2O3, InSnO, or Ag; and multiferroic layer comprises a material which includes one or more of: Lu, Fe, O, Fe, Bi, Fe, Pt, LuFe204, LuFe03, LU2O3, h-LuFe03, Fe 2 0 3 , Fe 3 0 4 , BiFe0 3 , Nd-BiFe0 3 , layers of Pt and BiFe0 3 , or layers of Pt and Nd-BiFe0 3 .
  • interlayer dielectric layer comprises a material which includes one or more of: Mg, O, Mg, Al, In, Sn, MgO, MgAlO, C-AI2O3, InSnO, or Ag
  • multiferroic layer comprises a material which
  • Example 24 is according to any one of examples 22 to 23, wherein when the multiferroic layer comprises BFO and the crystallinity templating layer is MgO, then a lattice of MgO is rotated by 45 degree relative to the lattice of BFO.
  • Example 25 includes all features of example 23, wherein a crystalline axis of the multiferroic layer is aligned with the crystallinity of the interlayer dielectric layer.
  • Example 26 is a system which comprises: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of apparatus examples 1 to 16, examples 17 to 21, or examples 22 to 25; and a wireless interface for allowing the processor to communicate with another device.
  • Example 27 is a method which comprises: forming a first magnet with perpendicular magnetic anisotropy (PMA); forming a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse Rashba- Bychkov effect; forming a second magnet with PMA; forming a templated magnetoelectric layer adjacent to the second magnet, wherein the templated magnetoelectric layer has an ordered crystalline structure; and forming a conductor coupled to at least a portion of the stack of layers and the templated magnetoelectric layer.
  • PMA perpendicular magnetic anisotropy
  • Example 28 includes all features of example 27, wherein the templated magnetoelectric layer comprises a pair of materials including material A and material B, wherein material A includes one or more of: Mg, Al, In, O, Sn, MgO, MgAlO, c-AhCb, or InSnO; and wherein material B includes one or more of: Lu, Fe, O, Nd, Bi, Pt, LuFe204, LuFe0 3 , LU2O3, h-LuFeCb, Fe 2 0 3 , Fe 3 0 4 , BiFe0 3 , Nd-BiFe0 3 , layers of Pt and BiFe0 3 , or layers of Pt and Nd-BiFe0 3 .
  • material A includes one or more of: Mg, Al, In, O, Sn, MgO, MgAlO, c-AhCb, or InSnO
  • material B includes one or more of: Lu, Fe, O, Nd, Bi
  • Example 29 includes all features of example 27, wherein the templated magnetoelectric layer comprises magnetoelectric oxides having out-of-plane magnetism without ferroelectricity.
  • Example 30 is according to any one of examples 27 to 29, wherein forming the stack of materials comprises forming two-dimensional materials (2D) with spin orbit interaction, wherein the 2D materials include one or more of: Graphene, Mo, S, W, Se, M0S2, ⁇ VSe2, WS2, or MoSe2, and wherein the 2D materials include an absorbent which comprises one of: Cu, Ag, Pt, Bi, Fr, and H absorbents.
  • 2D two-dimensional materials with spin orbit interaction
  • the 2D materials include one or more of: Graphene, Mo, S, W, Se, M0S2, ⁇ VSe2, WS2, or MoSe2
  • the 2D materials include an absorbent which comprises one of: Cu, Ag, Pt, Bi, Fr, and H absorbents.
  • Example 31 is according to any one of examples 27 to 29, wherein the first and second magnets are magnets comprise dopants which comprise one or more of: W, Ce, Al, Li, Mg, Na, Cr 2 0 3 , CoO, Dy, Dy 2 0, Er. Er 2 0 3 , Eu, Eu 2 0 3 , Gd, Gd 2 0 3 , Fe, O, FeO, Fe 2 0 3 , Nd, Nd 2 0 3 , K, KO2, Pr, Sm, Sm 2 0 3 , Tb, Tb 2 0 3 , Tm, Tm 2 0 3 , V, or V 2 0 3 .
  • dopants comprise one or more of: W, Ce, Al, Li, Mg, Na, Cr 2 0 3 , CoO, Dy, Dy 2 0, Er. Er 2 0 3 , Eu, Eu 2 0 3 , Gd, Gd 2 0 3 , Fe, O, FeO, Fe 2 0 3 , Nd, Nd 2
  • Example 32 is according to any one of examples 27 to 29, wherein the first and second magnets comprise one or a combination of materials: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG).
  • a Heusler alloy Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG).
  • Example 33 includes all features of example 32, wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Ga, Pd, Fe, Si, V, Ru, Cu 2 MnAl, Cu 2 MnIn, Cu 2 MnSn, Ni 2 MnAl, Ni 2 MnIn, Ni 2 MnSn, Ni 2 MnSb, Ni 2 MnGa Co 2 MnAl, Co 2 MnSi, Co 2 MnGa, Co 2 MnGe, PdJVInAl, PdJVInln, Pd 2 MnSn, Pd 2 MnSb, Co 2 FeSi, Co 2 FeAl, Fe 2 VAl, Mn 2 VGa, Co 2 FeGe, MnGa, MnGaRu, and Mn 3 X, where 'X' is one of Ga or Ge.
  • the Heusler alloy is a material which includes one or more of: Cu,
  • Example 34 is according to any one of examples 27 to 29, wherein the first and second magnets are formed of a stack of materials, wherein the materials for the stack include one or more of: Co, Pt, Pd, Ni, Mg, O, Fe, B, Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn x Ga y ; Materials with Llo symmetry; or materials with tetragonal crystal structure.
  • the materials for the stack include one or more of: Co, Pt, Pd, Ni, Mg, O, Fe, B, Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO;
  • Example 35 is according to any one of examples 27 to 29, wherein forming the first and second magnets comprise forming a single layer of one or more materials, and wherein the single layer comprises Mn and Ga.
  • Example 36 is according to any one of examples 27 to 29, wherein the conductor is formed of a material which includes one of: Cu, Ag, Al, or Au.
  • Example 37 is according to any one of examples 27 to 29comprises forming a layer sandwiched between the stack of layers and the first magnet.
  • Example 38 includes all features of example 37, wherein the layer comprises
  • Example 39 is according to any one of examples 27 to 29 comprises forming a transistor coupled to the first paramagnet.
  • Example 40 is according to any one of examples 27 to 29, wherein a portion of the stack of the layers is coupled to ground, wherein the first paramagnet is coupled to a negative supply, and wherein the second paramagnet is coupled to ground.
  • Example 41 is according to any one of examples 27 to 29, wherein a portion of the stack of the layers is coupled to ground, wherein the first paramagnet is coupled to a positive supply, and wherein the second paramagnet is coupled to ground.
  • Example 42 is according to any one of examples 27 to 29, wherein the stack of layers comprise materials ROCh2, where R is a material which includes one of: La, Ce, Pr, Nd, Sr, Sc, Ga, Al, or In, and where Ch is a chalcogenide which includes one of: S, Se, or Te.
  • Example 43 is a method which comprises: forming a multiferroic layer having an ordered crystalline structure; and forming a crystallinity templating layer adjacent to the multiferroic layer.
  • Example 44 includes all features of example 43, wherein the: crystallinity templating layer comprises a material which includes one or more of: Mg, Al, O, In, Sn, MgO, MgAlO, C-AI2O3, InSnO, or Ag; and multiferroic layer comprises a material which includes one or more of: Lu, Fe, O, Bi, Nd, Pt, LuFe204, LuFeC , LU2O3, h-LuFeC , Fe203, Fe 3 0 4 , BiFe0 3 , Nd-BiFe0 3 , layers of Pt and BiFeOs, or layers of Pt and Nd-BiFeCb.
  • the: crystallinity templating layer comprises a material which includes one or more of: Mg, Al, O, In, Sn, MgO, MgAlO, C-AI2O3, InSnO, or Ag
  • multiferroic layer comprises a material which includes one
  • Example 45 includes all features of example 44, wherein when the multiferroic layer comprises BFO and the crystallinity templating layer is MgO, then a lattice of MgO is rotated by 45 degree relative to the lattice of BFO.
  • Example 46 is according to any one of claims 44 to 45, wherein forming the multiferroic layer comprises aligning a crystalline axis of the multiferroic layer with the crystallinity of templating layer.
  • Example 47 is according to any one of examples 44 to 45 comprises positioning the crystallinity templating layer along: three sides of the multiferroic layer; four sides of the multiferroic layer; or one side of the multiferroic layer.
  • Example 48 is a method which comprises: forming an interlay er dielectric layer; and forming an interconnect formed within the interlay er dielectric layer, the interconnect comprising a crystalline multiferroic or ferroelectric.
  • Example 49 includes all features of example 48, wherein the: interlayer dielectric layer comprises a material which includes one or more of: Mg, O, Mg, Al, In, Sn, MgO, MgAlO, C-AI2O3, InSnO, or Ag; and multiferroic layer comprises a material which includes one or more of: Lu, Fe, O, Fe, Bi, Fe, Pt, LuFe204, LuFe03, LU2O3, h-LuFe03, Fe 2 0 3 , Fe 3 0 4 , BiFe0 3 , Nd-BiFe0 3 , layers of Pt and BiFe0 3 , or layers of Pt and Nd-BiFe0 3 .
  • interlayer dielectric layer comprises a material which includes one or more of: Mg, O, Mg, Al, In, Sn, MgO, MgAlO, C-AI2O3, InSnO, or Ag
  • multiferroic layer comprises a material
  • Example 50 includes all features of example 49, wherein when the multiferroic layer comprises BFO and the crystallinity templating layer is MgO, then a lattice of MgO is rotated by 45 degree relative to the lattice of BFO.
  • Example 51 is according to any one of examples 48 to 50, wherein forming the interconnect comprises aligning a crystalline axis of the multiferroic layer with the crystallinity of the interlayer dielectric layer.

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  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

L'invention concerne un appareil qui comprend : une couche multiferroïque comportant une structure cristalline ordonnée; et une couche de mise en forme de gabarit de cristallinité adjacente à la couche multiferroïque, la couche de mise en forme de gabarit de cristallinité comprenant une matière qui inclut l'un des éléments suivants : MgO, MgAlO, c-Al2O3, InSnO ou Ag; et la couche multiferroïque comprenant une matière qui inclut l'un des éléments suivants : LuFe2O4, LuFeO3, Lu2O3, h-LuFeO3, Fe2O3, Fe3O4, BiFeO3, Nd-BiFeO3, des couches de Pt et de BiFeO3 ou des couches de Pt et de Nd-BiFeO3.
PCT/US2016/069023 2016-12-28 2016-12-28 Mise en forme d'un gabarit d'oxydes complexes en vue d'une intégration ferroélectrique et magnétoélectrique WO2018125105A1 (fr)

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