WO2019066820A1 - Logique spin-orbite magnétoélectrique en cascade - Google Patents

Logique spin-orbite magnétoélectrique en cascade Download PDF

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WO2019066820A1
WO2019066820A1 PCT/US2017/053829 US2017053829W WO2019066820A1 WO 2019066820 A1 WO2019066820 A1 WO 2019066820A1 US 2017053829 W US2017053829 W US 2017053829W WO 2019066820 A1 WO2019066820 A1 WO 2019066820A1
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layer
logic device
magnet
stack
layers
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PCT/US2017/053829
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Huichu Liu
Sasikanth Manipatruni
Dmitri E. Nikonov
Tanay Karnik
Ian A. Young
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Intel Corporation
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Publication of WO2019066820A1 publication Critical patent/WO2019066820A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/18—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using Hall-effect devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1693—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/005—Digital stores in which the information is moved stepwise, e.g. shift registers with ferro-electric elements (condensers)
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
    • G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/20—Spin-polarised current-controlled devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00

Definitions

  • Spintronics is the study of intrinsic spin of the electron and its associated magnetic moment in solid-state devices.
  • Spintronic logic are integrated circuit devices that use a physical variable of magnetization or spin as a computation variable. Such variables can be non-volatile (e.g., preserving a computation state when the power to an integrated circuit is switched off). Non-volatile logic can improve the power and computational efficiency by allowing architects to put a processor to un-powered sleep states more often and therefore reduce energy consumption.
  • Existing spintronic logic generally suffer from high energy and relatively long switching times.
  • MRAM Magnetic Random Access Memory
  • MTJs Magnetic Tunnel Junctions
  • WERs write error rates
  • MgO magnesium oxide
  • Fig. 1A illustrates a magnetization response to an applied magnetic field for a ferromagnet.
  • Fig. IB illustrates a magnetization response to an applied magnetic field for a paramagnet.
  • Fig. 1C illustrates a magnetization response to an applied voltage field for a paramagnet connected to a magnetoelectric layer.
  • Fig. 2 ⁇ illustrates a unidirectional magnetoelectric spin orbit (MESO) logic, according to some embodiments of the disclosure.
  • Fig. 2B illustrates a spin orbit material stack at the input of an interconnect, according to some embodiments of the disclosure.
  • Fig. 2C illustrates a magnetoelectric material stack at the output of an interconnect, according to some embodiments of the disclosure.
  • Fig. 3A illustrates an equivalent circuit model for a first section of the unidirectional MESO logic of Fig. 2A, in accordance with some embodiments.
  • Fig. 3B illustrates an equivalent circuit model for a second section of the unidirectional MESO logic of Fig. 2A, in accordance with some embodiments.
  • Figs. 4A-B illustrate a ferroelectric Landau Khalatnikov (LK) model and corresponding plot showing two ferroelectric states.
  • LK Landau Khalatnikov
  • Fig. 5 illustrates a unidirectional cascaded MESO logic, according to some embodiments of the disclosure.
  • Fig. 6 illustrates a plot showing transient simulation of the unidirectional cascaded MESO logic of Fig. 5, according to some embodiments of the disclosure.
  • Fig. 7 illustrates a counter (or ring-oscillator) comprising a unidirectional cascaded MESO logic, according to some embodiments of the disclosure.
  • Figs. 8A-C illustrate plots showing simulation results of the counter of Fig. 7, according to some embodiments of the disclosure.
  • FIG. 9 illustrates an apparatus showing a series of cascaded unidirectional
  • Fig. 10 illustrates a smart device or a computer system or a SoC (System-on-
  • the Magnetoelectric (ME) effect has the ability to manipulate the
  • ME materials have the capability for next-generation memory and logic applications.
  • MESO Magnetoelectric Spin Orbit
  • Various embodiments describe a MESO Logic which is a combination of various physical phenomena for spin-to-charge and charge-to-spin conversion, where the MESO logic comprises an input magnet and stack of layers for spin-to-charge conversion.
  • Spin-to-charge conversion is achieved via one or more layers with the inverse Rashba- Edelstein effect (or spin Hall effect) wherein a spin current injected from the input magnet produces a charge current. The sign of the charge current is determined by the direction of the injected spin and thus of magnetization.
  • charge-to-spin conversion is achieved via magnetoelectric effect in which the charge current produces a voltage on a capacitor, comprising a layer with magnetoelectric effect, leading to switching magnetization of an output magnet.
  • magnetic response of a magnet is according to an applied exchange bias from the magnetoelectric effect.
  • a multi-phase clock is used with transistors to cascade multiple MESO logic devices.
  • a 3-phase clock is used to prevent back propagation of current from the output magnet to towards the input magnet.
  • the clocks control the power supply of each MESO logic/device. For example, when clock phase is low, power supply is coupled to the magnet of the MESO logic/device.
  • merely two series connected MESO devices conduct while other MESO devices in the cascaded logic are prevented from conducting. As such,
  • signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.
  • connection means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.
  • coupled means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.
  • circuit or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.
  • signal may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal.
  • the meaning of "a,” “an,” and “the” include plural references.
  • the meaning of "in” includes “in” and "on.”
  • phrases “A and/or B” and “A or B” mean (A), (B), or (A and B).
  • phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
  • the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals.
  • the transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices.
  • MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here.
  • a TFET device on the other hand, has asymmetric Source and Drain terminals.
  • BJT PNP/NPN Bi-polar junction transistors
  • BiCMOS BiCMOS
  • CMOS complementary metal-oxide-semiconductor
  • eFET eFET
  • MN indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.)
  • MP indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).
  • Fig. 1A illustrates a magnetization hysteresis plot 100 for ferromagnet 101.
  • the plot shows magnetization response to applied magnetic field for ferromagnet 101.
  • the x-axis of plot 100 is magnetic field 'H' while the y-axis is magnetization 'm' .
  • the relationship between 'FT and 'm' is not linear and results in a hysteresis loop as shown by curves 102 and 103.
  • the maximum and minimum magnetic field regions of the hysteresis loop correspond to saturated magnetization configurations 104 and 106, respectively. In saturated magnetization configurations 104 and 106, FM 101 has stable magnetizations.
  • FM 101 does not have a definite value of magnetization, but rather depends on the history of applied magnetic fields.
  • the magnetization of FM 101 in configuration 105 can be either in the +x direction or the -x direction for an in-plane FM.
  • changing or switching the state of FM 101 from one magnetization direction (e.g., configuration 104) to another magnetization direction (e.g., configuration 106) is time consuming resulting in slower nanomagnets response time. It is associated with the intrinsic energy of switching proportional to the area in the graph contained between curves 102 and 103.
  • Semi-insulating or insulating magnets also have a hysteresis curve, and can be used as magnets in various embodiments.
  • Fig. IB illustrates magnetization plot 120 for paramagnet 121.
  • Plot 120 shows the magnetization response to applied magnetic field for paramagnet 121.
  • the x-axis of plot 120 is magnetic field 'FT while the y-axis is magnetization 'm' .
  • a paramagnet as opposed to a ferromagnet, exhibits magnetization when a magnetic field is applied to it.
  • Paramagnets generally have magnetic permeability greater or equal to one and hence are attracted to magnetic fields.
  • the magnetic plot 120 of Fig. IB does not exhibit hysteresis which allows for faster switching speeds and smaller switching energies between the two saturated magnetization configurations 124 and 126 of curve 122.
  • Fig. 1C illustrates plot 130 showing magnetization response to applied voltage field for a paramagnet 131 connected to a magnetoelectric layer 132.
  • the x-axis is voltage 'V applied across ME layer 132 and y-axis is magnetization 'm'.
  • Ferroelectric polarization 'PFE' is in ME layer 132 is indicated by an arrow.
  • magnetization is driven by exchange bias exerted by a ME effect from ME layer 132.
  • a ME effect When positive voltage is applied to ME layer 132, paramagnet 131 establishes a deterministic magnetization (e.g., in the +x direction by voltage +V C ) as shown by configuration 136.
  • negative voltage is applied by ME layer 132, paramagnet 131 establishes a
  • Plot 130 shows that magnetization functions 133a and 133b have hysteresis.
  • ME layer 132 by combining ME layer 132 with paramagnet 131, switching speeds of paramagnet as shown in Fig. IB are achieved.
  • the hysteresis behavior of FM 131 is associated with the driving force of switching rather than the intrinsic resistance of the magnet to switching.
  • Fig. 2A illustrates a unidirectional magnetoelectric spin orbit (MESO) logic, according to some embodiments of the disclosure.
  • Fig. 2B illustrates a material stack at the input of an interconnect, according to some embodiments of the disclosure.
  • Fig. 2C illustrates a unidirectional magnetoelectric spin orbit (MESO) logic, according to some embodiments of the disclosure.
  • FIG. 2A-C illustrates a magnetoelectric material stack at the output of an interconnect, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 2A-C having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • MESO logic 200 comprises a first magnet 201, a stack of layers (e.g., layers 202, 203, and 204, also labeled as 202a/b, 203a/b, and 204a/b), interconnecting conductor 205 (e.g., a non-magnetic charge conductor), magnetoelectric (ME) layer 206 (206a/b), second magnet 207, first contact 209a, and second contact 209b.
  • interconnecting conductor 205 e.g., a non-magnetic charge conductor
  • ME magnetoelectric
  • first and second magnets 201 and 207 respectively, have in-plane magnetic anisotropy.
  • first magnet 201 comprises first and second portions, wherein the first portion of first magnet 201 is adjacent to the stack of layers (e.g., layers 202a, 203a, and 204a), and wherein the second portion of first magnet 201 is adjacent to a magnetoelectric material stack or layer 206b.
  • second magnet 207 comprises first and second portions, wherein the first portion of second magnet 207 is adjacent to the magnetoelectric material stack or layer 206a, and wherein the second portion of second magnet 207 is adjacent to stack of layers (e.g., layers 202b, 203b, and 204b).
  • conductor 205 (or charge interconnect) is coupled to at least a portion of the stack of layers (e.g., one of layers 202a, 203a, or 204a) and ME layer 206a.
  • conductor 205 is coupled to layer 204a of the stack.
  • the stack of layers (e.g., layers 202a/b, 203a/b, or
  • the stack of layers provide spin-to-charge conversion where a spin current Is (or spin energy J s ) is injected from first magnet 201 and charge current I c is generated by the stack of layers.
  • This charge current I c is provided to conductor 205 (e.g., charge interconnect).
  • conductor 205 e.g., charge interconnect
  • charge current does not attenuate in conductor 205.
  • the direction of the charge current I c depends on the direction of
  • the charge current I c charges the capacitor around ME layer 206a and switches its polarization.
  • ME layer 206a exerts exchange bias on second magnet layer 207, and the direction of the exchange bias determines the magnetization of second magnet 207.
  • ME layer 206b which exerts exchange bias on first magnet 201 according to input charge current on conductor 211a.
  • the length of first magnet 201 is L m , the width of conductor
  • conductor 205 is Wc
  • the length of conductor 205 from the interface of layer 204a to ME layer 206a is Lc
  • t c is the thickness of the magnets 201 and 207
  • ⁇ is the thickness of ME layer 206a.
  • conductor 205 comprises a material including one of: Cu, Ag, Al, or Au.
  • Icharge(iN) or IIN
  • interconnect 21 la e.g., charge interconnect made of same material as interconnect 205.
  • interconnect 21 la is coupled to first magnet 201 via ME layer 206b.
  • interconnect 21 la is orthogonal to first magnet 201.
  • interconnect 211a extends in the +x direction while first magnet 201 extends in the -y direction.
  • Icharge(iN) is converted to corresponding magnetic polarization of 201 by ME layer 206b.
  • the materials for ME layers 206a/b are the same as the materials of ME layer 206.
  • an output interconnect 21 lb is provided to transfer output charge current Icharge(OUT) to another logic or stage.
  • output interconnect 21 lb is coupled to second magnet 207 via a stack of layers that exhibit spin Hall effect and/or Rashba Edelstein effect.
  • layers 202b, 203b, and 204b are provided as a stack to couple output interconnect 21 1b with second magnet 207.
  • layers 202b, 203b, and 204b are formed of the same material as layers 202a, 203a, and 204a, respectively.
  • ME layer 206a/b forms the magnetoelectric capacitor to switch the magnets 201/207.
  • conductor 205 forms one plate of the capacitor
  • magnet 207 forms the other plate of the capacitor
  • layer 206a is the magnetic-electric oxide that provides out-of-plane exchange bias to second magnet 207.
  • the magnetoelectric oxide comprises perpendicular exchange bias due to partially
  • first magnet 201 injects a spin polarized current into the high spin-orbit coupling (SOC) material stack (e.g., layers 202a, 203a, and 204a).
  • SOC spin-orbit coupling
  • the stack comprises i) an interface 203a/b with a high density 2D (two dimensional) electron gas and with high SOC formed between 202a/b and 204a/b materials such as Ag or Bi, or ii) a bulk material 204 with high Spin Hall Effect (SHE) coefficient such as Ta, W, or Pt.
  • a spacer (or template layer) is formed between first magnet 201 and the injection stack. In some embodiments, this spacer is a templating metal layer which provides a template for forming first magnet 201.
  • the metal of the spacer which is directly coupled to first magnet 201 is a noble metal (e.g., Ag, Cu, or Au) doped with other elements from Group 4d and/or 5d of the Periodic Table.
  • first magnet 201 (and by extension first semi- insulating magnet 209a) are sufficiently lattice matched to Ag (e.g., a material which is engineered to have a lattice constant close (e.g., within 3%) to that of Ag).
  • sufficiently matched atomistic crystalline layers refer to matching of the lattice constant 'a' within a threshold level above which atoms exhibit dislocation which is harmful to the device (for instance, the number and character of dislocations lead to a significant (e.g., greater than 10%) probability of spin flip while an electron traverses the interface layer).
  • the threshold level is within 5% (i.e., threshold levels in the range of 0% to 5% of the relative difference of the lattice constants).
  • the matching improves (i.e., matching gets closer to perfect matching)
  • spin injection efficiency from spin transfer from first magnet 201 to first ISHE/ISOC stacked layer increases.
  • Poor matching e.g., matching worse than 5% implies dislocation of atoms that is harmful for the device.
  • Table 1 summarizes transduction mechanisms for converting magnetization to charge current and charge current to magnetization for bulk materials and interfaces.
  • Table 1 Transduction mechanisms for Spin to Charge and Charge to Spin Conversion
  • a transistor e.g., n-type transistor MN1 is coupled to first contact 209a.
  • the drain terminal of transistor MN1 is coupled to a supply Vdd
  • the gate terminal of transistor MN1 is coupled to a control voltage Vciki (e.g., a switching clock signal, which switches between Vdd and ground)
  • the source terminal of transistor MN1 is coupled to first contact 209a.
  • first contact 209a is made of any suitable conducting material used to connect the transistor to the first magnet 201.
  • the current Idrfve (or ISUPPLY) from transistor MN1 generates spin current into the stack of layers (e.g., layers 202a, 203a, and 204a).
  • an n-type transistor MN2 is provided which couples layer 203a of the stack of layers (202a, 203a, and 204a) to ground.
  • the drain terminal of transistor MN2 is coupled to layer 204a
  • the gate terminal of transistor MN2 is coupled to a control voltage Vdki (e.g., a switching clock signal, which switches between Vdd and ground)
  • the source terminal of transistor MN2 is coupled to ground.
  • n-type transistor MN3 is provided which is operable to couple power supply Vdd to second contact 209b.
  • the drain terminal of transistor MN3 is coupled to a supply Vdd
  • the gate terminal of transistor MN3 is coupled to a control voltage Vdk2 (e.g., a switching clock signal, which switches between Vdd and ground and is of different phase than Vdki)
  • the source terminal of transistor MN3 is coupled to second contact 209b.
  • second contact 209b is made of any suitable conducting material used to connect the transistor to the second magnet 207.
  • the current Idrive from transistor MN3 generates spin current into the stack of layers (e.g., layers 202b, 203b, and 204b).
  • an n-type transistor MN4 is provided which couples layer 204b of the stack of layers (202b, 203b, and 204b) to ground.
  • the drain terminal of transistor MN4 is coupled to layer 203b
  • the gate terminal of transistor MN4 is coupled to a control voltage V c ik2
  • the source terminal of transistor MN4 is coupled to ground.
  • MESO logic device can be considered to have two portions or sections.
  • the first portion/section comprises components/layers from 21 l a to the left of conductor 205, and the second portion/section comprises conductor 205 to layer 21 lb to the right.
  • An ideal unidirectional signal propagation scenario is as follows: an input charge current drives magnet 201 while a supply charge current is inj ected to the spin-orbit coupling (SOC) stack (202a, 203a, 204a).
  • SOC spin-orbit coupling
  • the magnet 201 switches and its directionality determines the output charge current ( ⁇ ) direction in conductor 205.
  • the output current ⁇ of the first MESO section drives the second MESO section, which continues to switch the MESO of that section.
  • transistors MN2 and MN4 simply connecting the two MESO sections in series can cause the ferroelectric capacitor in the second section of the MESO to switch input magnet 201 of the first section, which disturbs the logic operation.
  • transistors MN1 and MN2 of the first section are in series with the nanomagnet 201 and SOC stack (202a, 203a, and 204a). In some embodiments, transistors MN1 and MN2 of the first section are in series with the nanomagnet 201 and SOC stack (202a, 203a, and 204a). In some embodiments, transistors MN1 and MN2 of the first section are in series with the nanomagnet 201 and SOC stack (202a, 203a, and 204a). In some embodiments, transistors MN1 and MN2 of the first section are in series with the nanomagnet 201 and SOC stack (202a, 203a, and 204a). In some embodiments, transistors MN1 and MN2 of the first section are in series with the nanomagnet 201 and SOC stack (202a, 203a, and 204a). In some embodiments, transistors MN1 and MN2 of the first section are in series with the nanomagnet 201 and SOC stack (202
  • transistors MN3 and MN4 of the second section are in series with the nanomagnet 207 and SOC stack (202b, 203b, and 204b).
  • different clock signals Vdki and V c ik2 are applied to the gate terminals of the transistors, where transistors connected to the same MESO section share the same clock.
  • the polarization direction of the ferroelectric charge in the magnet stack determines the magnetic directions of the nano-magnets 201 and 207, which determines the output current direction.
  • IIN or Icharge(iN)
  • ISUPPLY or Idrive
  • output current ⁇ is generated on conductor 205 which is inversed from the input.
  • Current ⁇ then provides input current to the next MESO section.
  • This current induces a negative polarization charge on the bottom plate of the ferroelectric capacitor 206a of the next MESO section.
  • This polarization charge causes magnet 207 of the second MESO section to switch which results in the output current Ioim to be in the same direction as IIN (with the same ISUPPLY current direction).
  • the spin-orbit mechanism responsible for spin-to-charge conversion is described by the inverse Rashba-Edelstein effect in 2D electron gases.
  • the Hamiltonian (energy) of spin-orbit coupling electrons in a 2D electron gas is:
  • i3 ⁇ 4 is the Rashba-Edelstein coefficient
  • 'k' is the operator of momentum of electrons
  • z is a unit vector perpendicular to the 2D electron gas
  • ⁇ is the operator of spin of electrons.
  • w m is width of the input magnet 201
  • IREE is the IREE constant (with units of length) proportional to a R .
  • Both IREE and ISHE effects produce spin-to-charge current conversion around 0.1 with existing materials at 10 nm (nanometers) magnet width.
  • the spin-to-charge conversion efficiency can be between 1 and 2.5.
  • the net conversion of the drive charge current Idnve to magnetization dependent charge current is given as:
  • the charge current I c carried by interconnect 205, produces a voltage on the capacitor of ME layer 206a comprising magnetoelectric material dielectric (such as BiFeCb (BFO) or CnC ) in contact with second magnet 207 (which serves as one of the plates of the capacitor) and interconnect 205 (which series as the other of the plates of the capacitor).
  • magnetoelectric material dielectric such as BiFeCb (BFO) or CnC
  • magnetoelectric materials are either intrinsic multiferroic or composite multiferroic structures. As the charge accumulates on the magnetoelectric capacitor of ME layer 206a, a strong magnetoelectric interaction causes the switching of magnetization in second magnet 207 (and by extension second semi-insulating magnet 209b).
  • materials for first and second magnets 201 and 207 have saturated magnetization M s and effective anisotropy field Hk.
  • Saturated magnetization Ms is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material.
  • Anisotropy Hk generally refers material properties that are highly directionally dependent.
  • materials for first and second magnets 201 and 207, respectively are non-ferromagnetic elements with strong paramagnetism which have a high number of unpaired spins but are not room temperature ferromagnets. A paramagnet, as opposed to a ferromagnet, exhibits magnetization when a magnetic field is applied to it.
  • magnets 209a/b and 210a/b comprise a material which includes one or more of: Platinum(Pt), Palladium (Pd), Tungsten (W), Cerium (Ce), Aluminum (Al), Lithium (Li), Magnesium (Mg), Sodium (Na), Cr 2 Cb (chromium oxide), CoO (cobalt oxide), Dysprosium (Dy), Dy20 (dysprosium oxide), Erbium (Er), EnCb (Erbium oxide), Europium (Eu), EU2O3 (Europium oxide), Gadolinium (Gd), Gadolinium oxide (Gd203), FeO and Fe203 (Iron oxide), Neodymium (Nd), Nd2C (Neodymium oxide), KO2 (potassium superoxide), praseodymium (Pr), Samarium (Sm), SrmC (
  • the first and second paramagnets 201 and 207 comprise dopants selected from a group which includes one or more of: Ce, Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, or Yb.
  • first and second magnets 201 and 207 are ferromagnets.
  • first and second magnets 201 and 207 respectively, comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu 2 MnAl, Cu 2 MnIn, Cu 2 MnSn, Ni 2 MnAl, Ni 2 MnIn, Ni 2 MnSn, Ni 2 MnSb, Ni 2 MnGa Co 2 MnAl, Co 2 MnSi, Co 2 MnGa, Co 2 MnGe, Pd 2 MnAl, Pd 2 MnIn, P
  • the stack of layers providing spin orbit coupling comprises: a first layer 202a/b comprising Ag, wherein the first layer is adjacent to first magnet 209a/b; and a second layer 204a/b comprising Bi or W, wherein second layer 204a/b is adjacent to first layer 202a/b and to a conductor (e.g., 205, 21 lb).
  • a third layer 203a/b (having material which is one or more of Ta, W, or Pt) is sandwiched between first layer 202a/b and second layer 204a/b as shown.
  • the stack of layers comprises a material which includes one of: ⁇ -Ta, ⁇ -W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.
  • ME layer 206a/b is formed of a material which includes one of: CnCb and multiferroic material.
  • ME layer 206 comprises Cr and O.
  • the multiferroic material comprises BFO (e.g., BiFeC ), LFO (LuFeC , LuFe204), or La doped BiFeC .
  • the multiferroic material includes one of: Bi, Fe, O, Lu, or La.
  • ME layer 206a/b comprises one of: dielectric, para-electric, or ferro-electric material.
  • first contact 209a is replaced with a first semi- insulating magnet 209a
  • second contact 209b is replaced with a second semi-insulating magnet 209b
  • first semi-insulating magnet 209a is adjacent to first magnet 201 and is also coupled to a transistor (e.g., n-type transistor MNl).
  • first semi-insulating magnet 209a functions as a displacement capacitor between the transistor MNl and the first magnet 201.
  • the term "semi-insulating magnet” generally refers to a material that has magnetic properties but has higher resistivity compared to normal ferromagnets.
  • semi-insulating or insulating magnets may not be conductive for charge current, but exhibit magnetic properties.
  • the semi-insulating magnet or insulating magnet may have a Spinel crystal structure, can be hexagonal (e.g., Fe2Cb), or they can belong to any of the crystal classes.
  • materials for semi-insulating or insulating magnets include one of: Fe203, C02O3, Co2Fe04, or Ni2Fe04.
  • elements for semi-insulating or insulating magnets include one or more of: Fe, O, Co or Ni.
  • the direction of the charge current I c also depends on the direction of magnetization of first semi-insulating magnet 209a.
  • first semi-insulating magnet 209a and second semi- insulating magnet 209b form displacement capacitors.
  • the nature of the displacement capacitor may be set by the leakage and the dielectric constants of the semi-insulating magnets 209a/b.
  • first semi-insulating magnet 209a and second semi- insulating magnet 209b form dielectric capacitors, where a bound charge is generated at the plates.
  • first and second semi-insulating magnets 209a and 209b are identical to first and second semi-insulating magnets 209a and
  • first and second semi-insulating magnets 209a and 209b respectively, comprise a material which includes one or more of: Co, Fe, No, or O.
  • the first and second semi-insulating magnets 209a and 209b respectively, comprise a material which includes one or more of: C02O3, Fe2Cb, Co2Fe04,or Ni2Fe04.
  • first and second semi-insulating magnets 209a and 209b have Spinel crystal structure.
  • magnets 209a and 209b have non- insulating properties.
  • magnets 209a and 209b can be paramagnets or ferromagnets.
  • the magnetization of first semi-insulating magnet 209a is determined by the magnetization of first magnet 201. For example, when first magnet 201 has magnetizations pointing in -y direction, then first semi-insulating magnet 209a has magnetization pointing in the -y direction.
  • the magnetization of second semi-insulating magnet 209b is determined by the magnetization of second magnet 207. For example, when second magnet 207 has magnetizations pointing in -y direction, then second semi-insulating magnet 209b has magnetization pointing in the -y direction.
  • second semi-insulating magnet 209b is adjacent to second magnet 207 such that second magnet 207 is between second semi-insulating magnet 209b and the stack of layers providing spin orbit coupling.
  • n-type transistors can be used instead and the switching gate signals can be logically inversed.
  • a combination of n-type and p-type transistors are used.
  • the transistors coupled to power supply Vdd are p-type transistors while the transistors coupled to ground are n-type transistors.
  • Appropriate logic change can be made to the driving gate signals to achieve the same technical effect (e.g., unidirectionality) as achieved by the n-type transistors MN1, MN2, MN3, and MN3.
  • a combination of n-type and p-type devices e.g., transmission gates
  • Fig. 3A illustrates an equivalent circuit model 300 for the first section of the unidirectional MESO logic of Fig. 2A, in accordance with some embodiments. It is pointed out that those elements of Fig. 3A having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • Rmagnet, Rsi, Rsi, RIREE and Ric are the modeled resistances for magnet
  • the IREE effect from the current in the SOC stack is modeled as a current controlled current source, of which the current direction is determined by the magnet "state” (e.g., the nano-magnet direction, which is inconsistent with the polarization charge in the ferroelectric).
  • the ferroelectric 206b is modeled as a non-linear capacitor using Landau Khalatnikov (LK) equations. [0074] Fig.
  • FIG. 3B illustrates an equivalent circuit model 320 for the second section of the unidirectional MESO logic of Fig. 2A, in accordance with some embodiments. It is pointed out that those elements of Fig. 3B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • Rmagnet, Rsi, Rsi, RIREE and Ric are the modeled resistances for magnet
  • the IREE effect from the current in the SOC stack is modeled as a current controlled current source, of which the current direction is determined by the magnet "state" (e.g., the nano-magnet direction, which is inconsistent with the polarization charge in the ferroelectric).
  • the ferroelectric 206a is modeled as a non-linear capacitor using LK equations.
  • Vciki and V c ik2 are out-of-phase and with overlap.
  • VCM and V c ik2 are out-of-phase and non-overlapping. For example, Vciki and V c ik2 are out-of-phase by 180°.
  • Figs. 4A-B illustrate a ferroelectric Landau Khalatnikov (LK) model 400 and corresponding plot 420 showing two ferroelectric states.
  • positive polarization charge +QF corresponds to state ⁇ ' of the magnet
  • negative polarization charge -QF corresponds to state '0' of the magnet.
  • normalized +QF(1) and -QF(-l) are used in circuit simulation to indicate the ferroelectric states.
  • LK model 400 illustrates a circuit that provides ferroelectric voltage VFE and comprises capacitor CO in parallel with a series coupled resistance p and internal capacitance CF(QFE) that provides internal voltage Vim.
  • 'A' is the area of capacitor CO
  • 'd' is the distance between the plates of capacitor CO
  • E0 is the dielectric constant.
  • Plot 420 shows the capacitance behavior of a ferroelectric capacitor (FE-Cap) when connected with a load capacitor.
  • x-axis is the internal voltage Vint in volts
  • the y-axis is charge from the ferroelectric capacitor when connected with a load capacitor.
  • the dotted region in plot 420 represents the negative capacitance region between the coercive voltage bounds.
  • the operating region of a FE-cap is biased by the load capacitance.
  • the FE-Cap is biased at the negative capacitance region (e.g., charge on FE-cap is positive while the voltage across the FE-cap is negative, and vice versa)
  • the voltage across the load capacitance can be higher than the input voltage, owning to the ferroelectric polarity charge induced voltage amplification effect.
  • the FE-Cap is biased at the positive capacitance region, it operates as a regular capacitor.
  • the negative capacitance effect has been mainly utilized for transistor gate stack enhancement (e.g., negative capacitance FETs) for low-voltage transistors.
  • Fig. 5 illustrates a unidirectional cascaded MESO logic 500, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 5 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • MESO logic 500 comprises two MESO stages 501 and 502 that are cascaded with one another.
  • three different clocks are used to drive the transistor pairs— MN1, MN2; ⁇ , ⁇ 2'; and MN1 ", MN2”— to ensure unidirectional flow of current and integrity of logic operation.
  • Vdk3 is applied to control the input drivers (gates of transistors MN1 and MN2) of MESO stage 501.
  • the input driver provides a positive current IIN to the first ferroelectric capacitor 206b.
  • VDD 100 mV and Vciki, V c ik2, V c ik3 of 1 V with 12 ns (nanoseconds) clock period are used.
  • Fig. 6 illustrates plot 600 (which includes sub-plots 601, 602, and 603) showing transient simulation of the unidirectional cascaded MESO logic of Fig. 5, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • Sub-plot 601 illustrates Vciki, V c ik2, and V c ik3 which are control voltages to the drive transistors.
  • y-axis is voltage
  • the ferroelectric 206b in MESO stage 501 (MESOl .Fe) has a transient current path from the input driver VDD to the ground of MESO stage 501, while the transient conduction path from MESO stage 501 to MESO stage 502 through ⁇ is off.
  • ferroelectric 206b of MESO stage 501 switches from -QF to +QF due to positive current IIN, while the ferroelectric 206b of MESO stage 502 is unchanged.
  • 206b of MESO stages 501 and 502 are isolated since no conducting path exists.
  • +QF is deposited on ferroelectric 206b of MESO stage 501 (MESOl .QFe) during time tO, a negative transient current ⁇ is generated due to IREE and discharges ferroelectric 206b of MESO stage 501 (MES02.QFe).
  • magnet 201 of MESO stage 502 switches from state T to state '0' with negative polarization charge.
  • magnet 201 of MESO stage 501 switches when Vdk3 and Vdki overlap (e.g., at tO), and magnet 201 of MESO stage 502 switches when Vdki and Vdk2 overlap (e.g., t2).
  • each magnet 201 of a MESO stage switches once during one clock period.
  • more clocks may be used to ensure unidirectional flow of current.
  • no more clocks are used because uni directionality is preserved.
  • Fig. 7 illustrates a counter (or ring oscillator) 700 comprising a unidirectional cascaded MESO logic, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • a counter by cascading multiple MESO devices with 3-phase clocks, a counter can be realized.
  • the size of the counter depends on the number of cascaded MESO devices, in accordance with some embodiments.
  • Fig. 7 illustrates a 3-bit counter which is realized using three stages of cascaded MESO devices 701, 702, and 703 with three phase clocks (Vdki, Vdk2 and Vdk3), in accordance with some embodiments.
  • the output o3 of the MESO device 703 is connected to the input of MESO device 701.
  • the initial state of magnet 201 for MESO stage 710 is ⁇ '
  • magnet 201 for MESO stage 702 is ⁇ '
  • magnet 201 for MESO stage 703 is ⁇ '.
  • MES01.QFE -1 (state “0")
  • MES02.QFE 1 (state “1")
  • each MESO device/stage operates as an "inverter" for current.
  • this 3-stage MESO also operates as a ring-oscillator, in which the state of each MESO device changes when its own clock and previous stage's clock overlaps. For example, when magnet 201 of MESO stage 702 switches from state '0' to T when the state of magnet 201 of MESO stage 701 is ' ⁇ '). In another example, when
  • magnet 201 of MESO stage 702 switches from state T to '0' when the state of magnet 201 of MESO stage 701 is T.
  • the 3-phase clocks effectively prevent back propagation of adjacent series connected MESO devices, and provide unidirectional signal propagation.
  • Figs. 8A-C illustrate plots 800, 820, and 830, respectively, showing simulation results of the counter (or ring oscillator) of Fig. 7, according to some
  • Plot 800 illustrates overlapping clocks Vciki, V c ik2, and V c ik3 signals.
  • Plot 820 illustrates output currents ⁇ , Ioim, Ioiro from three MESO devices 701, 702, and 703.
  • Plot 830 illustrates normalized ferroelectric charges on the three MESO devices 701, 702, and 703 illustrating magnet state transition.
  • the vertical shades illustrate the overlapped duration of Vcik2/Vcik3, Vciki/Vdk2 and V c iki/V c ik3, respectively.
  • FIG. 9 illustrates apparatus 900 showing a series of cascaded unidirectional
  • Apparatus 900 shows 'N' MESO logic devices that are coupled in series or a chain using the 3-phase clock solution of various embodiments. As such, uni directionality of magnet state propagation is achieved which effectively prevents back signal propagation.
  • Fig. 10 illustrates a smart device or a computer system or a SoC (System-on-
  • Fig. 10 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used.
  • computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.
  • computing device 1600 includes first processor 1610 with unidirectional MESO logic, according to some embodiments discussed. Other blocks of the computing device 1600 may also include a unidirectional MESO logic, according to some embodiments.
  • the various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.
  • processor 1610 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means.
  • the processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed.
  • the processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device.
  • the processing operations may also include operations related to audio I/O and/or display I/O.
  • computing device 1600 includes audio subsystem
  • Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.
  • computing device 1600 comprises display subsystem
  • Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600.
  • Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user.
  • display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display.
  • display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.
  • computing device 1600 comprises I/O controller 1640.
  • I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.
  • I/O controller 1640 can interact with audio subsystem
  • display subsystem 1630 For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.
  • I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600.
  • the input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).
  • computing device 1600 includes power management
  • Memory subsystem 1660 includes memory devices for storing information in computing device 1600.
  • Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices.
  • Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.
  • Elements of embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein).
  • the machine-readable medium e.g., memory 1660
  • embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).
  • BIOS a computer program
  • a remote computer e.g., a server
  • a requesting computer e.g., a client
  • a communication link e.g., a modem or network connection
  • computing device 1600 comprises connectivity 1670.
  • Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices.
  • the computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.
  • Connectivity 1670 can include multiple different types of connectivity.
  • the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674.
  • Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards.
  • Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.
  • computing device 1600 comprises peripheral connections 1680.
  • Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections.
  • the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from” 1684) connected to it.
  • the computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600.
  • a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.
  • the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors.
  • Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.
  • USB Universal Serial Bus
  • MDP MiniDisplayPort
  • HDMI High Definition Multimedia Interface
  • Firewire or other types.
  • Example 1 An apparatus comprising: a magnet having a first portion and a second portion; a stack of layers, a portion of which is adjacent to the first portion of the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect; a layer adjacent to the second portion, the layer comprising a magnetoelectric material; a conductor adjacent to the layer; a first device coupled to a first supply node and to the magnet; and a second device coupled to a second supply node and to a layer of the stack of layers.
  • Example 2 The apparatus of example 1 comprises: a second magnet having a first portion and a second portion; a second stack of layers, a portion of which is adjacent to the first portion of the second magnet, wherein the second stack of layers is to provide an inverse spin orbit coupling effect; a second layer adjacent to the second portion of the second magnet, the second layer comprising a magnetoelectric material; a second conductor adjacent to the second layer; a third conductor adjacent to a portion of the stack of layers and the second layer; a third device coupled to the first supply node and to the second magnet; and a fourth device coupled to the second supply node and to a layer of the second stack of layers.
  • Example 3 The apparatus of example 2, wherein the first and second devices are controllable by a first switching signal, and wherein the third and fourth devices are controllable by a second switching signal.
  • Example 4 The apparatus of example 3, wherein the first switching signal has a first phase, wherein the second switching signal has a second phase, and wherein the first phase is different from the second phase.
  • Example 5 The apparatus of example 2, wherein the first, second, third, and fourth devices have the same conductivity type.
  • Example 6 The apparatus of example 2, wherein the first and third devices have a first conductivity type, and wherein the second and fourth devices have a second conductivity type.
  • Example 7 The apparatus according to any of examples 2 to 6, wherein the layer and second layer include one or more of: Cr 2 0 3 or multiferroic material, or wherein the layer and second layer comprise a material which includes one of: Cr, O, Cr 2 0 3 , or multiferroic material.
  • Example 8 The apparatus of example 7, wherein the multiferroic material includes one of: BiFeC , LuFeC , LuFe204, or La doped BiFeCb, or wherein the multiferroic material includes one of: Bi, Fe, O, Lu, or La.
  • Example 9 The apparatus according to any of examples 2 to 8, wherein the stack of layers and the second stack of layers comprises a material which includes one or more of: ⁇ -Ta, ⁇ -W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.
  • Example 10 The apparatus to any of examples 2 to 9, wherein the first and second magnets are a paramagnet or a ferromagnet, or wherein the first and second magnets comprises a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr 2 0 3 , CoO, Dy, Dy 2 0, Er, Er 2 0 3 , Eu, Eu 2 0 3 , Gd, Gd 2 0 3 , FeO, Fe 2 0 3 , Nd, Nd 2 0 3 , K0 2 , Pr, Sm, Sm 2 0 3 , Tb, Tb 2 0 3 , Tm, Tm 2 0 3 , V, or V 2 0 3 .
  • Example 11 The apparatus to any of examples 2 to 9, wherein the first and second magnets comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu 2 MnAl, Cu 2 MnIn, Cu 2 MnSn, NiJVInAl, Ni 2 MnIn, Ni 2 MnSn, Ni 2 MnSb, Ni 2 MnGa Co 2 MnAl, Co 2 MnSi, Co 2 MnGa, Co 2 MnGe, Pd 2 MnAl, Pd 2 MnIn, PdJVInSn, PdJVInSb, Co 2 FeSi, Co 2 FeA, Co 2
  • Example 12 An apparatus comprising: a first logic device according to any one of examples 4 to 11 ; a second logic device according to any one of examples 4 to 11, wherein the second conductor of the first logic device is coupled to the conductor of the second logic device; and a third logic device according to any one of examples 4 to 11, wherein the second conductor of the second logic device is coupled to the conductor of the third logic device.
  • Example 13 The apparatus of example 12, wherein: the second switching signal to the third and fourth devices of the first logic device has a first phase which is different than a second phase of the first switching signal to the first and second devices of the second logic device, and the second switching signal to the third and fourth devices of the second logic device has a third phase which is different than a first phase of the first switching signal to the first and second devices of the third logic device.
  • Example 14 An apparatus comprising: a first logic device including: a magnet having a first portion and a second portion; a stack of layers, a portion of which is adjacent to the first portion of the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect; a layer adjacent to the second portion, the layer comprising magnetoelectric material; a first conductor adjacent to the layer; a second conductor adjacent to a layer of the stack of layers, a first transistor coupled to a first supply node and to the magnet; and a second transistor coupled to a second supply node and to a layer of the stack of layers; a second logic device coupled to the first logic device, wherein the second logic device includes: a magnet having a first portion and a second portion; a stack of layers, a portion of which is adjacent to the first portion of the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect; a layer adjacent to the second portion, the layer comprising magnetoelectric material; a first conductor adj a
  • Example 15 The apparatus of example 14, wherein: the first and second transistors of the first logic device are controllable by a first switching signal, the first and second transistors of the second logic device are controllable by a second switching signal; and the first and second transistors of the third logic device are controllable by a third switching signal.
  • Example 16 The apparatus of example 15, wherein: the first switching signal has a first phase, the second switching signal has a second phase, the third switching signal has a third phase, wherein the first, second, and third phases are different from one another.
  • Example 17 The apparatus of example 16, wherein the first, second, and third phases are overlapping phases.
  • Example 18 An apparatus comprising: a first logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using first a clock signal; a second logic device coupled to the first logic device, the second logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using a second clock signal; and a third logic device coupled to the second logic device, the third logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using a third clock signal, wherein the first, second, and third clocks have overlapping phases.
  • Example 19 The apparatus of example 18, wherein the first logic device is according to any one of examples 1 to 11 , wherein the second logic device is according to any one of examples 1 to 1 1, wherein the third device is according to any one of examples 1 to 11.
  • Example 20 The apparatus of example 18, wherein the third logic device is coupled to the first logic device such that the first, second, and third logic devices together form a counter or a ring oscillator.
  • Example 21 A system comprising: a memory; a processor coupled to the memory, the processor including an apparatus according to any one of apparatus examples 1 to 11 , apparatus examples 12 to 13, apparatus examples 14 to 17; or apparatus examples 18 to 20; and a wireless interface to allow the processor to communicate with another device.
  • Example 22 A method comprising: forming a magnet having a first portion and a second portion; forming a stack of layers, a portion of which is adjacent to the first portion of the magnet, wherein the stack of layers is to provide an inverse spin orbit coupling effect; forming a layer adjacent to the second portion, the layer comprising magnetoelectric material; forming a conductor adjacent to the layer; forming a first transistor coupled to a first supply node and to the magnet; and forming a second transistor coupled to a second supply node and to a layer of the stack of layers.
  • Example 23 The method of example 22 comprises: forming a second magnet having a first portion and a second portion; forming a second stack of layers, a portion of which is adjacent to the first portion of the second magnet, wherein the second stack of layers is to provide an inverse spin orbit coupling effect; forming a second layer adjacent to the second portion of the second magnet, the second layer comprising magnetoelectric material; forming a second conductor adjacent to the second layer; forming a third conductor adjacent to a portion of the stack of layers and the second layer; forming a third transistor coupled to the first supply node and to the second magnet; and forming a fourth transistor coupled to the second supply node and to a layer of the second stack of layers.
  • Example 24 The method of example 23 comprises: controlling the first and second transistors by a first switching signal; and controlling the third and fourth transistors by a second switching signal.
  • Example 25 The method of example 24, wherein the first switching signal has a first phase, wherein the second switching signal has a second phase, and wherein the first phase is different from the second phase.
  • Example 26 The method of example 24, wherein the first, second, third, and fourth transistors have the same conductivity type.
  • Example 27 The method of example 24, wherein the first and third transistors have a first conductivity type, and wherein the second and fourth transistors have a second conductivity type.
  • Example 28 The method according to any of examples 22 to 27, wherein the layer and second layer include one or more of: CnCb or multiferroic material, or wherein the layer and second layer comprise a material which includes one of: Cr, O, CnCb or multiferroic material.
  • Example 29 The method of example 28 wherein the multiferroic material comprises BiFeCb, LuFeC , LuFe204, or La doped BiFeC , or wherein the multiferroic material includes one of: Bi, Fe, O, Lu, or La.
  • Example 30 The method according to any of examples 22 to 29, wherein the stack of layers and the second stack of layers comprises a material which includes one or more of: ⁇ -Ta, ⁇ -W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.
  • Example 31 The method according to any of examples 22 to 29, wherein the stack of layers and the second stack of layers comprises a material which includes one or more of: ⁇ -Ta, ⁇ -W, W, Pt, Cu doped with Iridium, Cu doped with Bismuth, or Cu doped an element of 3d, 4d, 5d, 4f, or 5f of periodic table groups.
  • first and second magnets are a paramagnet or a ferromagnet, or wherein the first and second magnets comprises a material which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr 2 0 3 , CoO, Dy, Dy 2 0, Er, Er 2 0 3 , Eu, Eu 2 0 3 , Gd, Gd 2 0 3 , FeO, Fe 2 0 3 , Nd, Nd 2 0 3 , K0 2 , Pr, Sm, Sm 2 0 3 , Tb, Tb 2 0 3 , Tm, Tm 2 0 3 , V, or V 2 0 3 .
  • Example 33 The method to any of examples 22 to 30, wherein the first and second magnet comprise one or a combination of materials which includes one or more of: a Heusler alloy, Co, Fe, Ni, Gd, B, Ge, Ga, permalloy, or Yttrium Iron Garnet (YIG), and wherein the Heusler alloy is a material which includes one or more of: Cu, Mn, Al, In, Sn, Ni, Sb, Ga, Co, Fe, Si, Pd, Sb, V, Ru, Cu 2 MnAl, Cu 2 MnIn, Cu 2 MnSn, Ni 2 MnAl, Ni 2 MnIn, Ni 2 MnSn, Ni 2 MnSb, Ni 2 MnGa Co 2 MnAl, Co 2 MnSi, Co 2 MnGa, Co 2 MnGe, Pd 2 MnAl, Pd 2 MnIn, Pd 2 MnSn, Pd 2 MnSb, Co 2 FeSi, Co 2 FeA
  • Example 34 A method comprising: forming a first logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using first a clock signal; forming a second logic device coupled to the first logic device, the second logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using a second clock signal; and forming a third logic device coupled to the second logic device, the third logic device including: a spin orbit coupling material, magnetostrictive material, and at least two transistors to operate using a third clock signal, wherein the first, second, and third clocks have overlapping phases.
  • Example 35 The method of example 33 comprises coupling the third logic device to the first logic device such that the first, second, and third logic devices together form a counter or a ring oscillator.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

L'invention concerne un appareil qui comprend : un premier dispositif logique comprenant : un matériau de couplage spin-orbite, un matériau magnétostrictif, et au moins deux transistors pour fonctionner à l'aide d'un premier signal d'horloge; un second dispositif logique couplé au premier dispositif logique, le second dispositif logique comprenant : un matériau de couplage spin-orbite, un matériau magnétostrictif, et au moins deux transistors pour fonctionner à l'aide d'un second signal d'horloge; et un troisième dispositif logique couplé au second dispositif logique, le troisième dispositif logique comprenant : un matériau de couplage spin-orbite, un matériau magnétostrictif et au moins deux transistors pour fonctionner à l'aide d'un troisième signal d'horloge, les première, secondes et troisième horloges comportant des phases de chevauchement.
PCT/US2017/053829 2017-09-27 2017-09-27 Logique spin-orbite magnétoélectrique en cascade WO2019066820A1 (fr)

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US11411172B2 (en) 2018-09-13 2022-08-09 Intel Corporation Magnetoelectric spin orbit logic based full adder
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US11411172B2 (en) 2018-09-13 2022-08-09 Intel Corporation Magnetoelectric spin orbit logic based full adder

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