WO2018123148A1 - Substrat épitaxique au carbure de silicium et procédé de production d'un dispositif semi-conducteur au carbure de silicium - Google Patents

Substrat épitaxique au carbure de silicium et procédé de production d'un dispositif semi-conducteur au carbure de silicium Download PDF

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WO2018123148A1
WO2018123148A1 PCT/JP2017/032220 JP2017032220W WO2018123148A1 WO 2018123148 A1 WO2018123148 A1 WO 2018123148A1 JP 2017032220 W JP2017032220 W JP 2017032220W WO 2018123148 A1 WO2018123148 A1 WO 2018123148A1
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silicon carbide
substrate
carbide epitaxial
main surface
layer
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PCT/JP2017/032220
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Japanese (ja)
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貴也 宮瀬
勉 堀
和田　圭司
洋典 伊東
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住友電気工業株式会社
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
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    • H01L21/02367—Substrates
    • H01L21/0237—Materials
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
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    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the present disclosure relates to a silicon carbide epitaxial substrate and a method for manufacturing a silicon carbide semiconductor device.
  • This application claims priority based on Japanese Patent Application No. 2016-253646, which is a Japanese patent application filed on December 27, 2016. All the descriptions described in the Japanese patent application are incorporated herein by reference.
  • Patent Document 1 discloses a method of epitaxially growing a silicon carbide layer on a silicon carbide single crystal substrate.
  • the silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial film.
  • the silicon carbide epitaxial film is on the silicon carbide substrate.
  • the polytype of the silicon carbide substrate and the silicon carbide epitaxial film is 4H.
  • the silicon carbide epitaxial film includes a first layer in contact with the silicon carbide substrate and a second layer on the first layer and constituting the main surface of the silicon carbide epitaxial film.
  • the silicon carbide substrate, the first layer, and the second layer contain n-type impurities.
  • the concentration of the n-type impurity included in the first layer is lower than the concentration of the n-type impurity included in the silicon carbide substrate and higher than the concentration of the n-type impurity included in the second layer.
  • FIG. 1 is a schematic plan view showing the configuration of the silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 2 is a schematic cross-sectional view showing the configuration of the silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 3 is a partial schematic cross-sectional view showing the configuration of the silicon carbide epitaxial substrate manufacturing apparatus according to this embodiment.
  • FIG. 4 is a flowchart schematically showing a method for manufacturing the silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 5 is a schematic cross-sectional view showing a first step of the method for manufacturing the silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 6 is a schematic cross-sectional view showing a second step of the method for manufacturing the silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 7 is a diagram showing a relationship between temperature and time in the method for manufacturing a silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 8 is a flowchart schematically showing a method for manufacturing the silicon carbide semiconductor device according to the present embodiment.
  • FIG. 9 is a schematic cross-sectional view showing a first step of the method for manufacturing the silicon carbide semiconductor device according to this embodiment.
  • FIG. 10 is a schematic cross-sectional view showing a second step of the method for manufacturing the silicon carbide semiconductor device according to this embodiment.
  • FIG. 11 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device according to this embodiment.
  • a silicon carbide epitaxial substrate 100 includes a silicon carbide substrate 10 and a silicon carbide epitaxial film 20.
  • Silicon carbide epitaxial film 20 is on silicon carbide substrate 10.
  • Polytype of silicon carbide substrate 10 and silicon carbide epitaxial film 20 is 4H.
  • Silicon carbide epitaxial film 20 includes a first layer 21 in contact with silicon carbide substrate 10 and a second layer 22 on first layer 21 and constituting main surface 14 of silicon carbide epitaxial film 20.
  • Silicon carbide substrate 10, first layer 21, and second layer 22 contain n-type impurities.
  • the concentration of n-type impurities included in first layer 21 is lower than the concentration of n-type impurities included in silicon carbide substrate 10 and higher than the concentration of n-type impurities included in second layer 22.
  • Main surface 12 of silicon carbide substrate 10 has basal plane dislocations 1 having a first surface density.
  • Main surface 14 of silicon carbide epitaxial film 20 has basal plane dislocations 1 having a second surface density lower than the first surface density.
  • a value obtained by dividing the second surface density by the first surface density is 2/10000 or less.
  • maximum diameter 111 of main surface 14 of silicon carbide epitaxial film 20 may be 150 mm or more.
  • the value obtained by dividing the second surface density by the first surface density may be 1/10000 or less.
  • the second surface density may be 1 cm ⁇ 2 or less.
  • the method for manufacturing the silicon carbide semiconductor device 300 according to the present disclosure includes the following steps. Silicon carbide epitaxial substrate 100 according to any one of (1) to (4) above is prepared. Silicon carbide epitaxial substrate 100 is processed.
  • silicon carbide epitaxial substrate 100 includes silicon carbide substrate 10 and silicon carbide epitaxial film 20. Silicon carbide epitaxial film 20 is on silicon carbide substrate 10. Silicon carbide substrate 10 has a first main surface 11 and a first main surface 12 opposite to first main surface 11. Silicon carbide epitaxial film 20 is in contact with first main surface 11. Silicon carbide epitaxial film 20 has a third main surface 13 in contact with first main surface 11 and a second main surface 14 opposite to third main surface 13. Polytype of silicon carbide substrate 10 and silicon carbide epitaxial film 20 is 4H. As shown in FIG. 1, the silicon carbide epitaxial substrate 100 may be provided with a first flat 16 extending in the first direction 101. Silicon carbide epitaxial substrate 100 may be provided with a second flat (not shown) extending in second direction 102.
  • the second direction 102 is, for example, the ⁇ 1-100> direction.
  • the first direction 101 is a direction parallel to the second main surface 14 and perpendicular to the second direction 102.
  • the first direction 101 is a direction including, for example, a ⁇ 11-20> direction component.
  • the maximum diameter 111 (diameter) of the second main surface 14 is, for example, 100 mm or more.
  • the maximum diameter 111 may be 150 mm or more, 200 mm or more, or 250 mm or more.
  • the upper limit of the maximum diameter 111 is not particularly limited.
  • the upper limit of the maximum diameter 111 may be 300 mm, for example.
  • Silicon carbide substrate 10 is made of, for example, a silicon carbide single crystal. Silicon carbide substrate 10 includes an n-type impurity such as nitrogen (N), for example. Silicon carbide substrate 10 has an n conductivity type, for example.
  • the first main surface 11 is a surface inclined by an angle of 8 ° or less from the ⁇ 0001 ⁇ plane. When the first main surface 11 is inclined from the ⁇ 0001 ⁇ plane, the inclination direction of the normal line of the first main surface 11 is, for example, the ⁇ 11-20> direction. Silicon carbide substrate 10 has a thickness of not less than 350 ⁇ m and not more than 500 ⁇ m, for example.
  • silicon carbide epitaxial film 20 is on first main surface 11 of silicon carbide substrate 10.
  • Silicon carbide epitaxial film 20 is an epitaxial layer. Silicon carbide epitaxial film 20 is in contact with first main surface 11.
  • Silicon carbide epitaxial film 20 includes an n-type impurity such as nitrogen.
  • the conductivity type of silicon carbide epitaxial film 20 is n-type, for example.
  • the second main surface 14 is a surface in which the ⁇ 0001 ⁇ plane is inclined in the off direction by an off angle ⁇ (°). Specifically, the second main surface 14 may be a surface in which the (0001) plane is inclined by 8 ° or less in the off direction.
  • the second main surface 14 may be a surface in which the (000-1) plane is inclined by 8 ° or less in the off direction.
  • the off direction is, for example, the ⁇ 11-20> direction. Note that the off direction is not limited to the ⁇ 11-20> direction.
  • the off direction may be, for example, a ⁇ 1-100> direction, or a direction having a ⁇ 1-100> direction component and a ⁇ 11-20> direction component.
  • the off angle ⁇ is an angle at which the second main surface 14 is inclined with respect to the ⁇ 0001 ⁇ plane.
  • the off-angle ⁇ is an angle at which the normal line of the second main surface 14 is inclined with respect to the ⁇ 0001> direction.
  • the off angle ⁇ is, for example, larger than 0 ° and not larger than 8 °.
  • the off angle ⁇ may be 1 ° or more, or 2 ° or more.
  • the off angle may be 7 ° or less, or 6 ° or less.
  • the surface indicated by a broken line is, for example, the ⁇ 0001 ⁇ surface.
  • the third direction 103 is a direction perpendicular to the ⁇ 0001 ⁇ plane.
  • the third direction 103 is, for example, the ⁇ 0001> direction.
  • the fourth direction 104 is a direction perpendicular to the third direction 103.
  • the fourth direction 104 is, for example, the ⁇ 11-20> direction.
  • the fourth direction 104 is an off direction.
  • the normal direction of the second main surface 14 is the fifth direction 105.
  • the fifth direction is a direction inclined by an off angle ⁇ in the off direction with respect to the ⁇ 0001> direction.
  • Silicon carbide epitaxial film 20 includes a first layer 21 and a second layer 22.
  • the first layer is, for example, the buffer layer 21.
  • the second layer 22 is, for example, the drift layer 22.
  • the buffer layer 21 is in contact with the first main surface 11.
  • the first layer 21 constitutes the third major surface 13.
  • the second layer 22 is on the first layer 21.
  • the second layer 22 constitutes the second main surface 14.
  • Silicon carbide substrate 10, first layer 21, and second layer 22 contain n-type impurities.
  • Buffer layer 21 contains an n-type impurity such as nitrogen, for example.
  • the concentration of the n-type impurity contained in the buffer layer 21 is, for example, 1 ⁇ 10 18 cm ⁇ 3 .
  • the concentration of the n-type impurity included in the buffer layer 21 may be, for example, 0.2 ⁇ 10 18 cm ⁇ 3 or more and 9 ⁇ 10 18 cm ⁇ 3 or less.
  • the concentration of the n-type impurity included in the drift layer is, for example, 8 ⁇ 10 15 cm ⁇ 3 .
  • the concentration of n-type impurities included in first layer 21 is lower than the concentration of n-type impurities included in silicon carbide substrate 10 and higher than the concentration of n-type impurities included in second layer 22.
  • the concentration of the n-type impurity is measured by, for example, a mercury probe type CV measuring device.
  • the area of the probe is, for example, 0.005 cm 2 .
  • Silicon carbide substrate 10 and silicon carbide epitaxial film 20 have basal plane dislocations 1.
  • Basal plane dislocation 1 is exposed on both first main surface 11 and first main surface 12 of silicon carbide substrate 10.
  • the basal plane dislocation 1 extends in a direction parallel to the ⁇ 0001 ⁇ plane.
  • the basal plane dislocation 1 has, for example, a first basal plane dislocation 25, a second basal plane dislocation 26, and a third basal plane dislocation 27.
  • Silicon carbide epitaxial film 20 has fourth basal plane dislocations 37 and threading edge dislocations 2.
  • the fourth basal plane dislocation 37 and the threading edge dislocation 2 are exposed on the second main surface 14.
  • the threading edge dislocation 2 has, for example, a first threading edge dislocation 35 and a second threading edge dislocation 36.
  • the first threading edge dislocation 35 is a dislocation formed by converting the first basal plane dislocation 25.
  • the second threading edge dislocation 36 is a dislocation formed by converting the second basal plane dislocation 26.
  • the threading edge dislocation 2 extends along a third direction 103 substantially perpendicular to ⁇ 0001 ⁇ .
  • the fourth basal plane dislocation 37 is a dislocation that inherits the third basal plane dislocation 27.
  • basal plane dislocation 1 exists in silicon carbide epitaxial substrate 100, for example, the reliability of the gate insulating film formed on silicon carbide epitaxial substrate 100 deteriorates.
  • the threading edge dislocation 2 exists in the silicon carbide epitaxial substrate, it hardly affects the reliability of the gate insulating film formed on the silicon carbide epitaxial substrate. Therefore, it is desirable to convert the basal plane dislocations 1 existing in the silicon carbide substrate 10 into threading edge dislocations 2 and reduce the number of basal plane dislocations 1 in the silicon carbide epitaxial film 20.
  • main surface 12 of silicon carbide substrate 10 has basal plane dislocations 1 having a first surface density.
  • Main surface 14 of silicon carbide epitaxial film 20 has basal plane dislocations 1 having a second surface density lower than the first surface density.
  • a value obtained by dividing the second surface density by the first surface density is 2/10000 or less. In other words, the ratio of conversion from the basal plane dislocation 1 to the threading edge dislocation 2 (conversion rate) is 99.98% or more.
  • a value obtained by dividing the second surface density by the first surface density may be, for example, 1/10000 or less. In other words, the ratio of conversion from the basal plane dislocation 1 to the threading edge dislocation 2 (conversion rate) is 99.99% or more.
  • the second surface density is, for example, 1 cm ⁇ 2 or less.
  • the second surface density may be, for example, 0.8 cm ⁇ 2 or less, or 0.5 cm ⁇ 2 or less.
  • the lower limit of the first surface density is limited, the first surface density may be for example 2000 cm -2 or more, or may be 2500 cm -2 or more.
  • the first surface density may be at 6000 cm -2 or less, may be 5500Cm -2 or less.
  • a photoluminescence imaging apparatus (model number: PLIS-100) manufactured by Photon Design Co., Ltd. is used.
  • PLIS-100 photoluminescence imaging apparatus
  • Excitation light from the light source passes through a 313 nm band-pass filter and is then applied to the measurement region.
  • the photoluminescence light reaches a light receiving element such as a camera after passing through a low pass filter of 750 nm, for example.
  • a photoluminescence image of the region to be measured is taken.
  • the measurement temperature is room temperature.
  • a photoluminescence image of the main surface is photographed while moving the silicon carbide epitaxial substrate in a direction parallel to the main surface (specifically, second main surface 14 or first main surface 12) of the silicon carbide epitaxial substrate. .
  • region of a main surface is mapped.
  • the basal plane dislocation is specified in the acquired photoluminescence image, and the total number of the basal plane dislocation is calculated. By dividing the total number of basal plane dislocations by the total measurement area, the surface density of the basal plane dislocations is calculated.
  • the calculation of the surface density of the basal plane dislocations on the main surface of the silicon carbide epitaxial substrate may be performed, for example, by counting pits generated using a potassium hydroxide (KOH) melt. Specifically, the main surface is etched using a KOH melt. The temperature of the KOH melt is, for example, about 500 ° C. or more and 550 ° C. or less. The etching time is, for example, about 5 to 10 minutes. After etching, the main surface is observed with a normalsky differential interference microscope. The basal plane dislocation is etched by the KOH melt to form pits. By dividing the total number of pits by the total measurement area, the surface density of the basal plane dislocation is calculated.
  • KOH potassium hydroxide
  • the threading edge dislocations also form pits in the same manner as the basal plane dislocations.
  • Pits derived from threading edge dislocations and pits derived from basal plane dislocations are distinguished as follows. Rounded hexagonal pits are derived from threading edge dislocations, and elliptical pits are derived from basal plane dislocations.
  • the basal plane dislocation penetrates the inside of the silicon carbide substrate and reaches each of the first main surface 12 and the first main surface 11. Therefore, it can be estimated that the surface density of the basal plane dislocations in the first main surface 12 is the same as the surface density of the basal plane dislocations in the first main surface 11.
  • the first main surface 12 is a (000-1) plane or a (000-1) plane inclined by 8 ° or less in the off direction
  • etch pits are formed on the first main surface 12 by the KOH melt. Hard to appear.
  • the surface density of basal plane dislocations on first main surface 11 of silicon carbide substrate 10 may be measured.
  • the (0001) plane or the (0001) plane is off the first main surface 11
  • the surface is inclined by 8 ° or less in the direction. Therefore, etch pits are likely to appear on the first main surface 11 as compared to the first main surface 12. It is estimated that the surface density of the basal plane dislocations in the first main surface 11 is the same as the surface density of the basal plane dislocations in the first main surface 12.
  • a silicon carbide epitaxial substrate 100 manufacturing apparatus 200 is, for example, a hot-wall lateral CVD (Chemical Vapor Deposition) apparatus.
  • the manufacturing apparatus 200 mainly includes a reaction chamber 201, a heating element 203, a quartz tube 204, a heat insulating material 205, and an induction heating coil 206.
  • the heating element 203 has a cylindrical shape, for example, and forms a reaction chamber 201 inside.
  • the heating element 203 is made of, for example, graphite.
  • the heat insulating material 205 surrounds the outer periphery of the heating element 203.
  • the heat insulating material 205 is provided inside the quartz tube 204 so as to contact the inner peripheral surface of the quartz tube 204.
  • the induction heating coil 206 is wound, for example, along the outer peripheral surface of the quartz tube 204.
  • the induction heating coil 206 is configured to be able to supply an alternating current by an external power source (not shown). Thereby, the heating element 203 is induction-heated. As a result, the reaction chamber 201 is heated by the heating element 203.
  • the reaction chamber 201 is a space formed by being surrounded by the heating element 203. Silicon carbide substrate 10 is arranged in reaction chamber 201. Reaction chamber 201 is configured to heat silicon carbide substrate 10. Reaction chamber 201 is provided with a susceptor 210 that holds silicon carbide substrate 10. The susceptor 210 is configured to be able to rotate around the rotation shaft 212.
  • the manufacturing apparatus 200 has a gas introduction port 207 and a gas exhaust port 208.
  • the gas exhaust port 208 is connected to an exhaust pump (not shown).
  • the arrows in FIG. 6 indicate the gas flow.
  • the gas is introduced into the reaction chamber 201 from the gas introduction port 207 and exhausted from the gas exhaust port 208.
  • the pressure in the reaction chamber 201 is adjusted by the balance between the gas supply amount and the gas exhaust amount.
  • the manufacturing apparatus 200 has a gas supply unit (not shown) configured to be able to supply, for example, a mixed gas containing silane, ammonia, hydrogen, and propane to the reaction chamber 201.
  • the gas supply unit includes a gas cylinder capable of supplying propane gas diluted with hydrogen, a gas cylinder capable of supplying hydrogen gas, a gas cylinder capable of supplying silane gas, and a gas cylinder capable of supplying ammonia gas. You may have.
  • propane gas diluted with hydrogen propane gas is 30% by volume and hydrogen gas is 70% by volume.
  • the winding density of the induction heating coil 206 may be changed.
  • the winding density [times / m] is the number of coil turns per unit length in the axial direction of the apparatus.
  • the winding density of the induction heating coil 206 on the upstream side may be higher than the winding density of the induction heating coil 206 on the downstream side.
  • a silicon carbide single crystal substrate preparation step (S11: FIG. 4) is performed.
  • a polytype 4H silicon carbide single crystal is manufactured by a sublimation method.
  • silicon carbide substrate 10 is prepared by slicing the silicon carbide single crystal with, for example, a wire saw.
  • Silicon carbide substrate 10 includes an n-type impurity such as nitrogen, for example.
  • Silicon carbide substrate 10 has an n conductivity type, for example.
  • silicon carbide substrate 10 has a first main surface 11 and a third main surface 13 on the opposite side of first main surface 11.
  • the first major surface 11 is, for example, a surface in which the ⁇ 0001 ⁇ plane is inclined in the off direction by the off angle ⁇ .
  • the off direction is, for example, the ⁇ 11-20> direction.
  • the maximum diameter of first main surface 11 of silicon carbide substrate 10 is, for example, 100 mm or more.
  • a plurality of basal plane dislocations 1 exist in silicon carbide substrate 10.
  • the basal plane dislocation 1 extends in a direction parallel to the ⁇ 0001 ⁇ plane.
  • the basal plane dislocation 1 has, for example, a first basal plane dislocation 25, a second basal plane dislocation 26, and a third basal plane dislocation 27.
  • Silicon carbide substrate 10 is arranged on susceptor 210 in reaction chamber 201 (see FIG. 3). For example, after the pressure in reaction chamber 201 is reduced from atmospheric pressure to about 1 ⁇ 10 ⁇ 6 Pa, the temperature rise of silicon carbide substrate 10 is started. As shown in FIG. 7, the temperature of silicon carbide substrate 10 increases from room temperature to first temperature A1 from time T0 to time T1. The first temperature A1 is 1605 ° C., for example.
  • a buffer layer forming step (S12: FIG. 4) is performed.
  • first temperature A1 source gas, dopant gas, and carrier gas are supplied to reaction chamber 201.
  • a mixed gas containing silane, propane, ammonia, and hydrogen is supplied to the reaction chamber 201.
  • silicon carbide substrate 10 is maintained at first temperature A1 from time T1 to time T2.
  • the time from time T1 to time T2 is, for example, not less than 3 minutes and not more than 60 minutes.
  • each gas is thermally decomposed, and buffer layer 21 is formed on silicon carbide substrate 10 (see FIG. 6).
  • the susceptor 210 rotates around the rotation shaft 212.
  • Silicon carbide substrate 10 revolves around rotating shaft 212 (see FIG. 3).
  • the flow rates of silane and propane are adjusted so that the C / Si ratio is, for example, 0.95.
  • the flow rate of the silane gas is adjusted to 57.6 sccm, for example.
  • the flow rate of the propane gas (30% by volume) diluted with hydrogen is adjusted to be, for example, 18.2 sccm.
  • the flow rate of hydrogen gas is adjusted to be 130 slm.
  • the concentration of the n-type impurity (N) doped in the buffer layer 21 is, for example, about 0.2 ⁇ 10 18 cm ⁇ 3 to 9 ⁇ 10 18 cm ⁇ 3 .
  • the thickness of the buffer layer 21 is, for example, 1 ⁇ m.
  • the pressure in the reaction chamber 201 is, for example, 5 kPa.
  • most of the plurality of basal plane dislocations 1 existing in the silicon carbide substrate 10 are converted into threading edge dislocations 2.
  • the first basal plane dislocation 25 is converted into the first threading edge dislocation 35.
  • the second basal plane dislocation 26 is converted into the second threading edge dislocation 36.
  • the third basal plane dislocations 27 are not converted into threading edge dislocations, but propagate in the buffer layer 21 as fourth basal plane dislocations 37.
  • the drift layer forming step (S13: FIG. 4) is performed.
  • the temperature rise of silicon carbide substrate 10 is started again. Specifically, the temperature of silicon carbide substrate 10 rises from first temperature A1 to second temperature A2 from time T2 to time T3.
  • the second temperature A2 is 1640 ° C., for example.
  • a mixed gas containing silane, propane, ammonia, and hydrogen is supplied to the reaction chamber 201 in a state where the temperature of the silicon carbide substrate 10 is maintained at the second temperature A2.
  • silicon carbide substrate 10 is maintained at second temperature A2.
  • the time from time T3 to time T4 is, for example, not less than 30 minutes and not more than 600 minutes.
  • each gas is thermally decomposed, and the drift layer 22 is formed on the buffer layer 21 (see FIGS. 2 and 5).
  • the susceptor 210 rotates around the rotation axis 212.
  • Silicon carbide substrate 10 revolves around rotating shaft 212 (see FIG. 3).
  • the flow rates of silane and propane are adjusted so that the C / Si ratio is about 1.35.
  • the flow rate of the silane gas is adjusted to 140 sccm, for example.
  • the flow rate of propane gas (30% by volume) diluted with hydrogen is adjusted to 63 sccm, for example.
  • the flow rate of hydrogen gas is adjusted to 134 slm.
  • the concentration of carriers doped in the drift layer 22 is, for example, about 8 ⁇ 10 15 cm ⁇ 3 .
  • the thickness of the drift layer 22 is, for example, about 10 ⁇ m to 30 ⁇ m.
  • the pressure in the reaction chamber 201 is, for example, 6 kPa.
  • the difference in thermal expansion between the buffer layer and the drift layer having different thermal expansion coefficients can be reduced. Since the absolute value becomes small and the strain can be kept small, the ratio of the basal plane dislocations to threading edge dislocations (conversion rate) can be improved.
  • a cooling process is performed. As shown in FIG. 7, from time T4 to time T5, the temperature of the silicon carbide substrate is reduced from second temperature A2 to room temperature. As described above, silicon carbide epitaxial substrate 100 is manufactured.
  • the method for manufacturing a silicon carbide semiconductor device mainly includes an epitaxial substrate preparation step (S10: FIG. 8) and a substrate processing step (S20: FIG. 8).
  • an epitaxial substrate preparation step (S10: FIG. 8) is performed. Specifically, silicon carbide epitaxial substrate 100 is prepared by the above-described method for manufacturing a silicon carbide epitaxial substrate (see FIG. 4).
  • a substrate processing step (S20: FIG. 8) is performed.
  • a silicon carbide semiconductor device is manufactured by processing a silicon carbide epitaxial substrate.
  • “Processing” includes, for example, various processes such as ion implantation, heat treatment, etching, oxide film formation, electrode formation, and dicing. That is, the substrate processing step may include at least one of ion implantation, heat treatment, etching, oxide film formation, electrode formation, and dicing.
  • the substrate processing step (S20: FIG. 8) includes, for example, an ion implantation step (S21: FIG. 8), an oxide film formation step (S22: FIG. 8), an electrode formation step (S23: FIG. 8), and a dicing step (S24: FIG. 8). )including.
  • an ion implantation step (S21: FIG. 8) is performed.
  • a p-type impurity such as aluminum (Al) is implanted into second main surface 14 on which a mask (not shown) having an opening is formed. Thereby, body region 132 having p-type conductivity is formed.
  • an n-type impurity such as phosphorus (P) is implanted into a predetermined position in body region 132. Thereby, a source region 133 having n-type conductivity is formed.
  • a p-type impurity such as aluminum is implanted into a predetermined position in the source region 133. As a result, a contact region 134 having a p-type conductivity is formed (see FIG. 9).
  • Source region 133 is separated from drift region 131 by body region 132.
  • Ion implantation may be performed by heating silicon carbide epitaxial substrate 100 to about 300 ° C. or more and 600 ° C. or less.
  • activation annealing is performed on silicon carbide epitaxial substrate 100.
  • the atmosphere of activation annealing is, for example, an argon (Ar) atmosphere.
  • the temperature of activation annealing is, for example, about 1800 ° C.
  • the activation annealing time is, for example, about 30 minutes.
  • oxide film forming step (S22: FIG. 8) is performed.
  • silicon carbide epitaxial substrate 100 is heated in an atmosphere containing oxygen, whereby oxide film 136 is formed on second main surface 14 (see FIG. 10).
  • Oxide film 136 is made of, for example, silicon dioxide.
  • the oxide film 136 functions as a gate insulating film.
  • the temperature of the thermal oxidation treatment is, for example, about 1300 ° C.
  • the time for the thermal oxidation treatment is, for example, about 30 minutes.
  • heat treatment may be performed in a nitrogen atmosphere.
  • the heat treatment is performed in an atmosphere of nitric oxide at about 1100 ° C. for about 1 hour.
  • heat treatment is performed in an argon atmosphere.
  • the heat treatment is performed in an argon atmosphere at about 1100 ° C. to 1500 ° C. for about 1 hour.
  • the first electrode 141 is formed on the oxide film 136.
  • the first electrode 141 functions as a gate electrode.
  • the first electrode 141 is formed by, for example, a CVD method.
  • the first electrode 141 is made of, for example, conductive polysilicon.
  • the first electrode 141 is formed at a position facing the source region 133 and the body region 132.
  • Interlayer insulating film 137 covering the first electrode 141 is formed.
  • Interlayer insulating film 137 is formed by, for example, a CVD method.
  • Interlayer insulating film 137 is made of, for example, silicon dioxide.
  • the interlayer insulating film 137 is formed so as to be in contact with the first electrode 141 and the oxide film 136.
  • the oxide film 136 and the interlayer insulating film 137 at predetermined positions are removed by etching. As a result, the source region 133 and the contact region 134 are exposed from the oxide film 136.
  • the second electrode 142 is formed on the exposed portion by, for example, a sputtering method.
  • the second electrode 142 functions as a source electrode.
  • Second electrode 142 is made of, for example, titanium, aluminum, silicon, or the like.
  • second electrode 142 and silicon carbide epitaxial substrate 100 are heated at a temperature of about 900 ° C. to 1100 ° C., for example. Thereby, second electrode 142 and silicon carbide epitaxial substrate 100 come into ohmic contact.
  • the wiring layer 138 is formed so as to be in contact with the second electrode 142.
  • the wiring layer 138 is made of a material containing aluminum, for example.
  • the third electrode 143 is formed on the third main surface 13.
  • the third electrode 143 functions as a drain electrode.
  • Third electrode 143 is made of, for example, an alloy containing nickel and silicon (eg, NiSi).
  • a dicing step (S24: FIG. 8) is performed.
  • silicon carbide epitaxial substrate 100 is diced along a dicing line, whereby silicon carbide epitaxial substrate 100 is divided into a plurality of semiconductor chips.
  • silicon carbide semiconductor device 300 is manufactured (see FIG. 11).
  • the method for manufacturing the silicon carbide semiconductor device according to the present disclosure has been described by exemplifying the MOSFET, but the manufacturing method according to the present disclosure is not limited to this.
  • the manufacturing method according to the present disclosure can be applied to silicon carbide semiconductor devices such as IGBT (Insulated Gate Bipolar Transistor), SBD (Schottky Barrier Diode), thyristor, GTO (Gate Turn Off thyristor), and PiN diode.
  • IGBT Insulated Gate Bipolar Transistor
  • SBD Schottky Barrier Diode
  • thyristor thyristor
  • GTO Gate Turn Off thyristor
  • PiN diode PiN diode
  • a silicon carbide substrate according to Sample 1-5 was prepared.
  • a silicon carbide epitaxial film was grown on the silicon carbide substrate according to Sample 1-5.
  • a silicon carbide epitaxial film was formed using the temperature profile shown by the solid line in FIG. 7 of the present embodiment. Specifically, the temperature of the step of forming the buffer layer (A1: see FIG. 7) was 1605 ° C., and the temperature of the step of forming the drift layer (A2: see FIG. 7) was 1640 ° C.
  • a silicon carbide epitaxial film was formed using the temperature profile shown by the one-dot chain line in FIG.
  • the temperature of the step of forming the buffer layer (A1: see FIG. 7) and the temperature of the step of forming the drift layer (A2: see FIG. 7) were both 1640 ° C.
  • the silicon carbide epitaxial substrate according to Sample 1-5 was manufactured.
  • the surface density of basal plane dislocations on the second main surface and main surface of the silicon carbide epitaxial substrate according to Sample 1-5 was measured.
  • the surface density of the basal plane dislocation was measured using the above-described measurement method.
  • Table 1 shows the surface density (first surface density) of basal plane dislocations on the main surface of the silicon carbide substrate, the surface density (second surface density) of basal plane dislocations on the main surface of the silicon carbide epitaxial film, and the second surface.
  • the value obtained by dividing the density by the first surface density and the conversion rate from the basal plane dislocation to the threading edge dislocation are shown.
  • the values obtained by dividing the second surface density by the first surface density are 0.000152, 0.000157, 0.000006, and 0, respectively. 0.00001 and 0.012032.
  • the conversion ratios obtained as values obtained by subtracting the second surface density from the first surface density by the first surface density were 99.9848%, 99.9843%, 99.99994%, 99.9989% and 98.7968%.

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Abstract

La présente invention concerne un substrat épitaxique au carbure de silicium qui comprend un substrat de carbure de silicium et une pellicule épitaxique au carbure de silicium. La pellicule épitaxique au carbure de silicium est présente sur le substrat au carbure de silicium. Le polytype du substrat au carbure de silicium et de la pellicule épitaxique au carbure de silicium est 4H. La pellicule épitaxique au carbure de silicium comprend une première couche qui est en contact avec le substrat au carbure de silicium et une deuxième couche qui est sur la première couche et qui constitue la surface principale de la pellicule épitaxique au carbure de silicium. Le substrat au carbure de silicium, la première couche et la deuxième couche contiennent une impureté de type n. La concentration de l'impureté de type n contenue dans la première couche est inférieure à la concentration de l'impureté de type n contenue dans le substrat au carbure de silicium, mais est supérieure à la concentration de l'impureté de type n contenue dans la deuxième couche. La surface principale du substrat au carbure de silicium a une dislocation de plan basal ayant une première densité d'aire. La surface principale de la pellicule épitaxique au carbure de silicium a une dislocation de plan basal ayant une deuxième densité d'aire qui est inférieure à la première densité d'aire. La valeur obtenue en divisant la deuxième densité d'aire par la première densité d'aire est inférieure ou égale à 2/10 000.
PCT/JP2017/032220 2016-12-27 2017-09-07 Substrat épitaxique au carbure de silicium et procédé de production d'un dispositif semi-conducteur au carbure de silicium WO2018123148A1 (fr)

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