WO2018123148A1 - Silicon carbide epitaxial substrate and method for producing silicon carbide semiconductor device - Google Patents

Silicon carbide epitaxial substrate and method for producing silicon carbide semiconductor device Download PDF

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WO2018123148A1
WO2018123148A1 PCT/JP2017/032220 JP2017032220W WO2018123148A1 WO 2018123148 A1 WO2018123148 A1 WO 2018123148A1 JP 2017032220 W JP2017032220 W JP 2017032220W WO 2018123148 A1 WO2018123148 A1 WO 2018123148A1
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silicon carbide
substrate
carbide epitaxial
main surface
layer
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PCT/JP2017/032220
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French (fr)
Japanese (ja)
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貴也 宮瀬
勉 堀
和田　圭司
洋典 伊東
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住友電気工業株式会社
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/42—Silicides
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide

Definitions

  • the present disclosure relates to a silicon carbide epitaxial substrate and a method for manufacturing a silicon carbide semiconductor device.
  • This application claims priority based on Japanese Patent Application No. 2016-253646, which is a Japanese patent application filed on December 27, 2016. All the descriptions described in the Japanese patent application are incorporated herein by reference.
  • Patent Document 1 discloses a method of epitaxially growing a silicon carbide layer on a silicon carbide single crystal substrate.
  • the silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial film.
  • the silicon carbide epitaxial film is on the silicon carbide substrate.
  • the polytype of the silicon carbide substrate and the silicon carbide epitaxial film is 4H.
  • the silicon carbide epitaxial film includes a first layer in contact with the silicon carbide substrate and a second layer on the first layer and constituting the main surface of the silicon carbide epitaxial film.
  • the silicon carbide substrate, the first layer, and the second layer contain n-type impurities.
  • the concentration of the n-type impurity included in the first layer is lower than the concentration of the n-type impurity included in the silicon carbide substrate and higher than the concentration of the n-type impurity included in the second layer.
  • FIG. 1 is a schematic plan view showing the configuration of the silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 2 is a schematic cross-sectional view showing the configuration of the silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 3 is a partial schematic cross-sectional view showing the configuration of the silicon carbide epitaxial substrate manufacturing apparatus according to this embodiment.
  • FIG. 4 is a flowchart schematically showing a method for manufacturing the silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 5 is a schematic cross-sectional view showing a first step of the method for manufacturing the silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 6 is a schematic cross-sectional view showing a second step of the method for manufacturing the silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 7 is a diagram showing a relationship between temperature and time in the method for manufacturing a silicon carbide epitaxial substrate according to the present embodiment.
  • FIG. 8 is a flowchart schematically showing a method for manufacturing the silicon carbide semiconductor device according to the present embodiment.
  • FIG. 9 is a schematic cross-sectional view showing a first step of the method for manufacturing the silicon carbide semiconductor device according to this embodiment.
  • FIG. 10 is a schematic cross-sectional view showing a second step of the method for manufacturing the silicon carbide semiconductor device according to this embodiment.
  • FIG. 11 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device according to this embodiment.
  • a silicon carbide epitaxial substrate 100 includes a silicon carbide substrate 10 and a silicon carbide epitaxial film 20.
  • Silicon carbide epitaxial film 20 is on silicon carbide substrate 10.
  • Polytype of silicon carbide substrate 10 and silicon carbide epitaxial film 20 is 4H.
  • Silicon carbide epitaxial film 20 includes a first layer 21 in contact with silicon carbide substrate 10 and a second layer 22 on first layer 21 and constituting main surface 14 of silicon carbide epitaxial film 20.
  • Silicon carbide substrate 10, first layer 21, and second layer 22 contain n-type impurities.
  • the concentration of n-type impurities included in first layer 21 is lower than the concentration of n-type impurities included in silicon carbide substrate 10 and higher than the concentration of n-type impurities included in second layer 22.
  • Main surface 12 of silicon carbide substrate 10 has basal plane dislocations 1 having a first surface density.
  • Main surface 14 of silicon carbide epitaxial film 20 has basal plane dislocations 1 having a second surface density lower than the first surface density.
  • a value obtained by dividing the second surface density by the first surface density is 2/10000 or less.
  • maximum diameter 111 of main surface 14 of silicon carbide epitaxial film 20 may be 150 mm or more.
  • the value obtained by dividing the second surface density by the first surface density may be 1/10000 or less.
  • the second surface density may be 1 cm ⁇ 2 or less.
  • the method for manufacturing the silicon carbide semiconductor device 300 according to the present disclosure includes the following steps. Silicon carbide epitaxial substrate 100 according to any one of (1) to (4) above is prepared. Silicon carbide epitaxial substrate 100 is processed.
  • silicon carbide epitaxial substrate 100 includes silicon carbide substrate 10 and silicon carbide epitaxial film 20. Silicon carbide epitaxial film 20 is on silicon carbide substrate 10. Silicon carbide substrate 10 has a first main surface 11 and a first main surface 12 opposite to first main surface 11. Silicon carbide epitaxial film 20 is in contact with first main surface 11. Silicon carbide epitaxial film 20 has a third main surface 13 in contact with first main surface 11 and a second main surface 14 opposite to third main surface 13. Polytype of silicon carbide substrate 10 and silicon carbide epitaxial film 20 is 4H. As shown in FIG. 1, the silicon carbide epitaxial substrate 100 may be provided with a first flat 16 extending in the first direction 101. Silicon carbide epitaxial substrate 100 may be provided with a second flat (not shown) extending in second direction 102.
  • the second direction 102 is, for example, the ⁇ 1-100> direction.
  • the first direction 101 is a direction parallel to the second main surface 14 and perpendicular to the second direction 102.
  • the first direction 101 is a direction including, for example, a ⁇ 11-20> direction component.
  • the maximum diameter 111 (diameter) of the second main surface 14 is, for example, 100 mm or more.
  • the maximum diameter 111 may be 150 mm or more, 200 mm or more, or 250 mm or more.
  • the upper limit of the maximum diameter 111 is not particularly limited.
  • the upper limit of the maximum diameter 111 may be 300 mm, for example.
  • Silicon carbide substrate 10 is made of, for example, a silicon carbide single crystal. Silicon carbide substrate 10 includes an n-type impurity such as nitrogen (N), for example. Silicon carbide substrate 10 has an n conductivity type, for example.
  • the first main surface 11 is a surface inclined by an angle of 8 ° or less from the ⁇ 0001 ⁇ plane. When the first main surface 11 is inclined from the ⁇ 0001 ⁇ plane, the inclination direction of the normal line of the first main surface 11 is, for example, the ⁇ 11-20> direction. Silicon carbide substrate 10 has a thickness of not less than 350 ⁇ m and not more than 500 ⁇ m, for example.
  • silicon carbide epitaxial film 20 is on first main surface 11 of silicon carbide substrate 10.
  • Silicon carbide epitaxial film 20 is an epitaxial layer. Silicon carbide epitaxial film 20 is in contact with first main surface 11.
  • Silicon carbide epitaxial film 20 includes an n-type impurity such as nitrogen.
  • the conductivity type of silicon carbide epitaxial film 20 is n-type, for example.
  • the second main surface 14 is a surface in which the ⁇ 0001 ⁇ plane is inclined in the off direction by an off angle ⁇ (°). Specifically, the second main surface 14 may be a surface in which the (0001) plane is inclined by 8 ° or less in the off direction.
  • the second main surface 14 may be a surface in which the (000-1) plane is inclined by 8 ° or less in the off direction.
  • the off direction is, for example, the ⁇ 11-20> direction. Note that the off direction is not limited to the ⁇ 11-20> direction.
  • the off direction may be, for example, a ⁇ 1-100> direction, or a direction having a ⁇ 1-100> direction component and a ⁇ 11-20> direction component.
  • the off angle ⁇ is an angle at which the second main surface 14 is inclined with respect to the ⁇ 0001 ⁇ plane.
  • the off-angle ⁇ is an angle at which the normal line of the second main surface 14 is inclined with respect to the ⁇ 0001> direction.
  • the off angle ⁇ is, for example, larger than 0 ° and not larger than 8 °.
  • the off angle ⁇ may be 1 ° or more, or 2 ° or more.
  • the off angle may be 7 ° or less, or 6 ° or less.
  • the surface indicated by a broken line is, for example, the ⁇ 0001 ⁇ surface.
  • the third direction 103 is a direction perpendicular to the ⁇ 0001 ⁇ plane.
  • the third direction 103 is, for example, the ⁇ 0001> direction.
  • the fourth direction 104 is a direction perpendicular to the third direction 103.
  • the fourth direction 104 is, for example, the ⁇ 11-20> direction.
  • the fourth direction 104 is an off direction.
  • the normal direction of the second main surface 14 is the fifth direction 105.
  • the fifth direction is a direction inclined by an off angle ⁇ in the off direction with respect to the ⁇ 0001> direction.
  • Silicon carbide epitaxial film 20 includes a first layer 21 and a second layer 22.
  • the first layer is, for example, the buffer layer 21.
  • the second layer 22 is, for example, the drift layer 22.
  • the buffer layer 21 is in contact with the first main surface 11.
  • the first layer 21 constitutes the third major surface 13.
  • the second layer 22 is on the first layer 21.
  • the second layer 22 constitutes the second main surface 14.
  • Silicon carbide substrate 10, first layer 21, and second layer 22 contain n-type impurities.
  • Buffer layer 21 contains an n-type impurity such as nitrogen, for example.
  • the concentration of the n-type impurity contained in the buffer layer 21 is, for example, 1 ⁇ 10 18 cm ⁇ 3 .
  • the concentration of the n-type impurity included in the buffer layer 21 may be, for example, 0.2 ⁇ 10 18 cm ⁇ 3 or more and 9 ⁇ 10 18 cm ⁇ 3 or less.
  • the concentration of the n-type impurity included in the drift layer is, for example, 8 ⁇ 10 15 cm ⁇ 3 .
  • the concentration of n-type impurities included in first layer 21 is lower than the concentration of n-type impurities included in silicon carbide substrate 10 and higher than the concentration of n-type impurities included in second layer 22.
  • the concentration of the n-type impurity is measured by, for example, a mercury probe type CV measuring device.
  • the area of the probe is, for example, 0.005 cm 2 .
  • Silicon carbide substrate 10 and silicon carbide epitaxial film 20 have basal plane dislocations 1.
  • Basal plane dislocation 1 is exposed on both first main surface 11 and first main surface 12 of silicon carbide substrate 10.
  • the basal plane dislocation 1 extends in a direction parallel to the ⁇ 0001 ⁇ plane.
  • the basal plane dislocation 1 has, for example, a first basal plane dislocation 25, a second basal plane dislocation 26, and a third basal plane dislocation 27.
  • Silicon carbide epitaxial film 20 has fourth basal plane dislocations 37 and threading edge dislocations 2.
  • the fourth basal plane dislocation 37 and the threading edge dislocation 2 are exposed on the second main surface 14.
  • the threading edge dislocation 2 has, for example, a first threading edge dislocation 35 and a second threading edge dislocation 36.
  • the first threading edge dislocation 35 is a dislocation formed by converting the first basal plane dislocation 25.
  • the second threading edge dislocation 36 is a dislocation formed by converting the second basal plane dislocation 26.
  • the threading edge dislocation 2 extends along a third direction 103 substantially perpendicular to ⁇ 0001 ⁇ .
  • the fourth basal plane dislocation 37 is a dislocation that inherits the third basal plane dislocation 27.
  • basal plane dislocation 1 exists in silicon carbide epitaxial substrate 100, for example, the reliability of the gate insulating film formed on silicon carbide epitaxial substrate 100 deteriorates.
  • the threading edge dislocation 2 exists in the silicon carbide epitaxial substrate, it hardly affects the reliability of the gate insulating film formed on the silicon carbide epitaxial substrate. Therefore, it is desirable to convert the basal plane dislocations 1 existing in the silicon carbide substrate 10 into threading edge dislocations 2 and reduce the number of basal plane dislocations 1 in the silicon carbide epitaxial film 20.
  • main surface 12 of silicon carbide substrate 10 has basal plane dislocations 1 having a first surface density.
  • Main surface 14 of silicon carbide epitaxial film 20 has basal plane dislocations 1 having a second surface density lower than the first surface density.
  • a value obtained by dividing the second surface density by the first surface density is 2/10000 or less. In other words, the ratio of conversion from the basal plane dislocation 1 to the threading edge dislocation 2 (conversion rate) is 99.98% or more.
  • a value obtained by dividing the second surface density by the first surface density may be, for example, 1/10000 or less. In other words, the ratio of conversion from the basal plane dislocation 1 to the threading edge dislocation 2 (conversion rate) is 99.99% or more.
  • the second surface density is, for example, 1 cm ⁇ 2 or less.
  • the second surface density may be, for example, 0.8 cm ⁇ 2 or less, or 0.5 cm ⁇ 2 or less.
  • the lower limit of the first surface density is limited, the first surface density may be for example 2000 cm -2 or more, or may be 2500 cm -2 or more.
  • the first surface density may be at 6000 cm -2 or less, may be 5500Cm -2 or less.
  • a photoluminescence imaging apparatus (model number: PLIS-100) manufactured by Photon Design Co., Ltd. is used.
  • PLIS-100 photoluminescence imaging apparatus
  • Excitation light from the light source passes through a 313 nm band-pass filter and is then applied to the measurement region.
  • the photoluminescence light reaches a light receiving element such as a camera after passing through a low pass filter of 750 nm, for example.
  • a photoluminescence image of the region to be measured is taken.
  • the measurement temperature is room temperature.
  • a photoluminescence image of the main surface is photographed while moving the silicon carbide epitaxial substrate in a direction parallel to the main surface (specifically, second main surface 14 or first main surface 12) of the silicon carbide epitaxial substrate. .
  • region of a main surface is mapped.
  • the basal plane dislocation is specified in the acquired photoluminescence image, and the total number of the basal plane dislocation is calculated. By dividing the total number of basal plane dislocations by the total measurement area, the surface density of the basal plane dislocations is calculated.
  • the calculation of the surface density of the basal plane dislocations on the main surface of the silicon carbide epitaxial substrate may be performed, for example, by counting pits generated using a potassium hydroxide (KOH) melt. Specifically, the main surface is etched using a KOH melt. The temperature of the KOH melt is, for example, about 500 ° C. or more and 550 ° C. or less. The etching time is, for example, about 5 to 10 minutes. After etching, the main surface is observed with a normalsky differential interference microscope. The basal plane dislocation is etched by the KOH melt to form pits. By dividing the total number of pits by the total measurement area, the surface density of the basal plane dislocation is calculated.
  • KOH potassium hydroxide
  • the threading edge dislocations also form pits in the same manner as the basal plane dislocations.
  • Pits derived from threading edge dislocations and pits derived from basal plane dislocations are distinguished as follows. Rounded hexagonal pits are derived from threading edge dislocations, and elliptical pits are derived from basal plane dislocations.
  • the basal plane dislocation penetrates the inside of the silicon carbide substrate and reaches each of the first main surface 12 and the first main surface 11. Therefore, it can be estimated that the surface density of the basal plane dislocations in the first main surface 12 is the same as the surface density of the basal plane dislocations in the first main surface 11.
  • the first main surface 12 is a (000-1) plane or a (000-1) plane inclined by 8 ° or less in the off direction
  • etch pits are formed on the first main surface 12 by the KOH melt. Hard to appear.
  • the surface density of basal plane dislocations on first main surface 11 of silicon carbide substrate 10 may be measured.
  • the (0001) plane or the (0001) plane is off the first main surface 11
  • the surface is inclined by 8 ° or less in the direction. Therefore, etch pits are likely to appear on the first main surface 11 as compared to the first main surface 12. It is estimated that the surface density of the basal plane dislocations in the first main surface 11 is the same as the surface density of the basal plane dislocations in the first main surface 12.
  • a silicon carbide epitaxial substrate 100 manufacturing apparatus 200 is, for example, a hot-wall lateral CVD (Chemical Vapor Deposition) apparatus.
  • the manufacturing apparatus 200 mainly includes a reaction chamber 201, a heating element 203, a quartz tube 204, a heat insulating material 205, and an induction heating coil 206.
  • the heating element 203 has a cylindrical shape, for example, and forms a reaction chamber 201 inside.
  • the heating element 203 is made of, for example, graphite.
  • the heat insulating material 205 surrounds the outer periphery of the heating element 203.
  • the heat insulating material 205 is provided inside the quartz tube 204 so as to contact the inner peripheral surface of the quartz tube 204.
  • the induction heating coil 206 is wound, for example, along the outer peripheral surface of the quartz tube 204.
  • the induction heating coil 206 is configured to be able to supply an alternating current by an external power source (not shown). Thereby, the heating element 203 is induction-heated. As a result, the reaction chamber 201 is heated by the heating element 203.
  • the reaction chamber 201 is a space formed by being surrounded by the heating element 203. Silicon carbide substrate 10 is arranged in reaction chamber 201. Reaction chamber 201 is configured to heat silicon carbide substrate 10. Reaction chamber 201 is provided with a susceptor 210 that holds silicon carbide substrate 10. The susceptor 210 is configured to be able to rotate around the rotation shaft 212.
  • the manufacturing apparatus 200 has a gas introduction port 207 and a gas exhaust port 208.
  • the gas exhaust port 208 is connected to an exhaust pump (not shown).
  • the arrows in FIG. 6 indicate the gas flow.
  • the gas is introduced into the reaction chamber 201 from the gas introduction port 207 and exhausted from the gas exhaust port 208.
  • the pressure in the reaction chamber 201 is adjusted by the balance between the gas supply amount and the gas exhaust amount.
  • the manufacturing apparatus 200 has a gas supply unit (not shown) configured to be able to supply, for example, a mixed gas containing silane, ammonia, hydrogen, and propane to the reaction chamber 201.
  • the gas supply unit includes a gas cylinder capable of supplying propane gas diluted with hydrogen, a gas cylinder capable of supplying hydrogen gas, a gas cylinder capable of supplying silane gas, and a gas cylinder capable of supplying ammonia gas. You may have.
  • propane gas diluted with hydrogen propane gas is 30% by volume and hydrogen gas is 70% by volume.
  • the winding density of the induction heating coil 206 may be changed.
  • the winding density [times / m] is the number of coil turns per unit length in the axial direction of the apparatus.
  • the winding density of the induction heating coil 206 on the upstream side may be higher than the winding density of the induction heating coil 206 on the downstream side.
  • a silicon carbide single crystal substrate preparation step (S11: FIG. 4) is performed.
  • a polytype 4H silicon carbide single crystal is manufactured by a sublimation method.
  • silicon carbide substrate 10 is prepared by slicing the silicon carbide single crystal with, for example, a wire saw.
  • Silicon carbide substrate 10 includes an n-type impurity such as nitrogen, for example.
  • Silicon carbide substrate 10 has an n conductivity type, for example.
  • silicon carbide substrate 10 has a first main surface 11 and a third main surface 13 on the opposite side of first main surface 11.
  • the first major surface 11 is, for example, a surface in which the ⁇ 0001 ⁇ plane is inclined in the off direction by the off angle ⁇ .
  • the off direction is, for example, the ⁇ 11-20> direction.
  • the maximum diameter of first main surface 11 of silicon carbide substrate 10 is, for example, 100 mm or more.
  • a plurality of basal plane dislocations 1 exist in silicon carbide substrate 10.
  • the basal plane dislocation 1 extends in a direction parallel to the ⁇ 0001 ⁇ plane.
  • the basal plane dislocation 1 has, for example, a first basal plane dislocation 25, a second basal plane dislocation 26, and a third basal plane dislocation 27.
  • Silicon carbide substrate 10 is arranged on susceptor 210 in reaction chamber 201 (see FIG. 3). For example, after the pressure in reaction chamber 201 is reduced from atmospheric pressure to about 1 ⁇ 10 ⁇ 6 Pa, the temperature rise of silicon carbide substrate 10 is started. As shown in FIG. 7, the temperature of silicon carbide substrate 10 increases from room temperature to first temperature A1 from time T0 to time T1. The first temperature A1 is 1605 ° C., for example.
  • a buffer layer forming step (S12: FIG. 4) is performed.
  • first temperature A1 source gas, dopant gas, and carrier gas are supplied to reaction chamber 201.
  • a mixed gas containing silane, propane, ammonia, and hydrogen is supplied to the reaction chamber 201.
  • silicon carbide substrate 10 is maintained at first temperature A1 from time T1 to time T2.
  • the time from time T1 to time T2 is, for example, not less than 3 minutes and not more than 60 minutes.
  • each gas is thermally decomposed, and buffer layer 21 is formed on silicon carbide substrate 10 (see FIG. 6).
  • the susceptor 210 rotates around the rotation shaft 212.
  • Silicon carbide substrate 10 revolves around rotating shaft 212 (see FIG. 3).
  • the flow rates of silane and propane are adjusted so that the C / Si ratio is, for example, 0.95.
  • the flow rate of the silane gas is adjusted to 57.6 sccm, for example.
  • the flow rate of the propane gas (30% by volume) diluted with hydrogen is adjusted to be, for example, 18.2 sccm.
  • the flow rate of hydrogen gas is adjusted to be 130 slm.
  • the concentration of the n-type impurity (N) doped in the buffer layer 21 is, for example, about 0.2 ⁇ 10 18 cm ⁇ 3 to 9 ⁇ 10 18 cm ⁇ 3 .
  • the thickness of the buffer layer 21 is, for example, 1 ⁇ m.
  • the pressure in the reaction chamber 201 is, for example, 5 kPa.
  • most of the plurality of basal plane dislocations 1 existing in the silicon carbide substrate 10 are converted into threading edge dislocations 2.
  • the first basal plane dislocation 25 is converted into the first threading edge dislocation 35.
  • the second basal plane dislocation 26 is converted into the second threading edge dislocation 36.
  • the third basal plane dislocations 27 are not converted into threading edge dislocations, but propagate in the buffer layer 21 as fourth basal plane dislocations 37.
  • the drift layer forming step (S13: FIG. 4) is performed.
  • the temperature rise of silicon carbide substrate 10 is started again. Specifically, the temperature of silicon carbide substrate 10 rises from first temperature A1 to second temperature A2 from time T2 to time T3.
  • the second temperature A2 is 1640 ° C., for example.
  • a mixed gas containing silane, propane, ammonia, and hydrogen is supplied to the reaction chamber 201 in a state where the temperature of the silicon carbide substrate 10 is maintained at the second temperature A2.
  • silicon carbide substrate 10 is maintained at second temperature A2.
  • the time from time T3 to time T4 is, for example, not less than 30 minutes and not more than 600 minutes.
  • each gas is thermally decomposed, and the drift layer 22 is formed on the buffer layer 21 (see FIGS. 2 and 5).
  • the susceptor 210 rotates around the rotation axis 212.
  • Silicon carbide substrate 10 revolves around rotating shaft 212 (see FIG. 3).
  • the flow rates of silane and propane are adjusted so that the C / Si ratio is about 1.35.
  • the flow rate of the silane gas is adjusted to 140 sccm, for example.
  • the flow rate of propane gas (30% by volume) diluted with hydrogen is adjusted to 63 sccm, for example.
  • the flow rate of hydrogen gas is adjusted to 134 slm.
  • the concentration of carriers doped in the drift layer 22 is, for example, about 8 ⁇ 10 15 cm ⁇ 3 .
  • the thickness of the drift layer 22 is, for example, about 10 ⁇ m to 30 ⁇ m.
  • the pressure in the reaction chamber 201 is, for example, 6 kPa.
  • the difference in thermal expansion between the buffer layer and the drift layer having different thermal expansion coefficients can be reduced. Since the absolute value becomes small and the strain can be kept small, the ratio of the basal plane dislocations to threading edge dislocations (conversion rate) can be improved.
  • a cooling process is performed. As shown in FIG. 7, from time T4 to time T5, the temperature of the silicon carbide substrate is reduced from second temperature A2 to room temperature. As described above, silicon carbide epitaxial substrate 100 is manufactured.
  • the method for manufacturing a silicon carbide semiconductor device mainly includes an epitaxial substrate preparation step (S10: FIG. 8) and a substrate processing step (S20: FIG. 8).
  • an epitaxial substrate preparation step (S10: FIG. 8) is performed. Specifically, silicon carbide epitaxial substrate 100 is prepared by the above-described method for manufacturing a silicon carbide epitaxial substrate (see FIG. 4).
  • a substrate processing step (S20: FIG. 8) is performed.
  • a silicon carbide semiconductor device is manufactured by processing a silicon carbide epitaxial substrate.
  • “Processing” includes, for example, various processes such as ion implantation, heat treatment, etching, oxide film formation, electrode formation, and dicing. That is, the substrate processing step may include at least one of ion implantation, heat treatment, etching, oxide film formation, electrode formation, and dicing.
  • the substrate processing step (S20: FIG. 8) includes, for example, an ion implantation step (S21: FIG. 8), an oxide film formation step (S22: FIG. 8), an electrode formation step (S23: FIG. 8), and a dicing step (S24: FIG. 8). )including.
  • an ion implantation step (S21: FIG. 8) is performed.
  • a p-type impurity such as aluminum (Al) is implanted into second main surface 14 on which a mask (not shown) having an opening is formed. Thereby, body region 132 having p-type conductivity is formed.
  • an n-type impurity such as phosphorus (P) is implanted into a predetermined position in body region 132. Thereby, a source region 133 having n-type conductivity is formed.
  • a p-type impurity such as aluminum is implanted into a predetermined position in the source region 133. As a result, a contact region 134 having a p-type conductivity is formed (see FIG. 9).
  • Source region 133 is separated from drift region 131 by body region 132.
  • Ion implantation may be performed by heating silicon carbide epitaxial substrate 100 to about 300 ° C. or more and 600 ° C. or less.
  • activation annealing is performed on silicon carbide epitaxial substrate 100.
  • the atmosphere of activation annealing is, for example, an argon (Ar) atmosphere.
  • the temperature of activation annealing is, for example, about 1800 ° C.
  • the activation annealing time is, for example, about 30 minutes.
  • oxide film forming step (S22: FIG. 8) is performed.
  • silicon carbide epitaxial substrate 100 is heated in an atmosphere containing oxygen, whereby oxide film 136 is formed on second main surface 14 (see FIG. 10).
  • Oxide film 136 is made of, for example, silicon dioxide.
  • the oxide film 136 functions as a gate insulating film.
  • the temperature of the thermal oxidation treatment is, for example, about 1300 ° C.
  • the time for the thermal oxidation treatment is, for example, about 30 minutes.
  • heat treatment may be performed in a nitrogen atmosphere.
  • the heat treatment is performed in an atmosphere of nitric oxide at about 1100 ° C. for about 1 hour.
  • heat treatment is performed in an argon atmosphere.
  • the heat treatment is performed in an argon atmosphere at about 1100 ° C. to 1500 ° C. for about 1 hour.
  • the first electrode 141 is formed on the oxide film 136.
  • the first electrode 141 functions as a gate electrode.
  • the first electrode 141 is formed by, for example, a CVD method.
  • the first electrode 141 is made of, for example, conductive polysilicon.
  • the first electrode 141 is formed at a position facing the source region 133 and the body region 132.
  • Interlayer insulating film 137 covering the first electrode 141 is formed.
  • Interlayer insulating film 137 is formed by, for example, a CVD method.
  • Interlayer insulating film 137 is made of, for example, silicon dioxide.
  • the interlayer insulating film 137 is formed so as to be in contact with the first electrode 141 and the oxide film 136.
  • the oxide film 136 and the interlayer insulating film 137 at predetermined positions are removed by etching. As a result, the source region 133 and the contact region 134 are exposed from the oxide film 136.
  • the second electrode 142 is formed on the exposed portion by, for example, a sputtering method.
  • the second electrode 142 functions as a source electrode.
  • Second electrode 142 is made of, for example, titanium, aluminum, silicon, or the like.
  • second electrode 142 and silicon carbide epitaxial substrate 100 are heated at a temperature of about 900 ° C. to 1100 ° C., for example. Thereby, second electrode 142 and silicon carbide epitaxial substrate 100 come into ohmic contact.
  • the wiring layer 138 is formed so as to be in contact with the second electrode 142.
  • the wiring layer 138 is made of a material containing aluminum, for example.
  • the third electrode 143 is formed on the third main surface 13.
  • the third electrode 143 functions as a drain electrode.
  • Third electrode 143 is made of, for example, an alloy containing nickel and silicon (eg, NiSi).
  • a dicing step (S24: FIG. 8) is performed.
  • silicon carbide epitaxial substrate 100 is diced along a dicing line, whereby silicon carbide epitaxial substrate 100 is divided into a plurality of semiconductor chips.
  • silicon carbide semiconductor device 300 is manufactured (see FIG. 11).
  • the method for manufacturing the silicon carbide semiconductor device according to the present disclosure has been described by exemplifying the MOSFET, but the manufacturing method according to the present disclosure is not limited to this.
  • the manufacturing method according to the present disclosure can be applied to silicon carbide semiconductor devices such as IGBT (Insulated Gate Bipolar Transistor), SBD (Schottky Barrier Diode), thyristor, GTO (Gate Turn Off thyristor), and PiN diode.
  • IGBT Insulated Gate Bipolar Transistor
  • SBD Schottky Barrier Diode
  • thyristor thyristor
  • GTO Gate Turn Off thyristor
  • PiN diode PiN diode
  • a silicon carbide substrate according to Sample 1-5 was prepared.
  • a silicon carbide epitaxial film was grown on the silicon carbide substrate according to Sample 1-5.
  • a silicon carbide epitaxial film was formed using the temperature profile shown by the solid line in FIG. 7 of the present embodiment. Specifically, the temperature of the step of forming the buffer layer (A1: see FIG. 7) was 1605 ° C., and the temperature of the step of forming the drift layer (A2: see FIG. 7) was 1640 ° C.
  • a silicon carbide epitaxial film was formed using the temperature profile shown by the one-dot chain line in FIG.
  • the temperature of the step of forming the buffer layer (A1: see FIG. 7) and the temperature of the step of forming the drift layer (A2: see FIG. 7) were both 1640 ° C.
  • the silicon carbide epitaxial substrate according to Sample 1-5 was manufactured.
  • the surface density of basal plane dislocations on the second main surface and main surface of the silicon carbide epitaxial substrate according to Sample 1-5 was measured.
  • the surface density of the basal plane dislocation was measured using the above-described measurement method.
  • Table 1 shows the surface density (first surface density) of basal plane dislocations on the main surface of the silicon carbide substrate, the surface density (second surface density) of basal plane dislocations on the main surface of the silicon carbide epitaxial film, and the second surface.
  • the value obtained by dividing the density by the first surface density and the conversion rate from the basal plane dislocation to the threading edge dislocation are shown.
  • the values obtained by dividing the second surface density by the first surface density are 0.000152, 0.000157, 0.000006, and 0, respectively. 0.00001 and 0.012032.
  • the conversion ratios obtained as values obtained by subtracting the second surface density from the first surface density by the first surface density were 99.9848%, 99.9843%, 99.99994%, 99.9989% and 98.7968%.

Abstract

This silicon carbide epitaxial substrate comprises a silicon carbide substrate and a silicon carbide epitaxial film. The silicon carbide epitaxial film is present on the silicon carbide substrate. The polytype of the silicon carbide substrate and the silicon carbide epitaxial film is 4H. The silicon carbide epitaxial film comprises a first layer that is in contact with the silicon carbide substrate and a second layer that is on the first layer and constitutes the main surface of the silicon carbide epitaxial film. The silicon carbide substrate, the first layer and the second layer contain an n-type impurity. The concentration of the n-type impurity contained in the first layer is lower than the concentration of the n-type impurity contained in the silicon carbide substrate, but is higher than the concentration of the n-type impurity contained in the second layer. The main surface of the silicon carbide substrate has a basal plane dislocation having a first area density. The main surface of the silicon carbide epitaxial film has a basal plane dislocation having a second area density that is lower than the first area density. The value obtained by dividing the second area density by the first area density is 2/10,000 or less.

Description

炭化珪素エピタキシャル基板および炭化珪素半導体装置の製造方法Silicon carbide epitaxial substrate and method for manufacturing silicon carbide semiconductor device
　本開示は、炭化珪素エピタキシャル基板および炭化珪素半導体装置の製造方法に関する。本出願は、２０１６年１２月２７日に出願した日本特許出願である特願２０１６－２５３６４６号に基づく優先権を主張する。当該日本特許出願に記載された全ての記載内容は、参照によって本明細書に援用される。 The present disclosure relates to a silicon carbide epitaxial substrate and a method for manufacturing a silicon carbide semiconductor device. This application claims priority based on Japanese Patent Application No. 2016-253646, which is a Japanese patent application filed on December 27, 2016. All the descriptions described in the Japanese patent application are incorporated herein by reference.
　特開２０１４－１７０８９１号公報（特許文献１）には、炭化珪素単結晶基板上に炭化珪素層をエピタキシャル成長させる方法が開示されている。 Japanese Patent Laying-Open No. 2014-170891 (Patent Document 1) discloses a method of epitaxially growing a silicon carbide layer on a silicon carbide single crystal substrate.
特開２０１４－１７０８９１号公報JP 2014-170891 A
　本開示に係る炭化珪素エピタキシャル基板は、炭化珪素基板と、炭化珪素エピタキシャル膜とを備えている。炭化珪素エピタキシャル膜は、炭化珪素基板上にある。炭化珪素基板および炭化珪素エピタキシャル膜のポリタイプは、４Ｈである。炭化珪素エピタキシャル膜は、炭化珪素基板に接する第１層と、第１層上にありかつ炭化珪素エピタキシャル膜の主表面を構成する第２層とを含む。炭化珪素基板と、第１層と、第２層とは、ｎ型不純物を含む。第１層が含むｎ型不純物の濃度は、炭化珪素基板が含むｎ型不純物の濃度より低く、かつ第２層が含むｎ型不純物の濃度より高い。炭化珪素基板の主表面には、第１面密度を有する基底面転位がある。炭化珪素エピタキシャル膜の主表面には、第１面密度よりも低い第２面密度を有する基底面転位がある。第２面密度を、第１面密度で除した値は、２／１００００以下である。 The silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial film. The silicon carbide epitaxial film is on the silicon carbide substrate. The polytype of the silicon carbide substrate and the silicon carbide epitaxial film is 4H. The silicon carbide epitaxial film includes a first layer in contact with the silicon carbide substrate and a second layer on the first layer and constituting the main surface of the silicon carbide epitaxial film. The silicon carbide substrate, the first layer, and the second layer contain n-type impurities. The concentration of the n-type impurity included in the first layer is lower than the concentration of the n-type impurity included in the silicon carbide substrate and higher than the concentration of the n-type impurity included in the second layer. There is a basal plane dislocation having a first surface density on the main surface of the silicon carbide substrate. There is a basal plane dislocation having a second surface density lower than the first surface density on the main surface of the silicon carbide epitaxial film. A value obtained by dividing the second surface density by the first surface density is 2/10000 or less.
図１は、本実施形態に係る炭化珪素エピタキシャル基板の構成を示す平面模式図である。FIG. 1 is a schematic plan view showing the configuration of the silicon carbide epitaxial substrate according to the present embodiment. 図２は、本実施形態に係る炭化珪素エピタキシャル基板の構成を示す断面模式図である。FIG. 2 is a schematic cross-sectional view showing the configuration of the silicon carbide epitaxial substrate according to the present embodiment. 図３は、本実施形態に係る炭化珪素エピタキシャル基板の製造装置の構成を示す一部断面模式図である。FIG. 3 is a partial schematic cross-sectional view showing the configuration of the silicon carbide epitaxial substrate manufacturing apparatus according to this embodiment. 図４は、本実施形態に係る炭化珪素エピタキシャル基板の製造方法を概略的に示すフローチャートである。FIG. 4 is a flowchart schematically showing a method for manufacturing the silicon carbide epitaxial substrate according to the present embodiment. 図５は、本実施形態に係る炭化珪素エピタキシャル基板の製造方法の第１工程を示す断面模式図である。FIG. 5 is a schematic cross-sectional view showing a first step of the method for manufacturing the silicon carbide epitaxial substrate according to the present embodiment. 図６は、本実施形態に係る炭化珪素エピタキシャル基板の製造方法の第２工程を示す断面模式図である。FIG. 6 is a schematic cross-sectional view showing a second step of the method for manufacturing the silicon carbide epitaxial substrate according to the present embodiment. 図７は、本実施形態に係る炭化珪素エピタキシャル基板の製造方法における温度と時間との関係を示す図である。FIG. 7 is a diagram showing a relationship between temperature and time in the method for manufacturing a silicon carbide epitaxial substrate according to the present embodiment. 図８は、本実施形態に係る炭化珪素半導体装置の製造方法を概略的に示すフローチャートである。FIG. 8 is a flowchart schematically showing a method for manufacturing the silicon carbide semiconductor device according to the present embodiment. 図９は、本実施形態に係る炭化珪素半導体装置の製造方法の第１工程を示す断面模式図である。FIG. 9 is a schematic cross-sectional view showing a first step of the method for manufacturing the silicon carbide semiconductor device according to this embodiment. 図１０は、本実施形態に係る炭化珪素半導体装置の製造方法の第２工程を示す断面模式図である。FIG. 10 is a schematic cross-sectional view showing a second step of the method for manufacturing the silicon carbide semiconductor device according to this embodiment. 図１１は、本実施形態に係る炭化珪素半導体装置の構成を示す断面模式図である。FIG. 11 is a schematic cross-sectional view showing the configuration of the silicon carbide semiconductor device according to this embodiment.
　［本開示の実施形態の概要］
　まず本開示の実施形態の概要について説明する。本明細書の結晶学的記載においては、個別方位を［］、集合方位を＜＞、個別面を（）、集合面を｛｝でそれぞれ示す。結晶学上の指数が負であることは、通常、数字の上に”－”（バー）を付すことによって表現されるが、本明細書では数字の前に負の符号を付すことによって結晶学上の負の指数を表現する。 [Outline of Embodiment of the Present Disclosure]
First, an outline of an embodiment of the present disclosure will be described. In the crystallographic description of the present specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. A negative crystallographic index is usually expressed by adding a “-” (bar) above a number, but in this specification the crystallographic index is preceded by a negative sign. Represents the negative exponent above.
　（１）本開示に係る炭化珪素エピタキシャル基板１００は、炭化珪素基板１０と、炭化珪素エピタキシャル膜２０とを備えている。炭化珪素エピタキシャル膜２０は、炭化珪素基板１０上にある。炭化珪素基板１０および炭化珪素エピタキシャル膜２０のポリタイプは、４Ｈである。炭化珪素エピタキシャル膜２０は、炭化珪素基板１０に接する第１層２１と、第１層２１上にありかつ炭化珪素エピタキシャル膜２０の主表面１４を構成する第２層２２とを含む。炭化珪素基板１０と、第１層２１と、第２層２２とは、ｎ型不純物を含む。第１層２１が含むｎ型不純物の濃度は、炭化珪素基板１０が含むｎ型不純物の濃度より低く、かつ第２層２２が含むｎ型不純物の濃度より高い。炭化珪素基板１０の主表面１２には、第１面密度を有する基底面転位１がある。炭化珪素エピタキシャル膜２０の主表面１４には、第１面密度よりも低い第２面密度を有する基底面転位１がある。第２面密度を、第１面密度で除した値は、２／１００００以下である。これにより、炭化珪素エピタキシャル基板１００を用いて製造される炭化珪素半導体装置の信頼性を向上することができる。 (1) A silicon carbide epitaxial substrate 100 according to the present disclosure includes a silicon carbide substrate 10 and a silicon carbide epitaxial film 20. Silicon carbide epitaxial film 20 is on silicon carbide substrate 10. Polytype of silicon carbide substrate 10 and silicon carbide epitaxial film 20 is 4H. Silicon carbide epitaxial film 20 includes a first layer 21 in contact with silicon carbide substrate 10 and a second layer 22 on first layer 21 and constituting main surface 14 of silicon carbide epitaxial film 20. Silicon carbide substrate 10, first layer 21, and second layer 22 contain n-type impurities. The concentration of n-type impurities included in first layer 21 is lower than the concentration of n-type impurities included in silicon carbide substrate 10 and higher than the concentration of n-type impurities included in second layer 22. Main surface 12 of silicon carbide substrate 10 has basal plane dislocations 1 having a first surface density. Main surface 14 of silicon carbide epitaxial film 20 has basal plane dislocations 1 having a second surface density lower than the first surface density. A value obtained by dividing the second surface density by the first surface density is 2/10000 or less. Thereby, the reliability of the silicon carbide semiconductor device manufactured using silicon carbide epitaxial substrate 100 can be improved.
　（２）上記（１）に係る炭化珪素エピタキシャル基板１００において、炭化珪素エピタキシャル膜２０の主表面１４の最大径１１１は、１５０ｍｍ以上であってもよい。 (2) In silicon carbide epitaxial substrate 100 according to (1) above, maximum diameter 111 of main surface 14 of silicon carbide epitaxial film 20 may be 150 mm or more.
　（３）上記（１）または（２）に係る炭化珪素エピタキシャル基板１００において、第２面密度を、第１面密度で除した値は、１／１００００以下であってもよい。 (3) In silicon carbide epitaxial substrate 100 according to (1) or (2) above, the value obtained by dividing the second surface density by the first surface density may be 1/10000 or less.
　（４）上記（１）～（３）のいずれかに係る炭化珪素エピタキシャル基板１００において、第２面密度は、１ｃｍ-2以下であってもよい。 (4) In silicon carbide epitaxial substrate 100 according to any one of (1) to (3), the second surface density may be 1 cm −2 or less.
　（５）本開示に係る炭化珪素半導体装置３００の製造方法は以下の工程を備えている。上記（１）～（４）のいずれかに係る炭化珪素エピタキシャル基板１００が準備される。炭化珪素エピタキシャル基板１００が加工される。 (5) The method for manufacturing the silicon carbide semiconductor device 300 according to the present disclosure includes the following steps. Silicon carbide epitaxial substrate 100 according to any one of (1) to (4) above is prepared. Silicon carbide epitaxial substrate 100 is processed.
　［本開示の実施形態の詳細］
　以下、本開示の実施形態の詳細について説明する。以下の説明では、同一または対応する要素には同一の符号を付し、それらについて同じ説明は繰り返さない。 [Details of Embodiment of the Present Disclosure]
Hereinafter, details of the embodiment of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description is not repeated.
　（炭化珪素エピタキシャル基板）
　図１および図２に示されるように、本実施形態に係る炭化珪素エピタキシャル基板１００は、炭化珪素基板１０と、炭化珪素エピタキシャル膜２０とを有している。炭化珪素エピタキシャル膜２０は、炭化珪素基板１０上にある。炭化珪素基板１０は、第１主面１１と、第１主面１１と反対側の第１主表面１２とを有する。炭化珪素エピタキシャル膜２０は、第１主面１１と接する。炭化珪素エピタキシャル膜２０は、第１主面１１と接する第３主面１３と、第３主面１３と反対側の第２主表面１４とを有する。炭化珪素基板１０および炭化珪素エピタキシャル膜２０のポリタイプは、４Ｈである。図１に示されるように、炭化珪素エピタキシャル基板１００には、第１方向１０１に延在する第１フラット１６が設けられて入れてもよい。炭化珪素エピタキシャル基板１００には、第２方向１０２に延在する第２フラット（図示せず）が設けられていてもよい。 (Silicon carbide epitaxial substrate)
As shown in FIGS. 1 and 2, silicon carbide epitaxial substrate 100 according to the present embodiment includes silicon carbide substrate 10 and silicon carbide epitaxial film 20. Silicon carbide epitaxial film 20 is on silicon carbide substrate 10. Silicon carbide substrate 10 has a first main surface 11 and a first main surface 12 opposite to first main surface 11. Silicon carbide epitaxial film 20 is in contact with first main surface 11. Silicon carbide epitaxial film 20 has a third main surface 13 in contact with first main surface 11 and a second main surface 14 opposite to third main surface 13. Polytype of silicon carbide substrate 10 and silicon carbide epitaxial film 20 is 4H. As shown in FIG. 1, the silicon carbide epitaxial substrate 100 may be provided with a first flat 16 extending in the first direction 101. Silicon carbide epitaxial substrate 100 may be provided with a second flat (not shown) extending in second direction 102.
　第２方向１０２は、たとえば＜１－１００＞方向である。第１方向１０１は、第２主表面１４に対して平行であり、かつ第２方向１０２に対して垂直な方向である。第１方向１０１は、たとえば＜１１－２０＞方向成分を含む方向である。図１に示されるように、第２主表面１４の最大径１１１（直径）は、たとえば１００ｍｍ以上である。最大径１１１は１５０ｍｍ以上でもよいし、２００ｍｍ以上でもよいし、２５０ｍｍ以上でもよい。最大径１１１の上限は特に限定されない。最大径１１１の上限は、たとえば３００ｍｍであってもよい。 The second direction 102 is, for example, the <1-100> direction. The first direction 101 is a direction parallel to the second main surface 14 and perpendicular to the second direction 102. The first direction 101 is a direction including, for example, a <11-20> direction component. As shown in FIG. 1, the maximum diameter 111 (diameter) of the second main surface 14 is, for example, 100 mm or more. The maximum diameter 111 may be 150 mm or more, 200 mm or more, or 250 mm or more. The upper limit of the maximum diameter 111 is not particularly limited. The upper limit of the maximum diameter 111 may be 300 mm, for example.
　炭化珪素基板１０は、たとえば炭化珪素単結晶から構成される。炭化珪素基板１０は、たとえば窒素（Ｎ）などのｎ型不純物を含んでいる。炭化珪素基板１０の導電型は、たとえばｎ型である。第１主面１１は、｛０００１｝面から８°以下の角度だけ傾斜した面である。第１主面１１が｛０００１｝面から傾斜している場合、第１主面１１の法線の傾斜方向は、たとえば＜１１－２０＞方向である。炭化珪素基板１０の厚みは、たとえば３５０μｍ以上５００μｍ以下である。 Silicon carbide substrate 10 is made of, for example, a silicon carbide single crystal. Silicon carbide substrate 10 includes an n-type impurity such as nitrogen (N), for example. Silicon carbide substrate 10 has an n conductivity type, for example. The first main surface 11 is a surface inclined by an angle of 8 ° or less from the {0001} plane. When the first main surface 11 is inclined from the {0001} plane, the inclination direction of the normal line of the first main surface 11 is, for example, the <11-20> direction. Silicon carbide substrate 10 has a thickness of not less than 350 μm and not more than 500 μm, for example.
　図２に示されるように、炭化珪素エピタキシャル膜２０は、炭化珪素基板１０の第１主面１１上にある。炭化珪素エピタキシャル膜２０は、エピタキシャル層である。炭化珪素エピタキシャル膜２０は、第１主面１１に接している。炭化珪素エピタキシャル膜２０は、たとえば窒素などのｎ型不純物を含んでいる。炭化珪素エピタキシャル膜２０の導電型は、たとえばｎ型である。第２主表面１４は、｛０００１｝面がオフ方向にオフ角θ（°）だけ傾斜した面である。具体的には、第２主表面１４は、（０００１）面がオフ方向に８°以下傾斜した面であってもよい。代替的に、第２主表面１４は、（０００－１）面がオフ方向に８°以下傾斜した面であってもよい。オフ方向は、たとえば＜１１－２０＞方向である。なお、オフ方向は、＜１１－２０＞方向に限定されない。オフ方向は、たとえば＜１－１００＞方向であってもよいし、＜１－１００＞方向成分と＜１１－２０＞方向成分とを有する方向であってもよい。 As shown in FIG. 2, silicon carbide epitaxial film 20 is on first main surface 11 of silicon carbide substrate 10. Silicon carbide epitaxial film 20 is an epitaxial layer. Silicon carbide epitaxial film 20 is in contact with first main surface 11. Silicon carbide epitaxial film 20 includes an n-type impurity such as nitrogen. The conductivity type of silicon carbide epitaxial film 20 is n-type, for example. The second main surface 14 is a surface in which the {0001} plane is inclined in the off direction by an off angle θ (°). Specifically, the second main surface 14 may be a surface in which the (0001) plane is inclined by 8 ° or less in the off direction. Alternatively, the second main surface 14 may be a surface in which the (000-1) plane is inclined by 8 ° or less in the off direction. The off direction is, for example, the <11-20> direction. Note that the off direction is not limited to the <11-20> direction. The off direction may be, for example, a <1-100> direction, or a direction having a <1-100> direction component and a <11-20> direction component.
　オフ角θは、第２主表面１４が｛０００１｝面に対して傾斜している角度である。言い換えれば、オフ角θは、第２主表面１４の法線が＜０００１＞方向に対して傾斜している角度である。オフ角θは、たとえば０°より大きく８°以下である。オフ角θは、１°以上であってもよいし、２°以上であってもよい。オフ角は、７°以下であってもよいし、６°以下であってもよい。 The off angle θ is an angle at which the second main surface 14 is inclined with respect to the {0001} plane. In other words, the off-angle θ is an angle at which the normal line of the second main surface 14 is inclined with respect to the <0001> direction. The off angle θ is, for example, larger than 0 ° and not larger than 8 °. The off angle θ may be 1 ° or more, or 2 ° or more. The off angle may be 7 ° or less, or 6 ° or less.
　図２において破線で記載された面は、たとえば｛０００１｝面である。第３方向１０３は、｛０００１｝面に対して垂直な方向である。第３方向１０３は、たとえば＜０００１＞方向である。第４方向１０４は、第３方向１０３に対して垂直な方向である。第４方向１０４は、たとえば＜１１－２０＞方向である。第４方向１０４は、オフ方向である。第２主表面１４の法線方向は、第５方向１０５である。第５方向は、＜０００１＞方向に対してオフ方向にオフ角θだけ傾斜した方向である。 In FIG. 2, the surface indicated by a broken line is, for example, the {0001} surface. The third direction 103 is a direction perpendicular to the {0001} plane. The third direction 103 is, for example, the <0001> direction. The fourth direction 104 is a direction perpendicular to the third direction 103. The fourth direction 104 is, for example, the <11-20> direction. The fourth direction 104 is an off direction. The normal direction of the second main surface 14 is the fifth direction 105. The fifth direction is a direction inclined by an off angle θ in the off direction with respect to the <0001> direction.
　炭化珪素エピタキシャル膜２０は、第１層２１と、第２層２２とを含む。第１層は、たとえばバッファ層２１である。第２層２２は、たとえばドリフト層２２である。バッファ層２１は、第１主面１１に接している。第１層２１は、第３主面１３を構成する。第２層２２は、第１層２１上にある。第２層２２は、第２主表面１４を構成する。 Silicon carbide epitaxial film 20 includes a first layer 21 and a second layer 22. The first layer is, for example, the buffer layer 21. The second layer 22 is, for example, the drift layer 22. The buffer layer 21 is in contact with the first main surface 11. The first layer 21 constitutes the third major surface 13. The second layer 22 is on the first layer 21. The second layer 22 constitutes the second main surface 14.
　炭化珪素基板１０と、第１層２１と、第２層２２とは、ｎ型不純物を含む。バッファ層２１は、たとえば窒素などのｎ型不純物を含んでいる。バッファ層２１が含むｎ型不純物の濃度は、たとえば１×１０18ｃｍ-3である。バッファ層２１が含むｎ型不純物の濃度は、たとえば０．２×１０18ｃｍ-3以上９×１０18ｃｍ-3以下であってもよい。ドリフト層が含むｎ型不純物の濃度は、たとえば８×１０15ｃｍ-3である。第１層２１が含むｎ型不純物の濃度は、炭化珪素基板１０が含むｎ型不純物の濃度より低く、かつ第２層２２が含むｎ型不純物の濃度より高い。ｎ型不純物の濃度は、たとえば水銀プローブ方式のＣ－Ｖ測定装置により測定される。プローブの面積は、たとえば０．００５ｃｍ2である。 Silicon carbide substrate 10, first layer 21, and second layer 22 contain n-type impurities. Buffer layer 21 contains an n-type impurity such as nitrogen, for example. The concentration of the n-type impurity contained in the buffer layer 21 is, for example, 1 × 10 18 cm −3 . The concentration of the n-type impurity included in the buffer layer 21 may be, for example, 0.2 × 10 18 cm −3 or more and 9 × 10 18 cm −3 or less. The concentration of the n-type impurity included in the drift layer is, for example, 8 × 10 15 cm −3 . The concentration of n-type impurities included in first layer 21 is lower than the concentration of n-type impurities included in silicon carbide substrate 10 and higher than the concentration of n-type impurities included in second layer 22. The concentration of the n-type impurity is measured by, for example, a mercury probe type CV measuring device. The area of the probe is, for example, 0.005 cm 2 .
　炭化珪素基板１０および炭化珪素エピタキシャル膜２０は、基底面転位１を有している。基底面転位１は、炭化珪素基板１０の第１主面１１および第１主表面１２の双方に露出している。基底面転位１は、｛０００１｝面と平行な方向に延在している。基底面転位１は、たとえば第１基底面転位２５と、第２基底面転位２６と、第３基底面転位２７とを有する。炭化珪素エピタキシャル膜２０は、第４基底面転位３７と、貫通刃状転位２とを有する。第４基底面転位３７と、貫通刃状転位２とは、第２主表面１４に露出している。貫通刃状転位２は、たとえば第１貫通刃状転位３５と、第２貫通刃状転位３６とを有する。第１貫通刃状転位３５は、第１基底面転位２５が転換して形成された転位である。同様に、第２貫通刃状転位３６は、第２基底面転位２６が転換して形成された転位である。貫通刃状転位２は、｛０００１｝に対してほぼ垂直な第３方向１０３に沿って延在している。第４基底面転位３７は、第３基底面転位２７を引き継いだ転位である。 Silicon carbide substrate 10 and silicon carbide epitaxial film 20 have basal plane dislocations 1. Basal plane dislocation 1 is exposed on both first main surface 11 and first main surface 12 of silicon carbide substrate 10. The basal plane dislocation 1 extends in a direction parallel to the {0001} plane. The basal plane dislocation 1 has, for example, a first basal plane dislocation 25, a second basal plane dislocation 26, and a third basal plane dislocation 27. Silicon carbide epitaxial film 20 has fourth basal plane dislocations 37 and threading edge dislocations 2. The fourth basal plane dislocation 37 and the threading edge dislocation 2 are exposed on the second main surface 14. The threading edge dislocation 2 has, for example, a first threading edge dislocation 35 and a second threading edge dislocation 36. The first threading edge dislocation 35 is a dislocation formed by converting the first basal plane dislocation 25. Similarly, the second threading edge dislocation 36 is a dislocation formed by converting the second basal plane dislocation 26. The threading edge dislocation 2 extends along a third direction 103 substantially perpendicular to {0001}. The fourth basal plane dislocation 37 is a dislocation that inherits the third basal plane dislocation 27.
　基底面転位１が炭化珪素エピタキシャル基板１００に存在すると、たとえば炭化珪素エピタキシャル基板１００上に形成されるゲート絶縁膜の信頼性が劣化する。一方、貫通刃状転位２は、炭化珪素エピタキシャル基板に存在していても、炭化珪素エピタキシャル基板上に形成されるゲート絶縁膜の信頼性にはほとんど影響を与えない。そのため、炭化珪素基板１０に存在する基底面転位１を貫通刃状転位２に転換し、炭化珪素エピタキシャル膜２０における基底面転位１の数を低減することが望ましい。 If basal plane dislocation 1 exists in silicon carbide epitaxial substrate 100, for example, the reliability of the gate insulating film formed on silicon carbide epitaxial substrate 100 deteriorates. On the other hand, even though the threading edge dislocation 2 exists in the silicon carbide epitaxial substrate, it hardly affects the reliability of the gate insulating film formed on the silicon carbide epitaxial substrate. Therefore, it is desirable to convert the basal plane dislocations 1 existing in the silicon carbide substrate 10 into threading edge dislocations 2 and reduce the number of basal plane dislocations 1 in the silicon carbide epitaxial film 20.
　本実施形態に係る炭化珪素エピタキシャル基板１００において、炭化珪素基板１０の主表面１２には、第１面密度を有する基底面転位１がある。炭化珪素エピタキシャル膜２０の主表面１４には、第１面密度よりも低い第２面密度を有する基底面転位１がある。第２面密度を、第１面密度で除した値は、２／１００００以下である。言い換えれば、基底面転位１から貫通刃状転位２に転換した割合（転換率）は、９９．９８％以上である。第２面密度を、第１面密度で除した値は、たとえば１／１００００以下であってもよい。言い換えれば、基底面転位１から貫通刃状転位２に転換した割合（転換率）は、９９．９９％以上である。 In silicon carbide epitaxial substrate 100 according to the present embodiment, main surface 12 of silicon carbide substrate 10 has basal plane dislocations 1 having a first surface density. Main surface 14 of silicon carbide epitaxial film 20 has basal plane dislocations 1 having a second surface density lower than the first surface density. A value obtained by dividing the second surface density by the first surface density is 2/10000 or less. In other words, the ratio of conversion from the basal plane dislocation 1 to the threading edge dislocation 2 (conversion rate) is 99.98% or more. A value obtained by dividing the second surface density by the first surface density may be, for example, 1/10000 or less. In other words, the ratio of conversion from the basal plane dislocation 1 to the threading edge dislocation 2 (conversion rate) is 99.99% or more.
　第２面密度は、たとえば１ｃｍ-2以下である。第２面密度は、たとえば０．８ｃｍ-2以下であってもよいし、０．５ｃｍ-2以下であってもよい。第１面密度の下限は特に限定されないが、第１面密度はたとえば２０００ｃｍ-2以上であってもよいし、２５００ｃｍ-2以上であってもよい。第１面密度の上限は特に限定されないが、第１面密度は６０００ｃｍ-2以下であってもよいし、５５００ｃｍ-2以下であってもよい。 The second surface density is, for example, 1 cm −2 or less. The second surface density may be, for example, 0.8 cm −2 or less, or 0.5 cm −2 or less. But the lower limit of the first surface density is limited, the first surface density may be for example 2000 cm -2 or more, or may be 2500 cm -2 or more. Although not limit the first surface density is limited, the first surface density may be at 6000 cm -2 or less, may be 5500Cm -2 or less.
　（基底面転位の面密度の測定方法）
　次に、基底面転位の面密度の測定方法について説明する。基底面転位の観察には、たとえば株式会社フォトンデザイン社製のフォトルミネッセンスイメージング装置（型番：ＰＬＩＳ－１００）が用いられる。炭化珪素エピタキシャル基板の被測定領域に対して励起光が照射されると、被測定領域からフォトルミネッセンス光が観測される。励起光源としては、たとえば水銀キセノンランプが使用される。光源からの励起光は、３１３ｎｍのバンドパスフィルターを通過した後、被測定領域に照射される。フォトルミネッセンス光は、たとえば７５０ｎｍのローパスフィルタを通過した後、カメラ等の受光素子に到達する。以上のように、被測定領域のフォトルミネッセンス画像が撮影される。測定温度は、室温である。 (Measurement method of areal density of basal plane dislocation)
Next, a method for measuring the surface density of basal plane dislocations will be described. For observation of basal plane dislocation, for example, a photoluminescence imaging apparatus (model number: PLIS-100) manufactured by Photon Design Co., Ltd. is used. When excitation light is irradiated to the measurement region of the silicon carbide epitaxial substrate, photoluminescence light is observed from the measurement region. For example, a mercury xenon lamp is used as the excitation light source. Excitation light from the light source passes through a 313 nm band-pass filter and is then applied to the measurement region. The photoluminescence light reaches a light receiving element such as a camera after passing through a low pass filter of 750 nm, for example. As described above, a photoluminescence image of the region to be measured is taken. The measurement temperature is room temperature.
　たとえば炭化珪素エピタキシャル基板の主面（具体的には、第２主表面１４または第１主表面１２）と平行な方向に炭化珪素エピタキシャル基板を移動させながら、主面のフォトルミネッセンス画像が撮影される。これにより、主面の全領域におけるフォトルミネッセンス画像がマッピングされる。取得されたフォトルミネッセンス画像において基底面転位が特定され、当該基底面転位の合計数が計算される。基底面転位の合計数を全測定面積で除することにより、基底面転位の面密度が算出される。 For example, a photoluminescence image of the main surface is photographed while moving the silicon carbide epitaxial substrate in a direction parallel to the main surface (specifically, second main surface 14 or first main surface 12) of the silicon carbide epitaxial substrate. . Thereby, the photoluminescence image in the whole area | region of a main surface is mapped. The basal plane dislocation is specified in the acquired photoluminescence image, and the total number of the basal plane dislocation is calculated. By dividing the total number of basal plane dislocations by the total measurement area, the surface density of the basal plane dislocations is calculated.
　炭化珪素エピタキシャル基板の主面における基底面転位の面密度の算出は、たとえば水酸化カリウム（ＫＯＨ）融液を用いて発生させたピットを数えることにより行われてもよい。具体的には、主面がＫＯＨ融液を用いてエッチングされる。ＫＯＨ融液の温度は、たとえば５００℃以上５５０℃以下程度とする。エッチング時間は、たとえば５以上１０分以下程度とする。エッチング後、ノルマルスキー微分干渉顕微鏡によって主面が観察される。基底面転位はＫＯＨ融液によりエッチングされてピットを形成する。ピットの合計数を全測定面積で除することにより、基底面転位の面密度が算出される。なお、貫通刃状転位も基底面転位と同様にピットを形成する。貫通刃状転位に由来するピットと、基底面転位に由来するピットとは、以下のように区別する。丸みを帯びた六角形状のピットが貫通刃状転位に由来するものであり、楕円形状のピットが基底面転位に由来するものである。 The calculation of the surface density of the basal plane dislocations on the main surface of the silicon carbide epitaxial substrate may be performed, for example, by counting pits generated using a potassium hydroxide (KOH) melt. Specifically, the main surface is etched using a KOH melt. The temperature of the KOH melt is, for example, about 500 ° C. or more and 550 ° C. or less. The etching time is, for example, about 5 to 10 minutes. After etching, the main surface is observed with a normalsky differential interference microscope. The basal plane dislocation is etched by the KOH melt to form pits. By dividing the total number of pits by the total measurement area, the surface density of the basal plane dislocation is calculated. The threading edge dislocations also form pits in the same manner as the basal plane dislocations. Pits derived from threading edge dislocations and pits derived from basal plane dislocations are distinguished as follows. Rounded hexagonal pits are derived from threading edge dislocations, and elliptical pits are derived from basal plane dislocations.
　図２に示されるように、基底面転位は、炭化珪素基板の内部を貫通し、第１主表面１２および第１主面１１の各々に達している。そのため、第１主表面１２における基底面転位の面密度は、第１主面１１における基底面転位の面密度と同じであると推定することができる。特に、第１主表面１２が（０００－１）面または（０００－１）面がオフ方向に８°以下傾斜した面である場合には、ＫＯＨ融液によって第１主表面１２にエッチピットが出現しづらい。この場合、炭化珪素基板１０から炭化珪素エピタキシャル膜２０を除去した後、炭化珪素基板１０の第１主面１１における基底面転位の面密度を測定してもよい。第１主表面１２が（０００－１）面または（０００－１）面がオフ方向に８°以下傾斜した面である場合、第１主面１１は（０００１）面または（０００１）面がオフ方向に８°以下傾斜した面である。そのため、第１主表面１２と比較して、第１主面１１にはエッチピットが出現しやすい。第１主面１１における基底面転位の面密度が、第１主表面１２における基底面転位の面密度と同じであると推定される。 As shown in FIG. 2, the basal plane dislocation penetrates the inside of the silicon carbide substrate and reaches each of the first main surface 12 and the first main surface 11. Therefore, it can be estimated that the surface density of the basal plane dislocations in the first main surface 12 is the same as the surface density of the basal plane dislocations in the first main surface 11. In particular, when the first main surface 12 is a (000-1) plane or a (000-1) plane inclined by 8 ° or less in the off direction, etch pits are formed on the first main surface 12 by the KOH melt. Hard to appear. In this case, after removing silicon carbide epitaxial film 20 from silicon carbide substrate 10, the surface density of basal plane dislocations on first main surface 11 of silicon carbide substrate 10 may be measured. When the first main surface 12 is a (000-1) plane or a (000-1) plane inclined by 8 ° or less in the off direction, the (0001) plane or the (0001) plane is off the first main surface 11 The surface is inclined by 8 ° or less in the direction. Therefore, etch pits are likely to appear on the first main surface 11 as compared to the first main surface 12. It is estimated that the surface density of the basal plane dislocations in the first main surface 11 is the same as the surface density of the basal plane dislocations in the first main surface 12.
　（炭化珪素エピタキシャル基板の製造装置）
　次に、本実施形態に係る炭化珪素エピタキシャル基板１００の製造装置２００の構成について説明する。 (Silicon carbide epitaxial substrate manufacturing equipment)
Next, the configuration of manufacturing apparatus 200 for silicon carbide epitaxial substrate 100 according to the present embodiment will be described.
　図３に示されるように、炭化珪素エピタキシャル基板１００の製造装置２００は、たとえばホットウォール方式の横型ＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）装置である。製造装置２００は、反応室２０１と、発熱体２０３、石英管２０４、断熱材２０５、誘導加熱コイル２０６とを主に有している。 As shown in FIG. 3, a silicon carbide epitaxial substrate 100 manufacturing apparatus 200 is, for example, a hot-wall lateral CVD (Chemical Vapor Deposition) apparatus. The manufacturing apparatus 200 mainly includes a reaction chamber 201, a heating element 203, a quartz tube 204, a heat insulating material 205, and an induction heating coil 206.
　発熱体２０３は、たとえば筒状の形状を有しており、内部に反応室２０１を形成している。発熱体２０３は、たとえば黒鉛製である。断熱材２０５は、発熱体２０３の外周を取り囲んでいる。断熱材２０５は、石英管２０４の内周面に接するように石英管２０４の内部に設けられている。誘導加熱コイル２０６は、たとえば石英管２０４の外周面に沿って巻回されている。誘導加熱コイル２０６は、外部電源（図示せず）により、交流電流が供給可能に構成されている。これにより、発熱体２０３が誘導加熱される。結果として、反応室２０１が発熱体２０３により加熱される。 The heating element 203 has a cylindrical shape, for example, and forms a reaction chamber 201 inside. The heating element 203 is made of, for example, graphite. The heat insulating material 205 surrounds the outer periphery of the heating element 203. The heat insulating material 205 is provided inside the quartz tube 204 so as to contact the inner peripheral surface of the quartz tube 204. The induction heating coil 206 is wound, for example, along the outer peripheral surface of the quartz tube 204. The induction heating coil 206 is configured to be able to supply an alternating current by an external power source (not shown). Thereby, the heating element 203 is induction-heated. As a result, the reaction chamber 201 is heated by the heating element 203.
　反応室２０１は、発熱体２０３に取り囲まれて形成された空間である。反応室２０１内には、炭化珪素基板１０が配置される。反応室２０１は、炭化珪素基板１０を加熱可能に構成されている。反応室２０１には、炭化珪素基板１０を保持するサセプタ２１０が設けられている。サセプタ２１０は、回転軸２１２の周りを自転可能に構成されている。 The reaction chamber 201 is a space formed by being surrounded by the heating element 203. Silicon carbide substrate 10 is arranged in reaction chamber 201. Reaction chamber 201 is configured to heat silicon carbide substrate 10. Reaction chamber 201 is provided with a susceptor 210 that holds silicon carbide substrate 10. The susceptor 210 is configured to be able to rotate around the rotation shaft 212.
　製造装置２００は、ガス導入口２０７およびガス排気口２０８を有している。ガス排気口２０８は、排気ポンプ（図示せず）に接続されている。図６中の矢印は、ガスの流れを示している。ガスは、ガス導入口２０７から反応室２０１に導入され、ガス排気口２０８から排気される。反応室２０１内の圧力は、ガスの供給量と、ガスの排気量とのバランスによって調整される。 The manufacturing apparatus 200 has a gas introduction port 207 and a gas exhaust port 208. The gas exhaust port 208 is connected to an exhaust pump (not shown). The arrows in FIG. 6 indicate the gas flow. The gas is introduced into the reaction chamber 201 from the gas introduction port 207 and exhausted from the gas exhaust port 208. The pressure in the reaction chamber 201 is adjusted by the balance between the gas supply amount and the gas exhaust amount.
　製造装置２００は、たとえば、シランと、アンモニアと、水素と、プロパンとを含む混合ガスを、反応室２０１に供給可能に構成されたガス供給部（図示せず）を有している。具体的には、ガス供給部は、水素で希釈されたプロパンガスを供給可能なガスボンベと、水素ガスを供給可能なガスボンベと、シランガスを供給可能なガスボンベと、アンモニアガスを供給可能なガスボンベとを有していてもよい。水素で希釈されたプロパンガスにおいて、プロパンガスは３０体積％であり、水素ガスは７０体積％である。水素で希釈されたプロパンガスを使用することにより、反応室２０１の上流側におけるプロパンガスの分解効率が向上する。 The manufacturing apparatus 200 has a gas supply unit (not shown) configured to be able to supply, for example, a mixed gas containing silane, ammonia, hydrogen, and propane to the reaction chamber 201. Specifically, the gas supply unit includes a gas cylinder capable of supplying propane gas diluted with hydrogen, a gas cylinder capable of supplying hydrogen gas, a gas cylinder capable of supplying silane gas, and a gas cylinder capable of supplying ammonia gas. You may have. In propane gas diluted with hydrogen, propane gas is 30% by volume and hydrogen gas is 70% by volume. By using propane gas diluted with hydrogen, the decomposition efficiency of propane gas on the upstream side of the reaction chamber 201 is improved.
　反応室２０１の軸方向において、誘導加熱コイル２０６の巻き密度を変化させてもよい。巻き密度［回／ｍ］とは、装置の軸方向の単位長さあたりのコイルの周回数である。たとえば、上流側でアンモニアを効果的に熱分解させるために、上流側の誘導加熱コイル２０６の巻き密度は、下流側の誘導加熱コイル２０６の巻き密度よりも高くてもよい。 In the axial direction of the reaction chamber 201, the winding density of the induction heating coil 206 may be changed. The winding density [times / m] is the number of coil turns per unit length in the axial direction of the apparatus. For example, in order to effectively thermally decompose ammonia on the upstream side, the winding density of the induction heating coil 206 on the upstream side may be higher than the winding density of the induction heating coil 206 on the downstream side.
　（炭化珪素エピタキシャル基板の製造方法）
　次に、本実施形態に係る炭化珪素エピタキシャル基板の製造方法について説明する。 (Method for producing silicon carbide epitaxial substrate)
Next, a method for manufacturing the silicon carbide epitaxial substrate according to this embodiment will be described.
　まず、炭化珪素単結晶基板準備工程（Ｓ１１：図４）が実施される。たとえば昇華法により、ポリタイプ４Ｈの炭化珪素単結晶が製造される。次に、たとえばワイヤーソーによって、炭化珪素単結晶をスライスすることにより、炭化珪素基板１０が準備される。炭化珪素基板１０は、たとえば窒素などのｎ型不純物を含んでいる。炭化珪素基板１０の導電型は、たとえばｎ型である。 First, a silicon carbide single crystal substrate preparation step (S11: FIG. 4) is performed. For example, a polytype 4H silicon carbide single crystal is manufactured by a sublimation method. Next, silicon carbide substrate 10 is prepared by slicing the silicon carbide single crystal with, for example, a wire saw. Silicon carbide substrate 10 includes an n-type impurity such as nitrogen, for example. Silicon carbide substrate 10 has an n conductivity type, for example.
　図５に示されるように、炭化珪素基板１０は、第１主面１１と、第１主面１１の反対側にある第３主面１３とを有する。第１主面１１は、たとえば｛０００１｝面がオフ角θだけオフ方向に傾斜した面である。オフ方向は、たとえば＜１１－２０＞方向である。炭化珪素基板１０の第１主面１１の最大径は、たとえば１００ｍｍ以上である。炭化珪素基板１０には、たとえば複数の基底面転位１が存在する。基底面転位１は、｛０００１｝面と平行な方向に延在している。基底面転位１は、たとえば第１基底面転位２５と、第２基底面転位２６と、第３基底面転位２７とを有する。 As shown in FIG. 5, silicon carbide substrate 10 has a first main surface 11 and a third main surface 13 on the opposite side of first main surface 11. The first major surface 11 is, for example, a surface in which the {0001} plane is inclined in the off direction by the off angle θ. The off direction is, for example, the <11-20> direction. The maximum diameter of first main surface 11 of silicon carbide substrate 10 is, for example, 100 mm or more. For example, a plurality of basal plane dislocations 1 exist in silicon carbide substrate 10. The basal plane dislocation 1 extends in a direction parallel to the {0001} plane. The basal plane dislocation 1 has, for example, a first basal plane dislocation 25, a second basal plane dislocation 26, and a third basal plane dislocation 27.
　次に、昇温工程が実施される。炭化珪素基板１０が反応室２０１内においてサセプタ２１０上に配置される（図３参照）。たとえば反応室２０１の圧力が大気圧から１×１０-6Ｐａ程度に低減された後、炭化珪素基板１０の昇温が開始される。図７に示されるように、時点Ｔ０から時点Ｔ１にかけて、炭化珪素基板１０の温度が室温から第１温度Ａ１まで上昇する。第１温度Ａ１は、たとえば１６０５℃である。 Next, a temperature raising step is performed. Silicon carbide substrate 10 is arranged on susceptor 210 in reaction chamber 201 (see FIG. 3). For example, after the pressure in reaction chamber 201 is reduced from atmospheric pressure to about 1 × 10 −6 Pa, the temperature rise of silicon carbide substrate 10 is started. As shown in FIG. 7, the temperature of silicon carbide substrate 10 increases from room temperature to first temperature A1 from time T0 to time T1. The first temperature A1 is 1605 ° C., for example.
　次に、バッファ層形成工程（Ｓ１２：図４）が実施される。炭化珪素基板１０の温度がたとえば第１温度Ａ１になった後、反応室２０１に、原料ガス、ドーパントガスおよびキャリアガスが供給される。具体的には、反応室２０１に、シランとプロパンとアンモニアと水素とを含む混合ガスが供給される。図７に示されるように、時点Ｔ１から時点Ｔ２までの間、炭化珪素基板１０は、第１温度Ａ１で維持される。時点Ｔ１から時点Ｔ２までの時間は、たとえば３分以上６０分以下である。反応室２０１において、それぞれのガスが熱分解され、炭化珪素基板１０上にバッファ層２１が形成される（図６参照）。バッファ層２１を形成する工程において、サセプタ２１０は回転軸２１２の周りを自転する。炭化珪素基板１０は回転軸２１２の周りを公転する（図３参照）。 Next, a buffer layer forming step (S12: FIG. 4) is performed. After the temperature of silicon carbide substrate 10 reaches, for example, first temperature A1, source gas, dopant gas, and carrier gas are supplied to reaction chamber 201. Specifically, a mixed gas containing silane, propane, ammonia, and hydrogen is supplied to the reaction chamber 201. As shown in FIG. 7, silicon carbide substrate 10 is maintained at first temperature A1 from time T1 to time T2. The time from time T1 to time T2 is, for example, not less than 3 minutes and not more than 60 minutes. In reaction chamber 201, each gas is thermally decomposed, and buffer layer 21 is formed on silicon carbide substrate 10 (see FIG. 6). In the step of forming the buffer layer 21, the susceptor 210 rotates around the rotation shaft 212. Silicon carbide substrate 10 revolves around rotating shaft 212 (see FIG. 3).
　バッファ層を形成する工程においては、Ｃ／Ｓｉ比がたとえば０．９５となるように、シランおよびプロパンの流量が調整される。具体的には、シランガスの流量がたとえば５７．６ｓｃｃｍとなるように調整される。水素で希釈されたプロパンガス（３０体積％）の流量がたとえば１８．２ｓｃｃｍとなるように調整される。水素ガスの流量が１３０ｓｌｍとなるように調整される。バッファ層２１にドーピングされるｎ型不純物（Ｎ）の濃度は、たとえば０．２×１０18ｃｍ-3以上９×１０18ｃｍ-3以下程度である。バッファ層２１の厚みは、たとえば１μｍである。反応室２０１の圧力は、たとえば５ｋＰａである。 In the step of forming the buffer layer, the flow rates of silane and propane are adjusted so that the C / Si ratio is, for example, 0.95. Specifically, the flow rate of the silane gas is adjusted to 57.6 sccm, for example. The flow rate of the propane gas (30% by volume) diluted with hydrogen is adjusted to be, for example, 18.2 sccm. The flow rate of hydrogen gas is adjusted to be 130 slm. The concentration of the n-type impurity (N) doped in the buffer layer 21 is, for example, about 0.2 × 10 18 cm −3 to 9 × 10 18 cm −3 . The thickness of the buffer layer 21 is, for example, 1 μm. The pressure in the reaction chamber 201 is, for example, 5 kPa.
　図６に示されるように、炭化珪素基板１０に存在していた複数の基底面転位１の大部分が貫通刃状転位２に転換される。具体的には、第１基底面転位２５は、第１貫通刃状転位３５に転換される。第２基底面転位２６は、第２貫通刃状転位３６に転換される。第３基底面転位２７は、貫通刃状転位に転換されず、第４基底面転位３７としてバッファ層２１内を伝搬する。 As shown in FIG. 6, most of the plurality of basal plane dislocations 1 existing in the silicon carbide substrate 10 are converted into threading edge dislocations 2. Specifically, the first basal plane dislocation 25 is converted into the first threading edge dislocation 35. The second basal plane dislocation 26 is converted into the second threading edge dislocation 36. The third basal plane dislocations 27 are not converted into threading edge dislocations, but propagate in the buffer layer 21 as fourth basal plane dislocations 37.
　次に、ドリフト層形成工程（Ｓ１３：図４）が実施される。図７に示されるように、時点Ｔ２において、炭化珪素基板１０の昇温が再度開始される。具体的には、時点Ｔ２から時点Ｔ３にかけて、炭化珪素基板１０の温度が第１温度Ａ１から第２温度Ａ２まで上昇する。第２温度Ａ２は、たとえば１６４０℃である。炭化珪素基板１０の温度が第２温度Ａ２に維持された状態で、反応室２０１に、シランとプロパンとアンモニアと水素とを含む混合ガスが供給される。時点Ｔ３から時点Ｔ４までの間、炭化珪素基板１０は、第２温度Ａ２で維持される。時点Ｔ３から時点Ｔ４までの時間は、たとえば３０分以上６００分以下である。反応室２０１において、それぞれのガスが熱分解され、バッファ層２１上にドリフト層２２が形成される（図２および図５参照）。ドリフト層２２を形成する工程において、サセプタ２１０は回転軸２１２の周りを自転する。炭化珪素基板１０は回転軸２１２の周りを公転する（図３参照）。 Next, the drift layer forming step (S13: FIG. 4) is performed. As shown in FIG. 7, at time T2, the temperature rise of silicon carbide substrate 10 is started again. Specifically, the temperature of silicon carbide substrate 10 rises from first temperature A1 to second temperature A2 from time T2 to time T3. The second temperature A2 is 1640 ° C., for example. A mixed gas containing silane, propane, ammonia, and hydrogen is supplied to the reaction chamber 201 in a state where the temperature of the silicon carbide substrate 10 is maintained at the second temperature A2. Between time T3 and time T4, silicon carbide substrate 10 is maintained at second temperature A2. The time from time T3 to time T4 is, for example, not less than 30 minutes and not more than 600 minutes. In the reaction chamber 201, each gas is thermally decomposed, and the drift layer 22 is formed on the buffer layer 21 (see FIGS. 2 and 5). In the step of forming the drift layer 22, the susceptor 210 rotates around the rotation axis 212. Silicon carbide substrate 10 revolves around rotating shaft 212 (see FIG. 3).
　ドリフト層を形成する工程においては、Ｃ／Ｓｉ比が１．３５程度となるように、シランおよびプロパンとの流量が調整される。具体的には、シランガスの流量がたとえば１４０ｓｃｃｍとなるように調整される。水素で希釈されたプロパンガス（３０体積％）の流量がたとえば６３ｓｃｃｍとなるように調整される。水素ガスの流量が１３４ｓｌｍとなるように調整される。ドリフト層２２にドーピングされるキャリアの濃度は、たとえば８×１０15ｃｍ-3程度である。ドリフト層２２の厚みは、たとえば１０μｍ以上３０μｍ以下程度である。反応室２０１の圧力は、たとえば６ｋＰａである。 In the step of forming the drift layer, the flow rates of silane and propane are adjusted so that the C / Si ratio is about 1.35. Specifically, the flow rate of the silane gas is adjusted to 140 sccm, for example. The flow rate of propane gas (30% by volume) diluted with hydrogen is adjusted to 63 sccm, for example. The flow rate of hydrogen gas is adjusted to 134 slm. The concentration of carriers doped in the drift layer 22 is, for example, about 8 × 10 15 cm −3 . The thickness of the drift layer 22 is, for example, about 10 μm to 30 μm. The pressure in the reaction chamber 201 is, for example, 6 kPa.
　以上のように、炭化珪素エピタキシャル膜のバッファ層２１の成長温度を、ドリフト層２２の成長温度よりもある程度低く維持することにより、熱膨張率の異なるバッファ層とドリフト層の間の熱膨張差の絶対値が小さくなり、歪を小さく抑えることができるため、基底面転位が貫通刃状転位に転換する割合（転換率）を向上することができる。 As described above, by maintaining the growth temperature of the buffer layer 21 of the silicon carbide epitaxial film to be somewhat lower than the growth temperature of the drift layer 22, the difference in thermal expansion between the buffer layer and the drift layer having different thermal expansion coefficients can be reduced. Since the absolute value becomes small and the strain can be kept small, the ratio of the basal plane dislocations to threading edge dislocations (conversion rate) can be improved.
　次に、冷却工程が行われる。図７に示されるように、時点Ｔ４から時点Ｔ５にかけて、炭化珪素基板の温度が第２温度Ａ２から室温まで低減される。以上のように、炭化珪素エピタキシャル基板１００が製造される。 Next, a cooling process is performed. As shown in FIG. 7, from time T4 to time T5, the temperature of the silicon carbide substrate is reduced from second temperature A2 to room temperature. As described above, silicon carbide epitaxial substrate 100 is manufactured.
　（炭化珪素半導体装置の製造方法）
　次に、本実施形態に係る炭化珪素半導体装置３００の製造方法について説明する。 (Method for manufacturing silicon carbide semiconductor device)
Next, a method for manufacturing the silicon carbide semiconductor device 300 according to this embodiment will be described.
　本実施形態に係る炭化珪素半導体装置の製造方法は、エピタキシャル基板準備工程（Ｓ１０：図８）と、基板加工工程（Ｓ２０：図８）とを主に有する。 The method for manufacturing a silicon carbide semiconductor device according to the present embodiment mainly includes an epitaxial substrate preparation step (S10: FIG. 8) and a substrate processing step (S20: FIG. 8).
　まず、エピタキシャル基板準備工程（Ｓ１０：図８）が実施される。具体的には、前述した炭化珪素エピタキシャル基板の製造方法によって、炭化珪素エピタキシャル基板１００が準備される（図４参照）。 First, an epitaxial substrate preparation step (S10: FIG. 8) is performed. Specifically, silicon carbide epitaxial substrate 100 is prepared by the above-described method for manufacturing a silicon carbide epitaxial substrate (see FIG. 4).
　次に、基板加工工程（Ｓ２０：図８）が実施される。具体的には、炭化珪素エピタキシャル基板を加工することにより、炭化珪素半導体装置が製造される。「加工」には、たとえば、イオン注入、熱処理、エッチング、酸化膜形成、電極形成、ダイシング等の各種加工が含まれる。すなわち基板加工ステップは、イオン注入、熱処理、エッチング、酸化膜形成、電極形成およびダイシングのうち、少なくともいずれかの加工を含むものであってもよい。 Next, a substrate processing step (S20: FIG. 8) is performed. Specifically, a silicon carbide semiconductor device is manufactured by processing a silicon carbide epitaxial substrate. “Processing” includes, for example, various processes such as ion implantation, heat treatment, etching, oxide film formation, electrode formation, and dicing. That is, the substrate processing step may include at least one of ion implantation, heat treatment, etching, oxide film formation, electrode formation, and dicing.
　以下では、炭化珪素半導体装置の一例としてのＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）の製造方法を説明する。基板加工工程（Ｓ２０：図８）は、たとえばイオン注入工程（Ｓ２１：図８）、酸化膜形成工程（Ｓ２２：図８）、電極形成工程（Ｓ２３：図８）およびダイシング工程（Ｓ２４：図８）を含む。 Hereinafter, a method for manufacturing a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as an example of a silicon carbide semiconductor device will be described. The substrate processing step (S20: FIG. 8) includes, for example, an ion implantation step (S21: FIG. 8), an oxide film formation step (S22: FIG. 8), an electrode formation step (S23: FIG. 8), and a dicing step (S24: FIG. 8). )including.
　まず、イオン注入工程（Ｓ２１：図８）が実施される。開口部を有するマスク（図示せず）が形成された第２主表面１４に対して、たとえばアルミニウム（Ａｌ）等のｐ型不純物が注入される。これにより、ｐ型の導電型を有するボディ領域１３２が形成される。次に、ボディ領域１３２内の所定位置に、たとえばリン（Ｐ）等のｎ型不純物が注入される。これにより、ｎ型の導電型を有するソース領域１３３が形成される。次に、アルミニウム等のｐ型不純物がソース領域１３３内の所定位置に注入される。これにより、ｐ型の導電型を有するコンタクト領域１３４が形成される（図９参照）。 First, an ion implantation step (S21: FIG. 8) is performed. A p-type impurity such as aluminum (Al) is implanted into second main surface 14 on which a mask (not shown) having an opening is formed. Thereby, body region 132 having p-type conductivity is formed. Next, an n-type impurity such as phosphorus (P) is implanted into a predetermined position in body region 132. Thereby, a source region 133 having n-type conductivity is formed. Next, a p-type impurity such as aluminum is implanted into a predetermined position in the source region 133. As a result, a contact region 134 having a p-type conductivity is formed (see FIG. 9).
　炭化珪素エピタキシャル膜２０において、ボディ領域１３２、ソース領域１３３およびコンタクト領域１３４以外の部分は、ドリフト領域１３１となる。ソース領域１３３は、ボディ領域１３２によってドリフト領域１３１から隔てられている。イオン注入は、炭化珪素エピタキシャル基板１００を３００℃以上６００℃以下程度に加熱して行われてもよい。イオン注入の後、炭化珪素エピタキシャル基板１００に対して活性化アニールが行われる。活性化アニールにより、炭化珪素エピタキシャル膜２０に注入された不純物が活性化し、各領域においてキャリアが生成される。活性化アニールの雰囲気は、たとえばアルゴン（Ａｒ）雰囲気である。活性化アニールの温度は、たとえば１８００℃程度である。活性化アニールの時間は、たとえば３０分程度である。 In silicon carbide epitaxial film 20, portions other than body region 132, source region 133, and contact region 134 become drift region 131. Source region 133 is separated from drift region 131 by body region 132. Ion implantation may be performed by heating silicon carbide epitaxial substrate 100 to about 300 ° C. or more and 600 ° C. or less. After the ion implantation, activation annealing is performed on silicon carbide epitaxial substrate 100. By the activation annealing, the impurities implanted into the silicon carbide epitaxial film 20 are activated, and carriers are generated in each region. The atmosphere of activation annealing is, for example, an argon (Ar) atmosphere. The temperature of activation annealing is, for example, about 1800 ° C. The activation annealing time is, for example, about 30 minutes.
　次に、酸化膜形成工程（Ｓ２２：図８）が実施される。たとえば炭化珪素エピタキシャル基板１００が酸素を含む雰囲気中において加熱されることにより、第２主表面１４上に酸化膜１３６が形成される（図１０参照）。酸化膜１３６は、たとえば二酸化珪素等から構成される。酸化膜１３６は、ゲート絶縁膜として機能する。熱酸化処理の温度は、たとえば１３００℃程度である。熱酸化処理の時間は、たとえば３０分程度である。 Next, an oxide film forming step (S22: FIG. 8) is performed. For example, silicon carbide epitaxial substrate 100 is heated in an atmosphere containing oxygen, whereby oxide film 136 is formed on second main surface 14 (see FIG. 10). Oxide film 136 is made of, for example, silicon dioxide. The oxide film 136 functions as a gate insulating film. The temperature of the thermal oxidation treatment is, for example, about 1300 ° C. The time for the thermal oxidation treatment is, for example, about 30 minutes.
　酸化膜１３６が形成された後、さらに窒素雰囲気中で熱処理が行なわれてもよい。たとえば、一酸化窒素の雰囲気中、１１００℃程度で１時間程度、熱処理が実施される。さらにその後、アルゴン雰囲気中で熱処理が行なわれる。たとえば、アルゴン雰囲気中、１１００℃以上１５００℃以下程度で、１時間程度、熱処理が行われる。 After the oxide film 136 is formed, heat treatment may be performed in a nitrogen atmosphere. For example, the heat treatment is performed in an atmosphere of nitric oxide at about 1100 ° C. for about 1 hour. Thereafter, heat treatment is performed in an argon atmosphere. For example, the heat treatment is performed in an argon atmosphere at about 1100 ° C. to 1500 ° C. for about 1 hour.
　次に、電極形成工程（Ｓ２３：図８）が実施される。第１電極１４１は、酸化膜１３６上に形成される。第１電極１４１は、ゲート電極として機能する。第１電極１４１は、たとえばＣＶＤ法により形成される。第１電極１４１は、たとえば導電性を有するポリシリコン等から構成される。第１電極１４１は、ソース領域１３３およびボディ領域１３２に対面する位置に形成される。 Next, an electrode formation step (S23: FIG. 8) is performed. The first electrode 141 is formed on the oxide film 136. The first electrode 141 functions as a gate electrode. The first electrode 141 is formed by, for example, a CVD method. The first electrode 141 is made of, for example, conductive polysilicon. The first electrode 141 is formed at a position facing the source region 133 and the body region 132.
　次に、第１電極１４１を覆う層間絶縁膜１３７が形成される。層間絶縁膜１３７は、たとえばＣＶＤ法により形成される。層間絶縁膜１３７は、たとえば二酸化珪素等から構成される。層間絶縁膜１３７は、第１電極１４１と酸化膜１３６とに接するように形成される。次に、所定位置の酸化膜１３６および層間絶縁膜１３７がエッチングによって除去される。これにより、ソース領域１３３およびコンタクト領域１３４が、酸化膜１３６から露出する。 Next, an interlayer insulating film 137 covering the first electrode 141 is formed. Interlayer insulating film 137 is formed by, for example, a CVD method. Interlayer insulating film 137 is made of, for example, silicon dioxide. The interlayer insulating film 137 is formed so as to be in contact with the first electrode 141 and the oxide film 136. Next, the oxide film 136 and the interlayer insulating film 137 at predetermined positions are removed by etching. As a result, the source region 133 and the contact region 134 are exposed from the oxide film 136.
　次に、たとえばスパッタリング法により当該露出部に第２電極１４２が形成される。第２電極１４２はソース電極として機能する。第２電極１４２は、たとえばチタン、アルミニウムおよびシリコン等から構成される。第２電極１４２が形成された後、第２電極１４２と炭化珪素エピタキシャル基板１００が、たとえば９００℃以上１１００℃以下程度の温度で加熱される。これにより、第２電極１４２と炭化珪素エピタキシャル基板１００とがオーミック接触するようになる。次に、第２電極１４２に接するように、配線層１３８が形成される。配線層１３８は、たとえばアルミニウムを含む材料から構成される。 Next, the second electrode 142 is formed on the exposed portion by, for example, a sputtering method. The second electrode 142 functions as a source electrode. Second electrode 142 is made of, for example, titanium, aluminum, silicon, or the like. After second electrode 142 is formed, second electrode 142 and silicon carbide epitaxial substrate 100 are heated at a temperature of about 900 ° C. to 1100 ° C., for example. Thereby, second electrode 142 and silicon carbide epitaxial substrate 100 come into ohmic contact. Next, the wiring layer 138 is formed so as to be in contact with the second electrode 142. The wiring layer 138 is made of a material containing aluminum, for example.
　次に、第３主面１３に第３電極１４３が形成される。第３電極１４３は、ドレイン電極として機能する。第３電極１４３は、たとえばニッケルおよびシリコンを含む合金（たとえばＮｉＳｉ等）から構成される。 Next, the third electrode 143 is formed on the third main surface 13. The third electrode 143 functions as a drain electrode. Third electrode 143 is made of, for example, an alloy containing nickel and silicon (eg, NiSi).
　次に、ダイシング工程（Ｓ２４：図８）が実施される。たとえば炭化珪素エピタキシャル基板１００がダイシングラインに沿ってダイシングされることにより、炭化珪素エピタキシャル基板１００が複数の半導体チップに分割される。以上より、炭化珪素半導体装置３００が製造される（図１１参照）。 Next, a dicing step (S24: FIG. 8) is performed. For example, silicon carbide epitaxial substrate 100 is diced along a dicing line, whereby silicon carbide epitaxial substrate 100 is divided into a plurality of semiconductor chips. Thus, silicon carbide semiconductor device 300 is manufactured (see FIG. 11).
　上記において、ＭＯＳＦＥＴを例示して、本開示に係る炭化珪素半導体装置の製造方法を説明したが、本開示に係る製造方法はこれに限定されない。本開示に係る製造方法は、たとえばＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）、ＳＢＤ（Ｓｃｈｏｔｔｋｙ　Ｂａｒｒｉｅｒ　Ｄｉｏｄｅ）、サイリスタ、ＧＴＯ（Ｇａｔｅ　Ｔｕｒｎ　Ｏｆｆ　ｔｈｙｒｉｓｔｏｒ）、ＰｉＮダイオード等の炭化珪素半導体装置に適用可能である。 In the above, the method for manufacturing the silicon carbide semiconductor device according to the present disclosure has been described by exemplifying the MOSFET, but the manufacturing method according to the present disclosure is not limited to this. The manufacturing method according to the present disclosure can be applied to silicon carbide semiconductor devices such as IGBT (Insulated Gate Bipolar Transistor), SBD (Schottky Barrier Diode), thyristor, GTO (Gate Turn Off thyristor), and PiN diode.
　次に、実施例について説明する。まず、サンプル１－５に係る炭化珪素基板が準備された。次に、サンプル１－５に係る炭化珪素基板上に炭化珪素エピタキシャル膜を成長させた。サンプル１－４に係る炭化珪素基板に対しては、本実施形態の図７において実線で示した温度プロファイルを用いて、炭化珪素エピタキシャル膜を形成した。具体的には、バッファ層を形成する工程の温度（Ａ１：図７参照）を１６０５℃とし、ドリフト層を形成する工程の温度（Ａ２：図７参照）を１６４０℃とした。サンプル５に係る炭化珪素基板に対しては、図７において一点鎖線で示した温度プロファイルを用いて、炭化珪素エピタキシャル膜を形成した。具体的には、バッファ層を形成する工程の温度（Ａ１：図７参照）およびドリフト層を形成する工程の温度（Ａ２：図７参照）を共に１６４０℃とした。以上のように、サンプル１－５に係る炭化珪素エピタキシャル基板が製造された。次に、サンプル１－５に係る炭化珪素エピタキシャル基板の第２主面および主表面における基底面転位の面密度が測定された。基底面転位の面密度は、前述の測定方法を用いて測定された。 Next, examples will be described. First, a silicon carbide substrate according to Sample 1-5 was prepared. Next, a silicon carbide epitaxial film was grown on the silicon carbide substrate according to Sample 1-5. For the silicon carbide substrate according to Sample 1-4, a silicon carbide epitaxial film was formed using the temperature profile shown by the solid line in FIG. 7 of the present embodiment. Specifically, the temperature of the step of forming the buffer layer (A1: see FIG. 7) was 1605 ° C., and the temperature of the step of forming the drift layer (A2: see FIG. 7) was 1640 ° C. For the silicon carbide substrate according to sample 5, a silicon carbide epitaxial film was formed using the temperature profile shown by the one-dot chain line in FIG. Specifically, the temperature of the step of forming the buffer layer (A1: see FIG. 7) and the temperature of the step of forming the drift layer (A2: see FIG. 7) were both 1640 ° C. As described above, the silicon carbide epitaxial substrate according to Sample 1-5 was manufactured. Next, the surface density of basal plane dislocations on the second main surface and main surface of the silicon carbide epitaxial substrate according to Sample 1-5 was measured. The surface density of the basal plane dislocation was measured using the above-described measurement method.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　表１は、炭化珪素基板の主表面の基底面転位の面密度（第１面密度）と、炭化珪素エピタキシャル膜の主表面の基底面転位の面密度（第２面密度）と、第２面密度を第１面密度で除した値と、基底面転位から貫通刃状転位への転換率とを示している。表１に示されるように、サンプル１－５に係る炭化珪素基板エピタキシャル基板において、第２面密度を第１面密度で除した値は、それぞれ０．０００１５２、０．０００１５７、０．０００００６、０．００００１１および０．０１２０３２であった。またサンプル１－５に係る炭化珪素基板エピタキシャル基板において、第１面密度から第２面密度を引いた値を第１面密度で除した値として求められる転換率は、それぞれ、９９．９８４８％、９９．９８４３％、９９．９９９４％、９９．９９８９％および９８．７９６８％であった。 Table 1 shows the surface density (first surface density) of basal plane dislocations on the main surface of the silicon carbide substrate, the surface density (second surface density) of basal plane dislocations on the main surface of the silicon carbide epitaxial film, and the second surface. The value obtained by dividing the density by the first surface density and the conversion rate from the basal plane dislocation to the threading edge dislocation are shown. As shown in Table 1, in the silicon carbide substrate epitaxial substrate according to Sample 1-5, the values obtained by dividing the second surface density by the first surface density are 0.000152, 0.000157, 0.000006, and 0, respectively. 0.00001 and 0.012032. Further, in the silicon carbide substrate epitaxial substrate according to Sample 1-5, the conversion ratios obtained as values obtained by subtracting the second surface density from the first surface density by the first surface density were 99.9848%, 99.9843%, 99.99994%, 99.9989% and 98.7968%.
　以上の結果より、バッファ層を形成する工程の温度を１６０５℃とし、ドリフト層を形成する工程の温度を１６４０℃としたエピタキシャル成長条件（条件Ａ）を用いて炭化珪素エピタキシャル基板を製造する場合は、バッファ層を形成する工程およびドリフト層を形成する工程の温度を共に１６４０℃としたエピタキシャル成長条件（条件Ｂ）を用いて炭化珪素エピタキシャル基板を製造する場合よりも、基底面転位を貫通刃状転位に転換する割合を高め、結果として、炭化珪素エピタキシャル膜における基底面転位の面密度を低減可能であることが確認された。 From the above results, when manufacturing a silicon carbide epitaxial substrate using epitaxial growth conditions (condition A) in which the temperature of the step of forming the buffer layer is 1605 ° C. and the temperature of the step of forming the drift layer is 1640 ° C., The basal plane dislocations are changed to threading edge dislocations, compared to the case of producing a silicon carbide epitaxial substrate using epitaxial growth conditions (condition B) in which the temperature of the buffer layer forming step and the drift layer forming step are both 1640 ° C. As a result, it was confirmed that the surface density of basal plane dislocations in the silicon carbide epitaxial film can be reduced.
　今回開示された実施形態はすべての点で例示であって、制限的なものではないと考えられるべきである。本発明の範囲は上記した実施形態ではなく請求の範囲によって示され、請求の範囲と均等の意味、および範囲内でのすべての変更が含まれることが意図される。 It should be considered that the embodiment disclosed this time is illustrative in all respects and not restrictive. The scope of the present invention is shown not by the above-described embodiment but by the scope of claims, and is intended to include meanings equivalent to the scope of claims and all modifications within the scope.
１　基底面転位、２　貫通刃状転位、１０　炭化珪素基板、１１　第１主面、１２　第１主表面、１３　第３主面、１４　第２主表面、１６　第１フラット、２０　炭化珪素エピタキシャル膜、２１　バッファ層（第１層）、２２　ドリフト層（第２層）、２５　第１基底面転位、２６　第２基底面転位、２７　第３基底面転位、３５　第１貫通刃状転位、３６　第２貫通刃状転位、３７　第４基底面転位、１００　炭化珪素エピタキシャル基板、１０１　第１方向、１０２　第２方向、１０３　第３方向、１０４　第４方向、１０５　第５方向、１１１　最大径、１３１　ドリフト領域、１３２　ボディ領域、１３３　ソース領域、１３４　コンタクト領域、１３６　酸化膜、１３７　層間絶縁膜、１３８　配線層、１４１　第１電極、１４２　第２電極、１４３　第３電極、２００　製造装置、２０１　反応室、２０３　発熱体、２０４　石英管、２０５　断熱材、２０６　誘導加熱コイル、２０７　ガス導入口、２０８　ガス排気口、２１０　サセプタ、２１２　回転軸、３００　炭化珪素半導体装置、Ａ１　第１温度、Ａ２　第２温度。 1 basal plane dislocation, 2 threading edge dislocation, 10 silicon carbide substrate, 11 first main surface, 12 first main surface, 13 third main surface, 14 second main surface, 16 first flat, 20 silicon carbide epitaxial film , 21 buffer layer (first layer), 22 drift layer (second layer), 25 first basal plane dislocation, 26 second basal plane dislocation, 27 third basal plane dislocation, 35 first threading edge dislocation, 36 th 2 threading edge dislocation, 37 4th basal plane dislocation, 100 silicon carbide epitaxial substrate, 101 first direction, 102 second direction, 103 third direction, 104 fourth direction, 105 fifth direction, 111 maximum diameter, 131 drift Region, 132 body region, 133 source region, 134 contact region, 136 oxide film, 137 interlayer insulating film, 138 wiring layer, 141 first electrode, 1 2 2nd electrode, 143 3rd electrode, 200 manufacturing equipment, 201 reaction chamber, 203 heating element, 204 quartz tube, 205 insulation, 206 induction heating coil, 207 gas inlet, 208 gas exhaust, 210 susceptor, 212 rotations Axis, 300 silicon carbide semiconductor device, A1 first temperature, A2 second temperature.

Claims (5)

  1. 　炭化珪素基板と、
    　前記炭化珪素基板上にある炭化珪素エピタキシャル膜とを備え、
    　前記炭化珪素基板および前記炭化珪素エピタキシャル膜のポリタイプは、４Ｈであり、
    　前記炭化珪素エピタキシャル膜は、前記炭化珪素基板と接する第１層と、前記第１層上にありかつ前記炭化珪素エピタキシャル膜の主表面を構成する第２層とを含み、
    　前記炭化珪素基板と、前記第１層と、前記第２層とは、ｎ型不純物を含み、
    　前記第１層が含むｎ型不純物の濃度は、前記炭化珪素基板が含むｎ型不純物の濃度より低く、かつ前記第２層が含むｎ型不純物の濃度より高く、
    　前記炭化珪素基板の主表面には、第１面密度を有する基底面転位があり、
    　前記炭化珪素エピタキシャル膜の主表面には、前記第１面密度よりも低い第２面密度を有する基底面転位があり、
    　前記第２面密度を、前記第１面密度で除した値は、２／１００００以下である、炭化珪素エピタキシャル基板。     A silicon carbide substrate;
    A silicon carbide epitaxial film on the silicon carbide substrate,
    The polytype of the silicon carbide substrate and the silicon carbide epitaxial film is 4H,
    The silicon carbide epitaxial film includes a first layer in contact with the silicon carbide substrate, and a second layer on the first layer and constituting a main surface of the silicon carbide epitaxial film,
    The silicon carbide substrate, the first layer, and the second layer include an n-type impurity,
    The concentration of the n-type impurity included in the first layer is lower than the concentration of the n-type impurity included in the silicon carbide substrate and higher than the concentration of the n-type impurity included in the second layer,
    The main surface of the silicon carbide substrate has a basal plane dislocation having a first surface density,
    The main surface of the silicon carbide epitaxial film has a basal plane dislocation having a second surface density lower than the first surface density,
    The silicon carbide epitaxial substrate, wherein a value obtained by dividing the second surface density by the first surface density is 2/10000 or less.
  2. 　前記炭化珪素エピタキシャル膜の主表面の最大径は、１５０ｍｍ以上である、請求項１に記載の炭化珪素エピタキシャル基板。 The silicon carbide epitaxial substrate according to claim 1, wherein the maximum diameter of the main surface of the silicon carbide epitaxial film is 150 mm or more.
  3. 　前記第２面密度を、前記第１面密度で除した値は、１／１００００以下である、請求項１または請求項２に記載の炭化珪素エピタキシャル基板。 3. The silicon carbide epitaxial substrate according to claim 1, wherein a value obtained by dividing the second surface density by the first surface density is 1/10000 or less.
  4. 　前記第２面密度は、１ｃｍ-2以下である、請求項１～請求項３のいずれか１項に記載の炭化珪素エピタキシャル基板。 The silicon carbide epitaxial substrate according to any one of claims 1 to 3, wherein the second areal density is 1 cm -2 or less.
  5. 　請求項１～請求項４のいずれか１項に記載の炭化珪素エピタキシャル基板を準備する工程と、
    　前記炭化珪素エピタキシャル基板を加工する工程と、を備える、炭化珪素半導体装置の製造方法。     Preparing a silicon carbide epitaxial substrate according to any one of claims 1 to 4,
    And a step of processing the silicon carbide epitaxial substrate.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190157395A1 (en) * 2017-11-17 2019-05-23 Infineon Technologies Ag Method for Forming a Semiconductor Device and a Semiconductor Device
JP2020068241A (en) * 2018-10-22 2020-04-30 株式会社東芝 Semiconductor device, substrate, and manufacturing method of semiconductor device

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008004888A (en) * 2006-06-26 2008-01-10 Hitachi Metals Ltd Manufacturing method for silicon carbide semiconductor epitaxial substrate
JP2008074661A (en) * 2006-09-21 2008-04-03 Nippon Steel Corp Epitaxial silicon carbide single crystal substrate and method for producing the same
JP2009295728A (en) * 2008-06-04 2009-12-17 Hitachi Cable Ltd Silicon carbide semiconductor substrate and method of manufacturing the same
JP2011219299A (en) * 2010-04-07 2011-11-04 Nippon Steel Corp Process for manufacturing epitaxial single-crystal silicon carbide substrate
JP2013107788A (en) * 2011-11-18 2013-06-06 Central Research Institute Of Electric Power Industry Method for manufacturing silicon carbide wafer, silicon carbide wafer, silicon carbide semiconductor element, and power converting device
JP2014027028A (en) * 2012-07-25 2014-02-06 Mitsubishi Electric Corp SiC EPITAXIAL SUBSTRATE MANUFACTURING DEVICE, METHOD FOR MANUFACTURING SiC EPITAXIAL SUBSTRATE, AND SiC EPITAXIAL SUBSTRATE
US20140054609A1 (en) * 2012-08-26 2014-02-27 Cree, Inc. Large high-quality epitaxial wafers
JP2015002207A (en) * 2013-06-13 2015-01-05 昭和電工株式会社 SiC EPITAXIAL WAFER AND MANUFACTURING METHOD THEREOF
JP2016166101A (en) * 2015-03-09 2016-09-15 新日鐵住金株式会社 Production of silicon carbide single crystal epitaxial wafer
WO2017018533A1 (en) * 2015-07-29 2017-02-02 新日鐵住金株式会社 Method for producing epitaxial silicon carbide single-crystal wafer
WO2017047350A1 (en) * 2015-09-16 2017-03-23 ローム株式会社 SiC EPITAXIAL WAFER, SiC EPITAXIAL WAFER PRODUCTION DEVICE, SiC EPITAXIAL WATER PRODUCTION METHOD, AND SEMICONDUCTOR DEVICE
WO2017094764A1 (en) * 2015-12-02 2017-06-08 三菱電機株式会社 Silicon carbide epitaxial substrate and silicon carbide semiconductor device

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008004888A (en) * 2006-06-26 2008-01-10 Hitachi Metals Ltd Manufacturing method for silicon carbide semiconductor epitaxial substrate
JP2008074661A (en) * 2006-09-21 2008-04-03 Nippon Steel Corp Epitaxial silicon carbide single crystal substrate and method for producing the same
JP2009295728A (en) * 2008-06-04 2009-12-17 Hitachi Cable Ltd Silicon carbide semiconductor substrate and method of manufacturing the same
JP2011219299A (en) * 2010-04-07 2011-11-04 Nippon Steel Corp Process for manufacturing epitaxial single-crystal silicon carbide substrate
JP2013107788A (en) * 2011-11-18 2013-06-06 Central Research Institute Of Electric Power Industry Method for manufacturing silicon carbide wafer, silicon carbide wafer, silicon carbide semiconductor element, and power converting device
JP2014027028A (en) * 2012-07-25 2014-02-06 Mitsubishi Electric Corp SiC EPITAXIAL SUBSTRATE MANUFACTURING DEVICE, METHOD FOR MANUFACTURING SiC EPITAXIAL SUBSTRATE, AND SiC EPITAXIAL SUBSTRATE
US20140054609A1 (en) * 2012-08-26 2014-02-27 Cree, Inc. Large high-quality epitaxial wafers
JP2015002207A (en) * 2013-06-13 2015-01-05 昭和電工株式会社 SiC EPITAXIAL WAFER AND MANUFACTURING METHOD THEREOF
JP2016166101A (en) * 2015-03-09 2016-09-15 新日鐵住金株式会社 Production of silicon carbide single crystal epitaxial wafer
WO2017018533A1 (en) * 2015-07-29 2017-02-02 新日鐵住金株式会社 Method for producing epitaxial silicon carbide single-crystal wafer
WO2017047350A1 (en) * 2015-09-16 2017-03-23 ローム株式会社 SiC EPITAXIAL WAFER, SiC EPITAXIAL WAFER PRODUCTION DEVICE, SiC EPITAXIAL WATER PRODUCTION METHOD, AND SEMICONDUCTOR DEVICE
WO2017094764A1 (en) * 2015-12-02 2017-06-08 三菱電機株式会社 Silicon carbide epitaxial substrate and silicon carbide semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190157395A1 (en) * 2017-11-17 2019-05-23 Infineon Technologies Ag Method for Forming a Semiconductor Device and a Semiconductor Device
US11107893B2 (en) * 2017-11-17 2021-08-31 Infineon Technologies Ag Method for forming a semiconductor device and a semiconductor device
US20210359087A1 (en) * 2017-11-17 2021-11-18 Infineon Technologies Ag Method for Forming a Semiconductor Device and a Semiconductor Device
DE102017127169B4 (en) 2017-11-17 2022-01-27 Infineon Technologies Ag PROCESS FOR MANUFACTURING A SEMICONDUCTOR DEVICE
JP2020068241A (en) * 2018-10-22 2020-04-30 株式会社東芝 Semiconductor device, substrate, and manufacturing method of semiconductor device

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