WO2018120332A1 - 扫描驱动电路及显示装置 - Google Patents

扫描驱动电路及显示装置 Download PDF

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WO2018120332A1
WO2018120332A1 PCT/CN2017/071340 CN2017071340W WO2018120332A1 WO 2018120332 A1 WO2018120332 A1 WO 2018120332A1 CN 2017071340 W CN2017071340 W CN 2017071340W WO 2018120332 A1 WO2018120332 A1 WO 2018120332A1
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Prior art keywords
transistor
pull
module
voltage
gate
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PCT/CN2017/071340
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English (en)
French (fr)
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王添鸿
郭平昇
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深圳市华星光电技术有限公司
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Priority to US15/502,569 priority Critical patent/US10262577B2/en
Publication of WO2018120332A1 publication Critical patent/WO2018120332A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/041—Temperature compensation

Definitions

  • the present invention relates to a scan driving circuit for a display device, and more particularly to a scan driving circuit having high reliability and a display device having the same.
  • the GOA technology that is, the Gate Driver on Array, is a technique for directly driving a gate driver circuit (Gate Driver IC) on an array substrate to realize a driving method of progressive scanning of the gate lines.
  • Gate Driver IC Gate Driver circuit
  • the existing GOA circuit generally includes a plurality of cascaded GOA units, and each stage of the GOA unit drives one scan line (or gate line).
  • the main structure of the GOA unit includes a pull-up part, a pull-up control part, a transfer part, a key pull-down part, and a pull-down maintenance module ( Pull-down Holding part).
  • the pull-up module is mainly responsible for outputting the clock signal (Clock) as a gate signal;
  • the pull-up driving module is responsible for controlling the opening time of the pull-up module, generally connecting the downlink signal or the gate signal transmitted by the GOA circuit of the previous stage;
  • the pull-down module is responsible for Pulling the gate signal low for the first time;
  • the pull-down sustain block is responsible for holding the gate signal and the gate signal of the pull-up circuit (commonly referred to as the Q point) in the off state (ie, the negative potential).
  • each transistor in the voltage stabilizing circuit of the pull-down maintaining module receives the maximum pressure. After a long period of high temperature and high humidity operation, the threshold voltage Vth of each transistor drifts severely, which may result in output to the scan line. The gate signal of the (or gate line) is abnormal, and the screen display is abnormal.
  • an object of the present invention is to provide a scan driving circuit including N series of GOA units, and an Nth stage GOA unit includes: a pull-up module that outputs a clock signal as a gate signal, Pull-up drive module that controls the pull-up module open time, pull-down maintenance a module and a pull-down module; the pull-up module is respectively connected to the node and the N-th gate signal output end; the pull-up drive module is connected to the N-th gate signal output end; and the pull-down maintenance module is configured to receive respectively a first DC voltage and a second DC voltage; the pull-down module is connected to the Nth stage gate signal output terminal and configured to receive the first DC voltage; the pull-down maintaining module is connected by the mirrored first pull-down maintaining circuit and the second The pull-down sustain circuit is configured to alternately operate the first pull-down sustain circuit and the second pull-down sustain circuit to maintain the Nth-level gate signal output terminal and the node at a negative potential.
  • the first pull-down maintaining circuit includes: a first voltage stabilizing circuit module, a first transistor and a fifth two transistor, a third transistor connected to the first voltage stabilizing circuit module; and a source of the fifth two transistor
  • the pole is connected to the drain and the gate of the third transistor, the source of the third transistor is for receiving the first DC voltage, the source of the first transistor is for receiving the second DC voltage, and the gate of the first transistor is for receiving the control voltage a drain of the first transistor and a drain of the fifth transistor are connected together for receiving the first low frequency clock signal;
  • the second pull-down maintaining circuit includes: a second voltage regulator circuit module, a drain and a second voltage regulator a second transistor and a sixth two transistor and a fourth transistor connected to the circuit module; a source of the sixth transistor is connected to the drain and the gate of the fourth transistor, and a source of the fourth transistor is used for receiving the first DC voltage, and second The source of the transistor is for receiving the second DC voltage, the gate of the second transistor is for receiving the control voltage, and the drain
  • the first voltage stabilizing circuit module includes: a third three transistor and a fourth three transistor; a gate of the third three transistor and a gate of the fourth three transistor are connected together and connected to the drain of the first transistor
  • the source of the third three transistor and the source of the fourth three transistor are respectively used for receiving the first direct current voltage
  • the drain of the third three transistor is connected to the output terminal of the Nth stage gate signal
  • the drain of the fourth three transistor Connect to the node.
  • the second voltage stabilizing circuit module includes a third two transistor and a fourth two transistor; a gate of the third two transistor and a gate of the fourth two transistor are connected together and connected to a drain of the first transistor,
  • the sources of the third and second transistors are respectively used to receive the first DC voltage, the drain of the third transistor is connected to the output of the Nth gate signal, and the drain of the fourth transistor is connected. To the node.
  • the pull-up driving module includes a second transistor, and a gate of the second transistor After receiving the downlink signal of the N-2th GOA unit, the drain and the source of the second transistor are respectively connected to the N-4th gate signal output terminal and the node.
  • the gate of the second transistor is used to connect the start signal terminal, and the drain and the source of the second transistor are respectively connected to the start signal terminal and the node; in the second level GOA unit The gate and the drain of the second transistor are both connected to the enable signal terminal, and the source of the second transistor is connected to the node.
  • the pull-down module includes a fourth transistor, a gate of the fourth transistor is connected to the N+2th gate signal output end, and a drain and a source of the fourth transistor are respectively connected to the Nth-level gate signal Output and second DC voltage.
  • the second DC voltage is -10V
  • the control voltage is -15V.
  • first low frequency clock signal and the second low frequency clock signal are opposite in phase.
  • Another object of the present invention is to provide a display device including the above-described scan driving circuit.
  • the scan driving circuit of the present invention is particularly highly reliable, so that an abnormality in a picture displayed by a display device using the scan driving circuit can be avoided.
  • FIG. 1 is a circuit diagram of an Nth stage GOA unit in accordance with an embodiment of the present invention.
  • FIG. 2 is a diagram showing operational timing signals of a scan driving circuit in accordance with an embodiment of the present invention.
  • FIG. 1 is a circuit diagram of an Nth stage GOA unit in accordance with an embodiment of the present invention.
  • the road includes N cascaded GOA units as shown in FIG.
  • an Nth-level GOA unit includes: a pull-up module 10 that outputs a clock signal CK as a gate signal, a pull-up driving module 20 that controls an opening time of the pull-up module 10, and a pull-down maintenance module. 30 and pull down module 40.
  • the pull-up module 10 is respectively connected to the node Q (N) and the N-th gate signal output terminal G (N); the pull-up driving module 20 is connected to the N-th gate signal output terminal G (N); and the pull-down maintaining module 30
  • the first DC voltage VSS1 and the second DC voltage VSS2 are respectively received; the pull-down module 40 is connected to the Nth-stage gate signal output terminal G(N) and is configured to receive the first DC voltage VSS1.
  • the pull-down maintaining module 30 is composed of a mirror-connected first pull-down maintaining circuit 31 and a second pull-down maintaining circuit 32.
  • the first pull-down maintaining circuit 31 and the second pull-down maintaining circuit 32 alternately operate to output the Nth-level gate signal. Terminal G(N) and node Q(N) remain at a negative potential.
  • the first pull-down maintaining circuit 31 includes: a first voltage stabilizing circuit module 311, a first transistor T1 and a fifth two-transistor T52, a third transistor T3 whose drain is connected to the first voltage stabilizing circuit module 311, and a fifth two-transistor T52.
  • the source is connected to the drain and the gate of the third transistor T3, the source of the third transistor T3 is for receiving the first DC voltage VSS1, and the source of the first transistor T1 is for receiving the second DC voltage VSS2, the first transistor T1
  • the gate is for receiving the control voltage RT, and the drain of the first transistor T1 and the drain of the fifth transistor T52 are connected together and used to receive the first low frequency clock signal LC1.
  • the second pull-down maintaining circuit 32 includes: a second voltage stabilizing circuit module 321 , a second transistor T2 and a sixth two-transistor T62 and a fourth transistor T4 connected to the second voltage-stabilizing circuit module 321 , and a sixth-second transistor T62
  • the source is connected to the drain and the gate of the fourth transistor (T4), the source of the fourth transistor T4 is for receiving the first DC voltage VSS1, and the source of the second transistor T2 is for receiving the second DC voltage VSS2, the second transistor
  • the gate of T2 is for receiving the control voltage RT, and the drain of the second transistor T2 and the drain of the sixth transistor T62 are connected together and used to receive the second low frequency clock signal LC2.
  • the first voltage stabilizing circuit module 311 and the second voltage stabilizing circuit module 321 are both connected to the Nth stage gate signal output terminal G(N), and the first DC voltage VSS1 is greater than the second DC voltage VSS2.
  • the first voltage stabilizing circuit module 311 includes: a third three transistor M33 and a fourth three transistor M43; a gate of the third three transistor M33 and a gate of the fourth three transistor M43 are connected together and connected to the The drain of one transistor T1, the source of the third three transistor M33 and the source of the fourth three transistor M43 are respectively used to receive the first DC voltage VSS1, and the drain of the third three transistor M33 is connected to the Nth gate signal
  • the output terminal G(N), the drain of the fourth three transistor M43 is connected to the node Q(N).
  • the second voltage stabilizing circuit module 321 includes a third two transistor M32 and a fourth two transistor M42; the gate of the third two transistor M32 and the gate of the fourth two transistor M42 are connected together and connected to the drain of the first transistor T1
  • the source of the third two transistor M32 and the source of the fourth two transistor M42 are respectively used to receive the first DC voltage VSS1, and the drain of the third two transistor M32 is connected to the Nth gate signal output terminal G(N)
  • the drain of the fourth transistor M42 is connected to the node Q(N).
  • the pull-up driving module 20 includes a second transistor T21, the gate of the second transistor T21 is connected to the down signal ST(N-2) of the N-2th GOA unit, and the drain and source of the second transistor T21 The poles are respectively connected to the N-4th gate signal output terminal G(N-4) and the node Q(N).
  • the gate of the second transistor T21 is used to connect the enable signal terminal STV, the drain and the source of the second transistor T21 are respectively connected to the enable signal terminal STV and the node Q (N);
  • the gate and the drain of the second transistor T21 are both connected to the enable signal terminal STV, and the source of the second transistor T21 is connected to the node Q(N).
  • the pull-down module 40 includes a fourth transistor T41.
  • the gate of the fourth transistor T41 is connected to the N+2th gate signal output terminal G(N+2), and the drain and the source of the fourth transistor T41 are respectively connected. N-stage gate signal output terminal G(N) and second DC voltage VSS2.
  • the second DC voltage VSS2 is -10 V
  • the control voltage RT is -15 V
  • the first low frequency clock signal LC1 and the second low frequency clock signal LC2 are opposite in phase.
  • each of the above transistors is a thin film transistor, but the present invention is not limited thereto.
  • FIG. 2 is a diagram showing operational timing signals of a scan driving circuit in accordance with an embodiment of the present invention.
  • the scanning signals are 2160, that is, G1, G2, ..., G2160, but the present invention is not limited thereto.
  • the first DC voltage VSS1 is changed from a low level to a high level in a gap time (V-Blanking time) from the end of all timing signals of one frame to the rising edge of the start signal STV of the next frame.
  • the control voltage RT is changed from a low level to a high level, and the first DC voltage VSS1 is greater than the second DC Voltage VSS2.
  • the gate-to-source voltage of the third two-transistor T32 and the fourth-second transistor T42 ends at a gap time (V-blanking time) of the rising edge of the start signal STV of the next frame.
  • the internal reverse bias is formed, and the rest of the time is configured as a positive bias.

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Abstract

一种扫描驱动电路，包括级连的N个GOA单元，第N级GOA单元包括：上拉模块(10)、控制上拉模块(10)打开时间的上拉驱动模块(20)、下拉维持模块(30)及下拉模块(40)；上拉模块(10)分别与节点（Q(N)）和第N级栅极信号输出端(G(N))连接；上拉驱动模块(20)与节点Q(N)连接；下拉维持模块(30)用于分别接收第一直流电压(V SS1)和第二直流电压(V SS2)；下拉模块(40)连接第N级栅极信号输出端(G(N))且用于接收第二直流电压（V SS2）；下拉维持模块(30)由镜像连接的第一下拉维持电路(31)与第二下拉维持电路(32)交替工作构成，用于将第N级栅极信号输出端(G(N))和节点（Q(N)）保持在负电位。该扫描驱动电路具有高可靠性。

Description

扫描驱动电路及显示装置 技术领域
本发明涉及用于显示装置的扫描驱动电路，尤其涉及到一种具有高可靠性的扫描驱动电路及具有该扫描驱动电路的显示装置。
背景技术
GOA技术即Gate Driver on Array(阵列基板栅极驱动)是直接将栅极驱动电路(Gate Driver IC)制作在阵列基板上，实现对栅极线的逐行扫描的驱动方式的一项技术。
现有的GOA电路，通常包括级联的多个GOA单元，每一级GOA单元对应驱动一条扫描线(或称栅极线)。GOA单元的主要结构包括上拉模块(Pull-up part)、上拉驱动模块(Pull-up control part)、下传模块(Transfer part)、下拉模块(Key Pull-down part)和下拉维持模块(Pull-down Holding part)。上拉模块主要负责将时钟信号(Clock)输出为栅极信号；上拉驱动模块负责控制上拉模块的打开时间，一般连接前级GOA电路传递过来的下传信号或者栅极信号；下拉模块负责在第一时间将栅极信号拉低为低电位；下拉维持模块则负责将栅极信号和上拉电路的栅极信号(通常称为Q点)维持(Holding)在关闭状态(即负电位)，通常有两个下拉维持模块交替作用。
在现有技术的GOA电路中，下拉维持模块的稳压电路中的各个晶体管受到的压力最大，经过长时间的高温高湿操作后，各晶体管的阈值电压Vth漂移严重，会导致输出到扫描线(或称栅极线)的栅极信号出现异常，从而画面显示出现异常。
发明内容
为了解决上述现有的技术问题，本发明的目的在于提供一种扫描驱动电路，包括级连的N个GOA单元，第N级GOA单元包括：将时钟信号输出为栅极信号的上拉模块、控制所述上拉模块打开时间的上拉驱动模块、下拉维持 模块及下拉模块；所述上拉模块分别与节点和第N级栅极信号输出端连接；所述上拉驱动模块与第N级栅极信号输出端连接；所述下拉维持模块用于分别接收第一直流电压和第二直流电压；所述下拉模块连接第N级栅极信号输出端且用于接收第一直流电压；所述下拉维持模块由镜像连接的第一下拉维持电路与第二下拉维持电路构成，所述第一下拉维持电路与所述第二下拉维持电路交替工作，以将第N级栅极信号输出端和节点保持在负电位。
进一步地，所述第一下拉维持电路包括：第一稳压电路模块、漏极与第一稳压电路模块连接的第一晶体管和第五二晶体管、第三晶体管；第五二晶体管的源极连接第三晶体管漏极和栅极，第三晶体管的源极用于接收第一直流电压，第一晶体管的源极用于接收第二直流电压，第一晶体管的栅极用于接收控制电压，第一晶体管的漏极和第五二晶体管的漏极连接在一起并用于接收第一低频时钟信号；所述第二下拉维持电路包括：第二稳压电路模块、漏极与第二稳压电路模块连接的第二晶体管和第六二晶体管、第四晶体管；第六二晶体管的源极连接第四晶体管漏极和栅极，第四晶体管的源极用于接收第一直流电压，第二晶体管的源极用于接收第二直流电压，第二晶体管的栅极用于接收控制电压，第二晶体管的漏极和第六二晶体管的漏极连接在一起并用于接收第二低频时钟信号；所述第一稳压电路模块及所述第二稳压电路模块均连接到第N级栅极信号输出端，所述第一直流电压大于所述第二直流电压。
进一步地，所述第一稳压电路模块包括：第三三晶体管和第四三晶体管；第三三晶体管的栅极和第四三晶体管的栅极连接在一起并连接到第一晶体管的漏极，第三三晶体管的源极和第四三晶体管的源极分别用于接收第一直流电压，第三三晶体管的漏极连接到第N级栅极信号输出端，第四三晶体管的漏极连接到节点。
进一步地，所述第二稳压电路模块包括第三二晶体管和第四二晶体管；第三二晶体管的栅极和第四二晶体管的栅极连接在一起并连接到第一晶体管的漏极，第三二晶体管的源极和第四二晶体管的源极分别用于接收第一直流电压，第三二晶体管的漏极连接到第N级栅极信号输出端，第四二晶体管的漏极连接到节点。
进一步地，所述上拉驱动模块包括第二一晶体管，第二一晶体管的栅极连 接到第N-2级GOA单元的下传信号，第二一晶体管的漏极和源极分别连接到第N-4级栅极信号输出端和节点。
进一步地，在第一级GOA单元中，第二一晶体管的栅极用于连接启动信号端，第二一晶体管的漏极和源极分别连接启动信号端和节点；在第二级GOA单元中，第二一晶体管的栅极和漏极都连接到启动信号端，第二一晶体管的源极连接到节点。
进一步地，所述下拉模块包括第四一晶体管，第四一晶体管的栅极连接第N+2级栅极信号输出端，第四一晶体管的漏极和源极分别连接第N级栅极信号输出端和第二直流电压。
进一步地，所述第二直流电压为-10V，所述控制电压为-15V。
进一步地，所述第一低频时钟信号和所述第二低频时钟信号相位相反。
本发明的另一目的还在于提供一种显示装置，其包括上述的扫描驱动电路。
本发明的有益效果：本发明的扫描驱动电路具体高可靠性，从而能够避免使用该扫描驱动电路的显示装置显示的画面出现异常。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的实施例的第N级GOA单元的电路图；
图2是根据本发明的实施例的扫描驱动电路的工作时序信号图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
图1是根据本发明的实施例的第N级GOA单元的电路图。通常GOA电 路包括级联的N个图1所示的GOA单元。
参照图1，根据本发明的实施例的第N级GOA单元包括：将时钟信号CK输出为栅极信号的上拉模块10、控制上拉模块10打开时间的上拉驱动模块20、下拉维持模块30及下拉模块40。
上拉模块10分别与节点Q(N)和第N级栅极信号输出端G(N)连接；上拉驱动模块20与第N级栅极信号输出端G(N)连接；下拉维持模块30用于分别接收第一直流电压VSS1和第二直流电压VSS2；下拉模块40连接第N级栅极信号输出端G(N)且用于接收第一直流电压VSS1。
下拉维持模块30由镜像连接的第一下拉维持电路31与第二下拉维持电路32构成，第一下拉维持电路31与第二下拉维持电路32交替工作，以将第N级栅极信号输出端G(N)和节点Q(N)保持在负电位。
第一下拉维持电路31包括：第一稳压电路模块311、漏极与第一稳压电路模块311连接的第一晶体管T1和第五二晶体管T52、第三晶体管T3；第五二晶体管T52的源极连接第三晶体管T3漏极和栅极，第三晶体管T3的源极用于接收第一直流电压VSS1，第一晶体管T1的源极用于接收第二直流电压VSS2，第一晶体管T1的栅极用于接收控制电压RT，第一晶体管T1的漏极和第五二晶体管T52的漏极连接在一起并用于接收第一低频时钟信号LC1。
第二下拉维持电路32包括：第二稳压电路模块321、漏极与第二稳压电路模块321连接的第二晶体管T2和第六二晶体管T62、第四晶体管T4；第六二晶体管T62的源极连接第四晶体管(T4)漏极和栅极，第四晶体管T4的源极用于接收第一直流电压VSS1，第二晶体管T2的源极用于接收第二直流电压VSS2，第二晶体管T2的栅极用于接收控制电压RT，第二晶体管T2的漏极和第六二晶体管T62的漏极连接在一起并用于接收第二低频时钟信号LC2。
第一稳压电路模块311及第二稳压电路模块321均连接到第N级栅极信号输出端G(N)，第一直流电压VSS1大于第二直流电压VSS2。
第一稳压电路模块311包括：第三三晶体管M33和第四三晶体管M43；第三三晶体管M33的栅极和第四三晶体管M43的栅极连接在一起并连接到第 一晶体管T1的漏极，第三三晶体管M33的源极和第四三晶体管M43的源极分别用于接收第一直流电压VSS1，第三三晶体管M33的漏极连接到第N级栅极信号输出端G(N)，第四三晶体管M43的漏极连接到节点Q(N)。
第二稳压电路模块321包括第三二晶体管M32和第四二晶体管M42；第三二晶体管M32的栅极和第四二晶体管M42的栅极连接在一起并连接到第一晶体管T1的漏极，第三二晶体管M32的源极和第四二晶体管M42的源极分别用于接收第一直流电压VSS1，第三二晶体管M32的漏极连接到第N级栅极信号输出端G(N)，第四二晶体管M42的漏极连接到节点Q(N)。
上拉驱动模块20包括第二一晶体管T21，第二一晶体管T21的栅极连接到第N-2级GOA单元的下传信号ST(N-2)，第二一晶体管T21的漏极和源极分别连接到第N-4级栅极信号输出端G(N-4)和节点Q(N)。
此外，在第一级GOA单元中，第二一晶体管T21的栅极用于连接启动信号端STV，第二一晶体管T21的漏极和源极分别连接启动信号端STV和节点Q(N)；在第二级GOA单元中，第二一晶体管T21的栅极和漏极都连接到启动信号端STV，第二一晶体管T21的源极连接到节点Q(N)。
下拉模块40包括第四一晶体管T41，第四一晶体管T41的栅极连接第N+2级栅极信号输出端G(N+2)，第四一晶体管T41的漏极和源极分别连接第N级栅极信号输出端G(N)和第二直流电压VSS2。
在本实施例中，第二直流电压VSS2为-10V，控制电压RT为-15V。此外，第一低频时钟信号LC1和第二低频时钟信号LC2相位相反。
进一步地，在本实施例中，上述的各晶体管为薄膜晶体管，但本发明并不限制于此。
图2是根据本发明的实施例的扫描驱动电路的工作时序信号图。其中，示意出扫描信号为2160个，即G1、G2、……、G2160，但本发明并不限制于此。
参照图2，在一帧的所有时序信号结束到下一帧的启动信号STV的上升沿的间隙时间(V-Blanking time)内，将第一直流电压VSS1由低电平转为高电平，将控制电压RT由低电平转为高电平，第一直流电压VSS1大于第二直流 电压VSS2。
此时，第三二晶体管T32及第四二晶体管T42的栅极到源极的电压在一帧的所有时序信号结束到下一帧的启动信号STV的上升沿的间隙时间(V-blanking time)内构成反偏压，其余时间构成为正偏压。
尽管上面对本发明说明性的具体实施方式进行了描述，以便于本技术领域的技术人员能够理解本发明，但是本发明不仅限于具体实施方式的范围，对本技术领域的普通技术人员而言，只要各种变化只要在所附的权利要求限定和确定的本发明精神和范围内，一切利用本发明构思的发明创造均在保护之列。

Claims (10)

  1. 一种扫描驱动电路，包括级连的N个GOA单元，其中，第N级GOA单元包括：将时钟信号输出为栅极信号的上拉模块、控制所述上拉模块打开时间的上拉驱动模块、下拉维持模块及下拉模块；
    所述上拉模块分别与节点和第N级栅极信号输出端连接；所述上拉驱动模块与第N级栅极信号输出端连接；所述下拉维持模块用于分别接收第一直流电压和第二直流电压；所述下拉模块连接第N级栅极信号输出端且用于接收第一直流电压；
    所述下拉维持模块由镜像连接的第一下拉维持电路与第二下拉维持电路构成，所述第一下拉维持电路与所述第二下拉维持电路交替工作，以将第N级栅极信号输出端和节点保持在负电位。
  2. 根据权利要求1所述的扫描驱动电路，其中，所述第一下拉维持电路包括：第一稳压电路模块、漏极与第一稳压电路模块连接的第一晶体管和第五二晶体管、第三晶体管；第五二晶体管的源极连接第三晶体管漏极和栅极，第三晶体管的源极用于接收第一直流电压，第一晶体管的源极用于接收第二直流电压，第一晶体管的栅极用于接收控制电压，第一晶体管的漏极和第五二晶体管的漏极连接在一起并用于接收第一低频时钟信号；
    所述第二下拉维持电路包括：第二稳压电路模块、漏极与第二稳压电路模块连接的第二晶体管和第六二晶体管、第四晶体管；第六二晶体管的源极连接第四晶体管漏极和栅极，第四晶体管的源极用于接收第一直流电压，第二晶体管的源极用于接收第二直流电压，第二晶体管的栅极用于接收控制电压，第二晶体管的漏极和第六二晶体管的漏极连接在一起并用于接收第二低频时钟信号；
    所述第一稳压电路模块及所述第二稳压电路模块均连接到第N级栅极信号输出端，所述第一直流电压大于所述第二直流电压。
  3. 根据权利要求2所述的扫描驱动电路，其中，所述第一稳压电路模块 包括：第三三晶体管和第四三晶体管；第三三晶体管的栅极和第四三晶体管的栅极连接在一起并连接到第一晶体管的漏极，第三三晶体管的源极和第四三晶体管的源极分别用于接收第一直流电压，第三三晶体管的漏极连接到第N级栅极信号输出端，第四三晶体管的漏极连接到节点。
  4. 根据权利要求2所述的扫描驱动电路，其中，所述第二稳压电路模块包括第三二晶体管和第四二晶体管；第三二晶体管的栅极和第四二晶体管的栅极连接在一起并连接到第一晶体管的漏极，第三二晶体管的源极和第四二晶体管的源极分别用于接收第一直流电压，第三二晶体管的漏极连接到第N级栅极信号输出端，第四二晶体管的漏极连接到节点。
  5. 根据权利要求2所述的扫描驱动电路，其中，所述上拉驱动模块包括第二一晶体管，第二一晶体管的栅极连接到第N-2级GOA单元的下传信号，第二一晶体管的漏极和源极分别连接到第N-4级栅极信号输出端和节点。
  6. 根据权利要求5所述的扫描驱动电路，其中，在第一级GOA单元中，第二一晶体管的栅极用于连接启动信号端，第二一晶体管的漏极和源极分别连接启动信号端和节点；
    在第二级GOA单元中，第二一晶体管的栅极和漏极都连接到启动信号端，第二一晶体管的源极连接到节点。
  7. 根据权利要求2所述的扫描驱动电路，其中，所述下拉模块包括第四一晶体管，第四一晶体管的栅极连接第N+2级栅极信号输出端，第四一晶体管的漏极和源极分别连接第N级栅极信号输出端和第二直流电压。
  8. 根据权利要求2所述的扫描驱动电路，其中，所述第二直流电压为-10V，所述控制电压为-15V。
  9. 根据权利要求2所述的扫描驱动电路，其中，所述第一低频时钟信号和所述第二低频时钟信号相位相反。
  10. 一种显示装置，其中，包括权利要求1所述的扫描驱动电路。
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CN106205458A (zh) * 2016-08-30 2016-12-07 深圳市华星光电技术有限公司 一种goa驱动单元
CN106157916A (zh) * 2016-08-31 2016-11-23 深圳市华星光电技术有限公司 一种栅极驱动单元及驱动电路

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