WO2018120141A1 - 线路板结构、面内驱动电路及显示装置 - Google Patents

线路板结构、面内驱动电路及显示装置 Download PDF

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Publication number
WO2018120141A1
WO2018120141A1 PCT/CN2016/113775 CN2016113775W WO2018120141A1 WO 2018120141 A1 WO2018120141 A1 WO 2018120141A1 CN 2016113775 W CN2016113775 W CN 2016113775W WO 2018120141 A1 WO2018120141 A1 WO 2018120141A1
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WO
WIPO (PCT)
Prior art keywords
line
lines
board structure
layer
circuit board
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PCT/CN2016/113775
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English (en)
French (fr)
Inventor
赵继刚
袁泽
Original Assignee
深圳市柔宇科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to PCT/CN2016/113775 priority Critical patent/WO2018120141A1/zh
Priority to CN201680039410.4A priority patent/CN107995990A/zh
Publication of WO2018120141A1 publication Critical patent/WO2018120141A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a circuit board structure, an in-plane driving circuit, and a display device.
  • the signal lines of the in-plane driving circuit are formed by the semiconductor process using the same metal layer. Short circuits between signal lines are likely to occur due to problems such as foreign matter, poor photolithography, and residual metal after etching.
  • the present invention aims to at least solve one of the technical problems existing in the related art. To this end, the present invention needs to provide a circuit board structure, an in-plane driving circuit, and a display device.
  • first circuit layer a first circuit layer, a second circuit layer and an insulating layer disposed on the base layer, the first circuit layer comprising a plurality of first lines spaced apart, the second circuit layer comprising a plurality of second lines, The insulating layer covers the plurality of first lines, and the plurality of second lines are spaced apart on the insulating layer.
  • the first line and the second line may be made of different materials to respectively form different signal lines, and the insulating layer covers the plurality of first lines so that the first line is The insulation is separated, so that the short circuit problem between adjacent lines can be prevented, and the line spacing of the same layer can be reduced.
  • the first line and the second line are spaced apart from each other.
  • the first circuit layer and the second circuit layer are separated by the insulating layer.
  • the plurality of first lines are parallel to each other
  • the plurality of second lines are parallel to each other
  • the first line and the second line are parallel to each other.
  • the orthographic projection of the first line on the base layer is spaced from the orthographic projection of the second line on the base layer.
  • the resistivity of the first line is greater than the resistivity of the second line, and the width of the first line is greater than the width of the second line;
  • the resistivity of the first line is less than the resistivity of the second line, and the width of the first line is smaller than the width of the second line;
  • the resistivity of the first line is equal to the resistivity of the second line, and the width of the first line is equal to the width of the second line.
  • the first line and the second line each comprise spaced multi-segment jumpers, the jumper of the second line electrically connecting two adjacent ones of the first line Said jumper, said plurality of said jumpers of said first line being separated by said insulating layer.
  • an orthographic projection of the jumper of one of the first lines on the base layer An orthogonal projection of the jumper on a corresponding one of the second lines on the base layer overlaps.
  • the jumper of the second line electrically connects two of the jumpers of the adjacent first line by way of vias.
  • the plurality of jumpers are equally spaced along the length of the first line or the second line.
  • the first line is a gate metal and the second line is a source and a drain metal.
  • the driving circuit unit of each stage is electrically connected to the first line and the second line.
  • the first line and the second line may be made of different materials to respectively form different signal lines, and the insulating layer covers the plurality of first lines so that the first line is between The insulation is separated, so that the short circuit problem between adjacent lines can be prevented, and the line spacing of the same layer can be reduced.
  • a display device includes the above-described in-plane driving circuit.
  • the first line and the second line may be made of different materials to respectively form different signal lines, and the insulating layer covers the plurality of first lines such that the first line is insulated. Open, this can prevent short-circuit problems between adjacent lines and reduce the line in the same layer. Road spacing.
  • FIG. 1 is a schematic cross-sectional view showing a structure of a wiring board according to an embodiment of the present invention along a width direction of a line.
  • FIG. 2 is a schematic structural view of an in-plane driving circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of functional blocks of a display device according to an embodiment of the present invention.
  • Fig. 4 is a schematic cross-sectional view showing the structure of a wiring board according to another embodiment of the present invention in the width direction of the line.
  • Fig. 5 is a schematic structural view of an in-plane driving circuit according to another embodiment of the present invention.
  • Fig. 6 is a schematic cross-sectional view showing the structure of a circuit board according to still another embodiment of the present invention along the longitudinal direction of the line.
  • Fig. 7 is a schematic structural view of an in-plane driving circuit according to still another embodiment of the present invention.
  • FIG. 8 is a process flow diagram of a circuit board structure according to an embodiment of the present invention.
  • the circuit board structure 10 the base layer 12, the first circuit layer 14, the first line 142, the second circuit layer 16, the second line 162, the insulating layer 18;
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include one or more of the described features either explicitly or implicitly.
  • the meaning of "a plurality" is two or more unless specifically defined otherwise.
  • connection should be understood broadly.
  • it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, or may be an electrical connection or may be Communicate with each other; it can be a direct connection or an indirect connection through an intermediate medium, which can be the internal communication of two components or the interaction of two components.
  • an intermediate medium which can be the internal communication of two components or the interaction of two components.
  • the "on" or “below” of the second feature may include direct contact of the first and second features, and may also include the first sum, unless otherwise specifically defined and defined.
  • the second feature is not in direct contact but through additional features between them.
  • the first feature “above”, “above” and “above” the second feature includes the first feature directly above and above the second feature, or merely indicating that the first feature level is higher than the second feature.
  • the first feature “below”, “below” and “below” the second feature includes the first feature directly below and below the second feature, or merely the first feature level being less than the second feature.
  • a circuit board structure 10 of an embodiment of the present invention includes a base layer 12, a first wiring layer 14, a second wiring layer 16, and an insulating layer 18.
  • the first wiring layer 14, the second wiring layer 16, and the insulating layer 18 are disposed on the base layer 12.
  • the first circuit layer 14 includes a plurality of first lines 142 that are spaced apart.
  • the second circuit layer 16 includes a plurality of second lines 162.
  • the insulating layer 18 covers the plurality of first lines 142.
  • a plurality of second lines 162 are spaced apart on the insulating layer 18.
  • the first line 142 and the second line 162 may be made of different materials to respectively form different signal lines, and the insulating layer 18 covers the plurality of first lines 142 so that A line 142 is insulated from each other, so that a short circuit problem between adjacent lines can be prevented, and the line spacing of the same layer can be reduced.
  • the in-plane driving circuit 100 of the embodiment of the present invention includes a multi-level driving circuit unit 20 and a circuit board structure 10. Each stage of the driving circuit unit 20 is electrically connected to the first line 142 and the second line 162.
  • the first line 142 and the second line 162 may be used to provide timing signals for the driving circuit unit 20.
  • the in-plane driving circuit 100 may be a GOA (Gate Driver on Array) circuit or a pixel driving control circuit such as EOA (Emitter on Array).
  • the in-plane driving circuit 100 of the embodiment of the present invention is explained by taking a GOA circuit as an example.
  • the in-plane driving circuit 100 of the embodiment of the present invention can be applied to the display device 1000 of the embodiment of the present invention.
  • the display device 1000 can be an LCD (Liquid Crystal Display)
  • An electronic display such as an AMOLED (Active-matrix organic light emitting diode).
  • the first line 142 and the second line 162 are spaced apart from each other.
  • the second line 162 is located above the first line 142, and in the length direction or the width direction of the first line 142 or the second line 162, the first line 142 and the second line 162 are alternately arranged. .
  • the first line 142 and the second line 162 can be used to form a plurality of signal lines to provide timing signals for the in-plane drive circuit 100.
  • the circuit board structure 10 of the embodiment of the present invention takes four signal lines as an example, and is a signal line CLK1, a signal line CLK2, a signal line CLK3, and a signal line CLK4.
  • the driving circuit unit 20 of each stage is connected to the signal line CLK1, the signal line CLK2, the signal line CLK3, and the signal line CLK4, respectively.
  • the signal line CLK1 and the signal line CLK3 are two first lines 142, and the signal line CLK2 and the signal line CLK4 are two second lines 162.
  • the first circuit layer 14 and the second circuit layer 16 are separated by an insulating layer 18.
  • the insulating layer 18 divides the first circuit layer 14 and the second circuit layer 16 into upper and lower layers, which can prevent the short circuit problem between the two layers, and can further reduce the spacing between adjacent lines during manufacture. It is advantageous for the narrowing of the entire circuit board structure 10.
  • the insulating layer 18 may be made of an inorganic material (such as SiOx, SiNx, AlOx), or an organic insulating material, or a composite of two or more layers of inorganic materials such as SiOx, SiNx, AlOx (such as SiNx/SiOx).
  • the plurality of first lines 142 are parallel to each other, the plurality of second lines 162 are parallel to each other, and the first line 142 and the second line 162 are parallel to each other.
  • the orthographic projection of the first line 142 on the base layer 12 is separated from the orthographic projection of the second line 162 on the base layer 12.
  • the first line 142 is located obliquely above the second line 162, and the orthographic projection of the first line 142 on the base layer 12 is spaced from the orthographic projection of the second line 162 on the base layer 12.
  • the signal line CLK1 and the signal line CLK3 of the embodiment of the present invention are formed by the first line 142, and the signal line CLK2 and the signal line CLK4 are formed by the second line 162.
  • the resistivity of the first line 142 is greater than the resistivity of the second line 162, the width of the first line 142 is greater than the width of the second line 162; or the first line 142
  • the resistivity is less than the resistivity of the second line 162, the width of the first line 142 is less than the width of the second line 162; or the resistivity of the first line 142 is equal to the resistivity of the second line 162, the first line
  • the width of the way 142 is equal to the width of the second line 162.
  • the impedance of each signal line can be kept uniform, thereby eliminating the delay or having the same delay to achieve the signal between the signal lines. Synchronize.
  • the resistivity of the first line 142 is greater than the resistivity of the second line 162.
  • the width of the first line 142 may be set larger than the second line. Width of 162.
  • the first line 142 and the second line 162 each include a plurality of spaced jumpers, and the jumpers of the second line 162 electrically connect the two adjacent first lines 142.
  • the jumpers, the plurality of jumpers of the first line 142 are separated by an insulating layer 18.
  • the impedance of each signal line can be kept consistent, thereby eliminating the delay or having the same delay to achieve synchronization of signals between the signal lines.
  • the signal line CLK1, the signal line CLK2, the signal line CLK3, and the signal line CLK4 are both the multi-segment jumper of the first line 142 and the multi-segment jumper of the second line 162. Connected.
  • the orthographic projection of the jumper of a first line 142 on the base layer 12 overlaps the orthographic projection of the jumper of the corresponding one of the second lines 162 on the base layer 12.
  • the jumper of the first line 142 may be connected to the jumper of the second line 162 through the overlapping portion.
  • the orthographic projection of the first jumper 142 may overlap with the orthographic projection of the second line 162 at an angle, or the orthographic projection of the first jumper 142 may be in line with the orthographic projection of the second jumper 162.
  • the orthographic projection of the first jumper 142 and the orthographic projection of the second jumper 162 are in a straight line, thus facilitating the arrangement of the signal lines and reducing the line margins, which is convenient for processing and manufacturing.
  • the jumpers of the second line 162 are electrically connected to the two jumpers of the adjacent first line 142 by vias.
  • the insulating layer 18 can be patterned by a via, that is, a VIA process, and a hole is formed at a predetermined position on the insulating layer 18, so that the jumper of the second line 162 is electrically connected to the adjacent first through the via hole.
  • Two jumpers of line 142 Two jumpers of line 142.
  • the patterning can be achieved by dry etching or wet etching.
  • the multi-segment jumpers are equally distributed along the length of the first line 142 or the second line 162.
  • the length of jumper a is the same as the length of jumper b.
  • each jumper of the first line 142 is equal to the length of each jumper of the second line 162.
  • Each jumper is connected to the primary drive circuit unit 20.
  • the positions of the first line 142 and the corresponding segments of the second line 162 are the same, facilitating the lateral connection between the signal line and the drive circuit unit 20.
  • the lengths of the jumper a, the jumper c, the jumper d, and the jumper e are equal, and correspond to the drive circuit unit 20 of the (n+4)th stage.
  • the driving circuit unit 20 is connected to the jumper a and the jumper c, respectively.
  • the jumper d and the jumper e are provided to provide timing signals for the (n+4)th stage of the driving circuit unit 20.
  • the first line 142 is a gate metal and the second line 162 is a source and a drain metal.
  • each signal line of the in-plane driving circuit 100 may be formed by a process such as deposition, photolithography, etching, or the like.
  • the formation of the first wiring layer 14 and the second wiring layer 16 can be realized by deposition of a gate metal, and is performed by a deposition method such as physical vapor deposition (PVD), such as sputtering.
  • the formation of the insulating layer 18 can be achieved by a deposition method such as chemical vapor deposition (PECVD/ALD).
  • the first conductive layer may be deposited on the base layer 12 by the above method, then the first conductive layer may be patterned and etched to form the first wiring layer 14, and then the insulating layer 18 may be formed on the first wiring layer 14 by the above method.
  • a second conductive layer is formed on the insulating layer 18 by the above method, and then the second conductive layer is patterned and etched to form the second wiring layer 16.
  • a "computer-readable medium” can be any apparatus that can contain, store, communicate, propagate, or transport a program for use in an instruction execution system, apparatus, or device, or in conjunction with the instruction execution system, apparatus, or device.
  • computer readable media include the following: electrical connections (IPM overcurrent protection circuits) with one or more wires, portable computer disk cartridges (magnetic devices), random access memories (RAM), read only memory (ROM), erasable editable read only memory (EPROM or flash memory), fiber optic devices, and portable compact disk read only memory (CDROM).
  • the computer readable medium may even be a paper or other suitable medium on which the program can be printed, as may be for example by paper Or other medium is optically scanned, then edited, interpreted, or otherwise processed in other suitable manners to electronically obtain the program and then stored in computer memory.
  • portions of the embodiments of the invention may be implemented in hardware, software, firmware or a combination thereof.
  • multiple steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system.
  • a suitable instruction execution system For example, if implemented in hardware, as in another embodiment, it can be implemented by any one or combination of the following techniques well known in the art: having logic gates for implementing logic functions on data signals. Discrete logic circuits, application specific integrated circuits with suitable combinational logic gates, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.
  • each functional unit in each embodiment of the present invention may be integrated into one processing module, or each unit may exist physically separately, or two or more units may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules.
  • the integrated modules, if implemented in the form of software functional modules and sold or used as stand-alone products, may also be stored in a computer readable storage medium.
  • the above mentioned storage medium may be a read only memory, a magnetic disk or an optical disk or the like.

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Abstract

一种线路板结构(10)，包括基层(12)和设置在基层（12）上的第一线路层(14)、第二线路层(16)和绝缘层(18)。第一线路层(14)包括间隔设置的多个第一线路(142)。第二线路层(16)包括多个第二线路(162)。绝缘层(18)包覆多个第一线路(142)。多个第二线路(162)间隔地位于绝缘层(18)上。在线路板结构(10)中，第一线路(142)和第二线路(162)可采用不同的材料制成以分别构成不同的信号线，且绝缘层(18)包覆多个第一线路(142)使得第一线路(142)之间绝缘隔开，如此，可以防止相邻的线路之间出现短路问题，并能缩小同层的线路间距。此外，还公开了一种包括该线路板结构(10)的面内驱动电路及显示装置。

Description

线路板结构、面内驱动电路及显示装置 技术领域
本发明涉及显示技术领域，特别涉及一种线路板结构、面内驱动电路及显示装置。
背景技术
在相关技术中，面内驱动电路的信号线采用同一金属层通过半导体工艺制成。由于异物、光刻不良、刻蚀后金属残留等问题，容易造成信号线间的短路。
发明内容
本发明旨在至少解决相关技术中存在的技术问题之一。为此，本发明需要提供一种线路板结构、面内驱动电路及显示装置。
本发明实施方式的线路板结构包括：
基层；
设置在所述基层上的第一线路层、第二线路层和绝缘层，所述第一线路层包括间隔设置的多个第一线路，所述第二线路层包括多个第二线路，所述绝缘层包覆所述多个第一线路，所述多个第二线路间隔地位于所述绝缘层上。
在本发明实施方式的线路板结构中，第一线路和第二线路可采用不同的材料制成以分别构成不同的信号线，且绝缘层包覆多个第一线路使得第一线路之 间绝缘隔开，如此，可以防止相邻的线路之间出现短路问题，并能缩小同层的线路间距。
在某些实施方式中，所述第一线路与所述第二线路上下交错间隔设置。
在某些实施方式中，所述第一线路层和所述第二线路层通过所述绝缘层隔开。
在某些实施方式中，所述多个第一线路相互平行，所述多个第二线路相互平行，所述第一线路和所述第二线路相互平行。
在某些实施方式中，所述第一线路在所述基层上的正投影与所述第二线路在所述基层上的正投影隔开。
在某些实施方式中，所述第一线路的电阻率大于所述第二线路的电阻率，所述第一线路的宽度大于所述第二线路的宽度；或
所述第一线路的电阻率小于所述第二线路的电阻率，所述第一线路的宽度小于所述第二线路的宽度；或
所述第一线路的电阻率等于所述第二线路的电阻率，所述第一线路的宽度等于所述第二线路的宽度。
在某些实施方式中，所述第一线路和所述第二线路均包括间隔的多段跳线，所述第二线路的所述跳线电连接相邻的所述第一线路的两个所述跳线，所述第一线路的多个所述跳线由所述绝缘层隔开。
在某些实施方式中，一个所述第一线路的所述跳线在所述基层上的正投影 与对应的一个所述第二线路的所述跳线在所述基层上的正投影重叠。
在某些实施方式中，所述第二线路的所述跳线通过过孔的方式电连接相邻的所述第一线路的两个所述跳线。
在某些实施方式中，所述多段跳线沿所述第一线路或所述第二线路的长度方向等长分布。
在某些实施方式中，所述第一线路为栅极金属，所述第二线路为源极和漏极金属。
本发明实施方式的一种面内驱动电路包括：
多级驱动电路单元；和
上述任一实施方式的所述的线路板结构，每级所述驱动电路单元电性连接所述第一线路和所述第二线路。
在本发明实施方式的面内驱动电路中，第一线路和第二线路可采用不同的材料制成以分别构成不同的信号线，且绝缘层包覆多个第一线路使得第一线路之间绝缘隔开，如此，可以防止相邻的线路之间出现短路问题，并能缩小同层的线路间距。
本发明实施方式的一种显示装置，包括上述面内驱动电路。
在本发明实施方式的显示装置中，第一线路和第二线路可采用不同的材料制成以分别构成不同的信号线，且绝缘层包覆多个第一线路使得第一线路之间绝缘隔开，如此，可以防止相邻的线路之间出现短路问题，并能缩小同层的线 路间距。
本发明的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
本发明的上述和/或附加的方面和优点可以从结合下面附图对实施方式的描述中将变得明显和容易理解，其中：
图1是本发明实施方式的线路板结构的沿线路的宽度方向的截面示意图。
图2是本发明实施方式的面内驱动电路的结构示意图。
图3是本发明实施方式的显示装置的功能模块示意图。
图4是本发明另一个实施方式的线路板结构的沿线路的宽度方向的截面示意图。
图5是本发明另一个实施方式的面内驱动电路的结构示意图。
图6是本发明又一个实施方式的线路板结构沿线路的长度方向的截面示意图。
图7是本发明又一个实施方式的面内驱动电路的结构示意图。
图8是本发明实施方式的线路板结构的工艺流程图。
主要元件及符号说明：
线路板结构10、基层12、第一线路层14、第一线路142、第二线路层16、第二线路162、绝缘层18；
驱动电路单元20；
面内驱动电路100；
显示装置1000。
具体实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中，相同或类似的标号自始至终表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明的实施方式，而不能理解为对本发明的实施方式的限制。
在本发明的实施方式的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明的实施方式和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的实施方式的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的实施方式的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的实施方式的描述中，需要说明的是，除非另有明确的规定和限 定，术语“安装”、“连接”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接连接，也可以通过中间媒介间接连接，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明的实施方式中的具体含义。
在本发明的实施方式中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的实施方式的不同结构。为了简化本发明的实施方式的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明的实施方式可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明的实施方式提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请参阅图1，本发明实施方式的线路板结构10包括基层12、第一线路层14、第二线路层16和绝缘层18。第一线路层14、第二线路层16和绝缘层18设置在基层12上。第一线路层14包括间隔设置的多个第一线路142。第二线路层16包括多个第二线路162。绝缘层18包覆多个第一线路142。多个第二线路162间隔地位于绝缘层18上。
在本发明实施方式的线路板结构10中，第一线路142和第二线路162可采用不同的材料制成以分别构成不同的信号线，且绝缘层18包覆多个第一线路142使得第一线路142之间绝缘隔开，如此，可以防止相邻的线路之间出现短路问题，并能缩小同层的线路间距。
请参阅图2，本发明实施方式的面内驱动电路100包括多级驱动电路单元20和线路板结构10。每级驱动电路单元20电性连接第一线路142和第二线路162。
第一线路142和第二线路162可以用于为驱动电路单元20提供时序信号，面内驱动电路100可以为GOA(Gate Driver on Array)电路或EOA(Emitter on Array)等像素驱动控制电路。
本发明实施方式的面内驱动电路100以GOA电路为例进行解释说明。
请参阅图3，本发明实施方式的面内驱动电路100可以应用于本发明实施方式的显示装置1000。
在一些示例中，显示装置1000可以为LCD(Liquid Crystal Display，液晶显 示器)或AMOLED(Active-matrix organic light emitting diode，有源矩阵有机发光二极体)等电子显示器。
在某些实施方式中，请参图1和4，第一线路142与第二线路162上下交错间隔设置。
也即是说，第二线路162位于第一线路142的上方，而在沿第一线路142或第二线路162的长度方向或宽度方向上，第一线路142和第二线路162交错间隔排布。
第一线路142和第二线路162可以用于形成多条信号线，以为面内驱动电路100提供时序信号。为了便于解释说明，本发明实施方式的线路板结构10以4条信号线为例，分别为信号线CLK1、信号线CLK2、信号线CLK3、信号线CLK4。每级的驱动电路单元20分别连接到信号线CLK1、信号线CLK2、信号线CLK3、信号线CLK4。
其中，信号线CLK1、信号线CLK3为两条第一线路142，信号线CLK2、信号线CLK4为两个第二线路162。
在某些实施方式中，请参图1和4，第一线路层14和第二线路层16通过绝缘层18隔开。
如此，绝缘层18将第一线路层14和第二线路层16分为上下两层，可以防止两层线路之间出现短路问题，而且制造时可以进一步缩小相邻的线路之间的间距，有利于线路板结构10整体的窄边化。
具体地，绝缘层18可以采用无机材料(如SiOx，SiNx，AlOx)，或有机绝缘材料，或SiOx，SiNx，AlOx等无机材料的两层或多层复合(如SiNx/SiOx)。
在某些实施方式中，多个第一线路142相互平行，多个第二线路162相互平行，第一线路142和第二线路162相互平行。
如此，有利于线路板结构10的制造工艺及线路板结构10所占用的空间较小。
在某些实施方式中，第一线路142在基层12上的正投影与第二线路162在基层12上的正投影隔开。
如此，有利于消除第一线路142与第二线路162的信号间的电容耦合。
当第二线路162位于第一线路142的正上方时，固然可以减少线路板结构10的整体边框，但容易增加信号间的电容耦合。因而较佳地，第一线路142位于第二线路162的斜上方，且第一线路142在基层12上的正投影与第二线路162在基层12上的正投影隔开。
可以理解，本发明实施方式的信号线CLK1和信号线CLK3由第一线路142形成，信号线CLK2和信号线CLK4由第二线路162形成。
请参阅图4及图5，在某些实施方式中，第一线路142的电阻率大于第二线路162的电阻率，第一线路142的宽度大于第二线路162的宽度；或第一线路142的电阻率小于第二线路162的电阻率，第一线路142的宽度小于第二线路162的宽度；或第一线路142的电阻率等于第二线路162的电阻率，第一线 路142的宽度等于第二线路162的宽度。
如此，通过对第一线路142与第二线路162的电阻率和宽度的关系的限定可以使得各信号线的阻抗保持一致，从而消除延迟或具有相同的延迟，以实现各信号线之间信号的同步。
例如，以图4和图5为例，第一线路142的电阻率大于第二线路162的电阻率，为了使得各信号线的阻抗保持一致，第一线路142的宽度可以设置为大于第二线路162的宽度。
请参阅图6及图7，在某些实施方式中，第一线路142和第二线路162均包括间隔的多段跳线，第二线路162的跳线电连接相邻的第一线路142的两个跳线，第一线路142的多个跳线由绝缘层18隔开。
如此，可以使得各信号线的阻抗保持一致，从而消除延迟或具有相同的延迟，以实现各信号线之间信号的同步。
可以理解，在图6和图7所示的实施方式中，信号线CLK1、信号线CLK2、信号线CLK3、信号线CLK4均由第一线路142的多段跳线和第二线路162的多段跳线连接而成。
在某些实施方式中，一个第一线路142的跳线在基层12上的正投影与对应的一个第二线路162的跳线的在基层12上的正投影重叠。
具体地，第一线路142的跳线可以通过重叠部分与第二线路162的跳线连接。
第一跳线142的正投影可以与第二线路162的正投影交叉成一定角度重叠，也可以为第一跳线142的正投影与第二跳线162的正投影在一条直线上。
较佳地，第一跳线142的正投影与第二跳线162的正投影在一条直线上，如此，有利于信号线的排布和减少线边距，便于加工制造。
在某些实施方式中，第二线路162的跳线通过过孔的方式电连接相邻的第一线路142的两个跳线。
具体地，可以通过过孔即VIA工艺对绝缘层18进行图形化，在绝缘层18上的预定位置进行开孔，使得第二线路162的跳线通过过孔的方式电连接相邻的第一线路142的两个跳线。
可以理解，图案化可以通过由干刻蚀或湿刻蚀实现。
在某些实施方式中，多段跳线沿第一线路142或第二线路162的长度方向等长分布。
例如，跳线a的长度和跳线b的长度相等。
在某些实施方式中，第一线路142的每段跳线的长度等于第二线路162的每段跳线的长度。每段跳线对应连接一级驱动电路单元20。
如此，第一线路142与第二线路162的对应分段的位置相同，有利于信号线与驱动电路单元20之间的横向连线。
具体地，以图7为例，跳线a、跳线c、跳线d和跳线e的长度相等，且对应第(n+4)级的驱动电路单元20。驱动电路单元20分别连接跳线a、跳线c、 跳线d和跳线e，以为第(n+4)级的驱动电路单元20提供时序信号。
在某些实施方式中，第一线路142为栅极金属，第二线路162为源极和漏极金属。
具体地，栅极金属、源极金属和漏极金属可以为金、银、铜、铁、铝等。在制造时，可以通过沉积、光刻、刻蚀等工艺以形成面内驱动电路100的各信号线。
请参阅图8，第一线路层14和第二线路层16的形成可以通过栅极金属的沉积来实现，采用物理气相沉积(PVD，Physical VaporDeposition)，如溅镀(sputtering)等沉积方法实现。绝缘层18的形成可以通过化学气相沉积(PECVD/ALD)等沉积方法实现。
例如，可先在基层12上利用上述方法沉积第一导电层，然后图案化蚀刻第一导电层来形成第一线路层14，然后在第一线路层14上利用上述方法形成绝缘层18，之后在绝缘层18上利用上述方法形成第二导电层，再图案化蚀刻第二导电层来形成第二线路层16。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”或“一些示例”等的描述意指结合所述实施方式或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多 个实施方式或示例中以合适的方式结合。
流程图中或在此以其他方式描述的任何过程或方法描述可以被理解为，表示包括一个或更多个用于实现特定逻辑功能或过程的步骤的可执行指令的代码的模块、片段或部分，并且本发明的优选实施方式的范围包括另外的实现，其中可以不按所示出或讨论的顺序，包括根据所涉及的功能按基本同时的方式或按相反的顺序，来执行功能，这应被本发明的实施例所属技术领域的技术人员所理解。
在流程图中表示或在此以其他方式描述的逻辑和/或步骤，例如，可以被认为是用于实现逻辑功能的可执行指令的定序列表，可以具体实现在任何计算机可读介质中，以供指令执行系统、装置或设备(如基于计算机的系统、包括处理模块的系统或其他可以从指令执行系统、装置或设备取指令并执行指令的系统)使用，或结合这些指令执行系统、装置或设备而使用。就本说明书而言，"计算机可读介质"可以是任何可以包含、存储、通信、传播或传输程序以供指令执行系统、装置或设备或结合这些指令执行系统、装置或设备而使用的装置。计算机可读介质的更具体的示例(非穷尽性列表)包括以下：具有一个或多个布线的电连接部(IPM过流保护电路)，便携式计算机盘盒(磁装置)，随机存取存储器(RAM)，只读存储器(ROM)，可擦除可编辑只读存储器(EPROM或闪速存储器)，光纤装置，以及便携式光盘只读存储器(CDROM)。另外，计算机可读介质甚至可以是可在其上打印所述程序的纸或其他合适的介质，因为可以例如通过对纸 或其他介质进行光学扫描，接着进行编辑、解译或必要时以其他合适方式进行处理来以电子方式获得所述程序，然后将其存储在计算机存储器中。
应当理解，本发明的实施方式的各部分可以用硬件、软件、固件或它们的组合来实现。在上述实施方式中，多个步骤或方法可以用存储在存储器中且由合适的指令执行系统执行的软件或固件来实现。例如，如果用硬件来实现，和在另一实施方式中一样，可用本领域公知的下列技术中的任一项或他们的组合来实现：具有用于对数据信号实现逻辑功能的逻辑门电路的离散逻辑电路，具有合适的组合逻辑门电路的专用集成电路，可编程门阵列(PGA)，现场可编程门阵列(FPGA)等。
本技术领域的普通技术人员可以理解实现上述实施例方法携带的全部或部分步骤是可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，该程序在执行时，包括方法实施例的步骤之一或其组合。
此外，在本发明的各个实施例中的各功能单元可以集成在一个处理模块中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。所述集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。
上述提到的存储介质可以是只读存储器，磁盘或光盘等。
尽管上面已经示出和描述了本发明的实施方式，可以理解的是，上述实施 方式是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施实施进行变化、修改、替换和变型。

Claims (13)

  1. 一种线路板结构，其特征在于，包括：
    基层；
    设置在所述基层上的第一线路层、第二线路层和绝缘层，所述第一线路层包括间隔设置的多个第一线路，所述第二线路层包括多个第二线路，所述绝缘层包覆所述多个第一线路，所述多个第二线路间隔地位于所述绝缘层上。
  2. 如权利要求1所述的线路板结构，其特征在于，所述第一线路与所述第二线路上下交错间隔设置。
  3. 如权利要求1所述的线路板结构，其特征在于，所述第一线路层和所述第二线路层通过所述绝缘层隔开。
  4. 如权利要求1所述的线路板结构，其特征在于，所述多个第一线路相互平行，所述多个第二线路相互平行，所述第一线路和所述第二线路相互平行。
  5. 如权利要求2所述的线路板结构，其特征在于，所述第一线路在所述基层上的正投影与所述第二线路在所述基层上的正投影隔开。
  6. 如权利要求1所述的线路板结构，其特征在于，所述第一线路的电阻率 大于所述第二线路的电阻率，所述第一线路的宽度大于所述第二线路的宽度；或
    所述第一线路的电阻率小于所述第二线路的电阻率，所述第一线路的宽度小于所述第二线路的宽度；或
    所述第一线路的电阻率等于所述第二线路的电阻率，所述第一线路的宽度等于所述第二线路的宽度。
  7. 如权利要求1所述的线路板结构，其特征在于，所述第一线路和所述第二线路均包括间隔的多段跳线，所述第二线路的所述跳线电连接相邻的所述第一线路的两个所述跳线，所述第一线路的多个所述跳线由所述绝缘层隔开。
  8. 如权利要求7所述的线路板结构，其特征在于，一个所述第一线路的所述跳线在所述基层上的正投影与对应的一个所述第二线路的所述跳线在所述基层上的正投影重叠。
  9. 如权利要求7所述的线路板结构，其特征在于，所述第二线路的所述跳线通过过孔的方式电连接相邻的所述第一线路的两个所述跳线。
  10. 如权利要求7所述的线路板结构，其特征在于，所述多段跳线沿所述第一线路或所述第二线路的长度方向等长分布。
  11. 如权利要求1至10任意一项所述的线路板结构，其特征在于，所述第一线路为栅极金属，所述第二线路为源极和漏极金属。
  12. 一种面内驱动电路，其特征在于，包括：
    多级驱动电路单元；和
    如权利要求1-11任意一项所述的线路板结构，每级所述驱动电路单元电性连接所述第一线路和所述第二线路。
  13. 一种显示装置，其特征在于，包括如权利要求12所述的面内驱动电路。
PCT/CN2016/113775 2016-12-30 2016-12-30 线路板结构、面内驱动电路及显示装置 WO2018120141A1 (zh)

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