WO2018113036A1 - 具有抗静电结构的封装结构 - Google Patents

具有抗静电结构的封装结构 Download PDF

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Publication number
WO2018113036A1
WO2018113036A1 PCT/CN2017/000253 CN2017000253W WO2018113036A1 WO 2018113036 A1 WO2018113036 A1 WO 2018113036A1 CN 2017000253 W CN2017000253 W CN 2017000253W WO 2018113036 A1 WO2018113036 A1 WO 2018113036A1
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antistatic
substrate
package structure
circuit
conductive pillar
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PCT/CN2017/000253
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English (en)
French (fr)
Inventor
谢明哲
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创智能科技股份有限公司
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Publication of WO2018113036A1 publication Critical patent/WO2018113036A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention relates to an electrostatic protection design of a package structure, in particular to a package structure with an antistatic structure integrating an antistatic structure and a package substrate.
  • electrostatic discharge causes electrostatic breakdown, which leads to failure of electronic components inside the integrated circuit, especially after miniaturization and densification of electronic components. Electrostatic protection requirements are becoming more and more demanding, and only the correct electrostatic protection components can be selected to exert the proper electrostatic protection function in the integrated circuit.
  • an antistatic structure is generally added directly to the package structure of the integrated circuit.
  • the substrate 10 includes a fingerprint identification chip 12 on the upper surface thereof, and a plurality of bonding wires 14 electrically connected to the substrate 10 and the fingerprint identification chip 12 .
  • An electrostatic discharge strip 16 is mounted on the active surface 121 of the fingerprint recognition wafer 12 .
  • a glue 18 is located on the substrate 10 and surrounds the fingerprint recognition wafer 12 to cover the bonding wires 14 and partially cover the active surface 121 of the fingerprint recognition wafer 12 and is connected to the electrostatic discharge strip 16. A portion of the electrostatic discharge strip 16 is exposed to the open edge of the encapsulant 18 to achieve electrostatic discharge on the wafer.
  • the present invention proposes a package structure having an antistatic structure to solve the defects existing in the background art.
  • the main object of the present invention is to provide a package structure having an antistatic structure, which is integrally formed by integrating an antistatic circuit into a substrate, and the antistatic circuit is electrically connected to the connection pad via a conductive post in the substrate.
  • the antistatic circuit is integrally formed by integrating an antistatic circuit into a substrate, and the antistatic circuit is electrically connected to the connection pad via a conductive post in the substrate.
  • the thin and light package structure can be achieved and the packaging process can be simplified.
  • Another object of the present invention is to provide a package structure having an antistatic structure, which is to resist static While the electrical circuit is integrated into the substrate, an integrally formed conductive pillar is disposed in the substrate, and the shape of the conductive pillar can be designed according to different electrical considerations of different components.
  • a package structure having an antistatic structure mainly includes a substrate having at least one groove integrally formed on the substrate, and at least one conductive post is disposed on the substrate around the groove. At least one connection pad is disposed on the lower surface and corresponding to the position of the conductive pillar; and at least one antistatic circuit is disposed on the substrate around the groove, and the antistatic circuit is electrically connected to the connection pad via the conductive pillar.
  • the invention can utilize at least one antistatic circuit to contact the surface of the wafer mounted in the groove to ground the unnecessary static electricity to achieve antistatic effect.
  • the substrate is an insulating substrate, preferably a ceramic substrate.
  • the at least one antistatic circuit is a closed circuit or has at least one opening.
  • the at least one antistatic circuit protrudes from the surface of the substrate to contact the surface of the wafer.
  • the conductive pillar is in the shape of a trapezoidal body, an inverted trapezoidal body, a cylinder, a rectangular parallelepiped or a cone.
  • the package structure with antistatic structure proposed by the invention integrates an antistatic circuit and a conductive column into a substrate and is integrally formed.
  • the conductive column is used as a channel for electrically connecting the antistatic circuit and the connection pad, and the antistatic circuit is provided.
  • the conductive material can be formed in the substrate by electroplating, electroless plating or sputtering, and the antistatic circuit can be in contact with the wafer, and unnecessary static electricity is guided to the ground via the connection pad to achieve electrostatic discharge protection by using the antistatic line.
  • the function is integrated into the process by the antistatic circuit and the conductive column directly formed integrally with the substrate, and the thin and light package structure can be realized, and the packaging process can be simplified, and the application is widely used.
  • FIG. 1 is a schematic view of a conventional package structure having an electrostatic discharge strip.
  • FIG. 2 is a perspective view of a package structure having a groove according to the present invention.
  • FIG 3 is a cross-sectional view showing the structure of a package structure having a recess of the present invention.
  • FIG. 4 is a perspective view of a package structure having two grooves according to the present invention.
  • FIG. 5 is a schematic view showing an embodiment of an antistatic structure having an opening on a substrate according to the present invention.
  • FIG. 6 is a schematic view showing an embodiment of an antistatic structure having two openings on a substrate according to the present invention.
  • FIG. 7A is a cross-sectional view showing a package structure of a trapezoidal conductive column of the present invention.
  • 7B is a cross-sectional view showing a package structure of an inverted trapezoidal conductive column of the present invention.
  • the invention integrates the antistatic circuit and the structural design of the conductive column at the same time in the manufacturing process of the substrate to form an integrally formed package structure with an antistatic structure.
  • FIG. 2 and FIG. 3 is a perspective view of a package structure having a recess and a cross-sectional view thereof.
  • a package structure 20 having an antistatic structure includes a substrate 22 and at least one anti-ring disposed thereon.
  • the upper surface of the substrate 22 has at least one recess 24 integrally formed.
  • a recess 24 is taken as an example.
  • the bottom surface of the recess 24 can be provided with a plurality of conductive pads (not shown) to make the recess.
  • At least one wafer (not shown) can be mounted in the slot 24 and electrically connected to the substrate 22 through the conductive pads; at least one conductive post 26 is disposed on the substrate 22 at a position peripheral to the recess 24, and the substrate 22 is disposed on the substrate 22
  • the lower surface is provided with at least one connecting pad.
  • the external connecting pad is exemplified by a plurality of connecting pads 28, and the conductive posts 26 are selectively electrically connected to the connecting pads 28 on the lower surface of the substrate 22 for external grounding;
  • the antistatic circuit 30 is a closed circuit and is a metal circuit. The antistatic circuit 30 is located on the substrate 22 around the recess 24 and exposed to the substrate 22 .
  • the antistatic circuit 30 is electrically connected to the connection pad 28 via the conductive post 26 .
  • the conductive pads (not shown) are combined to contact the wafer with the antistatic line 30 to direct the static electricity through the conductive posts 26 to the grounding pad 28 to achieve the electrostatic protection function.
  • the anti-static circuit line 30 drawn in the figure is located on the substrate 22 without protruding the surface of the substrate 22. Of course, if there are different design considerations, the antistatic circuit can also protrude from the substrate so as to be in contact with the surface of the wafer. This is limited to this.
  • an insulating substrate is used.
  • a ceramic substrate such as a High-Temperature Co-fired Creamics (HTCC) substrate or a low-temperature co-fired ceramic substrate (Low-Temperature) can be used.
  • Co-fired Creamics, LTCC Co-fired Creamics
  • the invention can have more than two grooves on the substrate, in addition to a groove formed integrally, and more than two different groove designs.
  • the package structure 20 of the present invention can directly provide two integrally formed grooves 24 and 32 on the substrate 22 to respectively provide two different wafers.
  • a sensing wafer is mounted in the recess 24, and a light-emitting chip is mounted in the recess 32;
  • the embodiments shown in the two figures are the same, and therefore will not be described again.
  • the antistatic circuit disposed on the substrate of the present invention has different implementation aspects in addition to the continuous closed circuit design described above, that is, the antistatic circuit 30 has at least one opening, for example, FIG. It is shown that the antistatic circuit 30 has an opening 34, or as shown in FIG. 6, the antistatic circuit 30 has two openings 34, 36, and the antistatic circuit 30 is designed as a discontinuous circuit to provide different package designs. select.
  • the conductive pillar structure design of the present invention can be structurally adjusted according to the degree of antistatic required, including the shape, the number, the relative position, and the like, for example, as shown in FIG. 7A, a plurality of trapezoidal bodies having an upper narrow width and a lower width.
  • the conductive column 26 as shown in FIG. 7B, a plurality of conductive columns 26 having an inverted trapezoidal body having an upper width and a lower width; or a shape design of other undrawn cylinders, cuboids or cones.
  • the package structure with antistatic structure proposed by the invention is integrated into the substrate by integrating the antistatic circuit and the conductive column into the substrate, and the conductive column is used as a channel for electrically connecting the antistatic circuit and the connection pad in the middle, and the antistatic is adopted.
  • the circuit can form the conductive material in the substrate by electroplating, electroless plating or sputtering, and the antistatic circuit can contact the wafer to guide unnecessary static electricity to the ground through the connection pad to achieve electrostatic discharge by using the antistatic line.
  • the function of protection, and integrated into the process by the antistatic circuit and the conductive column directly formed with the substrate can achieve a thin and light package structure and simplify the packaging process, and is widely used.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Packaging Frangible Articles (AREA)
  • Elimination Of Static Electricity (AREA)

Abstract

一种具有抗静电结构的封装结构（20），此封装结构（20）包括有一基板（22），其上具有一体成形的至少一凹槽（24），在凹槽（24）周围且位于基板（22）中设有至少一导电柱（26），在基板（22）下表面设有至少一连接垫（28）电性连接导电柱（26），并在凹槽（24）周围的基板（22）上设有至少一抗静电线路（30），其经由导电柱（26）而电性连接至连接垫（28），使安装于凹槽（24）内的晶片得以与抗静电线路（30）接触，经导电柱（26）导至连接垫（28）来达到引导静电接地的功效。将抗静电线路、导电柱整合至基板中而为一体成形，除了可利用抗静电线路达到静电放电防护功能之外，更因抗静电线路、导电柱直接与基板整合于同一制程中而一体成形，故可有效到轻薄化封装并可简化整个封装制程。

Description

具有抗静电结构的封装结构 技术领域
本发明涉及一种封装结构的静电防护设计，特别是关于一种将抗静电结构与封装基板整合为一体的具有抗静电结构的封装结构。
背景技术
在集成电路中，由于静电放电(Electrostatic discharge，ESD)会引起静电击穿，进而导致集成电路内部电子元件发生故障，尤其是对电子元件小型化与密集化后的影响更是日趋明显，所以对于静电保护要求也日益严苛，也只有选择正确的静电保护元件，才能于集成电路中发挥出应有的静电防护功能。
为达到静电防护作用，一般在集成电路的封装结构上会直接增设有抗静电结构，例如，现有技术揭示一种晶片上静电放电的指纹辨识器封装构造，如图1所示，此封装结构包括一基板10，其上表面安装有一指纹辨识晶片12，并有复数焊线14电性连接基板10及指纹辨识晶片12，一静电放电条16系安装于指纹辨识晶片12的主动面121上，一封胶体18位于基板10上且围绕指纹辨识晶片12，以覆盖住焊线14及部份覆盖住指纹辨识晶片12的主动面121且连接至静电放电条16。由于静电放电条16部份显露于封胶体18的开口边缘，以达到晶片上静电放电。
然而，将静电放电条直接安装于晶片的制程较为复杂，且过程中容易危害的晶片本身的功能，再者，因为封装结构一直向上堆迭，也难以达到封装轻薄程度的功效，效果有限。有鉴于此，本发明遂提出一种具有抗静电结构的封装结构，以解决存在于背景技术中的该些缺失。
发明内容
本发明的主要目的系在提供一种具有抗静电结构的封装结构，其是将抗静电线路整合至基板中而为一体成形者，且抗静电线路经由基板中的导电柱电性连接至连接垫，以利用此抗静电线路达到抗静电的功能，且因抗静电线路直接与基板一体成形，更可达到轻薄化封装结构并可简化封装制程。
本发明的另一目的是在提供一种具有抗静电结构的封装结构，其是将抗静 电线路整合至基板的同时，于该基板内设置有一体成形的导电柱，且导电柱的形状可依据不同元件的电性考量而有不同形状的结构设计。
为达到上述目的，本发明提出的具有抗静电结构的封装结构主要包括有一基板，基板上具有一体成形的至少一凹槽，且在凹槽周围的基板上穿设有至少一导电柱，于基板下表面且对应导电柱的位置设有至少一连接垫；另有至少一抗静电线路位于凹槽周围的基板上，此抗静电线路经由导电柱电性连接至连接垫。本发明可利用至少一抗静电线路与安装于凹槽内的晶片表面接触，以将不必要的静电引导接地，达到抗静电的功效。
其中，所述的基板是绝缘基板，较佳者为陶瓷基板。
其中，所述至少一抗静电线路是一封闭线路或是具有至少一开口。
其中，所述至少一抗静电线路更有突出基板表面，以便与晶片表面接触。
其中，所述的导电柱是梯形体、倒梯形体、圆柱体、长方体或锥形体等形状。
本发明提出的具有抗静电结构的封装结构，其是将抗静电线路、导电柱整合至基板中而为一体成形，中间利用导电柱作为抗静电线路与连接垫电性连接的通道，抗静电线路可以将导电材料利用电镀、化学镀或溅镀等方式形成于基板中，且抗静电线路可以与晶片接触，将不必要的静电经由连接垫引导至接地，以利用此抗静电线路达到静电放电防护的功能，且因抗静电线路、导电柱直接与基板一体成形而整合于制程中，更可达到轻薄化封装结构并可简化封装制程，应用甚广。
底下凭借具体实施例配合所附的图式详加说明，当更容易了解本发明的目的、技术内容及其所达成的功效。
附图说明
图1为现有具有静电放电条的封装结构示意图。
图2为本发明具有一凹槽的封装结构立体示意图。
图3为本发明具有一凹槽的封装结构的结构剖视图。
图4为本发明具有二凹槽的封装结构立体示意图。
图5为本发明于基板上具有一开口的抗静电结构的实施例示意图。
图6为本发明于基板上具有二开口的抗静电结构的实施例示意图。
图7A为本发明具有梯形体导电柱的封装结构剖视图。
图7B为本发明具有倒梯形体导电柱的封装结构剖视图。
附图标记说明：10-基板；12-指纹辨识晶片；121主动面；14-焊线；16-静电放电条；18-封胶体；20-封装结构；22-基板；24-凹槽；26-导电柱；28-连接垫；30-抗静电线路；32-凹槽；34、36-开口。
具体实施方式
本发明系在基板的制作过程中同时将抗静电线路以及导电柱等结构设计整合在一起，以形成一体成形的具有抗静电结构的封装结构。
请参阅图2及图3所示，其是本发明具有一凹槽的封装结构立体示意图以及其结构剖视图，一具有抗静电结构的封装结构20包括有一基板22及其上环设的至少一抗静电线路30，基板22上表面具有一体成形的至少一凹槽24，在此系以一个凹槽24为例，凹槽24内底面更可设有复数导电垫(图中未示)，使凹槽24内可供安装至少一晶片(图中未示)并通过这些导电垫与基板22形成电性连接；在基板22上且位于凹槽24外围位置设有至少一导电柱26，在基板22下表面设有至少一连接垫，此对外的连接垫在此系以复数连接垫28为例，导电柱26可选择性的电性连接至基板22下表面的连接垫28，以作为对外接地；另，抗静电线路30是一封闭线路且为金属线路，抗静电线路30位于凹槽24周围的基板22上且外露于基板22，此抗静电线路30经由导电柱26电性连接至连接垫28，以通过导电柱26配合晶片的导电垫(图中未示)而结合在一起，利用抗静电线路30接触到晶片而将静电经导电柱26引导至作为接地的连接垫28，进而达到静电防护功能。其中图中所绘制的抗静电路线路30位于基板22上而未突出基板22表面，当然，若有不同设计考量，抗静电线路也可突出于基板，以可以接触到晶片表面为诉求，当不能以此为限。
承上，本发明使用的基板22系使用绝缘基板，较佳者可以使用陶瓷基板，例如高温共烧陶瓷(High-Temperature Co-fired Creamics，HTCC)基板或是低温共烧陶瓷基板(Low-Temperature Co-fired Creamics，LTCC)。因此，本发明使用的一体成形陶瓷基板时，在制作过程中就能将抗静电电路30、导电柱26等结构一同压合并烧结在一起，并形成具有一体成形凹槽24的基板22。
本发明于基板上除了可以具有一体成形的一凹槽外，更可因不同的电路设计而具有二个以上的凹槽设计。请参阅图4所示，本发明的封装结构20更可于基板22上直接设有一体成形的二凹槽24、32，以分别提供安装二种不同的晶片， 例如，当本发明的封装结构20系作为指纹感测辨识封装结构时，于凹槽24内系供安装一感测晶片，而于凹槽32内则供安装一发光晶片；其余结构则与第二图所示的实施例相同，故于此不再赘述。
再者，本发明于基板上环设的抗静电线路除了前述的连续状封闭线路设计之外，尚具有不同的实施态样，也即此抗静电线路30具有至少一开口，例如，图5所示，抗静电线路30具有一开口34，抑或是如图6所示，抗静电线路30具有二开口34、36，此种抗静电线路30则为不连续状线路设计，以提供封装设计不同的选择。
此外，本发明的导电柱结构设计可以依据需要抗静电的程度，进行结构上的调整，包含形状、数量、相对位置等关系，例如图7A所示，复数个具有上窄下宽的梯形体的导电柱26；如图7B所示，复数个具有上宽下窄的倒梯形体的导电柱26；抑或是其他未绘制出来的圆柱体、长方体或锥形体等的形状设计。
本发明提出的具有抗静电结构的封装结构，其是将抗静电线路、导电柱整合至基板中而为一体成形者，中间利用导电柱作为抗静电线路与连接垫电性连接的通道，抗静电线路可以将导电材料利用电镀、化学镀或溅镀等方式形成于基板中，且抗静电线路可以与晶片接触，将不必要的静电经由连接垫引导至接地，以利用此抗静电线路达到静电放电防护的功能，且因抗静电线路、导电柱直接与基板一体成形而整合于制程中，更可达到轻薄化封装结构并可简化封装制程，应用甚广。
以上所述的实施例仅是说明本发明的技术思想及特点，其目的在使熟悉此项技术者能够了解本发明的内容并据以实施，当不能以的限定本发明的专利范围，即大凡依本发明所揭示的精神所作的均等变化或修饰，仍应涵盖在本发明的保护范围内。

Claims (9)

  1. 一种具有抗静电结构的封装结构，其特征在于，包括：
    一基板，其上具有一体成形的至少一凹槽，且在该凹槽周围的该基板上设有至少一导电柱；
    至少一连接垫，位于该基板下表面且电性连接该至少一导电柱；以及
    至少一抗静电线路，其位于该凹槽周围的该基板上，该至少一抗静电线路经由该至少一导电柱电性连接该至少一连接垫。
  2. 根据权利要求1所述的具有抗静电结构的封装结构，其特征在于，该基板是绝缘基板。
  3. 根据权利要求2所述的具有抗静电结构的封装结构，其特征在于，该绝缘基板是陶瓷基板。
  4. 根据权利要求1所述的具有抗静电结构的封装结构，其特征在于，该至少一抗静电线路是一封闭线路。
  5. 根据权利要求1所述的具有抗静电结构的封装结构，其特征在于，该至少一抗静电线路具有至少一开口。
  6. 根据权利要求1所述的具有抗静电结构的封装结构，其特征在于，还包括至少一晶片，其安装于该基板的该至少一凹槽内，并与该基板形成电性连接，该至少一抗静电线路接触该晶片。
  7. 根据权利要求1所述的具有抗静电结构的封装结构，其特征在于，该至少一抗静电线路是金属线路。
  8. 根据权利要求1所述的具有抗静电结构的封装结构，其特征在于，该导电柱是梯形体、倒梯形体、圆柱体、长方体或者锥形体的形状。
  9. 根据权利要求1所述的具有抗静电结构的封装结构，其特征在于，该至少一抗静电线路突出该基板表面。
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