WO2018103500A1 - 串行脉冲产生电路及充电装置 - Google Patents

串行脉冲产生电路及充电装置 Download PDF

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Publication number
WO2018103500A1
WO2018103500A1 PCT/CN2017/110499 CN2017110499W WO2018103500A1 WO 2018103500 A1 WO2018103500 A1 WO 2018103500A1 CN 2017110499 W CN2017110499 W CN 2017110499W WO 2018103500 A1 WO2018103500 A1 WO 2018103500A1
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Prior art keywords
signal
pulse
serial
unit
pulse width
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PCT/CN2017/110499
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English (en)
French (fr)
Inventor
王文情
蒋幸福
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比亚迪股份有限公司
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Publication of WO2018103500A1 publication Critical patent/WO2018103500A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/00711—Regulation of charging or discharging current or voltage with introduction of pulses during the charging process
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/02—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from ac mains by converters
    • H02J7/04—Regulation of charging current or voltage

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a serial pulse generating circuit and a charging device having the same.
  • the secondary chip of the charging device issues a corresponding serial pulse sequence combination according to the request voltage signal, and is supplied to the main edge chip through the optocoupler, so that the main edge chip controls the charging device to output a corresponding request voltage.
  • the serial pulse generating circuit of the related art charges and discharges the capacitor C1' by the current sources I1' and I2' to generate a pulse and a frequency period of a corresponding width by adjusting the magnitude of the charge and discharge current.
  • the related art has a disadvantage in that the accuracy of the frequency period and the pulse width of the output of the serial pulse generating circuit is low due to the limited accuracy of the capacitance and the current source. Moreover, if a pulse output of a hundred ⁇ s level is to be output, in order to increase the area of the capacitor too much, it is necessary to set the charge and discharge current to a small magnitude, further reducing the output accuracy.
  • the present invention aims to solve at least one of the technical problems in the related art to some extent. Accordingly, it is an object of the present invention to provide a serial pulse generating circuit that can output a high precision serial pulse signal.
  • Another object of the present invention is to provide a charging device.
  • an embodiment of the first aspect of the present invention provides a serial pulse generating circuit, including: a receiving end, the receiving end is configured to receive a request voltage signal output by a device to be charged; and a parallel conversion module, a parallel conversion module is connected to the receiving end, and the parallel conversion module is configured to generate an N parallel digital signal corresponding to the request voltage according to the request voltage signal; a serial pulse generating module, the serial pulse generating module Connected to the parallel conversion module, the serial pulse generation module is configured to divide a clock signal according to a state of each digital signal to generate a pulse signal corresponding to a pulse width, and control corresponding to the N parallel digital signals.
  • the pulse signals are sequentially output to output a serial pulse signal corresponding to the request voltage signal.
  • the receiving end receives the request voltage signal output by the charging device, and the parallel conversion module generates N parallel digital signals corresponding to the request voltage signal according to the request voltage signal, and the serial pulse generating module
  • the clock signal is divided according to the state of each digital signal to generate a pulse signal corresponding to the pulse width, and the pulse signals corresponding to the N parallel digital signals are sequentially outputted, thereby outputting a serial pulse signal corresponding to the requested voltage signal. Therefore, the serial pulse generating circuit of the embodiment of the present invention generates a serial pulse signal corresponding to the request voltage signal by using the high-precision clock signal, thereby improving the time precision of the signal output and effectively reducing the chip area.
  • the serial pulse generating module includes: a counting unit, the counting unit And configured to count the number of outputs of the N parallel digital signals to generate a count signal; a pulse width control signal generating unit, wherein the pulse width control signal generating unit is respectively connected to the counting unit and the parallel conversion module, The pulse width control signal generating unit is configured to control, according to the counting signal, the N parallel digital signals to be sequentially output; the frequency dividing unit, wherein the frequency dividing unit is connected to the pulse width control signal generating unit, and the frequency dividing unit The unit is configured to divide the clock signal according to the state of each digital signal to generate a pulse signal corresponding to the pulse width.
  • the frequency dividing unit comprises: a clock signal generator, the clock signal generator is configured to generate a clock signal; a first frequency divider, the first frequency divider and the clock signal are generated Connected to the first frequency divider for dividing the clock signal to generate a pulse signal of a first pulse width; a second frequency divider for the first frequency division
  • the clock signal is divided when the device is shielded to generate a pulse signal of a first pulse width, and the pulse signal of the first pulse width is divided by the first frequency divider to participate in frequency division to generate a second pulse width pulse signal; a logic control subunit, the logic control subunit and the pulse width control signal generating unit, the clock signal generator, the first frequency divider, and the second point, respectively
  • the frequency converters are connected, and the logic control subunit is configured to control the first frequency divider to participate in frequency division or be shielded according to the state of each digital signal.
  • the logic control subunit includes: a NOT gate, the input end of the NOT gate is connected to the pulse width control signal generating unit; a first NAND gate, the first NAND gate The first input end is connected to the output end of the NOT gate, the second input end of the first NAND gate is connected to the clock signal generator; the second NAND gate, the second NAND gate a first input end is connected to the pulse width control signal generating unit, a second input end of the second NAND gate is connected to the first frequency divider; a third NAND gate, the third NAND gate The first input end is connected to the output end of the first NAND gate, and the second input end of the third NAND gate is connected to the output end of the second NAND gate, the third NAND gate The output is connected to the second frequency divider.
  • the second pulse width may be an integer multiple of the first pulse width.
  • the serial pulse generating module further includes: a trigger, the first end of the flip-flop is respectively connected to the counting unit and the counting unit, and the second end of the trigger Connected to the frequency dividing unit, the third end of the trigger is configured to receive a trigger signal, and the trigger enables the counting unit and the minute after receiving the trigger signal by the third end Frequency unit.
  • the parallel conversion module includes: a determining unit, the determining unit is configured to determine a voltage level at which the request voltage signal is located; and a decoding unit, the decoding unit is connected to the determining unit, The decoding unit is configured to generate a voltage state signal according to a voltage level at which the request voltage signal is located; a parallel encoding unit, the parallel encoding unit is connected to the decoding unit, and the parallel encoding unit is configured to be according to the voltage state
  • the signal generates N parallel digital signals corresponding to the requested voltage signal.
  • the device to be charged may be a mobile phone or a tablet computer.
  • an embodiment of the second aspect of the present invention provides a charging apparatus including: a secondary chip including a serial pulse generating circuit according to an embodiment of the first aspect of the present invention, said The level chip is configured to generate a serial pulse signal corresponding to the request voltage signal according to the request voltage signal; a master chip, The main edge chip is configured to adjust a voltage output of the main side chip according to the serial pulse signal.
  • the secondary chip generates a serial pulse signal corresponding to the request voltage signal by the serial pulse generating circuit of the above embodiment, and further, the master chip adjusts the main edge chip according to the serial pulse signal. Voltage output. Therefore, the charging device of the embodiment of the present invention generates a serial pulse signal corresponding to the request voltage signal by using the high-precision clock signal, thereby improving the time precision of the signal output and effectively adjusting the voltage output.
  • the charging device is configured to charge a device to be charged, wherein the device to be charged may be a mobile phone or a tablet.
  • FIG. 1 is a circuit diagram of a serial pulse generating circuit in the related art.
  • FIG. 2 is a block schematic diagram of a serial pulse generating circuit in accordance with an embodiment of the present invention.
  • Figure 3a is a block schematic diagram of a serial pulse generation circuit in accordance with one embodiment of the present invention.
  • Figure 3b is a circuit diagram of a serial pulse generating circuit in accordance with another embodiment of the present invention.
  • FIG. 4 is a circuit schematic diagram of a serial pulse generating circuit in accordance with one embodiment of the present invention.
  • Figure 5 is a block schematic diagram of a serial pulse generating circuit in accordance with another embodiment of the present invention.
  • FIG. 6 is a waveform diagram of input and output signals of a serial pulse generating circuit according to an embodiment of the present invention.
  • FIG. 7 is a block schematic diagram of a charging device in accordance with an embodiment of the present invention.
  • FIG. 8 is a circuit diagram of a charging device in accordance with one embodiment of the present invention.
  • a receiving end 10 a parallel conversion module 20 and a serial pulse generating module 30;
  • a determining unit 201 a decoding unit 202, and a parallel encoding unit 203;
  • Counting unit 301 pulse width control signal generating unit 302, frequency dividing unit 303, flip-flop 304 and MCG module 305;
  • Secondary chip 100 serial pulse generating circuit 101 and main edge chip 200;
  • the serial pulse generating circuit includes a receiving end 10, a parallel conversion module 20, and a serial pulse generating module 30.
  • the receiving end 10 is configured to receive a request voltage signal output by the device to be charged; and the parallel conversion module 20 is connected The receiving end 10 is connected, and the parallel conversion module 20 is configured to generate N parallel digital signals corresponding to the request voltage signal according to the request voltage signal; the serial pulse generating module 30 is connected to the parallel converting module 20, and the serial pulse generating module 30 is configured to The state of each digital signal divides the clock signal to generate a pulse signal corresponding to the pulse width, and controls the pulse signals corresponding to the N parallel digital signals to be sequentially output to output a serial pulse signal SSO corresponding to the requested voltage signal (Serial) Signal Output, serial signal output).
  • the receiving end 10 of the serial pulse generating circuit can be connected to the voltage request ports D+ and D- of the device to be charged, and the receiving end 10 respectively detects the voltages of the voltage request ports D+ and D- to obtain The request voltage signal output by the device to be charged, wherein the serial pulse signal SSO corresponding to the different request voltage signals is different, and the charging device adjusts the voltage output according to the serial pulse signal SSO to meet the voltage requirement of the device to be charged.
  • the parallel conversion module 20 determines the request voltage signal received by the receiving end 10, and generates N parallel digital signals A0 to A(N-1) corresponding to the request voltage signal, where N is an integer greater than 1.
  • Each of the digital signals has a different high and low state, respectively, such that the serial pulse generating module 30 divides the clock signal according to the level state of each digital signal to generate a pulse signal corresponding to the pulse width, for example, if the number The signal A0 is in a low state, and the serial pulse generating module 30 generates a pulse signal of a first pulse width; if the digital signal A0 is in a high state, the serial pulse generating module 30 generates a pulse signal of a second pulse width.
  • the serial pulse generating module 30 controls the pulse signals corresponding to the N parallel digital signals to be sequentially output, wherein the pulse signals of different pulse widths correspond to different digital levels, for example, the pulse signal of the first pulse width corresponds to “0”, The pulse signal of the two pulse width corresponds to "1", so that serial conversion of the N parallel digital signals A0 to A(N-1) can be realized to output the serial pulse signal SSO corresponding to the requested voltage signal, and further the charging device The voltage output is adjusted according to the serial pulse signal SSO.
  • the parallel conversion module 20 includes a determination unit 201, a decoding unit 202, and a parallel encoding unit 203.
  • the determining unit 201 is configured to determine the voltage level at which the request voltage signal is located; the decoding unit 202 is connected to the determining unit 201, and the decoding unit 202 is configured to generate a voltage state signal according to the voltage level at which the voltage signal is requested; the parallel encoding unit 203 and The decoding unit 202 is connected, and the parallel encoding unit 203 is configured to generate N parallel digital signals A0 to A(N-1) corresponding to the request voltage signal according to the voltage state signal.
  • the receiving end 10 detects the voltages of the voltage request ports D+ and D- to obtain the request voltage signals (for example, 3.3V, 0.6V, and 0V) output by the device to be charged, and the determining unit 201 may include a plurality of comparators, and the determining unit After receiving the request voltage signal output by the device to be charged, the 201 determines the voltage level at which the request voltage signal is located, wherein the determination result can be represented by a combination of level states of D+H, D+L, DH, and DL, and The determination result is output to the decoding unit 202, and the decoding unit 202 generates corresponding voltage state signals, such as V5, V9, V12, and the like, according to the determination result.
  • the determining unit 201 may include a plurality of comparators, and the determining unit After receiving the request voltage signal output by the device to be charged, the 201 determines the voltage level at which the request voltage signal is located, wherein the determination result can be represented by a combination of level states of D
  • the parallel encoding unit 203 receives the voltage state signal, converts the voltage state signal into N parallel digital signals A0 to A(N-1), and outputs N parallel digital signals A0 to A(N-1) to serial pulse generation. Module 30.
  • the different level state combinations of the N parallel digital signals A0 to A(N-1) correspond to different voltage state signals.
  • the voltage state generated by the decoding unit 202 is determined according to the charging protocol Q2.0.
  • the correspondence between the signal and the request voltage signal can be as shown in Table 1 below:
  • the voltage state signal generated by the decoding unit 202 is V9, and the serial pulse generating module 30 outputs and requests the voltage.
  • the serial pulse signal SSO corresponding to the signal the charging device adjusts the voltage output according to the serial pulse signal SSO to 9V; when the voltage of the voltage request port D+ is 0.6V, and the voltage of the voltage request port D- is 0V, the decoding unit 202 generates The voltage state signal is V5, and the serial pulse generating module 30 outputs a serial pulse signal SSO corresponding to the request voltage signal, and the charging device adjusts the voltage output to 5V according to the serial pulse signal SSO.
  • the serial pulse generating circuit further includes a switch assembly 50 connected between the receiving end 10 and the parallel conversion module 20.
  • the USB BC1.2 detection is performed at the moment when the serial pulse generating circuit is powered on, and the voltage request port D+ and the voltage request port D-short connection are connected in the initial state, and the voltage request port D- is disconnected from the ground resistance. At the same time, the voltage of the voltage request port D+ is detected. When the voltage of the voltage request port D+ reaches a preset voltage value, for example, 0.6V, and the duration exceeds a preset time, for example, 1s, the control voltage requests the port D+ and the voltage request port.
  • a preset voltage value for example, 0.6V
  • a preset time for example, 1s
  • D- disconnects the short-circuit connection, and controls the voltage request port D- to be connected to the ground resistance, thereby determining the charging protocol, that is, detecting the voltages of the voltage request ports D+ and D- to obtain the request voltage signal output by the device to be charged.
  • the serial pulse generating circuit further includes: a power detecting unit 40, wherein the power detecting unit 40 is connected to the preset power source VDD, and the power detecting unit 40 is configured to detect the serial pulse. Whether the preset power supply VDD of the generating circuit is faulty, and controlling the serial pulse generating circuit to stop outputting the serial pulse signal SSO when the preset power supply VDD fails.
  • the serial pulse generating module 30 includes a counting unit 301, a pulse width control signal generating unit 302, and a frequency dividing unit 303.
  • the counting unit 301 is configured to count the number of outputs of the N parallel digital signals A0 to A(N-1) to generate a counting signal; the pulse width control signal generating unit 302 is connected to the counting unit 301 and the parallel conversion module 20, respectively.
  • the pulse width control signal generating unit 302 is configured to sequentially control the N parallel digital signals to be output according to the counting signal; the frequency dividing unit 303 is connected to the pulse width control signal generating unit 302, and the frequency dividing unit 303 is configured to perform state according to each digital signal.
  • the clock signal is divided to generate a pulse signal corresponding to the pulse width.
  • the serial pulse generating module 30 further includes a flip-flop 304.
  • the first end of the flip-flop 304 is connected to the counting unit 301, and the second end of the flip-flop 304 and the counting unit
  • the 301 and the frequency dividing unit 303 are respectively connected, the third end of the flip-flop 304 is for receiving a trigger signal, and the trigger 304 is passing through the third end.
  • the counting unit 301 and the frequency dividing unit 303 are enabled after receiving the trigger signal.
  • the third end of the flip-flop 304 can be connected to an MCG (Multipurpose Clock Generator) module 305, and the MCG module 305 is configured to output a trigger signal to the trigger. 304.
  • MCG Multipurpose Clock Generator
  • the MCG module 305 outputs a trigger signal (for example, a mode state).
  • the pulse signal is changed to the flip-flop 304, and the second end of the flip-flop 304 outputs a high level to enable the counting unit 301 and the frequency dividing unit 303.
  • the flip flop 304 can be an RS flip flop.
  • the reset end of the RS flip-flop is connected to the counting unit 301 as a first end to receive the PE signal (ie, the reset signal) output by the counting unit 301, and the output end of the RS flip-flop serves as the second end and the counting unit 301 and the frequency dividing unit 303.
  • the set end of the RS flip-flop is used as the third end for receiving the trigger signal.
  • the serial pulse generation module 30 can convert the N parallel digital signals A0 to A(N-1) into serial pulse signals corresponding to the requested voltage signals.
  • the signals A0 to A(N-1) are sequentially outputted to obtain a corresponding pulse width control signal PWct, and the pulse width control signal PWct is output to the frequency dividing unit 303. Further, the frequency dividing unit 303 divides the clock signal according to the state of each digital signal to generate a pulse signal corresponding to the pulse width.
  • the pulse signal may be a positive pulse (such as SSO-1 in Figure 6) or a negative pulse (such as SSO-2 in Figure 6).
  • the wide control signal generating unit 302 can sequentially output the N parallel digital signals A0 to A(N-1) according to the correspondence relationship of Table 2 to obtain a corresponding pulse width control signal PWct.
  • the pulse width control signal generating unit 302 can sequentially output the N parallel digital signals A0 to A(N-1) according to the corresponding system of Table 3 to obtain a corresponding pulse width control signal PWct.
  • the count signal B2B1B0 "001"
  • the counting signal B2B1B0 "111"
  • the PE signal (ie, the reset signal) output by the counting unit 301 is at a high level.
  • the reset terminal of the RS flip-flop receives a high level, so that the RS flip-flop outputs a low level to control the counting unit 301 to stop counting, and
  • the control frequency dividing unit 303 stops generating the pulse signal.
  • the frequency dividing unit 303 includes a clock signal generator 310, a first frequency divider 320, a second frequency divider 330, and a logic control sub-unit 340.
  • the clock signal generator 310 is configured to generate a clock signal; the first frequency divider 320 is coupled to the clock signal generator 310, and the first frequency divider 320 is configured to divide the clock signal to generate a pulse signal of a first pulse width.
  • the second frequency divider 330 is configured to divide the clock signal when the first frequency divider 320 is shielded to generate a pulse signal of a first pulse width, and to first when the first frequency divider 320 participates in frequency division.
  • the pulse width pulse signal is divided to generate a pulse signal of a second pulse width; the logic control sub-unit 340 and the pulse width control signal generating unit 302, the clock signal generator 310, the first frequency divider 320, and the second frequency dividing, respectively
  • the controller 330 is connected, and the logic control sub-unit 340 is configured to control the first frequency divider 320 to participate in frequency division or be masked according to the state of each digital signal.
  • the logic control subunit 340 includes: a NOT gate 341, a first NAND gate 342, a second NAND gate 343, and a third NAND gate 344, wherein the NOT gate The input end of the 341 is connected to the pulse width control signal generating unit 302; the first input end of the first NAND gate 342 is connected to the output end of the NOT gate 341, and the second input end of the first NAND gate 342 and the clock signal generator 310 is connected; the first input terminal of the second NAND gate 343 is connected to the pulse width control signal generating unit 302, and the second input terminal of the second NAND gate 343 is connected to the first frequency divider 320; the third NAND gate 344 The first input end is connected to the output end of the first NAND gate 342, the second input end of the third NAND gate 344 is connected to the output end of the second NAND gate 343, and the output end of the third NAND gate 344 is The second frequency divider 330 is connected.
  • the clock signal generator 310 may include a clock divider for dividing the high-precision clock signal CLK, and outputting a clock signal of a corresponding frequency, that is, a preset clock signal PUL, and pulse width control.
  • the signal generating unit 302 sequentially controls the N-way parallel digital signals A0 to A(N-1) to be output in accordance with the count signals B0 to Bm.
  • the pulse width control signal generating unit 302 when the digital signal output by the pulse width control signal generating unit 302 is at a high level (ie, the pulse width control signal PWct is at a high level), the NOT gate 341 outputs a low level, and the first NAND gate 342 is pre- The low level of the output of the clock signal PUL and the NOT gate 341 is logically processed to output a high level, and at the same time, the first frequency divider 320 participates in the frequency division to generate a pulse signal of the first pulse width, according to the logic of the NAND gate.
  • the logic control sub-unit 340 logically processes the pulse signal of the first pulse width to generate a first output signal, the first output signal is consistent with the pulse signal of the first pulse width, and the second frequency divider 330 is An output signal is frequency-divided to generate a pulse signal of a second pulse width.
  • the digital signal output from the pulse width control signal generating unit 302 is at a low level, the NOT gate 341 outputs a high level, and the enable terminal of the first frequency divider 320 receives a low level, so the first frequency divider 320 is shielded.
  • the second NAND gate 343 outputs a high level.
  • the logic control sub-unit 340 performs logic processing on the preset clock signal PUL to generate a second output signal, and the second output signal and the preset The clock signal PUL remains consistent, and the second frequency divider 330 divides the second output signal to generate a pulse signal of a first pulse width.
  • the second pulse width may be an integer multiple of the first pulse width.
  • the second pulse width may be twice the width of the first pulse.
  • the second frequency divider 330 can output the serial pulse signal SSO-1, wherein The pulse signal SSO-1 is a positive pulse; when the pulse width control signal generating unit 302 sequentially controls the N parallel digital signals A0 to A(N-1) according to the correspondence shown in Table 3, the second frequency divider 330
  • the serial pulse signal SSO-2 can be output, wherein the pulse signal SSO-2 is a negative pulse.
  • the frequency dividing unit 303 can divide the clock signal according to the state of each digital signal to generate a pulse signal corresponding to the pulse width (for example, the serial pulse signal SSO-1 or SSO-2), and the pulse signals of different pulse widths correspond to each other.
  • the pulse signal of the first pulse width corresponds to "0”
  • the pulse signal of the second pulse width corresponds to "1”.
  • the serial pulse signal sequence shown in FIG. 6 is "110101", so that serial conversion of N parallel digital signals A0 to A(N-1) can be realized to output a serial pulse signal corresponding to the requested voltage.
  • the SSO and in turn, the charging device adjusts the voltage output based on the serial pulse signal SSO.
  • the device to be charged may be a mobile phone or a tablet.
  • the serial pulse generating circuit receives the request voltage output by the charging device through the receiving end, and the parallel conversion module generates N parallel digital signals corresponding to the request voltage signal according to the request voltage signal, and the serial pulse The generating module divides the clock signal according to the state of each digital signal to generate a pulse signal corresponding to the pulse width, and controls the pulse signals corresponding to the N parallel digital signals to be sequentially output, thereby outputting a serial pulse corresponding to the requested voltage signal. signal. Therefore, the serial pulse generating circuit of the embodiment of the present invention generates a serial pulse signal corresponding to the request voltage signal by using the high-precision clock signal, thereby improving the time precision of the signal output and effectively reducing the chip area.
  • FIG. 7 is a block schematic diagram of a charging apparatus according to an embodiment of the present invention.
  • the charging device 300 includes a secondary chip 100 and a main chip 200, wherein the secondary chip 100 includes a serial pulse generating circuit 101 for generating and requesting a voltage according to a request voltage signal.
  • the serial pulse signal SSO corresponding to the signal; the master chip 200 is used to adjust the voltage output of the master chip according to the serial pulse signal SSO.
  • serial pulse generating circuit of the embodiment of the present invention can be applied to various charging protocols, and generates a corresponding serial pulse signal SSO according to the request voltage signal of the device to be charged according to the requirements of the charging protocol.
  • the charging protocol includes, but is not limited to, QC (Quick Charge) 2.0, QC 3.0, FCP (Fast Charger Protocol) and the like.
  • the parallel conversion module is further configured to generate, according to the charging protocol, an N parallel digital signal corresponding to the requested voltage signal according to the request voltage signal;
  • the serial pulse generating module is further configured to perform charging according to the The protocol outputs a serial pulse signal corresponding to the request voltage signal.
  • the voltage output in the charging protocol QC3.0 has a large adjustment level
  • the serial pulse signal SSO can be used for signal transmission.
  • pulses of different pulse widths are used.
  • the signals correspond to different digital levels, for example, the pulse signal of the first pulse width corresponds to “0”, the first The pulse signal of the two pulse width corresponds to "1", so that different request voltage signals can correspond to different pulse signals.
  • the serial pulse signal SSO requires higher precision to ensure that the main chip 200 can detect and decode the serial pulse signal SSO output by the secondary chip 100, thereby adjusting the main edge chip. Voltage output.
  • FIG. 8 is a circuit diagram of a charging device in accordance with one embodiment of the present invention.
  • the serial pulse generating circuit 101 is connected to the voltage request ports D+ and D- of the device to be charged to acquire a request voltage signal output from the device to be charged, and outputs a serial corresponding to the request voltage signal according to the request voltage signal.
  • the pulse signal SSO wherein the serial pulse signals SSO corresponding to different request voltage signals are different.
  • the serial pulse signal SSO outputted by the secondary chip 100 can be output to the main-side chip 200 through the optocoupler chip IC of the charging device 300, and the main-side chip 200 decodes the received signal and controls the switch according to the decoding result.
  • the tube Q is turned on or off to adjust the voltage output of the main-side chip, that is, to adjust the output voltages across Vout+ and Vout-.
  • the charging device is used to charge the device to be charged, wherein the device to be charged may be a mobile phone or a tablet computer.
  • the secondary chip generates a serial pulse signal corresponding to the requested voltage signal by the serial pulse generating circuit of the above embodiment, and further, the master chip adjusts the main signal according to the serial pulse signal.
  • the voltage output of the edge chip Therefore, the charging device of the embodiment of the present invention generates a serial pulse signal corresponding to the request voltage signal by using the high-precision clock signal, thereby improving the time precision of the signal output and effectively adjusting the voltage output.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include at least one of the features, either explicitly or implicitly.
  • the meaning of "a plurality” is at least two, such as two, three, etc., unless specifically defined otherwise.
  • the terms “installation”, “connected”, “connected”, “fixed” and the like shall be understood broadly, and may be either a fixed connection or a detachable connection, unless explicitly stated and defined otherwise. , or integrated; can be mechanical or electrical connection; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction of two elements, unless otherwise specified Limited.
  • the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.
  • the first feature "on” or “under” the second feature may be a direct contact of the first and second features, or the first and second features may be indirectly through an intermediate medium, unless otherwise explicitly stated and defined. contact.
  • the first A feature “above”, “above” and “above” the second feature may be that the first feature is directly above or above the second feature, or merely that the first feature level is higher than the second feature.
  • the first feature “below”, “below” and “below” the second feature may be that the first feature is directly below or obliquely below the second feature, or merely that the first feature level is less than the second feature.

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Abstract

本发明公开了一种串行脉冲产生电路及充电装置，该电路包括：接收端，其用于接收待充电设备输出的请求电压信号；并行转换模块，其与接收端相连，并行转换模块用于根据请求电压信号生成与请求电压信号对应的N路并行数字信号；串行脉冲生成模块，其与并行转换模块相连，串行脉冲生成模块用于根据每路数字信号的状态对时钟信号进行分频以生成对应脉冲宽度的脉冲信号，并控制N路并行数字信号对应的脉冲信号依次输出以输出与请求电压信号对应的串行脉冲信号。由此，本发明实施例的串行脉冲产生电路利用高精度时钟信号生成与请求电压信号对应的串行脉冲信号，提升了信号输出的时间精度，且有效减小了芯片面积。

Description

串行脉冲产生电路及充电装置 技术领域
本发明涉及通信技术领域，特别涉及一种串行脉冲产生电路和一种具有该电路的充电装置。
背景技术
在相关技术中，充电装置的次级芯片根据请求电压信号发出相应的串行脉冲序列组合，并通过光耦提供给主边芯片，以使主边芯片控制充电装置输出相应的请求电压。如图1所示，相关技术中的串行脉冲产生电路采用电流源I1’和I2’对电容C1’进行充放电，以通过调节充放电电流的大小产生相应宽度的脉冲与频率周期。
但是，相关技术存在的缺点是，由于电容和电流源的精度有限，导致串行脉冲产生电路输出的频率周期与脉冲宽度的精度较低。并且，如果要输出百μs级的脉冲输出，为了不过多增大电容的面积，需要将充放电电流设置在很小的量级，进一步降低了输出精度。
因此，相关技术需要进行改进。
发明内容
本发明旨在至少在一定程度上解决相关技术中的技术问题之一。为此，本发明的一个目的在于提出一种串行脉冲产生电路，该电路可输出高精度的串行脉冲信号。
本发明的另一个目的在于提出一种充电装置。
为达到上述目的，本发明第一方面的实施例提出了一种串行脉冲产生电路，包括：接收端，所述接收端用于接收待充电设备输出的请求电压信号；并行转换模块，所述并行转换模块与所述接收端相连，所述并行转换模块用于根据所述请求电压信号生成与所述请求电压对应的N路并行数字信号；串行脉冲生成模块，所述串行脉冲生成模块与所述并行转换模块相连，所述串行脉冲生成模块用于根据每路数字信号的状态对时钟信号进行分频以生成对应脉冲宽度的脉冲信号，并控制所述N路并行数字信号对应的脉冲信号依次输出以输出与所述请求电压信号对应的串行脉冲信号。
根据本发明实施例提出的串行脉冲产生电路，通过接收端接收充电设备输出的请求电压信号，并行转换模块根据请求电压信号生成与请求电压信号对应的N路并行数字信号，串行脉冲生成模块根据每路数字信号的状态对时钟信号进行分频，以生成对应脉冲宽度的脉冲信号，并控制N路并行数字信号对应的脉冲信号依次输出，从而输出与请求电压信号对应的串行脉冲信号。由此，本发明实施例的串行脉冲产生电路利用高精度时钟信号生成与请求电压信号对应的串行脉冲信号，提升了信号输出的时间精度，且有效减小了芯片面积。
根据本发明的一个实施例，所述串行脉冲生成模块包括：计数单元，所述计数单元 用于对所述N路并行数字信号的输出个数进行计数以生成计数信号；脉宽控制信号产生单元，所述脉宽控制信号产生单元分别与所述计数单元和所述并行转换模块相连，所述脉宽控制信号产生单元用于根据所述计数信号控制所述N路并行数字信号依次输出；分频单元，所述分频单元与所述脉宽控制信号产生单元相连，所述分频单元用于根据每路数字信号的状态对时钟信号进行分频以生成对应脉冲宽度的脉冲信号。
根据本发明的一个实施例，所述分频单元包括：时钟信号产生器，所述时钟信号产生器用于产生时钟信号；第一分频器，所述第一分频器与所述时钟信号产生器相连，所述第一分频器用于对所述时钟信号进行分频以生成第一脉冲宽度的脉冲信号；第二分频器，所述第二分频器用于在所述第一分频器被屏蔽时对所述时钟信号进行分频以生成第一脉冲宽度的脉冲信号，以及在所述第一分频器参与分频时对所述第一脉冲宽度的脉冲信号进行分频以生成第二脉冲宽度的脉冲信号；逻辑控制子单元，所述逻辑控制子单元分别与所述脉宽控制信号产生单元、所述时钟信号产生器、所述第一分频器和所述第二分频器相连，所述逻辑控制子单元用于根据每路数字信号的状态控制所述第一分频器参与分频或被屏蔽。
根据本发明的一个实施例，所述逻辑控制子单元包括：非门，所述非门的输入端与所述脉宽控制信号产生单元相连；第一与非门，所述第一与非门的第一输入端与所述非门的输出端相连，所述第一与非门的第二输入端与所述时钟信号产生器相连；第二与非门，所述第二与非门的第一输入端与所述脉宽控制信号产生单元相连，所述第二与非门的第二输入端与所述第一分频器相连；第三与非门，所述第三与非门的第一输入端与所述第一与非门的输出端相连，所述第三与非门的第二输入端与所述第二与非门的输出端相连，所述第三与非门的输出端与所述第二分频器相连。
根据本发明的一个具体实施例，所述第二脉冲宽度可为所述第一脉冲宽度的整数倍。
根据本发明的一个实施例，所述串行脉冲生成模块还包括：触发器，所述触发器的第一端与所述计数单元和所述计数单元分别相连，所述触发器的第二端与所述分频单元相连，所述触发器的第三端用于接收触发信号，所述触发器在通过所述第三端接收到所述触发信号后使能所述计数单元和所述分频单元。
根据本发明的一个实施例，所述并行转换模块包括：判断单元，所述判断单元用于判断所述请求电压信号所处的电压等级；解码单元，所述解码单元与所述判断单元相连，所述解码单元用于根据所述请求电压信号所处的电压等级生成电压状态信号；并行编码单元，所述并行编码单元与所述解码单元相连，所述并行编码单元用于根据所述电压状态信号生成与所述请求电压信号对应的N路并行数字信号。
根据本发明的一个具体实施例，所述待充电设备可为手机或平板电脑。
为达到上述目的，本发明第二方面的实施例提出了一种充电装置，包括：次级芯片，所述次级芯片包括根据本发明第一方面实施例的串行脉冲产生电路，所述次级芯片用于根据所述请求电压信号生成与所述请求电压信号对应的串行脉冲信号；主边芯片，所述 主边芯片用于根据所述串行脉冲信号调整所述主边芯片的电压输出。
根据本发明实施例提出的充电装置，次级芯片通过上述实施例的串行脉冲产生电路生成与请求电压信号对应的串行脉冲信号，进而，主边芯片根据串行脉冲信号调整主边芯片的电压输出。由此，本发明实施例的充电装置利用高精度时钟信号生成与请求电压信号对应的串行脉冲信号，提升了信号输出的时间精度，有效调节电压输出。
根据本发明的一个实施例，所述充电装置用于为待充电设备进行充电，其中，所述待充电设备可为手机或平板电脑。
附图说明
图1是相关技术中的串行脉冲产生电路的电路示意图。
图2是根据本发明实施例的串行脉冲产生电路的方框示意图。
图3a是根据本发明一个实施例的串行脉冲产生电路的方框示意图。
图3b是根据本发明另一个实施例的串行脉冲产生电路的电路示意图。
图4是根据本发明一个实施例的串行脉冲产生电路的电路原理图。
图5是根据本发明另一个实施例的串行脉冲产生电路的方框示意图。
图6是根据本发明一个实施例的串行脉冲产生电路的输入输出信号的波形示意图。
图7是根据本发明实施例的充电装置的方框示意图。
图8是根据本发明一个实施例的充电装置的电路示意图。
附图标记：
接收端10、并行转换模块20和串行脉冲生成模块30；
判断单元201、解码单元202和并行编码单元203；
计数单元301、脉宽控制信号产生单元302、分频单元303、触发器304和MCG模块305；
时钟信号产生器310、第一分频器320、第二分频器330和逻辑控制子单元340；非门341、第一与非门342、第二与非门343和第三与非门344；
次级芯片100、串行脉冲产生电路101和主边芯片200；
开关管Q和光耦芯片IC。
具体实施方式
下面详细描述本发明的实施例，实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本发明，而不能理解为对本发明的限制。
下面参考附图来描述本发明实施例提出的串行脉冲产生电路及具有其的充电装置。
图2是根据本发明实施例的串行脉冲产生电路的方框示意图。如图2所示，该串行脉冲产生电路包括：接收端10、并行转换模块20和串行脉冲生成模块30。
其中，接收端10用于接收待充电设备输出的请求电压信号；并行转换模块20与接 收端10相连，并行转换模块20用于根据请求电压信号生成与请求电压信号对应的N路并行数字信号；串行脉冲生成模块30与并行转换模块20相连，串行脉冲生成模块30用于根据各路数字信号的状态对时钟信号进行分频以生成对应脉冲宽度的脉冲信号，并控制N路并行数字信号对应的脉冲信号依次输出，以输出与请求电压信号对应的串行脉冲信号SSO(Serial Signal Output，串行信号输出)。
具体来说，如图2所示，串行脉冲产生电路的接收端10可与待充电设备的电压请求端口D+和D-相连，接收端10分别检测电压请求端口D+和D-的电压以获取待充电设备输出的请求电压信号，其中，不同的请求电压信号对应的串行脉冲信号SSO不同，进而充电装置根据串行脉冲信号SSO调整电压输出以满足待充电设备的电压需求。
进一步地，并行转换模块20对接收端10接收到的请求电压信号进行判断，并生成与请求电压信号对应的N路并行数字信号A0至A(N-1)，其中，N为大于1的整数，每路数字信号分别具有不同的高低电平状态，这样，串行脉冲生成模块30根据每路数字信号的电平状态对时钟信号进行分频以生成对应脉冲宽度的脉冲信号，例如，如果数字信号A0为低电平状态，串行脉冲生成模块30则生成第一脉冲宽度的脉冲信号；如果数字信号A0为高电平状态，串行脉冲生成模块30则生成第二脉冲宽度的脉冲信号。
这样，串行脉冲生成模块30控制N路并行数字信号对应的脉冲信号依次输出，其中，不同脉冲宽度的脉冲信号对应不同的数字电平，例如第一脉冲宽度的脉冲信号对应“0”，第二脉冲宽度的脉冲信号对应“1”，从而可以实现对N路并行数字信号A0至A(N-1)的串行转换，以输出与请求电压信号对应的串行脉冲信号SSO，进而充电装置根据串行脉冲信号SSO调整电压输出。
根据本发明的一个实施例，如图3a所示，并行转换模块20包括：判断单元201、解码单元202和并行编码单元203。
其中，判断单元201用于判断请求电压信号所处的电压等级；解码单元202与判断单元201相连，解码单元202用于根据请求电压信号所处的电压等级生成电压状态信号；并行编码单元203与解码单元202相连，并行编码单元203用于根据电压状态信号生成与请求电压信号对应的N路并行数字信号A0至A(N-1)。
具体来说，接收端10检测电压请求端口D+和D-的电压以获取待充电设备输出的请求电压信号(例如3.3V、0.6V和0V)，判断单元201可包括多个比较器，判断单元201在接收到待充电设备输出的请求电压信号后，判断请求电压信号所处的电压等级，其中，判断结果可用D+H、D+L、D-H和D-L的电平状态组合进行表示，并将判断结果输出至解码单元202，解码单元202根据判断结果生成相应的电压状态信号，例如V5、V9和V12等。并行编码单元203接收电压状态信号，将电压状态信号转换为N路并行数字信号A0至A(N-1)，并将N路并行数字信号A0至A(N-1)输出至串行脉冲生成模块30。其中，N路并行数字信号A0至A(N-1)不同的电平状态组合对应不同的电压状态信号。
根据本发明的一个具体实施例，依据充电协议Q2.0，解码单元202生成的电压状态 信号与请求电压信号的对应关系可如下表1所示：
表1
D+端口的电压 D-端口的电压 电压状态信号
0.6V 0.6V V12(即12V)
3.3V 0.6V V9(即9V)
3.3V 3.3V 20V
0.6V 0V V 5(即5V)
由表1可知，当电压请求端口D+的电压为3.3V，且电压请求端口D-的电压为0.6V时，解码单元202生成的电压状态信号为V9，串行脉冲生成模块30输出与请求电压信号对应的串行脉冲信号SSO，充电装置根据串行脉冲信号SSO调整电压输出为9V；当电压请求端口D+的电压为0.6V，且电压请求端口D-的电压为0V时，解码单元202生成的电压状态信号为V5，串行脉冲生成模块30输出与请求电压信号对应的串行脉冲信号SSO，充电装置根据串行脉冲信号SSO调整电压输出为5V。
根据本发明的一个具体实施例，如图3b所示，串行脉冲产生电路还包括开关组件50，开关组件50连接在接收端10和并行转换模块20之间。在串行脉冲产生电路上电的瞬间先进行USB BC1.2检测，在初始状态下控制电压请求端口D+和电压请求端口D-短路连接，并控制电压请求端口D-与对地电阻断开连接，同时对电压请求端口D+的电压进行检测，当电压请求端口D+的电压达到预设电压值，例如0.6V，且持续时间超过预设时间，例如1s时，控制电压请求端口D+和电压请求端口D-断开短路连接，并控制电压请求端口D-与对地电阻连接，进而进行充电协议的判断，即检测电压请求端口D+和D-的电压以获取待充电设备输出的请求电压信号。
根据本发明的一个具体实施例，如图3b所示，串行脉冲产生电路还包括：电源检测单元40，其中电源检测单元40与预设电源VDD相连，电源检测单元40用于检测串行脉冲产生电路的预设电源VDD是否发生故障，并在预设电源VDD发生故障时控制串行脉冲产生电路停止输出串行脉冲信号SSO。
根据本发明的一个实施例，如图4所示，串行脉冲生成模块30包括：计数单元301、脉宽控制信号产生单元302和分频单元303。
其中，计数单元301用于对N路并行数字信号A0至A(N-1)的输出个数进行计数以生成计数信号；脉宽控制信号产生单元302分别与计数单元301和并行转换模块20相连，脉宽控制信号产生单元302用于根据计数信号控制N路并行数字信号依次输出；分频单元303与脉宽控制信号产生单元302相连，分频单元303用于根据每路数字信号的状态对时钟信号进行分频以生成对应脉冲宽度的脉冲信号。
根据本发明的一个实施例，如图4所示，串行脉冲生成模块30还包括：触发器304，触发器304的第一端与计数单元301相连，触发器304的第二端与计数单元301和分频单元303分别相连，触发器304的第三端用于接收触发信号，触发器304在通过第三端 接收到触发信号后使能计数单元301和分频单元303。
根据本发明的一个实施例，如图4所示，触发器304的第三端可与MCG(Multipurpose Clock Generator，多功能时钟发生器)模块305相连，MCG模块305用于输出触发信号至触发器304，当待充电设备输出的请求电压信号发生变化时，相应的N路并行数字信号A0至A(N-1)的电平状态发生改变，此时，MCG模块305输出触发信号(例如模式状态改变脉冲信号)至触发器304，触发器304的第二端输出高电平，以使能计数单元301和分频单元303。
根据本发明的一个具体实施例，触发器304可为RS触发器。RS触发器的复位端作为第一端与计数单元301相连，以接收计数单元301输出的PE信号(即复位信号)，RS触发器的输出端作为第二端与计数单元301和分频单元303分别相连，RS触发器的置位端作为第三端用于接收触发信号。
具体来说，串行脉冲生成模块30可将N路并行数字信号A0至A(N-1)转换为与请求电压信号对应的串行脉冲信号。在触发器304使能计数单元301和分频单元303开始工作后，计数单元301对N路并行数字信号A0至A(N-1)的输出脉冲个数进行计数，计数信号可用(m+1)位二进制数进行表示。例如，当m＝2时，计数信号可用B2B1B0进行表示，计数单元301每接收到一个脉冲信号，计数信号可用B2B1B0的计数值增加1，脉宽控制信号产生单元302根据计数信号控制N路并行数字信号A0至A(N-1)依次输出,以得到相应的脉宽控制信号PWct，并将脉宽控制信号PWct输出至分频单元303。进而，分频单元303根据每路数字信号的状态对时钟信号进行分频以生成对应脉冲宽度的脉冲信号。
根据本发明的一个实施例，脉冲信号可为正脉冲(如图6中的SSO-1)或者负脉冲(如图6中的SSO-2)。
根据本发明的一个实施例，假设共有6路并行输入信号A0至A5，计数单元301生成的计数信号可用B2B1B0进行表示，即m＝2，产生的串行脉冲信号为正脉冲，此时，脉宽控制信号产生单元302可按照表2的对应关系控制N路并行数字信号A0至A(N-1)依次输出,以得到相应的脉宽控制信号PWct。
表2
计数信号 脉宽控制信号PWct
计数信号B2B1B0＝“000” A0
计数信号B2B1B0＝“001” A1
计数信号B2B1B0＝“010” A2
计数信号B2B1B0＝“011” A3
计数信号B2B1B0＝“100” A4
计数信号B2B1B0＝“101” A5
计数信号B2B1B0＝“110” PWct＝0，PE＝1
由表2可知，在默认情况下，计数信号B2B1B0＝“000”，脉宽控制信号PWct为数字信号A0；第1个脉冲周期后，计数信号B2B1B0＝“001”，输出的脉宽控制信号PWct为数字信号A1；第2个脉冲信号后，计数信号B2B1B0＝“010”，输出的脉宽控制信号PWct为数字信号A2；第3个脉冲信号后，计数信号B2B1B0＝“011”，输出的脉宽控制信号PWct为数字信号A3；第4个脉冲信号后，计数信号B2B1B0＝“100”，输出的脉宽控制信号PWct为数字信号A4；第5个脉冲信号后，计数信号B2B1B0＝“101”，输出的脉宽控制信号PWct为数字信号A5。在串行脉冲生成模块30输出第6个脉冲信号后，计数信号B2B1B0＝“110”，计数单元301输出的PE信号为高电平，此时，RS触发器的复位端接收到高电平，从而RS触发器输出低电平，以控制计数单元301停止计数，并控制分频单元303停止生成脉冲信号。
根据本发明的另一个具体实施例，同样假设共有6路并行输入信号A0至A5，计数单元301生成的计数信号可用B2B1B0进行表示，即m＝2，产生的串行脉冲信号为负脉冲，此时，脉宽控制信号产生单元302可按照表3的对应系控制N路并行数字信号A0至A(N-1)依次输出,以得到相应的脉宽控制信号PWct。
表3
条件 输出的脉宽控制信号PWct
计数信号B2B1B0＝“000” “1”
计数信号B2B1B0≠“000”且SSO＝“1” “0”
计数信号B2B1B0＝“001”且SSO＝“0” A0
计数信号B2B1B0＝“010”且SSO＝“0” A1
计数信号B2B1B0＝“011”且SSO＝“0” A2
计数信号B2B1B0＝“100”且SSO＝“0” A3
计数信号B2B1B0＝“101”且SSO＝“0” A4
计数信号B2B1B0＝“110”且SSO＝“0” A5
计数信号B2B1B0＝“111” PWct＝0，PE＝1
由表3可知，当计数信号B2B1B0＝“000”时，输出的脉宽控制信号PWct为高电平，串行脉冲信号SSO输出高电平；当计数信号B2B1B0≠“000”且串行脉冲信号SSO为高电平时，输出的脉宽控制信号PWct为低电平。这样，在第1个脉冲周期后，计数信号B2B1B0＝“001”，输出的脉宽控制信号PWct为数字信号A0；第2个脉冲信号后，计数信号B2B1B0＝“010”，输出的脉宽控制信号PWct为数字信号A1；第3个脉冲信号后，计数信号B2B1B0＝“011”，输出的脉宽控制信号PWct为数字信号A2；第4个脉冲信号后，计数信号B2B1B0＝“100”，输出的脉宽控制信号PWct为数字信号A3；第5个脉冲信号后，计数信号B2B1B0＝“101”，输出的脉宽控制信号PWct为数字信号A4；在第6个脉冲信号后，计数信号B2B1B0＝“110”，输出的脉宽控制信号PWct为数字信号A5。在串行脉冲生成模块30输出第7个脉冲信号后，计数信号B2B1B0＝“111”， 计数单元301输出的PE信号(即复位信号)为高电平，此时，RS触发器的复位端接收到高电平，从而RS触发器输出低电平，以控制计数单元301停止计数，并控制分频单元303停止生成脉冲信号。
根据本发明的一个实施例，如图5所示，分频单元303包括：时钟信号产生器310、第一分频器320、第二分频器330和逻辑控制子单元340。
其中，时钟信号产生器310用于产生时钟信号；第一分频器320与时钟信号产生器310相连，第一分频器320用于对时钟信号进行分频以生成第一脉冲宽度的脉冲信号；第二分频器330用于在第一分频器320被屏蔽时对时钟信号进行分频以生成第一脉冲宽度的脉冲信号，以及在第一分频器320参与分频时对第一脉冲宽度的脉冲信号进行分频以生成第二脉冲宽度的脉冲信号；逻辑控制子单元340分别与脉宽控制信号产生单元302、时钟信号产生器310、第一分频器320和第二分频器330相连，逻辑控制子单元340用于根据每路数字信号的状态控制第一分频器320参与分频或被屏蔽。
根据本发明的一个实施例，如图5所示，逻辑控制子单元340包括：非门341、第一与非门342、第二与非门343和第三与非门344，其中，非门341的输入端与脉宽控制信号产生单元302相连；第一与非门342的第一输入端与非门341的输出端相连，第一与非门342的第二输入端与时钟信号产生器310相连；第二与非门343的第一输入端与脉宽控制信号产生单元302相连，第二与非门343的第二输入端与第一分频器320相连；第三与非门344的第一输入端与第一与非门342的输出端相连，第三与非门344的第二输入端与第二与非门343的输出端相连，第三与非门344的输出端与第二分频器330相连。
具体来说，时钟信号产生器310可包括时钟分频器，时钟分频器用于对高精度时钟信号CLK进行分频处理，并输出相应频率的时钟信号即预设时钟信号PUL，并且脉宽控制信号产生单元302根据计数信号B0至Bm控制N路并行数字信号A0至A(N-1)依次输出。
更具体地，当脉宽控制信号产生单元302输出的数字信号为高电平(即脉宽控制信号PWct为高电平)时，非门341输出低电平，第一与非门342对预设时钟信号PUL和非门341输出的低电平进行逻辑处理，以输出高电平，同时，第一分频器320参与分频以生成第一脉冲宽度的脉冲信号，根据与非门的逻辑功能可知，逻辑控制子单元340对第一脉冲宽度的脉冲信号进行逻辑处理以生成第一输出信号，第一输出信号与第一脉冲宽度的脉冲信号保持一致，进而第二分频器330对第一输出信号进行分频处理，以生成第二脉冲宽度的脉冲信号。当脉宽控制信号产生单元302输出的数字信号为低电平时，非门341输出高电平，第一分频器320的使能端接收到低电平，因此第一分频器320被屏蔽，第二与非门343输出高电平，根据与非门的逻辑功能可知，逻辑控制子单元340对预设时钟信号PUL进行逻辑处理后以生成第二输出信号，第二输出信号与预设时钟信号PUL保持一致，进而第二分频器330对第二输出信号进行分频处理，以生成第一脉冲宽度的脉冲信号。
根据本发明的一个实施例，第二脉冲宽度可为第一脉冲宽度的整数倍。可选地，第二脉冲宽度可为第一脉冲宽度的两倍。
根据本发明的一个具体实施例，假设共有6路并行输入信号A0至A5，且6路并行输入信号A0至A5的电平状态如图6所示，结合表2和表3的分析可知，当脉宽控制信号产生单元302按照表2所示的对应关系控制N路并行数字信号A0至A(N-1)依次输出时,第二分频器330可输出串行脉冲信号SSO-1，其中，脉冲信号SSO-1为正脉冲；当脉宽控制信号产生单元302按照表3所示的对应关系控制N路并行数字信号A0至A(N-1)依次输出时,第二分频器330可输出串行脉冲信号SSO-2，其中，脉冲信号SSO-2为负脉冲。
这样，分频单元303可根据每路数字信号的状态对时钟信号进行分频以生成对应脉冲宽度的脉冲信号(例如串行脉冲信号SSO-1或SSO-2)，不同脉冲宽度的脉冲信号对应不同的数字电平，例如第一脉冲宽度的脉冲信号对应“0”，第二脉冲宽度的脉冲信号对应“1”。这样，图6所示的串行脉冲信号序列为“110101”，从而可以实现对N路并行数字信号A0至A(N-1)的串行转换，以输出与请求电压对应的串行脉冲信号SSO，进而充电装置根据串行脉冲信号SSO调整电压输出。
根据本发明的一个具体实施例，待充电设备可为手机或平板电脑。
综上，根据本发明实施例提出的串行脉冲产生电路，通过接收端接收充电设备输出的请求电压，并行转换模块根据请求电压信号生成与请求电压信号对应的N路并行数字信号，串行脉冲生成模块根据每路数字信号的状态对时钟信号进行分频，以生成对应脉冲宽度的脉冲信号，并控制N路并行数字信号对应的脉冲信号依次输出，从而输出与请求电压信号对应的串行脉冲信号。由此，本发明实施例的串行脉冲产生电路利用高精度时钟信号生成与请求电压信号对应的串行脉冲信号，提升了信号输出的时间精度，且有效减小了芯片面积。
图7是本发明实施例提出的充电装置的方框示意图。如图7所示，该充电装置300包括：次级芯片100和主边芯片200，其中，次级芯片100包括串行脉冲产生电路101，次级芯片100用于根据请求电压信号生成与请求电压信号对应的串行脉冲信号SSO；主边芯片200用于根据串行脉冲信号SSO调整主边芯片的电压输出。
需要说明的是，本发明实施例的串行脉冲产生电路可适用于各种充电协议，按照充电协议的需求，根据待充电设备的请求电压信号生成相应的串行脉冲信号SSO。所述充电协议包括但不限于QC(Quick Charge)2.0，QC3.0，FCP(Fast Charger Protocol)等。
此时，所述并行转换模块进一步用于按照充电协议，根据所述请求电压信号生成与所述请求电压信号对应的N路并行数字信号；所述串行脉冲生成模块进一步用于按照所述充电协议，输出与所述请求电压信号对应的串行脉冲信号。
例如，充电协议QC3.0(Quick Charge 3.0)中的电压输出的调整等级较多，可采用串行脉冲信号SSO进行信号传输，在采用串行脉冲信号SSO进行信号传输时，不同脉冲宽度的脉冲信号对应不同的数字电平，例如第一脉冲宽度的脉冲信号对应“0”，第 二脉冲宽度的脉冲信号对应“1”，这样，不同的请求电压信号可对应不同的脉冲信号。在本发明的实施例中，串行脉冲信号SSO需要较高的精度，以确保主边芯片200可以对次级芯片100输出的串行脉冲信号SSO进行检测和译码，从而调整主边芯片的电压输出。并且，为了降低信号传输过程中的信号延时的影响，提高串行脉冲信号SSO的抗干扰能力，需要保证串行脉冲信号SSO的脉冲宽度。
图8是根据本发明一个实施例的充电装置的电路示意图。如图8所示，串行脉冲产生电路101与待充电设备的电压请求端口D+和D-相连以获取待充电设备输出的请求电压信号，并根据请求电压信号输出与请求电压信号对应的串行脉冲信号SSO，其中，不同的请求电压信号对应的串行脉冲信号SSO不同。进而，次级芯片100输出的串行脉冲信号SSO可通过充电装置300的光耦芯片IC输出至主边芯片200，主边芯片200对接收到的信号进行译码，并根据译码结果控制开关管Q开通或关断，以调整主边芯片的电压输出，即调整Vout+和Vout-两端的输出电压。
根据本发明的一个具体实施例，充电装置用于为待充电设备进行充电，其中，待充电设备可为手机或平板电脑。
综上，根据本发明实施例提出的充电装置，次级芯片通过上述实施例的串行脉冲产生电路生成与请求电压信号对应的串行脉冲信号，进而，主边芯片根据串行脉冲信号调整主边芯片的电压输出。由此，本发明实施例的充电装置利用高精度时钟信号生成与请求电压信号对应的串行脉冲信号，提升了信号输出的时间精度，有效调节电压输出。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本发明的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
在本发明中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。而且，第 一特征在第二特征“之上”、“上方”和“上面”可是第一特征在第二特征正上方或斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”可以是第一特征在第二特征正下方或斜下方，或仅仅表示第一特征水平高度小于第二特征。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本发明的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本发明的限制，本领域的普通技术人员在本发明的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (12)

  1. 一种串行脉冲产生电路，其特征在于，包括：
    接收端，所述接收端用于接收待充电设备输出的请求电压信号；
    并行转换模块，所述并行转换模块与所述接收端相连，所述并行转换模块用于根据所述请求电压信号生成与所述请求电压信号对应的N路并行数字信号；
    串行脉冲生成模块，所述串行脉冲生成模块与所述并行转换模块相连，所述串行脉冲生成模块用于根据每路数字信号的状态对时钟信号进行分频以生成对应脉冲宽度的脉冲信号，并控制所述N路并行数字信号对应的脉冲信号依次输出以输出与所述请求电压信号对应的串行脉冲信号。
  2. 根据权利要求1所述的串行脉冲产生电路，其特征在于，所述串行脉冲生成模块包括：
    计数单元，所述计数单元用于对所述N路并行数字信号的输出个数进行计数以生成计数信号；
    脉宽控制信号产生单元，所述脉宽控制信号产生单元分别与所述计数单元和所述并行转换模块相连，所述脉宽控制信号产生单元用于根据所述计数信号控制所述N路并行数字信号依次输出；
    分频单元，所述分频单元与所述脉宽控制信号产生单元相连，所述分频单元用于根据每路数字信号的状态对时钟信号进行分频以生成对应脉冲宽度的脉冲信号。
  3. 根据权利要求2所述的串行脉冲产生电路，其特征在于，所述分频单元包括：
    时钟信号产生器，所述时钟信号产生器用于产生时钟信号；
    第一分频器，所述第一分频器与所述时钟信号产生器相连，所述第一分频器用于对所述时钟信号进行分频以生成第一脉冲宽度的脉冲信号；
    第二分频器，所述第二分频器用于在所述第一分频器被屏蔽时对所述时钟信号进行分频以生成第一脉冲宽度的脉冲信号，以及在所述第一分频器参与分频时对所述第一脉冲宽度的脉冲信号进行分频以生成第二脉冲宽度的脉冲信号；
    逻辑控制子单元，所述逻辑控制子单元分别与所述脉宽控制信号产生单元、所述时钟信号产生器、所述第一分频器和所述第二分频器相连，所述逻辑控制子单元用于根据每路数字信号的状态控制所述第一分频器参与分频或被屏蔽。
  4. 根据权利要求3所述的串行脉冲产生电路，其特征在于，所述逻辑控制子单元包括：
    非门，所述非门的输入端与所述脉宽控制信号产生单元相连；
    第一与非门，所述第一与非门的第一输入端与所述非门的输出端相连，所述第一与 非门的第二输入端与所述时钟信号产生器相连；
    第二与非门，所述第二与非门的第一输入端与所述脉宽控制信号产生单元相连，所述第二与非门的第二输入端与所述第一分频器相连；
    第三与非门，所述第三与非门的第一输入端与所述第一与非门的输出端相连，所述第三与非门的第二输入端与所述第二与非门的输出端相连，所述第三与非门的输出端与所述第二分频器相连。
  5. 根据权利要求3或4所述的串行脉冲产生电路，其特征在于，其中，所述第二脉冲宽度为所述第一脉冲宽度的整数倍。
  6. 根据权利要求2-5中任意一项所述的串行脉冲产生电路，其特征在于，所述串行脉冲生成模块还包括：
    触发器，所述触发器的第一端与所述计数单元相连，所述触发器的第二端与所述计数单元和所述分频单元分别相连，所述触发器的第三端用于接收触发信号，所述触发器在通过所述第三端接收到所述触发信号后使能所述计数单元和所述分频单元。
  7. 根据权利要求1-6中任意一项所述的串行脉冲产生电路，其特征在于，所述并行转换模块包括:
    判断单元，所述判断单元用于判断所述请求电压信号所处的电压等级；
    解码单元，所述解码单元与所述判断单元相连，所述解码单元用于根据所述请求电压信号所处的电压等级生成电压状态信号；
    并行编码单元，所述并行编码单元与所述解码单元相连，所述并行编码单元用于根据所述电压状态信号生成与所述请求电压对应的N路并行数字信号。
  8. 根据权利要求1-7中任意一项所述的串行脉冲产生电路，其特征在于，其中，所述待充电设备为手机或平板电脑。
  9. 根据权利要求1-8中任意一项所述的串行脉冲产生电路，其特征在于，
    所述并行转换模块进一步用于按照充电协议，根据所述请求电压信号生成与所述请求电压信号对应的N路并行数字信号；
    所述串行脉冲生成模块进一步用于按照所述充电协议，输出与所述请求电压信号对应的串行脉冲信号。
  10. 根据权利要求9所述的串行脉冲产生电路，其特征在于，所述充电协议包括QC2.0协议，QC3.0协议和FCP协议。
  11. 一种充电装置，其特征在于，包括:
    次级芯片，所述次级芯片包括根据权利要求1-10中任一项所述的串行脉冲产生电路，所述次级芯片用于根据所述请求电压信号生成与所述请求电压信号对应的串行脉冲信号；
    主边芯片，所述主边芯片用于根据所述串行脉冲信号调整所述主边芯片的电压输出。
  12. 根据权利要求10所述的充电装置，其特征在于，所述充电装置用于为待充电设备进行充电，其中，所述待充电设备为手机或平板电脑。
PCT/CN2017/110499 2016-12-09 2017-11-10 串行脉冲产生电路及充电装置 WO2018103500A1 (zh)

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