WO2018094817A1 - 一种goa驱动电路 - Google Patents

一种goa驱动电路 Download PDF

Info

Publication number
WO2018094817A1
WO2018094817A1 PCT/CN2016/112987 CN2016112987W WO2018094817A1 WO 2018094817 A1 WO2018094817 A1 WO 2018094817A1 CN 2016112987 W CN2016112987 W CN 2016112987W WO 2018094817 A1 WO2018094817 A1 WO 2018094817A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
inverter
inputting
signal
input
Prior art date
Application number
PCT/CN2016/112987
Other languages
English (en)
French (fr)
Inventor
赵莽
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US15/326,575 priority Critical patent/US10373578B2/en
Publication of WO2018094817A1 publication Critical patent/WO2018094817A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0294—Details of sampling or holding circuits arranged for use in a driver for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Definitions

  • the present invention belongs to the field of display control technology, and in particular, to a GOA driving circuit.
  • GOA Gate Driver On Array
  • CMOS GOA circuit design is quite satisfactory, and its use of the clock control signal is not optimized too much, resulting in a large load and power consumption for generating a clock signal, making it difficult to reduce the power consumption of the entire GOA circuit. .
  • the invention provides a GOA driving circuit, which can control the input control module without using a clock control signal, and can effectively reduce the load of the clock control signal and the power consumption of the circuit.
  • a GOA driving circuit including:
  • An input control module for inputting a level signal
  • a latch module for latching the input level signal
  • a processing module configured to process the level-transmitted signal output by the latch module into a first intermediate signal
  • a buffer module configured to buffer and process the first intermediate signal as a gate driving signal and a second intermediate signal, where the first intermediate signal and the second intermediate signal are opposite in phase
  • first intermediate signal and/or the second intermediate signal output by the upper level GOA driving circuit and the next stage GOA driving circuit controls the input control module to input a level transmission signal, and control
  • the latch module latches a level pass signal input by the input control module.
  • the input control module comprises:
  • a first transistor which is a P-type transistor, a gate for inputting a first intermediate signal outputted by a next-stage GOA driving circuit, a source for inputting a first control signal, and a drain for connecting the latch module;
  • a second transistor which is an N-type transistor, a gate for inputting a second intermediate signal outputted by the upper stage GOA driving circuit, a source for inputting the second control signal, and a drain connected to the latch module.
  • the latch module comprises:
  • a first inverter having an input connected to the drains of the first transistor and the second transistor, the output being connected to the processing module;
  • a third transistor which is a P-type transistor, a gate for inputting a second intermediate signal outputted by the upper stage GOA driving circuit, and a drain connected to an input end of the first inverter;
  • a fourth transistor which is an N-type transistor, a gate for inputting a first intermediate signal outputted by the next-stage GOA driving circuit, and a drain connected to a source of the third transistor;
  • the second inverter has an input connected to the output of the first inverter and an output connected to the source of the fourth transistor.
  • the input control module comprises:
  • a first transistor which is a P-type transistor, a gate for inputting a first intermediate signal outputted by the upper stage GOA driving circuit, a source for inputting the first control signal, and a drain connected to the latch module;
  • the second transistor which is an N-type transistor, has a gate for inputting a second intermediate signal outputted by the next-stage GOA driving circuit, a source for inputting the second control signal, and a drain connected to the latch module.
  • the latch module comprises:
  • a first inverter having an input connected to the drains of the first transistor and the second transistor;
  • a second inverter having an input connected to an output of the first inverter and an output connected to the processing module
  • a third transistor which is an N-type transistor, a gate for inputting a first intermediate signal outputted by the upper stage GOA driving circuit, and a drain connected to an input end of the first inverter;
  • a fourth transistor which is a P-type transistor, a gate for inputting a second intermediate signal outputted by the next-stage GOA driving circuit, a drain connected to a source of the third transistor, and a source connected to the second inverter The output.
  • the input control module comprises:
  • a first transistor which is an N-type transistor, and a gate for inputting an output of a GOA driving circuit of a previous stage a second intermediate signal, the source is used to input a second control signal, and the drain is connected to the latch module;
  • the second transistor which is an N-type transistor, has a gate for inputting a second intermediate signal outputted by the next-stage GOA driving circuit, a source for inputting the second control signal, and a drain connected to the latch module.
  • the latch module comprises:
  • a first inverter having an input connected to a drain of the first transistor and an output connected to the processing module
  • a third transistor which is a P-type transistor, a gate for inputting a second intermediate signal outputted by the upper stage GOA driving circuit, and a drain connected to an input end of the first inverter;
  • a fourth transistor which is a P-type transistor, a gate for inputting a second intermediate signal outputted by the next-stage GOA driving circuit, and a source connected to an output end of the first inverter;
  • a second inverter having an input connected to a drain of the third transistor and an output connected to a source of the fourth transistor.
  • the input control module comprises:
  • a first transistor which is a P-type transistor, a gate for inputting a first intermediate signal outputted by a next-stage GOA driving circuit, a source for inputting a first control signal, and a drain for connecting the latch module;
  • the second transistor which is a P-type transistor, has a gate for inputting a first intermediate signal output by the upper stage GOA driving circuit, a source for inputting the first control signal, and a drain connected to the latch module.
  • the latch module comprises:
  • a first inverter having an input connected to a drain of the first transistor and an output connected to the processing module
  • a third transistor which is an N-type transistor, a gate for inputting a first intermediate signal outputted by the next-stage GOA driving circuit, and a drain connected to an input end of the first inverter;
  • a fourth transistor which is an N-type transistor, a gate for inputting a first intermediate signal output by the upper stage GOA driving circuit, and a source connected to an output end of the first inverter;
  • the second inverter has an input connected to the drain of the fourth transistor and an output connected to the source of the third transistor.
  • the processing module includes a NAND gate, a first input end of which is connected to an output end of the latch module, a second input end is connected to the first timing driving signal, and an output end is connected to the cache module and outputs the first Intermediate signal,
  • the cache module includes a third inverter, a fourth inverter, and a fifth inverter connected in series, wherein
  • An input end of the third inverter is connected to the processing module, and an output end is connected to an input end of the fourth inverter;
  • An output end of the fourth inverter is connected to an input end of the fifth inverter, and outputs the second intermediate signal
  • the output of the fifth inverter outputs a gate driving signal
  • the reset module includes a sixth inverter and a fifth transistor connected to the sixth inverter, wherein
  • An output end of the sixth inverter is connected to an output end of the buffer module, and an input end is respectively connected to a drain of the fifth transistor and an input end of the sixth inverter;
  • the source of the fifth transistor introduces a first control signal and the gate introduces a reset signal.
  • the GOA driving circuit provided by the invention does not use a clock control signal to control the input control module, thereby effectively reducing the load of the clock control signal and the power consumption of the circuit.
  • FIG. 1 is a schematic diagram of a GOA driving circuit in the prior art
  • FIG. 2a-2c are schematic diagrams showing internal structures of some circuit components in FIG. 1;
  • Figure 3 is a timing chart of the operation of Figure 1 when scanning
  • FIG. 4 is a structural diagram of a driving circuit in accordance with an embodiment of the present invention.
  • Figure 5 is a structural diagram of a driving circuit in accordance with a first embodiment of the present invention.
  • Figure 6 is a structural diagram of a driving circuit in accordance with a second embodiment of the present invention.
  • Figure 7 is a structural diagram of a driving circuit in accordance with a third embodiment of the present invention.
  • Figure 8 is a structural diagram of a driving circuit in accordance with a fourth embodiment of the present invention.
  • Figure 9 is a schematic diagram of a drive architecture in accordance with one embodiment of the present invention.
  • Figure 10 is a timing chart showing the operation of the driving circuit when scanning according to an embodiment of the present invention.
  • FIG. 11 is a timing diagram of simulated waveforms at the time of scanning according to an embodiment of the present invention.
  • Figure 12 is a timing diagram of simulated waveforms at the time of scanning in accordance with another embodiment of the present invention.
  • CMOS GOA driving circuit As shown in FIG. 1 , a conventional CMOS GOA driving circuit in the prior art, the circuit adopts an interleaved driving mode, and the single-sided GOA driving circuit requires two clock control signals CK to be traced (such as the clock control signal CK1 routing, clock) Control signal CK2 is routed), a start signal STV trace (not shown), a reset signal RESET trace, a high potential signal VGH trace and a low potential signal VGL trace.
  • this CMOS GOA driving circuit is mainly composed of the following parts.
  • the input control module 100 is used for signal input control of the GOA driving circuit, and controls the internal clock control inverter through the CK1 signal and the XCK1 signal to realize transmission of the upper Q point signal; the latch module 200 controls the internal clock thereof.
  • the control of the inverter realizes the latching of the Q-point signal of the current stage;
  • the RESET module 300 includes a transistor PTFT1 and an inverter IN2 for reset processing of signal nodes in the circuit; and a processing module 400 of the Q-point signal (NAND gate) NAND) generates a gate drive signal of the current stage by NAND processing of the CK3 signal and the Q point signal;
  • the gate drive signal buffer processing module 500 includes three inverters IN3, IN4, and IN5 connected in series for improving the gate The drive capability of the pole drive signal.
  • Q(N) in FIG. 1 represents a Q point signal of the Nth stage GOA driving circuit
  • Q point is a point for controlling the gate driving signal output
  • P(N) represents a P point of the Nth stage GOA driving circuit.
  • Point P is used to control the point at which the circuit maintains a stable output during circuit inactivity.
  • the CK1 signal is inverted by the inverter IN1 to obtain the XCK1 signal.
  • Q(N-1) is a level-transmitted signal of the N-th stage GOA driving circuit.
  • FIG. 2a-2c are equivalent circuit diagrams of some components in the CMOS GOA driving circuit of FIG. 1, wherein FIG. 2a is an equivalent circuit corresponding to each inverter in FIG. 1, and FIG. 2b is a clock control inversion in FIG.
  • the equivalent circuit corresponding to the device, FIG. 2c is the equivalent circuit corresponding to the NAND gate in FIG.
  • FIG. 3 is a timing chart of the operation of the GOA driving circuit shown in FIG. 1. As can be seen from the analysis of FIG. 3, the working principle of the circuit shown in FIG. 1 is: before the input signal Q(N-1) is input, all GOA driving circuits are first performed.
  • Q node of all circuits is reset to low level, gate drive signal is low level;
  • the first-level Q-point signal and the high-level pulse signal of the CK1 signal of the control input of the current stage come at the same time, the Q(N) point is charged to the high level, and when the CK1 signal of the control input becomes the low level, the latch module 200
  • the high level signal of the Q(N) point is latched; when the high level pulse signal of the NAND gate control CK3 signal comes, the GATE(n) signal outputs a high level signal, that is, the gate drive signal of the current stage is generated.
  • the present invention provides a GOA drive circuit whose input control module 100 does not require CK1 signals for control, effectively reducing the power consumption of the load and circuitry used to generate the CK1 signal.
  • 4 is a structural diagram of a GOA driving circuit according to an embodiment of the present invention, and the present invention will be described in detail below with reference to FIG.
  • the GOA driving circuit includes an input control module 21, a latch module 22, a processing module 23, and a cache module 24.
  • the input control module 21 is used to input the level transfer signal;
  • the latch module 22 is used to latch the input level transfer signal;
  • the processing module 23 is configured to process the level transfer signal output by the latch module into the first intermediate signal;
  • the first intermediate signal is buffered and processed as a gate driving signal and a second intermediate signal, and the phases of the first intermediate signal and the second intermediate signal are opposite, wherein the output of the upper level GOA driving circuit and the next stage GOA driving circuit are
  • the first intermediate signal and/or the second intermediate signal controls the input control module 21 to input the level transfer signal, and the control latch module 22 latches the level transfer signal input by the input control module 21.
  • the GOA driving circuit provided by the present invention, the latch module 22 and the input control module 21 do not adopt clock control signal control, which effectively reduces the load of the clock control signal and the power consumption of the circuit.
  • the input control module 21 includes a first transistor T11 and a second transistor T12, as shown in FIG.
  • the first transistor T11 is a P-type transistor, and the gate thereof is used for inputting the first intermediate signal XP ((N+1) output of the next-stage GOA driving circuit, the source is for inputting the first control signal VGH, and the drain connection is locked
  • the second transistor T12 is an N-type transistor, the gate is used for inputting the second intermediate signal P ((N-1) outputted by the previous stage GOA driving circuit, and the source is used for inputting the second control signal VGL, drain
  • the pole is connected to the latch module 22.
  • the T12, T13, and P(N-1) signals are used to pull up the Q point signal of the current stage, the T12 transistor is used for the transmission of the Q point signal, and the T13 transistor is used for the switching control of the latch loop.
  • P(N-1) is the second intermediate signal of the upper level GOA circuit for switching control of the T12 and T13 transistors.
  • the T11, T14 and XP(N+1) signals are used to pull down the Q-point signal of this stage, the T11 transistor is used for the transmission of the low-level signal of the Q-point signal, and the T14 transistor is used for the switching control of the latching loop, XP (N +1) is the first intermediate signal of the next stage GOA circuit.
  • the circuit shown in FIG. 5 uses the PTFT to transmit the VGH signal, and the NTFT performs the VGL signal transmission, which can reduce the threshold voltage Vth loss of the transmitted signal.
  • the latch module includes a first inverter IN11, a second inverter IN12, a third transistor T13, and a fourth transistor T14, as shown in FIG.
  • the input end of the first inverter IN11 is connected to the drains of the first transistor T11 and the second transistor T12, and the output terminal is connected to the processing module 23;
  • the third transistor T13 is a P-type transistor, and the gate is used for inputting the upper-level GOA driving circuit.
  • the output second intermediate signal P(N-1) has a drain connected to the input end of the first inverter IN11; the fourth transistor T14 is an N-type transistor, and the gate is used to input the first output of the next-stage GOA driving circuit
  • the intermediate signal XP(N+1) has a drain connected to the source of the third transistor T13; the input of the second inverter IN12 is connected to the output of the first inverter IN11, and the output is connected to the source of the fourth transistor T14.
  • the input control module comprises a first transistor T21 and a second transistor T22, as shown in FIG.
  • the first transistor T21 is a P-type transistor
  • the gate is used for inputting the first intermediate signal XP(N-1) outputted by the upper-level GOA driving circuit
  • the source is for inputting the first control signal VGH
  • the drain is connected to the latch module.
  • the second transistor T22 is an N-type transistor
  • the gate is for inputting a second intermediate signal P(N+1) outputted by the next-stage GOA driving circuit
  • the source is for inputting the second control signal VGL
  • the drain is connected with a lock Save module 23.
  • the latch module includes a first inverter IN21, a second inverter IN22, a third transistor T23, and a fourth transistor T24, as shown in FIG.
  • the input end of the first inverter T21 is connected to the drain of the first transistor T11 and the second transistor T12; the input end of the second inverter IN22 is connected to the output end of the first inverter IN21, and the output is connected to the processing module 23;
  • the third transistor T23 is a P-type transistor, the gate is used for inputting the second intermediate signal P(N+1) outputted by the next-stage GOA driving circuit, and the drain is connected to the output end of the second inverter IN22;
  • the fourth transistor T24 For the N-type transistor, the gate is used to input the first intermediate signal XP(N-1) outputted by the upper-level GOA driving circuit, the drain is connected to the source of the third transistor T23, and the source is connected to the first inverter IN21. Input.
  • the third transistor and the fourth transistor are used for switching control of the latch loop in the latch module.
  • the latch circuit is composed of a first inverter IN11, a second inverter IN12, and a third The transistor T13 and the fourth transistor T14 are formed.
  • the second intermediate signal P(N-1) outputted by the upper-level GOA driving circuit is at a low level, and the next-stage GOA driving circuit outputs
  • the first intermediate signal XP(N+1) is high and low, and at this time, the third transistor T13 and the fourth transistor T14 are turned on, and the level transmission signal is stored in the latch circuit.
  • the latch circuit is composed of a first inverter IN21, a second inverter IN22, a third transistor T23, and a fourth transistor T24.
  • the first intermediate signal XP(N-1) outputted by the upper-level GOA driving circuit is at a high level, and the next-stage GOA driving circuit outputs
  • the second intermediate signal P(N+1) is at a low level, at which time the third transistor T23 and the fourth transistor T24 are turned on, and the level transfer signal is held in the latch loop.
  • the latch module does not employ clock control signal control, and can effectively reduce the load of the clock control signal and the power consumption of the circuit.
  • the input control module comprises a first transistor T31 and a second transistor T32, as shown in FIG.
  • the first transistor T31 is an N-type transistor, the gate is used for inputting the second intermediate signal P(N-1) outputted by the upper-level GOA driving circuit, the source is for inputting the second control signal VGL, and the drain is connected to the latch module. 22;
  • the second transistor T32 is an N-type transistor, the gate is used for inputting the second intermediate signal P(N+1) outputted by the next-stage GOA driving circuit, the source is used for inputting the second control signal VGL, and the drain connection is locked
  • the module 22 is stored.
  • the latch module includes a first inverter IN31, a second inverter IN32, a third transistor T33, and a fourth transistor T34, as shown in FIG.
  • the input end of the first inverter IN31 is connected to the drain of the first transistor T31, the output end is connected to the processing module;
  • the third transistor T33 is a P-type transistor, and the gate is used for inputting the second intermediate signal P outputted by the GOA driving circuit of the previous stage.
  • the drain is connected to the input terminal of the first inverter IN31;
  • the fourth transistor T34 is a P-type transistor, and the gate thereof is used for inputting the second intermediate signal P(N+1) outputted by the next-stage GOA driving circuit
  • the source is connected to the output of the first inverter IN31;
  • the output of the second inverter IN32 is connected to the source of the third transistor T33, and the input is connected to the drain of the fourth transistor T34.
  • the T8, T34, and P(N+1) signals are used to pull down the Q-point signal of the current stage
  • the T32 transistor is used for the transmission of the Q-point signal
  • the T34 transistor is used for the switching control of the latching loop.
  • (N+1) is the second intermediate signal of the next stage GOA circuit for switching control of the T32 and T34 transistors.
  • the T31, T33 and P(N-1) signals are used to pull down the Q-point signal of the current level.
  • the T31 transistor is used for the transmission of the low-level signal of the Q-point signal
  • the T33 transistor is used for the switching control of the latching loop.
  • the circuit shown in Fig. 7 uses the NTFT to transmit the VGL signal, which can reduce the threshold voltage Vth loss of the transmitted signal.
  • the input control module comprises a first transistor T41 and a second transistor T42, as shown in FIG.
  • the first transistor T41 is a P-type transistor
  • the gate is used for inputting the first intermediate signal XP(N+1) outputted by the next-stage GOA driving circuit
  • the source is for inputting the first control signal VGH
  • the drain is connected to the latch module.
  • the second transistor T42 is a P-type transistor
  • the gate is used for inputting the first intermediate signal P(N-1) outputted by the upper-level GOA driving circuit
  • the source is for inputting the first control signal VGH
  • the drain is connected to the latch module. twenty two.
  • the latch module includes a first inverter IN41, a second inverter IN42, a third transistor T43, and a fourth transistor T44, as shown in FIG.
  • the input end of the first inverter IN41 is connected to the drain of the first transistor T41, the output end is connected to the processing module 23;
  • the third transistor T43 is an N-type transistor, and the gate is used to input the first middle of the output of the next-stage GOA driving circuit.
  • the signal XP(N+1) is connected to the input terminal of the first inverter IN41;
  • the fourth transistor T44 is an N-type transistor, and the gate is used for inputting the first intermediate signal XP(N) outputted by the upper-level GOA driving circuit.
  • the drain is connected to the output terminal of the first inverter IN41;
  • the input terminal of the second inverter IN42 is connected to the drain of the fourth transistor T44, and the output terminal is connected to the source of the third transistor T43.
  • the third transistor and the fourth transistor are used for switching control of the latch circuit in the latch module.
  • the latch circuit is composed of a first inverter IN31, a second inverter IN32, a third transistor T33, and a fourth transistor T34.
  • the second intermediate signal P(N-1) outputted by the upper-level GOA driving circuit is at a low level, and the next-stage GOA driving circuit outputs
  • the second intermediate signal P(N+1) is at a low level, at which time the third transistor T33 and the fourth transistor T34 are turned on, and the level transfer signal is held in the latch loop.
  • the latch circuit is composed of a first inverter IN41, a second inverter IN42, a third transistor T43, and a fourth transistor T44.
  • the first intermediate signal XP(N-1) outputted by the upper-level GOA driving circuit is at a high level
  • the next-stage GOA driving circuit outputs
  • the first intermediate signal XP(N+1) is at a low level, at which time the third transistor T43 and the fourth transistor T44 are turned on, and the level transfer signal is held in the latch loop.
  • the latch module does not employ clock control signal control, and can effectively reduce the load of the clock control signal and the power consumption of the circuit.
  • the processing module 23 includes a NAND gate NAND having a first input connected to the output of the latch module, a second input coupled to the first timing drive signal CK3, and an output coupled to the cache module.
  • the first intermediate signal P(N) of the current stage is output, as shown in FIGS. 5-8.
  • the cache module 24 includes a third inverter IN23 connected in series, The fourth inverter IN24 and the fifth inverter IN25, wherein the input end of the third inverter IN23 is connected to the processing module, the output end is connected to the input end of the fourth inverter IN24; the output end of the fourth inverter IN24 The input terminal of the fifth inverter IN25 is connected, and a second intermediate signal is output; the output terminal of the fifth inverter IN25 outputs a gate drive signal, as shown in FIG. 5-8.
  • the reset module comprises a sixth inverter IN26 and a fifth transistor T25 connected to the sixth inverter IN26, wherein the output of the sixth inverter IN26 is connected to the output of the buffer module,
  • the input terminal is respectively connected to the drain of the fifth transistor T25 and the input terminal of the sixth inverter IN26; the source of the fifth transistor T25 introduces a first control signal, and the gate introduces a reset signal.
  • FIG. 9 is a driving frame diagram of the circuit shown in FIG. 5 to FIG. 8.
  • the driving frame diagram is a single-side driving frame diagram corresponding to odd-numbered rows of scanning lines, wherein the single-sided GOA circuit requires two STV signals to go.
  • the line is used for the pull-up of the Q point of the first-stage GOA circuit and the pull-down of the Q point of the last stage GOA circuit; two CK signal traces are required for the unilateral side for the generation of the gate shift drive signal;
  • a RESET trace is used for reset processing of each stage of the GOA circuit; a VGH trace and a VGL trace are required on one side for driving the CMOS GOA circuit.
  • FIG. 10 is a scan driving timing diagram of the driving frame shown in FIG. 9. It can be seen from the timing diagram analysis that the working principle of the GOA circuit provided by this patent is: when the RESETt signal is low-level pulse signal, all GOA circuits are reset. Processing, after the Q point reset, the low level signal is latched; when the XP0 low level pulse or the P0 high level pulse signal comes, the Q point is charged to the high level, then the Q point latches the high level signal; when the CK3 signal The high level pulse comes to generate the first intermediate signal XP1 of the current stage; the first intermediate signal XP1 of the current stage is processed by the buffer module as the gate drive signal GATE1 of the stage; when the low level pulse of XP2 is alive of the high level of P2 When the pulse signal comes, the Q point is charged to a low level, and then the Q point always latches a low level signal, and the GOA circuit stably outputs a low level gate drive signal.
  • FIG. 11 is a schematic diagram of a first scan driving simulation according to an embodiment of the present invention.
  • FIG. 12 is a schematic diagram of a second scan driving simulation according to an embodiment of the present invention.
  • FIG. 11 and FIG. The circuit can output a scan signal in forward or reverse direction.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)

Abstract

一种GOA驱动电路，包括：输入控制模块(21)、锁存模块(22)、处理模块(23)和缓存模块(24)。由于不采用时钟控制信号(CK1,XCK1)控制输入控制模块(21)，有效地降低了产生时钟控制信号(CK1,XCK1)的负载和电路的功耗。

Description

一种GOA驱动电路
相关申请的交叉引用
本申请要求享有2016年11月28日提交的名称为“一种GOA驱动电路”的中国专利申请CN201611061519.6的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明属于显示控制技术领域，具体地说，尤其涉及一种GOA驱动电路。
背景技术
GOA(Gate Driver On Array，集成在阵列基板上的行扫描)是利用现有薄膜晶体管液晶显示器阵列制程，将行扫描驱动信号电路制作在阵列基板上，实现逐行扫描驱动的一项技术。
现有传统的CMOS GOA电路设计中规中矩，其对时钟控制信号的使用并没有进行太多的优化，导致用于产生时钟信号的负载和功耗较大，使得整个GOA电路的功耗很难减小。
发明内容
本发明提供了一种GOA驱动电路，不采用时钟控制信号控制输入控制模块，可以有效地降低产生时钟控制信号的负载和电路的功耗。
根据本发明的一个实施例，提供了一种GOA驱动电路，包括：
输入控制模块，用于输入级传信号；
锁存模块，用于锁存输入的级传信号；
处理模块，用于将所述锁存模块输出的级传信号处理为第一中间信号；
缓存模块，用于缓存并处理所述第一中间信号为栅极驱动信号和第二中间信号，所述第一中间信号和所述第二中间信号的相位相反，
其中，由上一级GOA驱动电路和下一级GOA驱动电路输出的所述第一中间信号和/或所述第二中间信号控制所述输入控制模块来输入级传信号，以及控 制所述锁存模块锁存由所述输入控制模块输入的级传信号。
根据本发明的一个实施例，所述输入控制模块包括：
第一晶体管，其为P型晶体管，栅极用于输入下一级GOA驱动电路输出的第一中间信号，源极用于输入第一控制信号，漏极连接所述锁存模块；
第二晶体管，其为N型晶体管，栅极用于输入上一级GOA驱动电路输出的第二中间信号，源极用于输入第二控制信号，漏极连接所述锁存模块。
根据本发明的一个实施例，所述锁存模块包括：
第一反相器，其输入端连接所述第一晶体管和所述第二晶体管的漏极，输出端连接所述处理模块；
第三晶体管，其为P型晶体管，栅极用于输入上一级GOA驱动电路输出的第二中间信号，漏极连接所述第一反相器的输入端；
第四晶体管，其为N型晶体管，栅极用于输入下一级GOA驱动电路输出的第一中间信号，漏极连接所述第三晶体管的源极；
第二反相器，其输入端连接所述第一反相器的输出端，输出端连接所述第四晶体管的源极。
根据本发明的一个实施例，所述输入控制模块包括：
第一晶体管，其为P型晶体管，栅极用于输入上一级GOA驱动电路输出的第一中间信号，源极用于输入第一控制信号，漏极连接所述锁存模块；
第二晶体管，其为N型晶体管，栅极用于输入下一级GOA驱动电路输出的第二中间信号，源极用于输入第二控制信号，漏极连接所述锁存模块。
根据本发明的一个实施例，所述锁存模块包括：
第一反相器，其输入端连接所述第一晶体管和所述第二晶体管的漏极；
第二反相器，其输入端连接所述第一反相器的输出端，输出端连接所述处理模块；
第三晶体管，其为N型晶体管，栅极用于输入上一级GOA驱动电路输出的第一中间信号，漏极连接所述第一反相器的输入端；
第四晶体管，其为P型晶体管，栅极用于输入下一级GOA驱动电路输出的第二中间信号，漏极连接所述第三晶体管的源极，源极连接所述第二反相器的输出端。
根据本发明的一个实施例，所述输入控制模块包括：
第一晶体管，其为N型晶体管，栅极用于输入上一级GOA驱动电路输出的 第二中间信号，源极用于输入第二控制信号，漏极连接所述锁存模块；
第二晶体管，其为N型晶体管，栅极用于输入下一级GOA驱动电路输出的第二中间信号，源极用于输入第二控制信号，漏极连接所述锁存模块。
根据本发明的一个实施例，所述锁存模块包括：
第一反相器，其输入端连接所述第一晶体管的漏极，输出端连接所述处理模块；
第三晶体管，其为P型晶体管，栅极用于输入上一级GOA驱动电路输出的第二中间信号，漏极连接所述第一反相器的输入端；
第四晶体管，其为P型晶体管，栅极用于输入下一级GOA驱动电路输出的第二中间信号，源极连接所述第一反相器的输出端；
第二反相器，其输入端连接所述第三晶体管的漏极，输出端连接所述第四晶体管的源极。
根据本发明的一个实施例，所述输入控制模块包括：
第一晶体管，其为P型晶体管，栅极用于输入下一级GOA驱动电路输出的第一中间信号，源极用于输入第一控制信号，漏极连接所述锁存模块；
第二晶体管，其为P型晶体管，栅极用于输入上一级GOA驱动电路输出的第一中间信号，源极用于输入第一控制信号，漏极连接所述锁存模块。
根据本发明的一个实施例，所述锁存模块包括：
第一反相器，其输入端连接所述第一晶体管的漏极，输出端连接所述处理模块；
第三晶体管，其为N型晶体管，栅极用于输入下一级GOA驱动电路输出的第一中间信号，漏极连接所述第一反相器的输入端；
第四晶体管，其为N型晶体管，栅极用于输入上一级GOA驱动电路输出的第一中间信号，源极连接所述第一反相器的输出端；
第二反相器，其输入端连接所述第四晶体管的漏极，输出端连接所述第三晶体管的源极。
根据本发明的一个实施例，
所述处理模块包括一与非门，其第一输入端连接所述锁存模块的输出端，第二输入端连接第一时序驱动信号，输出端与所述缓存模块连接并输出所述第一中间信号，
所述缓存模块包括串联的第三反相器、第四反相器和第五反相器，其中，
所述第三反相器的输入端连接所述处理模块，输出端连接所述第四反相器的输入端；
所述第四反相器的输出端连接所述第五反相器的输入端，并输出所述第二中间信号；
所述第五反相器的输出端输出栅极驱动信号，
所述复位模块包括第六反相器及与所述第六反相器连接的第五晶体管，其中，
所述第六反相器的输出端连接所述缓存模块的输出端，输入端分别连接所述第五晶体管的漏极和所述第六反相器的输入端；
所述第五晶体管的源极引入第一控制信号，栅极引入复位信号。
本发明的有益效果：
本发明提供的GOA驱动电路，不采用时钟控制信号控制输入控制模块，有效地降低了产生时钟控制信号的负载和电路的功耗。
本发明的其他优点、目标，和特征在某种程度上将在随后的说明书中进行阐述，并且在某种程度上，基于对下文的考察研究对本领域技术人员而言将是显而易见的，或者可以从本发明的实践中得到教导。本发明的目标和其他优点可以通过下面的说明书，权利要求书，以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请的技术方案或现有技术的进一步理解，并且构成说明书的一部分。其中，表达本申请实施例的附图与本申请的实施例一起用于解释本申请的技术方案，但并不构成对本申请技术方案的限制。
图1是现有技术中一种GOA驱动电路示意图；
图2a-2c是图1中部分电路元器件的内部结构示意图；
图3是图1扫描时的工作时序图；
图4是根据本发明的一个实施例的驱动电路结构图；
图5是根据本发明的第一个实施例的驱动电路结构图；
图6是根据本发明的第二个实施例的驱动电路结构图；
图7是根据本发明的第三个实施例的驱动电路结构图；
图8是根据本发明的第四个实施例的驱动电路结构图；
图9是根据本发明的一个实施例的驱动架构示意图；
图10是根据本发明的一个实施例的驱动电路扫描时的工作时序图；
图11是根据本发明的一个实施例的扫描时的仿真波形时序图；
图12是根据本发明的另一个实施例的扫描时的仿真波形时序图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成相应技术效果的实现过程能充分理解并据以实施。本申请实施例以及实施例中的各个特征，在不相冲突前提下可以相互结合，所形成的技术方案均在本发明的保护范围之内。
如图1所示是现有技术中一种传统的CMOS GOA驱动电路，该电路采用交错驱动方式，单边GOA驱动电路需要两条时钟控制信号CK走线(如时钟控制信号CK1走线、时钟控制信号CK2走线)，一条启动信号STV走线(未示出)，一条复位信号RESET走线，一条高电位信号VGH走线和一条低电位信号VGL走线。如图1所示，这种CMOS GOA驱动电路主要由如下几个部分组成。
输入控制模块100用于GOA驱动电路的信号输入控制，通过CK1信号和XCK1信号控制其内部的时钟控制反相器，实现上一级Q点信号的传输；锁存模块200通过对其内部时钟控制反相器的控制，实现本级Q点信号的锁存；RESET模块300包括一晶体管PTFT1和反相器IN2，用于电路中信号节点的复位处理；Q点信号的处理模块400(与非门NAND)通过CK3信号与Q点信号的与非处理，产生本级的栅极驱动信号；栅极驱动信号缓存处理模块500，包括三个串联的反相器IN3、IN4、IN5，用于提高栅极驱动信号的驱动能力。其中，图1中的Q(N)表示第N级GOA驱动电路的Q点信号，Q点是用于控制栅极驱动信号输出的点；P(N)表示第N级GOA驱动电路的P点信号，P点是用于控制在电路非作用期间保持电路稳定输出的点。CK1信号经反相器IN1反相后得到XCK1信号。Q(N-1)是第N级GOA驱动电路的级传信号。
如图2a-2c是图1中CMOS GOA驱动电路中部分元器件的等效电路图，其中，图2a为图1中各反相器对应的等效电路，图2b为图1中时钟控制反相器对应的等效电路，图2c为图1中与非门对应的等效电路。
图3是图1所示GOA驱动电路的工作时序图，由图3分析可知，图1所示电路的工作原理为：在级传信号Q(N-1)输入之前，所有GOA驱动电路先进行复位处理，所有电路的Q节点复位为低电平，栅极驱动信号为低电平；当上 一级Q点信号和本级控制输入的CK1信号的高电平脉冲信号同时来临时，Q(N)点被充电至高电平，当控制输入的CK1信号变成低电平时，锁存模块200锁存Q(N)点的高电平信号；当与非门的控制CK3信号的高电平脉冲信号来临时，GATE(n)信号输出高电平信号，即产生本级的栅极驱动信号；当控制输入的CK1信号的高电平脉冲信号再一次来临时，Q(N)点被充电至低电平，之后，Q(N)点一直锁存和输入低电平信号，GATE(N)信号维持稳定的低电平输出。
由以上分析可知，现有的COMS GOA驱动电路输入控制模块100需要CK1信号进行控制，其用于产生CK1信号的电路和负载消耗较大，使得整个GOA电路的功耗很难减小。
因此，本发明提供了一种GOA驱动电路，其输入控制模块100不需要CK1信号进行控制，有效地降低用于产生CK1信号的负载和电路的功耗。如图4所示为根据本发明的一个实施例的GOA驱动电路结构图，以下参考图4来对本发明进行详细说明。
该GOA驱动电路包括输入控制模块21、锁存模块22、处理模块23和缓存模块24。输入控制模块21用于输入级传信号；锁存模块22用于锁存输入的级传信号；处理模块23用于将锁存模块输出的级传信号处理为第一中间信号；缓存模块24用于缓存并处理第一中间信号为栅极驱动信号和第二中间信号，第一中间信号和第二中间信号的相位相反，其中，由上一级GOA驱动电路和下一级GOA驱动电路输出的第一中间信号和/或第二中间信号控制输入控制模块21来输入级传信号，以及控制锁存模块22锁存由输入控制模块21输入的级传信号。
本发明提供的GOA驱动电路，锁存模块22与输入控制模块21不采用时钟控制信号控制，有效地降低了产生时钟控制信号的负载和电路的功耗。
根据本发明的一个实施例，该输入控制模块21包括第一晶体管T11和第二晶体管T12，如图5所示。第一晶体管T11为P型晶体管，其栅极用于输入下一级GOA驱动电路输出的第一中间信号XP((N+1)，源极用于输入第一控制信号VGH，漏极连接锁存模块22；第二晶体管T12为N型晶体管，栅极用于输入上一级GOA驱动电路输出的第二中间信号P((N-1)，源极用于输入第二控制信号VGL，漏极连接锁存模块22。图5所示的GOA驱动电路去除了传统CMOS GOA电路中的时钟控制反相器模块，输入控制模块不采用CK1信号进行控制，直接采用上一级的第一中间信号和下一级的第二中间信号分别对本级的Q点进行上拉和下拉的处理。
如图5所示，利用T12、T13和P(N-1)信号对本级Q点信号进行上拉处理，T12晶体管用于Q点信号的传输，T13晶体管用于锁存环路的开关控制，P(N-1)为上一级GOA电路的第二中间信号，用于T12和T13晶体管的开关控制。利用T11、T14和XP(N+1)信号对本级Q点信号进行下拉处理，T11晶体管用于Q点信号低电平信号的传输，T14晶体管用于锁存环路的开关控制，XP(N+1)为下一级GOA电路的第一中间信号。图5所示电路利用PTFT进行VGH信号的传递，利用NTFT进行VGL信号的传递，可以减小传输信号的门限电压Vth损失。
根据本发明的一个实施例，该锁存模块包括第一反相器IN11、第二反相器IN12、第三晶体管T13和第四晶体管T14，如图5所示。第一反相器IN11的输入端连接第一晶体管T11和第二晶体管T12的漏极，输出端连接处理模块23；第三晶体管T13为P型晶体管，栅极用于输入上一级GOA驱动电路输出的第二中间信号P(N-1)，漏极连接第一反相器IN11的输入端；第四晶体管T14为N型晶体管，栅极用于输入下一级GOA驱动电路输出的第一中间信号XP(N+1)，漏极连接第三晶体管T13的源极；第二反相器IN12的输入端连接第一反相器IN11的输出端，输出端连接第四晶体管T14的源极。
根据本发明的一个实施例，该输入控制模块包括第一晶体管T21和第二晶体管T22，如图6所示。第一晶体管T21为P型晶体管，栅极用于输入上一级GOA驱动电路输出的第一中间信号XP(N-1)，源极用于输入第一控制信号VGH，漏极连接锁存模块23.第二晶体管T22为N型晶体管，栅极用于输入下一级GOA驱动电路输出的第二中间信号P(N+1)，源极用于输入第二控制信号VGL，漏极连接锁存模块23。
根据本发明的一个实施例，该锁存模块包括第一反相器IN21、第二反相器IN22、第三晶体管T23和第四晶体管T24，如图6所示。第一反相器IN21的输入端连接第一晶体管T11和第二晶体管T12的漏极；第二反相器IN22的输入端连接第一反相器IN21的输出端，输出端连接处理模块23；第三晶体管T23为P型晶体管，栅极用于输入下一级GOA驱动电路输出的第二中间信号P(N+1)，漏极连接第二反相器IN22的输出端；第四晶体管T24为N型晶体管，栅极用于输入上一级GOA驱动电路输出的第一中间信号XP(N-1)，漏极连接第三晶体管T23的源极，源极连接第一反相器IN21的输入端。
由图5和图6可知，第三晶体管和第四晶体管用于锁存模块中锁存回路的开关控制。如图5所示，该锁存回路由第一反相器IN11、第二反相器IN12、第三 晶体管T13和第四晶体管T14构成。当级传信号通过第一晶体管T11或第二晶体管T12到达锁存模块后，上一级GOA驱动电路输出的第二中间信号P(N-1)为低电平，下一级GOA驱动电路输出的第一中间信号XP(N+1)为高低电平，此时第三晶体管T13和第四晶体管T14打开，级传信号保存在锁存回路中。如图6所示，该锁存回路由第一反相器IN21、第二反相器IN22、第三晶体管T23和第四晶体管T24构成。当级传信号通过第一晶体管T21或第二晶体管T22到达锁存模块后，上一级GOA驱动电路输出的第一中间信号XP(N-1)为高电平，下一级GOA驱动电路输出的第二中间信号P(N+1)为低电平，此时第三晶体管T23和第四晶体管T24打开，级传信号保存在锁存回路中。在本发明中，锁存模块不采用时钟控制信号控制，可以有效降低产生时钟控制信号的负载和电路的功耗。
根据本发明的一个实施例，该输入控制模块包括第一晶体管T31和第二晶体管T32，如图7所示。第一晶体管T31为N型晶体管，栅极用于输入上一级GOA驱动电路输出的第二中间信号P(N-1)，源极用于输入第二控制信号VGL，漏极连接锁存模块22；第二晶体管T32为N型晶体管，栅极用于输入下一级GOA驱动电路输出的第二中间信号P(N+1)，源极用于输入第二控制信号VGL，漏极连接锁存模块22。
根据本发明的一个实施例，该锁存模块包括第一反相器IN31、第二反相器IN32、第三晶体管T33和第四晶体管T34，如图7所示。第一反相器IN31输入端连接第一晶体管T31的漏极，输出端连接处理模块；第三晶体管T33为P型晶体管，栅极用于输入上一级GOA驱动电路输出的第二中间信号P(N-1，漏极连接第一反相器IN31的输入端；第四晶体管T34为P型晶体管，其栅极用于输入下一级GOA驱动电路输出的第二中间信号P(N+1)，源极连接第一反相器IN31的输出端；第二反相器IN32输出端连接第三晶体管T33的源极，输入端连接第四晶体管T34的漏极。
如图7所示，利用T32、T34和P(N+1)信号对本级Q点信号进行下拉处理，T32晶体管用于Q点信号的传输，T34晶体管用于锁存环路的开关控制，P(N+1)为下一级GOA电路的第二中间信号，用于T32和T34晶体管的开关控制。利用T31、T33和P(N-1)信号对本级Q点信号进行下拉处理，T31晶体管用于Q点信号低电平信号的传输，T33晶体管用于锁存环路的开关控制。图7所示电路利用NTFT进行VGL信号的传递，可以减小传输信号的门限电压Vth损失。
根据本发明的一个实施例，该输入控制模块包括第一晶体管T41和第二晶体管T42，如图8所示。第一晶体管T41为P型晶体管，栅极用于输入下一级GOA驱动电路输出的第一中间信号XP(N+1)，源极用于输入第一控制信号VGH，漏极连接锁存模块22。第二晶体管T42为P型晶体管，栅极用于输入上一级GOA驱动电路输出的第一中间信号P(N-1)，源极用于输入第一控制信号VGH，漏极连接锁存模块22。
根据本发明的一个实施例，该锁存模块包括第一反相器IN41、第二反相器IN42、第三晶体管T43和第四晶体管T44，如图8所示。第一反相器IN41的输入端连接第一晶体管T41的漏极，输出端连接处理模块23；第三晶体管T43为N型晶体管，栅极用于输入下一级GOA驱动电路输出的第一中间信号XP(N+1)，漏极连接第一反相器IN41的输入端；第四晶体管T44为N型晶体管，栅极用于输入上一级GOA驱动电路输出的第一中间信号XP(N-1)，漏极连接第一反相器IN41的输出端；第二反相器IN42的输入端连接第四晶体管T44的漏极，输出端连接第三晶体管T43的源极。
由图7和图8可知，第三晶体管和第四晶体管用于锁存模块中锁存回路的开关控制。如图7所示，该锁存回路由第一反相器IN31、第二反相器IN32、第三晶体管T33和第四晶体管T34构成。当级传信号通过第一晶体管T31或第二晶体管T32到达锁存模块后，上一级GOA驱动电路输出的第二中间信号P(N-1)为低电平，下一级GOA驱动电路输出的第二中间信号P(N+1)为低电平，此时第三晶体管T33和第四晶体管T34打开，级传信号保存在锁存回路中。如图8所示，该锁存回路由第一反相器IN41、第二反相器IN42、第三晶体管T43和第四晶体管T44构成。当级传信号通过第一晶体管T41或第二晶体管T42到达锁存模块后，上一级GOA驱动电路输出的第一中间信号XP(N-1)为高电平，下一级GOA驱动电路输出的第一中间信号XP(N+1)为低电平，此时第三晶体管T43和第四晶体管T44打开，级传信号保存在锁存回路中。在本发明中，锁存模块不采用时钟控制信号控制，可以有效降低产生时钟控制信号的负载和电路的功耗。
根据本发明的一个实施例，该处理模块23包括一与非门NAND，其第一输入端连接锁存模块的输出端，第二输入端连接第一时序驱动信号CK3，输出端连接缓存模块并输出本级的第一中间信号P(N)，如图5-图8所示。
根据本发明的一个实施例，该缓存模块24包括串联的第三反相器IN23、第 四反相器IN24和第五反相器IN25，其中，第三反相器IN23的输入端连接处理模块，输出端连接第四反相器IN24的输入端；第四反相器IN24的输出端连接第五反相器IN25的输入端，并输出第二中间信号；第五反相器IN25的输出端输出栅极驱动信号，如图5-图8所示。
根据本发明的一个实施例，复位模块包括第六反相器IN26及与第六反相器IN26连接的第五晶体管T25，其中，第六反相器IN26的输出端连接缓存模块的输出端，输入端分别连接第五晶体管T25的漏极和第六反相器IN26的输入端；第五晶体管T25的源极引入第一控制信号，栅极引入复位信号。
如图9所示为图5-至图8所示电路的驱动框架图，该驱动框架图为单边驱动框架图，对应奇数行的扫描线，其中，单边GOA电路需要两根STV信号走线，分别用于第一级GOA电路Q点的上拉和最后一级GOA电路Q点的下拉；单边需要两根CK信号走线，用于栅极移位驱动信号的产生；单边需要一根RESET走线，用于每一级GOA电路的复位处理；单边需要一条VGH走线和一条VGL走线，用于CMOS GOA电路的驱动。
如图10为图9所示驱动框架的扫描驱动时序图，由时序图分析可知，本专利提供的GOA电路的工作原理为：当RESETt信号低电平脉冲信号来临时，所有的GOA电路进行复位处理，Q点复位后锁存低电平信号；当XP0低电平脉冲或者P0高电平脉冲信号来临时，Q点被充电至高电平，之后Q点锁存高电平信号；当CK3信号的高电平脉冲来临时，产生本级第一中间信号XP1；本级第一中间信号XP1经缓存模块处理为本级栅极驱动信号GATE1；当XP2的低电平脉冲活着P2的高电平脉冲信号来临时，Q点被充电至低电平，之后Q点一直锁存低电平信号，GOA电路稳定输出低电平栅极驱动信号。
如图11为根据本发明的一个实施例的第一种扫描驱动仿真示意图，如图12为根据本发明的一个实施例的第二种扫描驱动仿真示意图，由图11和图12可知，本发明的电路可以实现正向或反向输出扫描信号。
虽然本发明所揭露的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (10)

  1. 一种GOA驱动电路，包括：
    输入控制模块，用于输入级传信号；
    锁存模块，用于锁存输入的级传信号；
    处理模块，用于将所述锁存模块输出的级传信号处理为第一中间信号；
    缓存模块，用于缓存并处理所述第一中间信号为栅极驱动信号和第二中间信号，所述第一中间信号和所述第二中间信号的相位相反，
    其中，由上一级GOA驱动电路和下一级GOA驱动电路输出的所述第一中间信号和/或所述第二中间信号控制所述输入控制模块来输入级传信号，以及控制所述锁存模块锁存由所述输入控制模块输入的级传信号。
  2. 根据权利要求1所述的电路，其中，所述输入控制模块包括：
    第一晶体管，其为P型晶体管，栅极用于输入下一级GOA驱动电路输出的第一中间信号，源极用于输入第一控制信号，漏极连接所述锁存模块；
    第二晶体管，其为N型晶体管，栅极用于输入上一级GOA驱动电路输出的第二中间信号，源极用于输入第二控制信号，漏极连接所述锁存模块。
  3. 根据权利要求2所述的电路，其中，所述锁存模块包括：
    第一反相器，其输入端连接所述第一晶体管和所述第二晶体管的漏极，输出端连接所述处理模块；
    第三晶体管，其为P型晶体管，栅极用于输入上一级GOA驱动电路输出的第二中间信号，漏极连接所述第一反相器的输入端；
    第四晶体管，其为N型晶体管，栅极用于输入下一级GOA驱动电路输出的第一中间信号，漏极连接所述第三晶体管的源极；
    第二反相器，其输入端连接所述第一反相器的输出端，输出端连接所述第四晶体管的源极。
  4. 根据权利要求1所述的电路，其中，所述输入控制模块包括：
    第一晶体管，其为P型晶体管，栅极用于输入上一级GOA驱动电路输出的第一中间信号，源极用于输入第一控制信号，漏极连接所述锁存模块；
    第二晶体管，其为N型晶体管，栅极用于输入下一级GOA驱动电路输出的第二中间信号，源极用于输入第二控制信号，漏极连接所述锁存模块。
  5. 根据权利要求4所述的电路，其中，所述锁存模块包括：
    第一反相器，其输入端连接所述第一晶体管和所述第二晶体管的漏极；
    第二反相器，其输入端连接所述第一反相器的输出端，输出端连接所述处理模块；
    第三晶体管，其为N型晶体管，栅极用于输入上一级GOA驱动电路输出的第一中间信号，漏极连接所述第一反相器的输入端；
    第四晶体管，其为P型晶体管，栅极用于输入下一级GOA驱动电路输出的第二中间信号，漏极连接所述第三晶体管的源极，源极连接所述第二反相器的输出端。
  6. 根据权利要求1所述的电路，其中，所述输入控制模块包括：
    第一晶体管，其为N型晶体管，栅极用于输入上一级GOA驱动电路输出的第二中间信号，源极用于输入第二控制信号，漏极连接所述锁存模块；
    第二晶体管，其为N型晶体管，栅极用于输入下一级GOA驱动电路输出的第二中间信号，源极用于输入第二控制信号，漏极连接所述锁存模块。
  7. 根据权利要求6所述的电路，其中，所述锁存模块包括：
    第一反相器，其输入端连接所述第一晶体管的漏极，输出端连接所述处理模块；
    第三晶体管，其为P型晶体管，栅极用于输入上一级GOA驱动电路输出的第二中间信号，漏极连接所述第一反相器的输入端；
    第四晶体管，其为P型晶体管，栅极用于输入下一级GOA驱动电路输出的第二中间信号，源极连接所述第一反相器的输出端；
    第二反相器，其输入端连接所述第三晶体管的漏极，输出端连接所述第四晶体管的源极。
  8. 根据权利要求1所述的电路，其中，所述输入控制模块包括：
    第一晶体管，其为P型晶体管，栅极用于输入下一级GOA驱动电路输出的第一中间信号，源极用于输入第一控制信号，漏极连接所述锁存模块；
    第二晶体管，其为P型晶体管，栅极用于输入上一级GOA驱动电路输出的第一中间信号，源极用于输入第一控制信号，漏极连接所述锁存模块。
  9. 根据权利要求8所述的电路，其中，所述锁存模块包括：
    第一反相器，其输入端连接所述第一晶体管的漏极，输出端连接所述处理模块；
    第三晶体管，其为N型晶体管，栅极用于输入下一级GOA驱动电路输出的第一中间信号，漏极连接所述第一反相器的输入端；
    第四晶体管，其为N型晶体管，栅极用于输入上一级GOA驱动电路输出的第一中间信号，源极连接所述第一反相器的输出端；
    第二反相器，其输入端连接所述第四晶体管的漏极，输出端连接所述第三晶体管的源极。
  10. 根据权利要求1所述的电路，其中，
    所述处理模块包括一与非门，其第一输入端连接所述锁存模块的输出端，第二输入端连接第一时序驱动信号，输出端与所述缓存模块连接并输出所述第一中间信号，
    所述缓存模块包括串联的第三反相器、第四反相器和第五反相器，其中，
    所述第三反相器的输入端连接所述处理模块，输出端连接所述第四反相器的输入端；
    所述第四反相器的输出端连接所述第五反相器的输入端，并输出所述第二中间信号；
    所述第五反相器的输出端输出栅极驱动信号，
    所述复位模块包括第六反相器及与所述第六反相器连接的第五晶体管，其中，
    所述第六反相器的输出端连接所述缓存模块的输出端，输入端分别连接所述第五晶体管的漏极和所述第六反相器的输入端；
    所述第五晶体管的源极引入第一控制信号，栅极引入复位信号。
PCT/CN2016/112987 2016-11-28 2016-12-29 一种goa驱动电路 WO2018094817A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/326,575 US10373578B2 (en) 2016-11-28 2016-12-29 GOA driving circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201611061519 2016-11-28
CN201611061519.6 2016-11-28

Publications (1)

Publication Number Publication Date
WO2018094817A1 true WO2018094817A1 (zh) 2018-05-31

Family

ID=62194660

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/112987 WO2018094817A1 (zh) 2016-11-28 2016-12-29 一种goa驱动电路

Country Status (2)

Country Link
US (1) US10373578B2 (zh)
WO (1) WO2018094817A1 (zh)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110150169A1 (en) * 2009-12-22 2011-06-23 Au Optronics Corp. Shift register
CN104409054A (zh) * 2014-11-03 2015-03-11 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管goa电路
CN105096853A (zh) * 2015-07-02 2015-11-25 武汉华星光电技术有限公司 一种扫描驱动电路
CN105702223A (zh) * 2016-04-21 2016-06-22 武汉华星光电技术有限公司 减小时钟信号负载的cmos goa电路
CN106057131A (zh) * 2016-05-27 2016-10-26 武汉华星光电技术有限公司 扫描驱动电路及具有该电路的平面显示装置
CN106098015A (zh) * 2016-08-23 2016-11-09 武汉华星光电技术有限公司 栅极驱动电路
CN106409261A (zh) * 2016-11-29 2017-02-15 武汉华星光电技术有限公司 一种goa驱动电路
CN106782358A (zh) * 2016-11-29 2017-05-31 武汉华星光电技术有限公司 一种goa驱动电路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014153297A1 (en) * 2013-03-16 2014-09-25 Lawrence Livermore National Security, Llc Multi-electrode neural prothesis system
DE102014201742A1 (de) * 2014-01-31 2015-08-06 Johnson Controls Metals and Mechanisms GmbH & Co. KG Stellantrieb für ein kraftfahrzeug, insbesondere für einen kraftfahrzeugsitz
CN104700806B (zh) * 2015-03-26 2017-01-25 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路、显示面板及显示装置
CN104732940B (zh) * 2015-03-30 2017-03-15 深圳市华星光电技术有限公司 Cmos栅极驱动电路
US20170003997A1 (en) * 2015-07-01 2017-01-05 Dell Products, Lp Compute Cluster Load Balancing Based on Memory Page Contents
US9824658B2 (en) * 2015-09-22 2017-11-21 Shenzhen China Star Optoelectronics Technology Co., Ltd GOA circuit and liquid crystal display device
CN105355179B (zh) 2015-12-03 2018-03-02 武汉华星光电技术有限公司 一种扫描驱动电路及其显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110150169A1 (en) * 2009-12-22 2011-06-23 Au Optronics Corp. Shift register
CN104409054A (zh) * 2014-11-03 2015-03-11 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管goa电路
CN105096853A (zh) * 2015-07-02 2015-11-25 武汉华星光电技术有限公司 一种扫描驱动电路
CN105702223A (zh) * 2016-04-21 2016-06-22 武汉华星光电技术有限公司 减小时钟信号负载的cmos goa电路
CN106057131A (zh) * 2016-05-27 2016-10-26 武汉华星光电技术有限公司 扫描驱动电路及具有该电路的平面显示装置
CN106098015A (zh) * 2016-08-23 2016-11-09 武汉华星光电技术有限公司 栅极驱动电路
CN106409261A (zh) * 2016-11-29 2017-02-15 武汉华星光电技术有限公司 一种goa驱动电路
CN106782358A (zh) * 2016-11-29 2017-05-31 武汉华星光电技术有限公司 一种goa驱动电路

Also Published As

Publication number Publication date
US20180336858A1 (en) 2018-11-22
US10373578B2 (en) 2019-08-06

Similar Documents

Publication Publication Date Title
CN108389539B (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
US7420402B2 (en) Flip-flops, shift registers, and active-matrix display devices
JP4737627B2 (ja) スタティッククロックパルス発生器およびディスプレイ
KR102275425B1 (ko) 시프트 레지스터 및 그 구동 방법, 게이트 구동 회로, 및 디스플레이 디바이스
KR102043533B1 (ko) 게이트 구동 회로 및 시프트 레지스터
CN106409261B (zh) 一种goa驱动电路
WO2018205543A1 (zh) 移位寄存器、其驱动方法、栅极集成驱动电路及显示装置
WO2017107295A1 (zh) 适用于In Cell型触控显示面板的的GOA电路
US10923207B2 (en) Shift register unit and method for driving the same, gate driving circuit and display apparatus
WO2018040465A1 (zh) 一种goa驱动单元
WO2017054338A1 (zh) Cmos goa电路
WO2017181481A1 (zh) 减小时钟信号负载的cmos goa电路
JP7296729B2 (ja) シフトレジスター及びその駆動方法、ゲート駆動回路、並び表示装置
TWI505276B (zh) 移位暫存電路及移位暫存器
CN106782358B (zh) 一种goa驱动电路
JP2018510446A (ja) Ｎａｎｄラッチの駆動回路及びｎａｎｄラッチのシフトレジスタ
CN112102768B (zh) Goa电路及显示面板
JP2011049779A (ja) レベルシフト回路及びそれを用いたドライバと表示装置
WO2022160802A1 (zh) 移位寄存器及其控制方法、栅极驱动电路和显示面板
WO2017008488A1 (zh) 移位寄存单元、移位寄存器、栅极驱动电路和显示装置
WO2016106870A1 (zh) 一种液晶显示器驱动电路
TWI529692B (zh) 驅動電路和顯示裝置
WO2021135102A1 (zh) 时钟产生电路及应用其的锁存器和计算设备
WO2018094817A1 (zh) 一种goa驱动电路
TW201913614A (zh) 閘極驅動電路

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15326575

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16922111

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16922111

Country of ref document: EP

Kind code of ref document: A1