WO2018076741A1 - 移位寄存器及其驱动方法、显示装置 - Google Patents

移位寄存器及其驱动方法、显示装置 Download PDF

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Publication number
WO2018076741A1
WO2018076741A1 PCT/CN2017/090262 CN2017090262W WO2018076741A1 WO 2018076741 A1 WO2018076741 A1 WO 2018076741A1 CN 2017090262 W CN2017090262 W CN 2017090262W WO 2018076741 A1 WO2018076741 A1 WO 2018076741A1
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Prior art keywords
pull
output
node
terminal
shift register
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Ceased
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PCT/CN2017/090262
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English (en)
French (fr)
Inventor
王光兴
张斌
董殿正
张强
陈鹏名
张衎
解宇
王峥
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US15/750,679 priority Critical patent/US10665191B2/en
Publication of WO2018076741A1 publication Critical patent/WO2018076741A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • Embodiments of the present disclosure relate to a shift register, a method of driving the same, and a display device.
  • TFT-LCDs Thin film transistor liquid crystal displays
  • the driving circuit of the TFT-LCD mainly includes a gate driving circuit and a data driving circuit.
  • the data driving circuit is configured to sequentially latch the input data according to the timing of the clock signal and convert the latched data into an analog signal and input the data to the data line of the display panel.
  • the gate driving circuit is usually implemented by a shift register that converts a clock signal into an on/off voltage, which are respectively output to respective gate lines of the display panel.
  • a gate line on the display panel is typically docked with a shift register (ie, the stage of the shift register).
  • Progressive scanning of pixels in the display panel is achieved by causing the respective shift registers to sequentially output the turn-on voltage.
  • At least one embodiment of the present disclosure provides a shift register and a method of driving the same. By adding one input and two P-type transistors to suppress output noise and improve the stability of the operation, the lifetime of the TFT-LCD to which the shift register is applied can be extended.
  • a shift register comprising:
  • An input unit having a first end coupled to the first input of the shift register for use from the first input
  • the input end receives the first input signal, the second end is connected to the pull-up node, and the third end is connected to the first clock signal end;
  • the output unit has a first end connected to the second clock signal end, a second end connected to the pull-up node, and a third end connected to the output end of the shift register;
  • a reset unit the first end of which is connected to the reset signal end, the second end is connected to the pull-up node, the third end is connected to the first power supply voltage end, and the fourth end is connected to the output end of the shift register;
  • a pull-down unit the first end of which is connected to the pull-down node, the second end is connected to the output end of the shift register, the third end is connected to the pull-up node, and the fourth end is connected to the first power supply voltage end;
  • the pull-down control unit has a first end connected to the first clock signal end, a second end connected to the second clock signal end, a third end connected to the pull-down node, a fourth end connected to the first power voltage end, and a fifth end connected to the first power supply voltage end Pull-up node connection;
  • a first noise reduction unit having a first end coupled to the second input of the shift register for receiving a second input signal from the second input, the second end being coupled to the first input of the shift register Receiving a first input signal from the first input end, the third end is connected to the output end of the shift register, and the fourth end is connected to the first power supply voltage end, configured to continuously lower the shift register when there is no input signal The noise at the output.
  • a driving method of a shift register comprising: an input unit, an output unit, a reset unit, a pull-down unit, a pull-down control unit, and a first noise reduction unit, the method comprising:
  • the first noise reduction unit continuously reduces the noise at the output of the shift register when there is no input signal.
  • a display device including the above shift register is provided.
  • one input terminal and two P-type transistors are added to suppress output noise caused by voltage abnormality at the pull-up node, thereby extending the TFT-LCD to which the shift register is applied. The service life.
  • FIG. 1 shows a block diagram of a shift register in accordance with an embodiment of the present disclosure.
  • FIG. 2 shows an example circuit configuration diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 3 shows an operational timing diagram of an example circuit of the shift register of FIG. 2.
  • FIG. 4 illustrates a display device in accordance with an embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or He has the same features.
  • the connection modes of the drain and the source of each transistor are interchangeable. Therefore, the drain and source of each transistor in the embodiment of the present disclosure are practically indistinguishable.
  • the drain and source of each transistor in the embodiment of the present disclosure are practically indistinguishable.
  • the gate one of which is called the drain and the other is called the source.
  • At least one embodiment of the present disclosure utilizes a P-type TFT cell to implement GOA, which can reduce GOA circuit related defects, improve GOA circuit stability, and eliminate charge residual charge in the GOA circuit.
  • FIG. 1 shows a block diagram of a shift register in accordance with one embodiment of the present disclosure.
  • the shift register 100 includes an input unit 11, an output unit 12, a reset unit 13, a pull down unit 14, a pull down control unit 15, and a first noise reduction unit 16.
  • the first end of the input unit 11 is connected to the first input terminal INPUT of the shift register for receiving the first input signal from the first input terminal INPUT, the second end is connected to the pull-up node PU, and the third end is first
  • the clock signal terminal CLKB is connected.
  • the input unit 11 is configured to receive the first when the first input signal of the first input terminal INPUT is at the active input level, or when the first clock signal at the first clock signal terminal CLKB is at the active control level The input signal is passed to the pull-up node PU.
  • the first end of the output unit 12 is connected to the second clock signal terminal CLK, the second end is connected to the pull-up node PU, and the third end is connected to the output terminal OUTPUT of the shift register.
  • the output unit 12 is configured to output a second clock signal of the second clock signal terminal CLK to the output terminal OUTPUT when the pull-up signal at the pull-up node PU is at an active pull-up level.
  • the first end of the reset unit 13 is connected to the reset signal terminal RESET, the second end is connected to the pull-up node PU, the third end is connected to the first power supply voltage terminal VSS, and the fourth end is connected to the output terminal OUTPUT of the shift register.
  • the reset unit 13 is configured to reset the pull-up signal at the pull-up node PU to the power supply voltage of the first power supply voltage terminal VSS when the reset signal of the reset signal terminal RESET is at the active control level, and output signal of the output terminal OUTPUT Reset to the supply voltage of the first supply voltage terminal VSS.
  • the first end of the pull-down unit 14 is connected to the pull-down node PD, the second end is connected to the output terminal OUTPUT of the shift register, the third end is connected to the pull-up node PU, and the fourth end is connected to the first power supply voltage terminal VSS.
  • the pull-down unit 14 is configured to pull the output terminal OUTPUT and the pull-up node PU to the first power supply when the pull-down signal at the pull-down node PD is at a valid pull-down level The power supply voltage of the VSS terminal.
  • the first end of the pull-down control unit 15 is connected to the first clock signal terminal CLKB, the second end is connected to the second clock signal terminal CLK, the third end is connected to the pull-down node PD, and the fourth end is connected to the first power supply voltage terminal to the VSS.
  • the fifth end is connected to the pull-up node PU.
  • the pull-down control unit 15 is configured to control whether the pull-down unit 14 operates. For example, the pull-down control unit 15 generates at the pull-down node PD when the pull-up signal at the pull-up node PU is at the active pull-up level, or when the first clock signal at the first clock signal terminal CLKB is at the active control level.
  • the first end of the first noise reduction unit 16 is connected to the second input terminal INPUTB of the shift register for receiving a second input signal from the second input terminal INPUTB, the second end and the first input end of the shift register
  • the INPUT connection is for receiving a first input signal from the first input terminal INPUT
  • the third terminal is connected to the output terminal OUTPUT of the shift register
  • the fourth terminal is connected to the first power supply voltage terminal VSS.
  • the noise reduction unit 16 is configured to continuously reduce the noise at the output of the shift register when there is no input signal.
  • the first clock signal of the first clock signal terminal CLKB is inverted with the second clock signal of the second clock signal terminal CLK.
  • the first power supply voltage terminal VSS is a low power supply voltage terminal.
  • the shift register further includes a second noise reduction unit 17.
  • the first end of the second noise reduction unit 17 is connected to the first clock signal terminal CLKB, the second end is connected to the output terminal OUTPUT of the shift register, and the third end is connected to the first power supply voltage terminal VSS.
  • the second noise reduction unit 17 is configured to pull down an output signal of the output terminal OUTPUT of the shift register to the first power voltage terminal when the first clock signal at the first clock signal terminal CLKB is at an active control level VSS supply voltage.
  • FIG. 2 shows an example circuit configuration diagram of a shift register according to an embodiment of the present disclosure.
  • the first noise reduction transistor M13 and the second noise reduction transistor M14 in FIG. 2 are P-type transistors, and the other transistors are all N-type transistors as an example.
  • the N-type transistor is turned on when the gate input is high level, and the P-type transistor is turned on when the gate input is low level.
  • the N type can be selected as needed.
  • Transistor or P-type transistor Corresponding units or sub-circuits, the embodiments of the present disclosure do not limit this.
  • the input unit 11 includes a first input transistor M1 and a second input transistor M2.
  • the gate and the first pole of the first input transistor M1 are connected to the first input terminal INPUT, and the second pole is connected to the pull-up node PU.
  • the gate of the second input transistor M2 is connected to the first clock signal terminal CLKB, the first pole is connected to the INPUT, and the second pole is connected to the pull-up node PU.
  • the first input signal of the first input terminal INPUT is at a high level
  • the first input transistor M1 is turned on, and the first input signal of the first input terminal INPUT is transmitted to the pull-up node PU.
  • the second input transistor M2 is turned on, and the first input signal of the first input terminal INPUT is transmitted to the pull-up node PU.
  • the output unit 12 includes an output transistor M3 and a first capacitor C1.
  • the gate of the output transistor M3 is connected to the pull-up node PU, the first pole is connected to the second clock signal terminal CLK, and the second pole is connected to the output terminal OUTPUT.
  • the first end of the first capacitor C1 is connected to the pull-up node PU, and the second end is connected to the output terminal OUTPUT.
  • the reset unit 13 includes a node reset transistor M4 and an output reset transistor M5.
  • the gate of the node reset transistor M4 is connected to the reset signal terminal RESET, the first pole is connected to the pull-up node PU, and the second pole is connected to the first power supply voltage terminal VSS.
  • the gate of the output reset transistor M5 is connected to the reset signal terminal RESET, the first pole is connected to the output terminal OUTPUT, and the second pole is connected to the first power supply voltage terminal VSS.
  • the node reset transistor M4 When the reset signal at the reset signal terminal RESET is at a high level, the node reset transistor M4 is turned on, the pull-up signal at the pull-up node PU is reset to the power supply voltage of the first power supply voltage terminal VSS, and the output reset transistor M5 is turned on. The output signal of the output terminal OUTPUT is reset to the power supply voltage of the first power supply voltage terminal VSS.
  • pull-down unit 14 includes a node pull-down transistor M6 and an output pull-down transistor M7.
  • the gate of the node pull-down transistor M6 is connected to the pull-down node PD, the first pole is connected to the pull-up node PU, and the second pole is connected to the first power supply voltage terminal VSS.
  • the gate of the output pull-down transistor M7 is connected to the pull-down node PD, the first pole is connected to the output terminal OUTPUT, and the second pole is connected to the first power supply voltage terminal VSS.
  • the node pull-down transistor M6 and the output pull-down transistor M7 are turned on, respectively outputting an output signal of the output terminal OUTPUT of the shift register and a pull-up at the pull-up node PU Signal down to the first power source
  • the power supply voltage at the voltage terminal VSS When the pull-down signal at the pull-down node PD is at a high level, the node pull-down transistor M6 and the output pull-down transistor M7 are turned on, respectively outputting an output signal of the output terminal OUTPUT of the shift register and a pull-up at the pull-up node PU Signal down to the first power source The power supply voltage at the voltage terminal VSS.
  • the pull-down control unit 15 includes a first pull-down control transistor M8, a second pull-down control transistor M9, a third pull-down control transistor M10, a fourth pull-down control transistor M11, and a fifth pull-down control transistor M12.
  • the gate of the first pull-down control transistor M8 is connected to the pull-down control node PD_CN, the first pole is connected to the second clock signal terminal CLK, and the second pole is connected to the pull-down node PD.
  • the gate of the second pull-down control transistor M9 is connected to the pull-up node PU, the first pole is connected to the pull-down node PD, and the second pole is connected to the first power supply voltage terminal VSS.
  • the gate of the third pull-down control transistor M10 is connected to the first clock signal terminal CLKB, the first pole is connected to the pull-down node PD, and the second pole is connected to the first power supply voltage terminal VSS.
  • the gate of the fourth pull-down control transistor M11 is connected to the first clock signal terminal CLKB, the first pole is connected to the pull-down control node PD_CN, and the second pole is connected to the first power supply voltage terminal VSS.
  • the gate and the first pole of the fifth pull-down control transistor M12 are connected to the second clock signal terminal CLK, and the second pole is connected to the pull-down control node PD_CN.
  • the second pull-down control transistor M9 is turned on, or when the first clock signal at the first clock signal terminal CLKB is at a high level, the third pull-down control The transistor M10 is turned on, thereby generating a pull-down signal at a low level at the pull-down node PD, and the node pull-down transistor M6 and the output pull-down transistor M7 are not turned on.
  • the first noise reduction unit 16 includes a first noise reduction transistor M13 and a second noise reduction transistor M14.
  • the gate of the first noise reduction transistor M13 is connected to the second input terminal INPUTB, and the first pole is connected to the output terminal OUTPUT.
  • the gate of the second noise reduction transistor M14 is connected to the first input terminal INPUT, the first pole is connected to the second pole of the first noise reduction transistor M13, and the second pole is connected to the first power supply voltage terminal VSS.
  • the first noise reduction transistor M13 and the second noise reduction transistor M14 are both P-type transistors, when there is no input signal at the first input terminal INPUT and the second input terminal INPUTB, the first noise reduction transistor M13 and the second drop The noise transistor M14 is both turned on, so that the output signal of the output terminal OUTPUT of the shift register is continuously pulled down to the power supply voltage of the first power supply voltage terminal VSS, thereby reducing the residual charge in the first capacitor C1 to the pull-up node PU. And the influence of the voltage of the output terminal OUTPUT, reducing the noise of the output terminal OUTPUT.
  • the pull-up signal at the pull-up node PU should be at a high level, and the first noise reduction transistor M13 and/or the second noise reduction transistor M14 are turned off; when the first input terminal INPUT and the second input terminal INPUTB are both When inputting a low level input signal, the pull-up signal at the pull-up node PU should be at a low level, and the first noise reduction transistor M13 and the second noise reduction transistor M14 are turned on to eliminate the residual charge in the first capacitor C1.
  • the influence of the voltage of the pull-up node PU and the output terminal OUTPUT reduces the noise of the output terminal OUTPUT, which can improve the stability of the GOA unit.
  • an input terminal INPUTB and two P-type transistors are added to suppress output noise caused by a voltage abnormality at the pull-up node PU, thereby extending the TFT to which the shift register is applied. - The life of the LCD.
  • the shift register further includes a second noise reduction unit 17.
  • the second noise reduction unit 17 includes a third noise reduction transistor M15.
  • the gate of the third noise reduction transistor M15 is connected to the first clock signal terminal CLKB, the first pole is connected to the output terminal OUTPUT, and the second pole is connected to the first power supply voltage terminal VSS.
  • the third noise reduction transistor M15 is turned on, and the output signal of the output terminal OUTPUT of the shift register is pulled down to the first power supply voltage terminal VSS.
  • the power supply voltage reduces the noise at the output.
  • FIG. 3 shows an operational timing diagram of an example circuit of the shift register of FIG. 2.
  • the driving method of the shift register in FIG. 2 will be described below with reference to FIGS. 2 and 3.
  • the first input signal of the first input terminal INPUT, the second input signal of the second input terminal INPUTB, and the first clock signal at the first clock signal terminal CLKB are both at a low level.
  • the first input transistor M1 and the second input transistor M2 are both turned off, although the second clock signal at the second clock signal terminal CLK is at a high level, but since the pull-up signal at the pull-up node PU is at a low level, the output transistor M3 is turned off, and the output terminal OUTPUT outputs a low level.
  • the first noise reduction transistor M13 and the second noise reduction transistor M14 are both turned on, and the output signal of the output terminal OUTPUT is pulled down to the power supply voltage of the first power supply voltage terminal VSS.
  • the first input signal of the first input terminal INPUT and the first clock signal at the first clock signal terminal CLKB are both at a high level
  • the second input signal of the second input terminal INPUTB is
  • the second clock signal at the second clock signal terminal CLK is at a low level.
  • the first input transistor M1 and the second input transistor M2 are turned on, and the high level of the first input terminal INPUT is transmitted to the pull-up node PU, and at this time, the pull-up node PU is at the first high voltage, so that the output transistor M3 is turned on. Since the second clock signal of the second clock signal terminal CLK is at a low level, the output end OUTPUT output is low.
  • the first noise reduction transistor M13 is turned on
  • the second noise reduction transistor M14 is turned off, and the first power supply voltage terminal VSS does not affect the output signal of the output terminal OUTPUT.
  • the first input signal of the first input terminal INPUT and the first clock signal at the first clock signal terminal CLKB are both at a low level
  • the second input signal of the second input terminal INPUTB is
  • the second clock signal at the second clock signal terminal CLK is at a high level.
  • the first input transistor M1 and the second input transistor M2 are turned off, the reset signal terminal RESET is at a low level, the node reset transistor M4 is kept off, the pull-up node PU continues to turn on the output transistor M3, and the second clock signal terminal CLK is second.
  • the clock signal is at a high level
  • the output terminal OUTPUT outputs a high level.
  • the pull-up node PU Due to the voltage coupling of the first capacitor C1, the pull-up node PU is raised from the first high voltage to the second high voltage, further improving the output transistor M3. Charging ability to ensure pixel charging.
  • the second pull-down control transistor M9 since the pull-up node PU is still at a high level, the second pull-down control transistor M9 remains turned on, and the pull-down node PD is still at a low level, and accordingly the node pull-down transistor M6 and the output pull-down transistor M7 remain cutoff.
  • the first noise reduction transistor M13 is turned off, the second noise reduction transistor M14 is turned on, and the first power supply voltage terminal VSS does not affect the output signal of the output terminal OUTPUT.
  • the first input signal of the first input terminal INPUT, the second input signal of the second input terminal INPUTB, and the second clock signal at the second clock signal terminal CLK are both at a low level.
  • the first clock signal at the first clock signal terminal CLKB and the reset signal at the reset signal terminal RESET are both at a high level.
  • the input transistor M1 remains off, and the second input transistor M2 is turned on, passing the low level of the first input terminal INPUT to the pull-up node PU.
  • the reset signal of the reset signal terminal RESET is at a high level, and the node reset transistor M4 and the output reset transistor M5 are turned on to reset the pull-up signal at the pull-up node PU and the output signal of the output terminal OUTPUT to the first power supply voltage terminal VSS, respectively. Power supply voltage.
  • the second pull-down control transistor M9 is turned off. Since the first clock signal of the first clock signal terminal CLKB is at a high level, the third pull-down control transistor M10 is turned on, so that the pull-down node PD is still at a low level, and both the node pull-down transistor M6 and the output pull-down transistor M7 remain off.
  • the third noise reduction transistor M15 is turned on, and the output signal of the output terminal OUTPUT of the shift register is pulled down to the power supply voltage of the first power supply voltage terminal VSS to reduce the noise at the output end.
  • the first noise reduction transistor M13 and the second noise reduction transistor M14 are both turned on, and the output signal of the output terminal OUTPUT is pulled down to the power supply voltage of the first power supply voltage terminal VSS, thereby reducing the noise at the output end.
  • the first input signal of the first input terminal INPUT, the second input signal of the second input terminal INPUTB, and the first clock signal at the first clock signal terminal CLKB are both at a low level.
  • the second clock signal at the second clock signal terminal CLK is at a high level.
  • the third pull-down control transistor M10, the fourth pull-down control transistor M11, and the third noise reduction transistor M15 are all turned off. Since the pull-up node PU is at a low level, the second pull-down control transistor M9 is turned off.
  • the first pull-down control transistor M8 and the fifth pull-down control transistor M12 are both turned on, so that the pull-down node PD is at a high level, the node pull-down transistor M6 and The output pull-down transistor M7 is turned on, and the output signal of the output terminal OUTPUT of the shift register and the pull-up signal at the pull-up node PU are pulled down to the power supply voltage of the first power supply voltage terminal VSS.
  • the first noise reduction transistor M13 and the second noise reduction transistor M14 are both kept turned on, reducing the noise at the output end.
  • the third pull-down control transistor M10 is turned on, so that the pull-down node PD is at a low level, and the node pull-down transistor M6 and the output pull-down transistor M7 are both turned off.
  • the third noise reduction transistor M15 is turned on to reduce noise at the output end.
  • the first noise reduction transistor M13 and the second noise reduction transistor M14 are both kept turned on, reducing the noise at the output end.
  • the pull-up node PU is always at a low level
  • the level at the pull-down node PD alternates between high and low levels
  • the first noise reduction transistor M13 and the second noise reduction transistor M14 remain Turn on, continuously reduce the noise of the output OUTPUT.
  • the shift register receives the high level signal of the first input terminal INPUT and re-executes the second phase.
  • the first power supply voltage terminal VSS is a low power supply voltage terminal.
  • the first clock signal of the first clock signal terminal CLKB is inverted with the second clock signal of the second clock signal terminal CLK.
  • the shift register 100 includes an input unit 11, an output unit 12, a reset unit 13, a pull-down unit 14, a pull-down control unit 15, and a first noise reduction unit 16.
  • the method includes the following operations.
  • the received input signal is passed to the pull-up node PU by the input unit 11; the second clock signal of the second clock signal terminal CLK is outputted by the output unit 12 to the output of the shift register OUTPUT; reset signal 13 resets the pull-up signal at the pull-up node PU to the power supply voltage of the first power supply voltage terminal VSS and resets the output signal of the output terminal OUTPUT of the shift register to the power supply voltage VSS of the first power supply voltage terminal Controlling whether the pull-down unit 14 operates by the pull-down control unit 15; pulling down the output signal of the output terminal OUTPUT of the shift register and the pull-up signal at the pull-up node PU to the first power supply by the pull-down unit 14
  • the power supply voltage of the voltage terminal VSS; and the noise of the output terminal OUTPUT of the shift register is continuously reduced by the first noise reduction unit 16 when there is no input signal.
  • the shift register 100 further includes a second noise reduction unit 17, the method further comprising: pulling, by the second noise reduction unit 17, an output signal of the output terminal OUTPUT of the shift register to the first A power supply voltage at the supply voltage terminal VSS.
  • the first power supply voltage terminal VSS is a low power supply voltage terminal.
  • one input terminal and two P-type transistors are added to suppress output noise caused by an abnormal voltage at the pull-up node, thereby extending the TFT to which the shift register is applied. - The life of the LCD.
  • FIG. 4 shows a schematic view of the display device.
  • the display device 200 includes a gate driver 210, a data driver 220, and a display panel 230.
  • the gate driver 210 and the data driver 220 are respectively signal-connected to the display panel 230 through gate lines and data lines, respectively.
  • the gate driver 210 includes at least one shift register 211, which may be the shift register of any of the above embodiments.
  • the display panel 230 may be a liquid crystal display panel, an organic light emitting diode display panel, an electronic paper display panel, or the like, which is not limited by the embodiments of the present disclosure.

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Abstract

一种移位寄存器（100）及其驱动方法、显示装置。该移位寄存器(100)包含：输入单元(11)，连接该移位寄存器(100)的第一输入端(INPUT)、上拉节点(PU)和第一时钟信号端(CLKB)；输出单元(12)，连接第二时钟信号端(CLK)、上拉节点(PU)和该移位寄存器(100)的输出端(OUTPUT)；复位单元(13)，连接复位信号端(RESET)、上拉节点(PU)、第一电源电压端(VSS)和输出端(OUTPUT)；下拉单元(14)，连接下拉节点(PD)、输出端(OUTPUT)、上拉节点(PU)和第一电源电压端(VSS)；下拉控制单元(15)，连接第一时钟信号端(CLKB)、第二时钟信号端(CLK)、下拉节点(PD)、第一电源电压端(VSS)和上拉节点(PU)；第一降噪单元(16)，连接该移位寄存器(100)的第二输入端(INPUTB)、第一输入端(INPUT)、输出端(OUTPUT)和第一电源电压端(VSS)。该移位寄存器(100)可以有效降低输出端(OUTPUT)噪声。

Description

移位寄存器及其驱动方法、显示装置 技术领域
本公开的实施例涉及一种移位寄存器及其驱动方法、显示装置。
背景技术
薄膜晶体管液晶显示器(TFT-LCD)广泛应用于生产生活的各个领域，其采用M*N点排列的逐行扫描矩阵显示。在进行显示时，TFT-LCD通过驱动电路来驱动显示面板中的各个像素进行显示。TFT-LCD的驱动电路主要包含栅极驱动电路和数据驱动电路。数据驱动电路用于依据时钟信号定时将输入的数据顺序锁存并将锁存的数据转换成模拟信号后输入到显示面板的数据线。栅极驱动电路通常用移位寄存器来实现，所述移位寄存器将时钟信号转换成开启/断开电压，分别输出到显示面板的各条栅线上。显示面板上的一条栅线通常与一个移位寄存器(即移位寄存器的一级)对接。通过使得各个移位寄存器依序轮流输出开启电压，实现对显示面板中像素的逐行扫描。
另一方面，随着平板显示的发展，高分辨率、窄边框成为发展的趋势。针对这一趋势，出现了阵列基板栅极驱动(Gate Driver on Array，GOA)技术。GOA技术直接将TFT-LCD的栅极驱动电路集成制作在阵列基板上，由此来代替在面板外沿邦定的、由硅芯片制作的驱动芯片。由于该技术可以将驱动电路直接做在阵列基板上，面板周围无需再粘接IC和布线，减少了面板的制作程序，降低了产品成本，同时提高了TFT-LCD面板的集成度，使面板实现窄边框和高分辨率。
发明内容
本公开的至少一个实施例提供了一种移位寄存器及其驱动方法。通过增加一个输入端和两个P型晶体管来抑制输出端噪声，提高工作的稳定性，从而可以延长应用该移位寄存器的TFT-LCD的使用寿命。
根据本公开的一方面，公开了一种移位寄存器，包含：
输入单元，其第一端与该移位寄存器的第一输入端连接用于从该第一输 入端接收第一输入信号，第二端与上拉节点连接，第三端与第一时钟信号端连接；
输出单元，其第一端与第二时钟信号端连接，第二端与上拉节点连接，第三端与该移位寄存器的输出端连接；
复位单元，其第一端与复位信号端连接，第二端与上拉节点连接，第三端与第一电源电压端连接，第四端与该移位寄存器的输出端连接；
下拉单元，其第一端与下拉节点连接，第二端与该移位寄存器的输出端连接，第三端与上拉节点连接，第四端与第一电源电压端连接；
下拉控制单元，其第一端与第一时钟信号端连接，第二端与第二时钟信号端连接，第三端与下拉节点连接，第四端与第一电源电压端连接，第五端与上拉节点连接；以及
第一降噪单元，其第一端与该移位寄存器的第二输入端连接用于从该第二输入端接收第二输入信号，第二端与该移位寄存器的第一输入端连接用于从该第一输入端接收第一输入信号，第三端与该移位寄存器的输出端连接，第四端与第一电源电压端连接，配置为在无输入信号时持续降低该移位寄存器的输出端的噪声。
根据本公开的又一实施例提供了一种移位寄存器的驱动方法，该移位寄存器包含输入单元、输出单元、复位单元、下拉单元、下拉控制单元和第一降噪单元，该方法包含：
由输入单元将所接收的输入信号传递到上拉节点；
由输出单元将第二时钟信号端的第二时钟信号输出到该移位寄存器的输出端；
由复位单元将上拉节点处的上拉信号复位至第一电源电压端的电源电压以及将该移位寄存器的输出端的输出信号复位至第一电源电压端的电源电压；
由下拉控制单元控制下拉单元是否进行操作；
由下拉单元将所述移位寄存器的输出端的输出信号和所述上拉节点处的上拉信号下拉至所述第一电源电压端的电源电压；以及
由第一降噪单元在无输入信号时持续降低该移位寄存器的输出端的噪声。
根据本公开的再一实施例提供了一种显示装置，该显示装置包括上述移位寄存器。
在本公开至少一个实施例的移位寄存器中，增加了一个输入端和两个P型晶体管来抑制上拉节点处电压异常导致的输出端噪声，从而可以延长应用该移位寄存器的TFT-LCD的使用寿命。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1示出了根据本公开实施例的移位寄存器的框图。
图2示出了根据本公开实施例的移位寄存器的一种示例电路结构图。
图3示出了图2中的移位寄存器的示例电路的操作时序图。
图4示出了根据本公开实施例的显示装置。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其 他特性相同的器件。在本实施例中，每个晶体管的漏极和源极的连接方式可以互换，因此，本公开实施例中各晶体管的漏极、源极实际是没有区别的。这里，仅仅是为了区分晶体管除栅极之外的两极，而将其中一极称为漏极，另一极称为源极。
传统GOA电路输出端存在噪声。本公开的至少一个实施例利用P型TFT单元来实现GOA，可以减少GOA电路相关不良，提高GOA电路稳定性，消除GOA电路中的电容残留的电荷。
图1示出了根据本公开一个实施例的移位寄存器的框图。如图1所示，在一个实施例中，该移位寄存器100包含输入单元11、输出单元12、复位单元13、下拉单元14、下拉控制单元15和第一降噪单元16。
输入单元11的第一端与该移位寄存器的第一输入端INPUT连接用于从该第一输入端INPUT接收第一输入信号，第二端与上拉节点PU连接，第三端与第一时钟信号端CLKB连接。该输入单元11被配置为在第一输入端INPUT的第一输入信号处于有效输入电平时，或者在第一时钟信号端CLKB处的第一时钟信号处于有效控制电平时，将所接收的第一输入信号传递到上拉节点PU。
输出单元12的第一端与第二时钟信号端CLK连接，第二端与上拉节点PU连接，第三端与该移位寄存器的输出端OUTPUT连接。该输出单元12被配置来在上拉节点PU处的上拉信号处于有效上拉电平时将第二时钟信号端CLK的第二时钟信号输出到输出端OUTPUT。
复位单元13的第一端与复位信号端RESET连接，第二端与上拉节点PU连接，第三端与第一电源电压端VSS连接，第四端与该移位寄存器的输出端OUTPUT连接。该复位单元13被配置来在复位信号端RESET的复位信号处于有效控制电平时将上拉节点PU处的上拉信号复位至第一电源电压端VSS的电源电压，以及将输出端OUTPUT的输出信号复位至第一电源电压端VSS的电源电压。
下拉单元14的第一端与下拉节点PD连接，第二端与该移位寄存器的输出端OUTPUT连接，第三端与上拉节点PU连接，第四端与第一电源电压端VSS连接。该下拉单元14被配置来在下拉节点PD处的下拉信号处于有效下拉电平时将所述输出端OUTPUT和所述上拉节点PU下拉至所述第一电源电 压端VSS的电源电压。
下拉控制单元15的第一端与第一时钟信号端CLKB连接，第二端与第二时钟信号端CLK连接，第三端与下拉节点PD连接，第四端与第一电源电压端连接VSS，第五端与上拉节点PU连接。该下拉控制单元15被配置为控制下拉单元14是否进行操作。例如，下拉控制单元15在上拉节点PU处的上拉信号处于有效上拉电平时，或在第一时钟信号端CLKB处的第一时钟信号处于有效控制电平时，在下拉节点PD处产生处于非有效下拉电平的下拉信号，而在上拉节点PU处的上拉信号处于非有效上拉电平时并且在第二时钟信号端CLK处的第二时钟信号处于有效控制电平时，在下拉节点PD处产生处于有效下拉电平的下拉信号。
第一降噪单元16的第一端与该移位寄存器的第二输入端INPUTB连接用于从该第二输入端INPUTB接收第二输入信号，第二端与该移位寄存器的第一输入端INPUT连接用于从该第一输入端INPUT接收第一输入信号，第三端与该移位寄存器的输出端OUTPUT连接，第四端与第一电源电压端VSS连接。该降噪单元16被配置为在无输入信号时持续降低该移位寄存器的输出端的噪声。
所述第一时钟信号端CLKB的第一时钟信号与第二时钟信号端CLK的第二时钟信号反相。
第一电源电压端VSS是低电源电压端。
如图1所示，在另一个实施例中，该移位寄存器进一步包含第二降噪单元17。第二降噪单元17的第一端与第一时钟信号端CLKB连接，第二端与该移位寄存器的输出端OUTPUT连接，第三端与第一电源电压端VSS连接。第二降噪单元17被配置为在第一时钟信号端CLKB处的第一时钟信号处于有效控制电平时，将所述移位寄存器的输出端OUTPUT的输出信号下拉至所述第一电源电压端VSS的电源电压。
图2示出了根据本公开实施例的移位寄存器的一种示例电路结构图。下面以图2中的第一降噪晶体管M13和第二降噪晶体管M14为P型晶体管，其它晶体管均为N型晶体管为例进行说明。如本领域技术人员所熟知的，N型晶体管在栅极输入高电平时导通，P型晶体管在栅极输入低电平时导通，在本公开的至少一个实施例中可以根据需要选择N型晶体管或P型晶体管实 现相应的单元或子电路，本公开的实施例对此不作限制。
如图2所示，在一个实施例中，例如，输入单元11包括第一输入晶体管M1和第二输入晶体管M2。第一输入晶体管M1的栅极和第一极与第一输入端INPUT连接，第二极与上拉节点PU连接。第二输入晶体管M2的栅极与第一时钟信号端CLKB连接，第一极与INPUT连接，第二极与上拉节点PU连接。在第一输入端INPUT的第一输入信号处于高电平时，第一输入晶体管M1导通，将第一输入端INPUT的第一输入信号传递到上拉节点PU。或者，在第一时钟信号端CLKB处的第一时钟信号处于高电平时，第二输入晶体管M2导通，将第一输入端INPUT的第一输入信号传递到上拉节点PU。
在一个实施例中，例如，输出单元12包括输出晶体管M3和第一电容C1。输出晶体管M3的栅极与上拉节点PU连接，第一极与第二时钟信号端CLK连接，第二极与输出端OUTPUT连接。第一电容C1的第一端与上拉节点PU连接，第二端与输出端OUTPUT连接。在上拉节点PU处的上拉信号处于高电平时，输出晶体管M3导通，将第二时钟信号端CLK的第二时钟信号输出到输出端OUTPUT。
在一个实施例中，例如，复位单元13包括节点复位晶体管M4和输出复位晶体管M5。节点复位晶体管M4的栅极与复位信号端RESET连接，第一极与上拉节点PU连接，第二极与第一电源电压端VSS连接。输出复位晶体管M5的栅极与所述复位信号端RESET连接，第一极与所述输出端OUTPUT连接，第二极与所述第一电源电压端VSS连接。在复位信号端RESET处的复位信号处于高电平时，节点复位晶体管M4导通，将上拉节点PU处的上拉信号复位至第一电源电压端VSS的电源电压，并且输出复位晶体管M5导通，将输出端OUTPUT的输出信号复位至第一电源电压端VSS的电源电压。
在一个实施例中，例如，下拉单元14包括节点下拉晶体管M6和输出下拉晶体管M7。节点下拉晶体管M6的栅极与下拉节点PD连接，第一极与上拉节点PU连接，第二极与第一电源电压端VSS连接。输出下拉晶体管M7的栅极与下拉节点PD连接，第一极与输出端OUTPUT连接，第二极与第一电源电压端VSS连接。在下拉节点PD处的下拉信号处于高电平时，节点下拉晶体管M6和输出下拉晶体管M7导通，分别将所述移位寄存器的输出端OUTPUT的输出信号和所述上拉节点PU处的上拉信号下拉至所述第一电源 电压端VSS的电源电压。
在一个实施例中，例如，下拉控制单元15包括第一下拉控制晶体管M8、第二下拉控制晶体管M9、第三下拉控制晶体管M10、第四下拉控制晶体管M11和第五下拉控制晶体管M12。第一下拉控制晶体管M8的栅极和下拉控制节点PD_CN连接，第一极与第二时钟信号端CLK连接，第二极与下拉节点PD连接。第二下拉控制晶体管M9的栅极与上拉节点PU连接，第一极与下拉节点PD连接，第二极与第一电源电压端VSS连接。第三下拉控制晶体管M10的栅极与第一时钟信号端CLKB连接，第一极与下拉节点PD连接，第二极与第一电源电压端VSS连接。第四下拉控制晶体管M11的栅极与第一时钟信号端CLKB连接，第一极与下拉控制节点PD_CN连接，第二极与第一电源电压端VSS连接。第五下拉控制晶体管M12的栅极和第一极与第二时钟信号端CLK连接，第二极与下拉控制节点PD_CN连接。例如，在上拉节点PU处的上拉信号PU处于高电平时，第二下拉控制晶体管M9导通，或在第一时钟信号端CLKB处的第一时钟信号处于高电平时，第三下拉控制晶体管M10导通，从而在下拉节点PD处产生处于低电平的下拉信号，节点下拉晶体管M6和输出下拉晶体管M7不导通。而在上拉节点PU处的上拉信号处于低电平时并且在第二时钟信号端CLK处的第二时钟信号处于高电平时，在下拉节点PD处产生处于高的下拉信号，节点下拉晶体管M6和输出下拉晶体管M7导通。
在一个实施例中，例如，第一降噪单元16包括第一降噪晶体管M13和第二降噪晶体管M14。第一降噪晶体管M13的其栅极与第二输入端INPUTB连接，第一极与输出端OUTPUT连接。第二降噪晶体管M14的栅极与第一输入端INPUT连接，第一极与第一降噪晶体管M13的第二极连接，第二极与第一电源电压端VSS连接。由于第一降噪晶体管M13和第二降噪晶体管M14均为P型晶体管，因此，在第一输入端INPUT和第二输入端INPUTB均无输入信号时，第一降噪晶体管M13和第二降噪晶体管M14均导通，从而将所述移位寄存器的输出端OUTPUT的输出信号持续下拉至所述第一电源电压端VSS的电源电压，从而降低第一电容C1中残存电荷对上拉节点PU和输出端OUTPUT的电压的影响，降低输出端OUTPUT的噪声。
当第一输入端INPUT和第二输入端INPUTB其中任意一个输入高电平 的输入信号时，上拉节点PU处的上拉信号应处于高电平，第一降噪晶体管M13和/或第二降噪晶体管M14截止；当第一输入端INPUT和第二输入端INPUTB均输入低电平的输入信号时，上拉节点PU处的上拉信号应处于低电平，第一降噪晶体管M13和第二降噪晶体管M14导通，以达到消除第一电容C1中残存电荷对上拉节点PU和输出端OUTPUT的电压的影响，降低输出端OUTPUT的噪声，可提高GOA单元稳定性。
在本公开至少一个实施例的移位寄存器中，增加了一个输入端INPUTB和两个P型晶体管来抑制上拉节点PU处电压异常导致的输出端噪声，从而可以延长应用该移位寄存器的TFT-LCD的使用寿命。
在另一个实施例中，例如，该移位寄存器进一步包含第二降噪单元17。第二降噪单元17包括第三降噪晶体管M15。第三降噪晶体管M15的栅极与第一时钟信号端CLKB连接，第一极与输出端OUTPUT连接，第二极与第一电源电压端VSS连接。在第一时钟信号端CLKB处的第一时钟信号处于高电平时，第三降噪晶体管M15导通，将所述移位寄存器的输出端OUTPUT的输出信号下拉至所述第一电源电压端VSS的电源电压，降低输出端噪声。
图3示出了图2中的移位寄存器的示例电路的操作时序图。下面结合图2和图3对图2中的移位寄存器的驱动方法进行说明。
在第一阶段1(无输入阶段)，第一输入端INPUT的第一输入信号、第二输入端INPUTB的第二输入信号和第一时钟信号端CLKB处的第一时钟信号均处于低电平。第一输入晶体管M1和第二输入晶体管M2均截止，虽然第二时钟信号端CLK处的第二时钟信号处于高电平，但是由于上拉节点PU处的上拉信号处于低电平，输出晶体管M3截止，输出端OUTPUT输出低电平。第一降噪晶体管M13和第二降噪晶体管M14均导通，将输出端OUTPUT的输出信号下拉至第一电源电压端VSS的电源电压。
在第二阶段2(输入阶段)，第一输入端INPUT的第一输入信号和第一时钟信号端CLKB处的第一时钟信号均处于高电平，第二输入端INPUTB的第二输入信号和第二时钟信号端CLK处的第二时钟信号均处于低电平。第一输入晶体管M1和第二输入晶体管M2导通，将第一输入端INPUT的高电平传递到上拉节点PU，此时上拉节点PU处于第一高电压，使得输出晶体管M3导通，由于第二时钟信号端CLK的第二时钟信号处于低电平，输出端 OUTPUT输出低电平。第一降噪晶体管M13导通，第二降噪晶体管M14截止，第一电源电压端VSS不影响输出端OUTPUT的输出信号。
在第三阶段3(输出阶段)，第一输入端INPUT的第一输入信号和第一时钟信号端CLKB处的第一时钟信号均处于低电平，第二输入端INPUTB的第二输入信号和第二时钟信号端CLK处的第二时钟信号均处于高电平。第一输入晶体管M1和第二输入晶体管M2截止，复位信号端RESET处于低电平，节点复位晶体管M4保持截止，上拉节点PU继续使得输出晶体管M3导通，第二时钟信号端CLK的第二时钟信号处于高电平，输出端OUTPUT输出高电平，由于第一电容C1的电压耦合作用，此时上拉节点PU被从第一高电压抬升到第二高电压，进一步提高输出晶体管M3的充电能力，保证像素充电。此外，在该阶段中，由于上拉节点PU仍处于高电平，第二下拉控制晶体管M9保持导通，下拉节点PD仍处于低电平，相应地节点下拉晶体管M6和输出下拉晶体管M7均保持截止。第一降噪晶体管M13截止，第二降噪晶体管M14导通，第一电源电压端VSS不影响输出端OUTPUT的输出信号。
在第四阶段4(复位阶段)，第一输入端INPUT的第一输入信号、第二输入端INPUTB的第二输入信号和第二时钟信号端CLK处的第二时钟信号均处于低电平，第一时钟信号端CLKB处的第一时钟信号和复位信号端RESET的复位信号均处于高电平。输入晶体管M1保持截止，第二输入晶体管M2导通，将第一输入端INPUT的低电平传递到上拉节点PU。复位信号端RESET的复位信号处于高电平，节点复位晶体管M4和输出复位晶体管M5导通，分别将上拉节点PU处的上拉信号和输出端OUTPUT的输出信号复位至第一电源电压端VSS的电源电压。此外，在该阶段中，由于上拉节点PU处于低电平，第二下拉控制晶体管M9截止。由于第一时钟信号端CLKB的第一时钟信号处于高电平，第三下拉控制晶体管M10导通，使得下拉节点PD仍处于低电平，节点下拉晶体管M6和输出下拉晶体管M7均保持截止。第三降噪晶体管M15导通，将所述移位寄存器的输出端OUTPUT的输出信号下拉至所述第一电源电压端VSS的电源电压，降低输出端噪声。第一降噪晶体管M13和第二降噪晶体管M14均导通，将输出端OUTPUT的输出信号下拉至第一电源电压端VSS的电源电压，降低输出端噪声。
在第五阶段5(保持阶段)，第一输入端INPUT的第一输入信号、第二输入端INPUTB的第二输入信号和第一时钟信号端CLKB处的第一时钟信号均处于低电平，第二时钟信号端CLK处的第二时钟信号处于高电平。第三下拉控制晶体管M10、第四下拉控制晶体管M11和第三降噪晶体管M15均截止。由于上拉节点PU处于低电平，第二下拉控制晶体管M9截止。由于第二时钟信号端CLK处的第二时钟信号处于高电平，第一下拉控制晶体管M8和第五下拉控制晶体管M12均导通，使得下拉节点PD处于高电平，节点下拉晶体管M6和输出下拉晶体管M7均导通，将移位寄存器的输出端OUTPUT的输出信号和上拉节点PU处的上拉信号下拉至所述第一电源电压端VSS的电源电压。第一降噪晶体管M13和第二降噪晶体管M14均保持导通，降低输出端噪声。
此后，第一时钟信号端CLKB处的第一时钟信号均处于高电平，第三下拉控制晶体管M10导通，使得下拉节点PD处于低电平，节点下拉晶体管M6和输出下拉晶体管M7均截止。第三降噪晶体管M15导通，降低输出端噪声。第一降噪晶体管M13和第二降噪晶体管M14均保持导通，降低输出端噪声。
在此之后，在下一帧到来之前，上拉节点PU一直处于低电平，下拉节点PD处的电平在高低电平之间交替，第一降噪晶体管M13和第二降噪晶体管M14均保持导通，持续地降低输出端OUTPUT的噪声。直至下一帧到来，所述移位寄存器接收到第一输入端INPUT的高电平信号后，重新执行上述第二阶段。
第一电源电压端VSS是低电源电压端。
由图3可以看出，第一时钟信号端CLKB的第一时钟信号与第二时钟信号端CLK的第二时钟信号反相。
本公开的至少一个实施例还提供了一种上述移位寄存器的驱动方法。下面结合图2和图3对该方法进行说明。在一个实施例中，例如，如图2所示，该移位寄存器100包含输入单元11、输出单元12、复位单元13、下拉单元14、下拉控制单元15和第一降噪单元16。该方法包含如下操作。
由输入单元11将所接收的输入信号传递到上拉节点PU；由输出单元12将第二时钟信号端CLK的第二时钟信号输出到该移位寄存器的输出端 OUTPUT；由复位单元13将上拉节点PU处的上拉信号复位至第一电源电压端VSS的电源电压以及将该移位寄存器的输出端OUTPUT的输出信号复位至第一电源电压端的电源电压VSS；由下拉控制单元15控制下拉单元14是否进行操作；由下拉单元14将所述移位寄存器的输出端OUTPUT的输出信号和所述上拉节点PU处的上拉信号下拉至所述第一电源电压端VSS的电源电压；以及由第一降噪单元16在无输入信号时持续降低该移位寄存器的输出端OUTPUT的噪声。
在一个实施例中，该移位寄存器100还包含第二降噪单元17，该方法还包含由该第二降噪单元17将所述移位寄存器的输出端OUTPUT的输出信号下拉至所述第一电源电压端VSS的电源电压。这里，第一电源电压端VSS是低电源电压端。
在本公开实施例的移位寄存器及其驱动方法中，增加了一个输入端和两个P型晶体管来抑制上拉节点处电压异常导致的输出端噪声，从而可以延长应用该移位寄存器的TFT-LCD的使用寿命。
本公开的至少一个实施例还提供了一种包括上述移位寄存器的显示装置。图4示出了该显示装置的示意图。该显示装置200包括栅极驱动器210、数据驱动器220以及显示面板230，栅极驱动器210和数据驱动器220分别通过栅线和数据线分别与显示面板230信号连接。该栅极驱动器210包括至少一个移位寄存器211，该移位寄存器211可以是上述任一实施例的移位寄存器。该显示面板230可以是液晶显示面板、有机发光二极管显示面板、电子纸显示面板等，本公开的实施例对此不作限制。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2016年10月26日递交的中国专利申请第201610947335.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (16)

  1. 一种移位寄存器，包括：
    输入单元，其第一端与所述移位寄存器的第一输入端连接用于从所述第一输入端接收第一输入信号，第二端与上拉节点连接，第三端与第一时钟信号端连接；
    输出单元，其第一端与第二时钟信号端连接，第二端与所述上拉节点连接，第三端与所述移位寄存器的输出端连接；
    复位单元，其第一端与复位信号端连接，第二端与所述上拉节点连接，第三端与第一电源电压端连接，第四端与所述移位寄存器的输出端连接；
    下拉单元，其第一端与下拉节点连接，第二端与所述移位寄存器的输出端连接，第三端与所述上拉节点连接，第四端与所述第一电源电压端连接；
    下拉控制单元，其第一端与所述第一时钟信号端连接，第二端与所述第二时钟信号端连接，第三端与所述下拉节点连接，第四端与所述第一电源电压端连接，第五端与所述上拉节点连接；以及
    第一降噪单元，其第一端与所述移位寄存器的第二输入端连接用于从所述第二输入端接收第二输入信号，第二端与所述移位寄存器的第一输入端连接用于从所述第一输入端接收第一输入信号，第三端与所述移位寄存器的输出端连接，第四端与所述第一电源电压端连接，配置为在无输入信号时持续降低所述移位寄存器的输出端的噪声。
  2. 根据权利要求1所述的移位寄存器，进一步包括第二降噪单元，其中，所述第二降噪单元的第一端与所述第一时钟信号端连接，第二端与所述移位寄存器的输出端连接，第三端与所述第一电源电压端连接。
  3. 根据权利要求2所述的移位寄存器，其中，所述第一降噪单元包括：
    第一降噪晶体管，其栅极与所述第二输入端连接，第一极与所述输出端连接；以及
    第二降噪晶体管，其栅极与所述第一输入端连接，第一极与所述第一降噪晶体管的第二极连接，第二极与所述第一电源电压端连接。
  4. 根据权利要求2所述的移位寄存器，其中，所述第二降噪单元包括第三降噪晶体管，其栅极与所述第一时钟信号端连接，第一极与所述输出端连 接，第二极与所述第一电源电压端连接。
  5. 根据权利要求2所述的移位寄存器，其中，所述输入单元包括：
    第一输入晶体管，其栅极和第一极与所述第一输入端连接，第二极与所述上拉节点连接；以及
    第二输入晶体管，其栅极与所述第一时钟信号端连接，第一极与所述第一输入端连接，第二极与所述上拉节点连接。
  6. 根据权利要求2所述的移位寄存器，其中，所述输出单元包括：
    输出晶体管，其栅极与所述上拉节点连接，第一极与所述第二时钟信号端连接，第二极与所述输出端连接；以及
    第一电容，其第一端与所述上拉节点连接，第二端与所述输出端连接。
  7. 根据权利要求2所述的移位寄存器，其中，所述复位单元包括：
    节点复位晶体管，其栅极与所述复位信号端连接，第一极与所述上拉节点连接，第二极与所述第一电源电压端连接；以及
    输出复位晶体管，其栅极与所述复位信号端连接，第一极与所述输出端连接，第二极与所述第一电源电压端连接。
  8. 根据权利要求2所述的移位寄存器，其中，所述下拉单元包括：
    节点下拉晶体管，其栅极与所述下拉节点连接，第一极与所述上拉节点连接，第二极与所述第一电源电压端连接；
    输出下拉晶体管，其栅极与所述下拉节点连接，第一极与所述输出端连接，第二极与所述第一电源电压端连接。
  9. 根据权利要求2所述的移位寄存器，其中，所述下拉控制单元包括：
    第一下拉控制晶体管，其栅极和下拉控制节点连接，第一极与所述第二时钟信号端连接，第二极与所述下拉节点连接；
    第二下拉控制晶体管，其栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极与所述第一电源电压端连接；
    第三下拉控制晶体管，其栅极与所述第一时钟信号端连接，第一极与所述下拉节点连接，第二极与所述第一电源电压端连接；
    第四下拉控制晶体管，其栅极与所述第一时钟信号端连接，第一极与所述下拉控制节点连接，第二极与所述第一电源电压端连接；以及
    第五下拉控制晶体管，其栅极和第一极与所述第二时钟信号端连接，第 二极与所述下拉控制节点连接。
  10. 根据权利要求3-9中任一项所述的移位寄存器，其中，所述第一降噪晶体管和所述第二降噪晶体管为P型晶体管，其它晶体管均为N型晶体管。
  11. 根据权利要求1所述的移位寄存器，其中，所述第二时钟信号端的第二时钟信号与所述第一时钟信号端的第一时钟信号反相。
  12. 根据权利要求1所述的移位寄存器，其中，所述第一电源电压端是低电源电压端。
  13. 一种移位寄存器的驱动方法，所述移位寄存器包含输入单元、输出单元、复位单元、下拉单元、下拉控制单元和第一降噪单元，该方法包括：
    由所述输入单元将所接收的输入信号传递到上拉节点；
    由所述输出单元将第二时钟信号端的第二时钟信号输出到所述移位寄存器的输出端；
    由所述复位单元将所述上拉节点处的上拉信号复位至第一电源电压端的电源电压以及将所述移位寄存器的输出端的输出信号复位至所述第一电源电压端的电源电压；
    由所述下拉控制单元控制所述下拉单元是否进行操作；
    由所述下拉单元将所述移位寄存器的输出端的输出信号和所述上拉节点处的上拉信号下拉至所述第一电源电压端的电源电压；以及
    由所述第一降噪单元在无输入信号时持续降低所述移位寄存器的输出端的噪声。
  14. 根据权利要求13所述的驱动方法，其中，所述移位寄存器还包含第二降噪单元，该方法还包括：
    由所述第二降噪单元将所述移位寄存器的输出端的输出信号下拉至所述第一电源电压端的电源电压。
  15. 根据权利要求13或14所述的驱动方法，其中，所述第一电源电压端是低电源电压端。
  16. 一种显示装置，包括根据权利要求1-12任一所述的移位寄存器。
PCT/CN2017/090262 2016-10-26 2017-06-27 移位寄存器及其驱动方法、显示装置 Ceased WO2018076741A1 (zh)

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