WO2018054096A1 - 半导体器件的测试优化方法和系统及建模优化方法和系统 - Google Patents

半导体器件的测试优化方法和系统及建模优化方法和系统 Download PDF

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WO2018054096A1
WO2018054096A1 PCT/CN2017/087282 CN2017087282W WO2018054096A1 WO 2018054096 A1 WO2018054096 A1 WO 2018054096A1 CN 2017087282 W CN2017087282 W CN 2017087282W WO 2018054096 A1 WO2018054096 A1 WO 2018054096A1
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test
direct current
parasitic resistance
parasitic
testing
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PCT/CN2017/087282
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English (en)
French (fr)
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刘林林
郭奥
王全
周伟
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上海集成电路研发中心有限公司
成都微光集电科技有限公司
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Priority to US16/311,163 priority Critical patent/US20190179991A1/en
Publication of WO2018054096A1 publication Critical patent/WO2018054096A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/333—Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation

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  • the present invention relates to the field of test modeling of semiconductor devices, and more particularly to test optimization methods and systems for semiconductor devices, and modeling optimization methods and systems for semiconductor devices.
  • the DC test data of the semiconductor device includes a DC parameter such as a current voltage of the semiconductor device.
  • the following two methods can be adopted: separately designing the DC test structure for the semiconductor device; or directly obtaining the DC characteristics of the semiconductor device on the test structure of other parameters.
  • the acquisition of the same device test data (DC test data and other parameter test data) needs to be performed on two test structures respectively. Due to the fluctuation of the process, it is difficult to guarantee DC even if the device size is the same.
  • the test structure is identical in performance to the devices under the test structure of other parameters.
  • the connection methods and parasitic factors of the two test structures are different, and the methods for removing the parasitic factors are also different, which makes it more difficult to ensure the identity of the acquired data.
  • semiconductor device modeling when the performance of the semiconductor devices characterized by the acquired test data of different parameters is inconsistent, the extraction of the model will be more difficult.
  • the present invention corrects the DC test data of the semiconductor device by extracting the parasitic element of the non-DC parameter test structure under the DC bias condition to realize the optimization of the semiconductor device test and modeling.
  • the present invention provides a test optimization method for a semiconductor device, which performs the following steps based on testing a test structure of a specific non-DC parameter:
  • the present invention also provides a corresponding test optimization system for a semiconductor device, based on testing a test structure of a specific non-DC parameter, including:
  • An auxiliary structure testing module configured to perform testing of the non-direct current parameter on the auxiliary structure of the tested structure, based on the auxiliary structure, a parasitic network model based on the auxiliary structure And testing results to calculate parallel parasitic resistance and series parasitic resistance of the test structure;
  • a DC equivalent sub-circuit construction module configured to linearly fit the parallel parasitic resistance and the series parasitic resistance, obtain a zero-frequency fitting value as a DC parasitic resistance of the test structure, and construct the test structure DC equivalent subcircuit model;
  • a DC test module configured to perform DC test on the test structure to obtain DC test data, and correct the DC test data based on the DC equivalent sub-circuit model.
  • the invention also provides a modeling optimization method for a semiconductor device, comprising:
  • the modeling data includes at least DC test data and test data of the test structure to test the non-direct current parameters.
  • the invention also provides a modeling optimization system for a semiconductor device, comprising:
  • a modeling data acquisition unit for obtaining a test structure for testing a specific non-direct current parameter, obtaining modeling data from a test optimization system of the semiconductor device as described above;
  • the modeling data includes at least DC test data and test data of the test structure to test the non-direct current parameters.
  • the test structure of the non-direct current parameter is directly used, and the influence of the parasitic element of the test structure on the DC test data is eliminated, so that the semiconductor device characterized by the DC test data and the corresponding parameter test data tends to be consistent, thereby
  • the evaluation of semiconductor device characteristics is more accurate and provides reliable data for modeling.
  • Fig. 1 shows a basic flow chart of a test optimization method of a semiconductor device of the present invention.
  • Figure 2 illustrates a schematic diagram of a test structure for a DUT.
  • Figure 3 illustrates a parasitic network model of the DUT test structure.
  • Figure 4 illustrates the open auxiliary structure of the test structure.
  • Figure 5 illustrates the short auxiliary structure of the test structure.
  • Fig. 6 illustrates a parasitic network model of the open auxiliary structure shown in Fig. 4.
  • Figure 7 illustrates a parasitic network model of the short auxiliary structure shown in Figure 5.
  • Figure 8 illustrates a DC equivalent sub-circuit model of the test structure.
  • Figure 9a shows the IdVd data before and after correction.
  • Figure 9b shows the corresponding gate voltage bias Vgs before and after the correction of the five IdVd curves.
  • Figure 10a shows the IdVg data before and after correction.
  • Figure 10b shows the corresponding leakage pressure bias Vds before and after the correction of the five IdVg curves.
  • Figure 11a shows a plot of the S22 component of the S-parameter for NMOS devices under different DC bias conditions.
  • Figure 11b shows a schematic of the correction for the S-parameter DC bias condition.
  • FIG. 12 shows a test optimization system and a modeling optimization system of a semiconductor device.
  • a test optimization scheme and a modeling optimization scheme of a semiconductor device are disclosed.
  • the present invention is applicable to high frequency semiconductor devices having the problems indicated by the background art, such as radio frequency (RF) devices, microwave devices, and the like.
  • RF radio frequency
  • the main process of the semiconductor device should be a MOS process, but it does not mean that the technical solution of the present invention is only applicable to the MOS semiconductor device, but is equivalent to an equivalent replacement for other processes.
  • the invention provides a test optimization method for a semiconductor device. Based on testing a test structure of a specific non-direct current parameter of the semiconductor device, the DC test is directly tested and optimized, and the basic flow chart is shown in FIG. 1 .
  • non-direct current parameters refer to parameters that are different from the DC test data but are required for modeling the semiconductor device, which are specified or selected by the technician according to actual conditions, for example, Scattering parameters (S parameters).
  • the S parameter characterizes the high frequency performance of the semiconductor device.
  • the current S-parameter test structure itself will bring The large parasitic nature of the S-parameters directly obtained by testing semiconductor devices does not accurately characterize the performance of the device. Therefore, the technician will further design the de-embedded structure to define the de-embedding plane of the semiconductor device, that is, define the intrinsic device and the parasitic element, and obtain the accurate parasitic element brought by the S-parameter test structure in the high-frequency working state, thereby obtaining accurate S parameter data.
  • the parasitic resistance problem introduced in the DC state of the S-parameter test structure is also not negligible. Especially for semiconductor devices with large crossover index and large drain current, the parasitic resistance introduced will affect the transconductance and source-drain resistance of the device. At the same time, in view of the relatively simple design of the connection line of the S-parameter test structure, the influence of parasitic resistance will be further increased if the design is not optimized.
  • the prior art only pays attention to the influence of parasitic elements in the high frequency state, and eliminates the parasitic influence by de-embedding the plane, but does not take the influence of parasitic elements into consideration during the testing of the DC characteristics of the semiconductor device. This results in inconsistencies in the performance of the device characterized by the DC test data and the actual performance of the intrinsic device. Therefore, when the DC bias condition is applied directly using the S-parameter test structure, the problems described in the background art are inevitable.
  • selecting the S-parameter test structure is a preferred choice of the present invention, because the S-parameter is a network parameter based on the relationship between the incident wave and the reflected wave, and is convenient for establishing a parasitic network model.
  • FIG. 2 shows a schematic diagram of a semiconductor device as a device under test (DUT) in a GSGpad (Ground-Signal-Ground pad), which can be used as an S-parameter test structure.
  • DUT device under test
  • GSGpad Ground-Signal-Ground pad
  • the test structure introduces parasitic elements and there are targeted de-parasitic measures.
  • the invention designs an auxiliary structure based on the existing de-parasitic measures and constructs an auxiliary structure, and pays attention to series parasitic factors and parallel parasitic factors, thereby preparing basic data for obtaining parasitic resistance related to DC characteristics.
  • Figure 3 shows the parasitic network model of the DUT test structure itself as shown in Figure 2.
  • Y p1 , Y p1 , Y p1 are the parallel parasitic elements introduced by the test structure
  • Z l1 , Z l2 , Z l3 are the series parasitic elements introduced by the test structure
  • the intermediate devices are intrinsic.
  • the auxiliary structure of the selected test structure is constructed and the selected non-DC parameters are tested.
  • the parasitic network model and the test result of the auxiliary structure are used to calculate the parallel parasitic resistance and the series parasitic resistance of the test structure, which are identified by step S1.
  • the auxiliary structure as an open (open) auxiliary structure and a short (short circuit) auxiliary structure. Still taking the DUT under the GSGpad as an example, the open auxiliary structure of the DUT is shown in Figure 4, and the short auxiliary structure is shown in Figure 5.
  • the steps of calculating the parallel parasitic resistance and the series parasitic resistance of the test structure include:
  • a set of non-DC parameters are tested on the short auxiliary structure, and the series parasitic resistance is calculated based on the parasitic network model of the short auxiliary structure and the test result.
  • the open-short auxiliary structure is only an example of the auxiliary structure selected in this embodiment, and those skilled in the art can completely fabricate other auxiliary structures of the test structure to perform parallel parasitic resistance and series parasitic resistance calculation of the test structure.
  • a through-reflection-transmission line (TRL) auxiliary structure an open-thru auxiliary structure, a through-short circuit can be constructed.
  • TRL through-reflection-transmission line
  • (thru-short) auxiliary structure open-short-through-left-right auxiliary structure, etc.
  • FIG. 6 shows a parasitic network model of the open auxiliary structure shown in FIG. 4.
  • the step of calculating the parallel parasitic resistance is: performing corresponding non-DC parameters on the open auxiliary structure.
  • the test calculates the admittance of each element in the pi network based on the test result, and takes the reciprocal of the real part of each element admittance as a parallel parasitic resistance.
  • FIG. 7 shows a parasitic network model of the short auxiliary structure shown in FIG. 5.
  • the step of calculating the series parasitic resistance is: The short auxiliary structure tests the corresponding non-DC parameters, calculates the impedance of each element in the T-type network based on the test result, and takes the real part of each element impedance as a series parasitic resistance; wherein the pi-type network is under the open auxiliary structure
  • the parasitic network model is determined.
  • step S1 since the two sets of tests are performed on non-direct current parameters, the input and output are frequency-dependent data.
  • the parasitic network model of Figures 6 and 7 is a simplified ideal type, and the situation in practice is much more complicated.
  • the series and parallel parasitic resistances solved in step S1 are also the amount of change with frequency, not a constant, and do not meet the requirements of DC parasitic resistance. Therefore, we obtain a zero-frequency fitting by performing linear fitting. The value is used as a DC parasitic resistance of the test structure to solve this problem.
  • the serial-parallel parasitic resistance data of the low frequency band can be taken for linear linearization.
  • the resistors that are extrapolated to 0hz are taken as the series and parallel parasitic resistances in the DC operating state.
  • the DUT can be mimicked as a FET, the series parasitic resistance includes R1, R2, and R3, and the parallel parasitic resistance includes R4, R5, and R6; then the gate, drain, and source of the FET are connected in series R1, respectively.
  • R2, R3; R4, R5, and R6 are connected in parallel between the gate and drain of the field effect transistor, between the gate and source, and between the source and the drain, as shown in Fig. 8.
  • test structure is subjected to a DC test to obtain DC test data, and the DC test data is corrected based on the DC equivalent sub-circuit model.
  • the DC test performed on the test structure in this step can be realized by directly applying a DC bias.
  • the DC test data is, for example, an IV curve of a semiconductor device.
  • the identifier is S3, it does not mean that this step all occurs after the step S1/S2, for example, the DC test of the test structure is performed to obtain the DC test data, and the auxiliary structure can be tested in the step S1. Executing before or after, does not affect the implementation of the technical solution of the present invention and the realization of the technical effects.
  • the focus of the present invention is mainly on the optimization of the DC test data, and does not affect the test of the corresponding non-DC parameters of the test structure according to its original design intention, nor does it affect the normality of other test structures. test. That is to say, the test structure used in the present invention for performing the DC test will still perform the test of the corresponding non-DC parameters, and the other test structures will still perform the respective tests.
  • the step of performing the DC test on the test structure in step S3 to obtain the DC test data may be performed before or after the test of each non-DC parameter, without affecting the implementation of the technical solution of the present invention and the realization of the technical effect.
  • the test since the test structure is subjected to the corresponding non-direct current parameter test, the test may be performed under the condition of applying a DC bias, so that the obtained non-DC parameter test data and the semiconductor device are obtained. The DC performance is correlated and there is an error, so a better technical effect can be obtained if the correction is implemented.
  • the preferred embodiment can optimize the DC bias conditions of the selected test structure, including correcting the DC bias conditions applied when testing the corresponding non-DC parameters for the test structure based on the DC equivalent sub-circuit model.
  • the DC bias condition is a DC bias condition corresponding to the obtained S parameter, wherein the S parameter is a de-embedded S parameter, and the specific de-embedding method is not within the scope of the present invention.
  • the test optimization method of the semiconductor device provided by the present invention has been described above. Those skilled in the art can understand that the present invention directly performs DC data testing by means of a non-DC parameter test structure, and does not need to add a new structure to remove the parasitic influence of the test structure, and realizes correction of the DC characteristics of the semiconductor device, so that the DC test data
  • the semiconductor devices characterized by the corresponding parameter test data tend to be consistent, which makes the evaluation of the characteristics of the semiconductor device more accurate and also provides reliable data for modeling the semiconductor device.
  • test structure type In this embodiment, a preferred S-parameter test structure is employed.
  • the semiconductor device obtains the relevant performance of the intrinsic device by testing the S parameter and de-embedding, in which the intrinsic device portion and the parasitic portion of the device can be distinguished.
  • the present invention takes the following operations to obtain the DC performance of the intrinsic device, that is, to remove the influence of parasitic elements caused by the S-parameter test structure.
  • the GSGpad structure is adopted as a specific implementation structure of the S-parameter test.
  • the source, the bulk of the NMOS device are shorted to the ground pad, and the gate and drain are respectively connected to the two Signal pads of the GSGpad.
  • the de-embedded plane is constructed.
  • the de-embedded plane of the two ports of gate and drain is M3 (the third layer metal in the CMOS process)
  • the de-embedded plane of the source and bulk ends is M1 (the first metal connection in the CMOS process)
  • the embedded plane defines the extent of the intrinsic device.
  • M1, M3 is only used as a practical example to illustrate, the technician can take other choices as needed.
  • the parasitic network model of this example can follow the schematic diagram of FIG. 3, that is, Y p1 , Y p1 , Y p1 are parallel parasitic elements introduced by the test structure, and Z l1 , Z l2 , Z l3 are introduced for the test structure. Parasitic elements in series, intermediate intrinsic devices.
  • the open auxiliary structure is based on the DUT structure to remove the device under test.
  • the de-embedded plane is selected. For example, the position of the de-embedded plane is determined in the DUT structure, and the device structure within the de-embedded plane is removed. Form the open auxiliary structure.
  • the gate, drain, source, and bulk ends are shorted by metal wires to form a short auxiliary structure.
  • R l1 real(Z l1 )
  • R l2 real(Z l2 )
  • R l3 real(Z l3 )
  • the embodiment adopts a method of linearly fitting the low-band resistance to the zero-frequency point to determine the resistance value.
  • the lowest frequency of the S parameter test is 50Mhz, so it is possible to select between 50Mhz and 2GHz, calculate the corresponding resistance point at a certain interval, and then perform a linear fitting of the frequency, and read the point corresponding to 0hz after fitting as DC.
  • R 1 in Figure 7 takes the zero-frequency fitting value of R l1
  • R 2 takes the fitting value of the zero-frequency of R l2
  • R 3 takes the fitting value of the zero-frequency of R l3
  • R 4 takes the value of R p3
  • the zero-frequency fitting value, R 5 takes the zero-frequency fitting value of R p1
  • R 6 takes the zero-frequency fitting value of R p2 .
  • NMOS S-parameter test structure that is, the GSGpad
  • DC bias conditions are applied for DC test to obtain DC test data such as an IV curve of the semiconductor device.
  • V ds , V gs is the voltage applied to the test structure, the drain and gate of the semiconductor device relative to the source
  • V ds ', V gs ' is actually applied to the drain and gate of the semiconductor device after being corrected Relative to the source voltage
  • I ds ' is the calibrated drain current.
  • the IV characteristic curve of the semiconductor device is corrected, and in this embodiment, the IdVd curve and the IdVg curve.
  • Fig. 9a shows the IdVd data before and after the correction.
  • the actual line portion is the IdVd data tested before the uncorrection, and the symbol portion is the corrected data. It can be seen that the IV characteristic has shifted due to the parasitic resistance.
  • Figure 9b shows the gate voltage offset Vgs corresponding to the five IdVd curves. For each curve, the constant set for us before uncorrection is shown by the solid line. After the correction, the Vds increases and gradually deviates from the set value. Part of it.
  • Fig. 10a shows the IdVg data before and after the correction.
  • the actual line portion is the uncorrected test IdVg data, and the symbol portion is the corrected data. It can be seen that the IV characteristic has shifted due to the parasitic resistance.
  • Figure 10b shows the leakage pressure bias Vds corresponding to the five IdVg curves. For each curve, the constant set for us before uncorrection is shown by the solid line. After the correction, the Vgs increases gradually from the set value, such as the symbol part. Shown.
  • the drain-source voltage Vds scans 5 points of 0.05-1.1V in steps of 0.2625V, and Vgs also scans 5 points of 0.05-1.1V in steps of 0.2625V, so that 25 sets of DC bias conditions can be obtained.
  • the DC bias condition can be corrected.
  • Figure 11b shows the correction for the DC bias condition, reflecting the difference in DC bias voltage for each curve before and after the correction.
  • the circle is the 25 sets of bias conditions of the S parameter of the device we set, and the asterisk is the actual bias condition corresponding to the S parameter of the corrected device. It can be seen that the error becomes larger as the bias voltage increases. .
  • the present invention also provides a test optimization system 01 for a semiconductor device based on a test structure for testing a specific non-direct current parameter, as shown in FIG. 12, including a DC test/optimization unit 11 .
  • the DC test/optimization unit 11 includes:
  • the auxiliary structure testing module 111 is configured to perform the non-direct current parameter test on the auxiliary structure of the constructed test structure, and calculate the parallel parasitic resistance and the series parasitic resistance of the test structure 02 based on the parasitic network model of the auxiliary structure and the test result;
  • the DC equivalent sub-circuit construction module 112 is configured to linearly fit the parallel parasitic resistance and the series parasitic resistance, obtain a zero-frequency fitting value as a DC parasitic resistance of the test structure, and construct a DC equivalent sub-circuit model of the test structure;
  • the DC test module 113 is configured to perform DC test on the test structure to obtain DC test data, and correct DC test data based on the DC equivalent sub-circuit model.
  • the system 01 further includes a specific non-direct current parameter test/optimization unit 12, which specifically includes a specific non-direct current parameter test module 121 that dominates the corresponding non-direct current parameter test, and a DC bias condition correction module 122.
  • the DC bias condition correction module 122 is configured to implement a correction of the DC bias condition applied when the test structure tests the non-DC parameter based on the DC equivalent sub-circuit model provided by 112.
  • the present invention also provides a modeling optimization scheme for a semiconductor device based on the test optimization scheme of the semiconductor device provided above.
  • the modeling optimization method of the semiconductor device includes: obtaining a modeling data for performing a test optimization method of the semiconductor device provided by the present invention for a test structure of a specific non-direct current parameter; and performing modeling.
  • the modeling data includes at least the DC test data and the test data of the corresponding non-DC parameters, and may of course include other test data of non-DC parameters.
  • the DC test and the non-DC parameter test are performed in no particular order, that is, the DC test can occur before and after the test of the non-DC parameter. Of course, it is in the same order as other non-DC parameters.
  • the modeling optimization system of the semiconductor device is as shown in FIG. 12, and includes: a modeling data acquiring unit 02 for obtaining a test structure for testing specific non-direct current parameters, and obtaining the test optimization system 01 of the semiconductor device provided by the present invention. Modal data; and, modeling unit 03, for modeling.
  • the modeling data also includes at least the DC test data and the test structure to test the corresponding non-DC parameters.

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Abstract

一种半导体器件的测试优化和建模优化方法及系统，该测试优化方法及系统基于测试特定非直流参数的测试结构，构建测试结构的辅助结构并进行该非直流参数的测试，基于辅助结构的寄生网络模型和测试结果来计算该测试结构的并联寄生电阻和串联寄生电阻（S1），进行线性拟合获得测试结构的直流寄生电阻（S2），以及对该测试结构执行直流测试获得直流测试数据，并基于直流等效子电路模型来校正直流测试数据（S3）。该方法及系统直接借助非直流参数的测试结构，并消除该测试结构的寄生元素对直流测试数据的影响，使得直流测试数据和该非直流参数的测试数据所表征的半导体器件趋向一致，从而对半导体器件特性的评估更为准确，也为建模提供了可靠的数据。

Description

半导体器件的测试优化方法和系统及建模优化方法和系统 技术领域
本发明涉及半导体器件的测试建模领域，尤其涉及半导体器件的测试优化方法和系统，以及半导体器件的建模优化方法和系统。
技术背景
实现对半导体器件的建模，需保证对其直流测试数据的准确获取。其中，半导体器件的直流测试数据包括半导体器件的电流电压等直流参数。
要获取半导体器件的直流测试数据，可以采取以下两种方式：为半导体器件单独设计直流测试结构；或者，直接在其他参数的测试结构上获取半导体器件的直流特性。
由于在半导体器件的测试和建模过程中，所需参数并不仅仅是直流测试数据一种，因而导致上述两种方式均存在问题。
对于前一种方式而言，同一颗器件测试数据(直流测试数据和其他参数测试数据)的获取需要分别在两个测试结构上进行，由于工艺的波动影响，即便器件尺寸完全相同也难以保证直流测试结构与其他参数的测试结构下的器件在性能上完全一致。此外两种测试结构的连接方式及寄生因素都会不同，去除寄生因素的方法也不同，这就更加难以保证获取数据的同一性。作为半导体器件建模的基础，当所获取的不同参数的测试数据所表征的半导体器件的性能不一致时，将会给模型的提取带来较大困难。
与之相比，采取后一种方式看起来就尤为必要，至少在硬件上保证了不同参数测试结构的同一性，因此所获得的直流测试数据和其他参数所表征的半导体对象在理想状态下是一致的。但实际上，任何参数的测试结构本身都 不可避免会带来寄生，因此会配套设计针对该参数的去寄生措施；然而当我们转用这样的测试结构来获取直流测试数据时，却难以适用针对该参数的去寄生措施，这就导致了尽管直流测试数据和其他参数由相同测试结构获得，但所表征的半导体器件依然不一致，同样会给模型的提取带来较大困难。
发明概要
为了解决该问题，本发明通过提取非直流参数测试结构在直流偏置条件下的寄生元素，来对半导体器件的直流测试数据加以校正，以实现对半导体器件测试和建模的优化。
本发明提供了一种半导体器件的测试优化方法，基于测试特定非直流参数的测试结构执行以下步骤：
构建所述测试结构的辅助结构并进行所述非直流参数的测试，基于所述辅助结构的寄生网络模型和测试结果来计算所述测试结构的并联寄生电阻和串联寄生电阻；
对所述并联寄生电阻和所述串联寄生电阻进行线性拟合，获得零频拟合值作为所述测试结构的直流寄生电阻，并构建所述测试结构的直流等效子电路模型；
对所述测试结构进行直流测试获得直流测试数据，并基于所述直流等效子电路模型来校正所述直流测试数据。
基于本发明所提供的半导体器件的测试优化方法，本发明还提供了相应的半导体器件的测试优化系统，基于测试特定非直流参数的测试结构，包括：
辅助结构测试模块，用于对所构建的所述测试结构的辅助结构进行所述非直流参数的测试，基于所述辅助结构，基于所述辅助结构的寄生网络模型 和测试结果来计算所述测试结构的并联寄生电阻和串联寄生电阻；
直流等效子电路构建模块，用于对所述并联寄生电阻和所述串联寄生电阻进行线性拟合，获得零频拟合值作为所述测试结构的直流寄生电阻，并构建所述测试结构的直流等效子电路模型；
直流测试模块，用于对所述测试结构进行直流测试获得直流测试数据，并基于所述直流等效子电路模型来校正所述直流测试数据。
本发明还提供了半导体器件的建模优化方法，包括：
对于测试特定非直流参数的测试结构，执行如上所述的半导体器件的测试优化方法获得建模数据；
进行建模；
其中，所述建模数据至少包括直流测试数据和所述测试结构测试所述非直流参数的测试数据。
本发明还提供了半导体器件的建模优化系统，包括：
建模数据获取单元，用于对于测试特定非直流参数的测试结构，从如上所述的半导体器件的测试优化系统获得建模数据；
建模单元，用于进行建模；
其中，所述建模数据至少包括直流测试数据和所述测试结构测试所述非直流参数的测试数据。
通过本发明的技术方案，直接借助非直流参数的测试结构，并消除该测试结构的寄生元素对直流测试数据的影响，使得直流测试数据和相应参数测试数据所表征的半导体器件趋向一致，从而对半导体器件特性的评估更为准确，也为建模提供了可靠的数据。
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
以下结合附图，详细说明本发明的优点和特征。
附图说明
图1示出了本发明半导体器件的测试优化方法的基本流程图。
图2例示了DUT一个测试结构的示意图。
图3例示了DUT测试结构的寄生网络模型。
图4例示了测试结构的open辅助结构。
图5例示了测试结构的short辅助结构。
图6例示了图4所示open辅助结构的寄生网络模型。
图7例示了图5所示short辅助结构的寄生网络模型。
图8例示了测试结构的一个直流等效子电路模型。
图9a示出了校正前后的IdVd数据。
图9b示出了5条IdVd曲线校正前后对应的栅压偏置Vgs。
图10a示出了校正前后的IdVg数据。
图10b示出了5条IdVg曲线校正前后对应的漏压偏置Vds。
图11a示出了NMOS器件在不同的直流偏置条件下，S参数中S22分量的曲线示意图。
图11b示出了对于S参数直流偏置条件的校正示意图。
图12示出了半导体器件的测试优化系统和建模优化系统。
发明内容
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员来说显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
为了彻底了解本发明，将在下列的描述中提出详细的结构或过程。显然，本发明的施行并不限定于本领域的技术人员所熟习的特殊细节。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
在本发明中，公开了半导体器件的测试优化方案和建模优化方案。本领域技术人员可以理解，本发明的适用对象为存在背景技术所指出问题的高频半导体器件，例如射频(RF)器件、微波器件等。以及，目前以及可预见的相当时期内，半导体器件的主要工艺应为MOS工艺，但并不意味着本发明的技术方案仅仅适用于MOS半导体器件，而是适用于其他工艺的等同替代。
本发明提供了一种半导体器件的测试优化方法，基于测试半导体器件特定非直流参数的测试结构，直接对其进行直流测试并加以优化，其基本流程图如图1所示。
本领域技术人员可以理解，这里所说的特定非直流参数，是指由技术人员根据实际情况所指定或选定的、不同于直流测试数据的但同为半导体器件建模所需的参数，例如散射参数(S参数)。
S参数的选择符合本发明的要求，具体而言：
S参数表征半导体器件的高频性能。目前的S参数测试结构本身会带来 很大的寄生，使对半导体器件进行测试所直接获取的S参数无法准确表征该器件的性能。因此，技术人员会进一步设计去嵌结构来定义半导体器件的去嵌平面，即定义本征器件与寄生元素，通过去除S参数测试结构在高频工作状态下带来的寄生元素，从而得到准确的S参数数据。
同时我们注意到，在S参数测试结构直流状态下引入的寄生电阻问题同样不可忽略。尤其对于叉指数较大和漏级电流较大的半导体器件，其引入的寄生电阻对该器件的跨导、源漏电阻的评估等都会造成影响。同时，鉴于S参数测试结构本身的连接线设计较为自由，在设计没有做到最优化的情况下将会进一步加大寄生电阻的影响。
然而，现有技术仅注意到了高频状态下寄生元素的影响，并通过去嵌平面来消除寄生影响的处理，而在半导体器件直流特性的测试过程中却并未将寄生元素的影响纳入考量，这就导致直流测试数据所表征的器件性能与本征器件实际性能的不一致。因此，当直接采用S参数测试结构施加直流偏置条件时，必然存在背景技术所述的问题。
进一步的，选择S参数测试结构是本发明的较佳选择，因为S参数是建立在入射波、反射波关系基础上的网络参数，便于寄生网络模型的建立。
图2示出了半导体器件作为待测器件(DUT)，在GSGpad(Ground－Signal－Ground焊盘)中的示意图，该GSGpad可作为S参数测试结构。
如背景技术部分所描述的，半导体器件的参数测试过程中，其测试结构会引入寄生元素并存在针对性的去寄生措施。本发明基于现有的去寄生措施设计辅助结构并构建辅助结构，关注串联寄生因素和并联寄生因素，从而为获取与直流特性相关的寄生电阻准备好基础数据。
图3示出了如图2所示的DUT测试结构本身的寄生网络模型。
其中，Yp1、Yp1、Yp1为测试结构所引入的并联寄生元素，Zl1、Zl2、Zl3为测试结构所引入的串联寄生元素，中间为本征器件。
以下结合附图对本发明的实施例做详细描述。
首先，构建所选定测试结构的辅助结构并进行选定的非直流参数的测试，基于辅助结构的寄生网络模型和测试结果来计算测试结构的并联寄生电阻和串联寄生电阻，以步骤S1标识。
具体而言，为了实现并联寄生电阻和串联寄生电阻的计算，我们需要先构建该测试结构的辅助结构。
作为一个较佳实施例，我们可以构建该辅助结构为open(开路)辅助结构和short(短路)辅助结构。仍以GSGpad下的DUT为例，则DUT的open辅助结构如图4所示，short辅助结构如图5所示。
则基于上述open辅助结构和short辅助结构，计算测试结构的并联寄生电阻和串联寄生电阻的步骤包括：
对该open辅助结构进行一组非直流参数的测试，基于open辅助结构的寄生网络模型和测试结果来计算并联寄生电阻；以及
对该short辅助结构进行一组非直流参数的测试，基于short辅助结构的寄生网络模型和测试结果计算串联寄生电阻。
应当了解，open-short辅助结构只是本实施例所选取制作的辅助结构示例，本领域技术人员完全可以根据需要制作测试结构的其他辅助结构来进行该测试结构的并联寄生电阻和串联寄生电阻的计算，例如可以构建直通-反射-传输线(TRL)辅助结构、开路-直通(open-thru)辅助结构、直通-短路 (thru-short)辅助结构、开路-短路-直通-左电阻-右电阻(open-short-through-left-right)辅助结构等。
作为一个具体实施例，图6示出了图4所示open辅助结构的寄生网络模型，为三元素的pi型网络，则计算并联寄生电阻的步骤为：对该open辅助结构进行相应非直流参数的测试，基于测试结果计算该pi网络中每一个元素的导纳，并取每个元素导纳的实部的倒数作为并联寄生电阻。
作为一个具体实施例，图7示出了图5所示short辅助结构的寄生网络模型，为三元素的pi型网络和三元素的T型网络之并联，则计算串联寄生电阻的步骤为：对该short辅助结构进行相应非直流参数的测试，基于测试结果计算该T型网络中每一个元素的阻抗，并取每个元素阻抗的实部作为串联寄生电阻；其中pi型网络由open辅助结构下的寄生网络模型确定。
在上述以S1标识的步骤确定了并联和串联寄生电阻之后，我们进入下一步骤的处理，即对并联寄生电阻和串联寄生电阻进行线性拟合，获得零频拟合值作为测试结构的直流寄生电阻，并构建该测试结构的直流等效子电路模型，以S2标识。
本领域技术人员应当理解，在步骤S1的处理过程中，由于是对非直流参数进行的两组测试，因此输入、输出均为频率相关的数据。进一步如我们所发现的，图6和图7的寄生网络模型是一种简化的理想型，实践中的情况要复杂的多。事实上，步骤S1所求解的串联和并联寄生电阻也均是随频率变化的量，而非一个常数，并不符合直流寄生电阻的要求，因此，我们通过进行线性拟合，获得零频拟合值作为测试结构的直流寄生电阻来解决这一问题。作为一个优选实施例，可以取低频段的串并联寄生电阻数据进行线性拟 合，将外推至0hz求取的电阻作为直流工作状态下的串联和并联寄生电阻。
接下来，我们需要构建测试结构的直流等效子电路模型。作为一个优选实施例，可以将DUT拟态为场效应管，串联寄生电阻包括R1、R2、R3，并联寄生电阻包括R4、R5、R6；则场效应管的栅、漏、源极分别串联R1、R2、R3；场效应管的栅漏极之间、栅源极之间、源漏极之间分别并联R4、R5、R6，如图8所示。
接下来，如S3所标识的，对该测试结构进行直流测试获得直流测试数据，并基于该直流等效子电路模型来校正直流测试数据。
其中，本步骤对测试结构所进行的直流测试可以通过直接施加直流偏置实现。
其中，直流测试数据例如半导体器件的IV曲线。
有必要说明的是，虽然标识为S3，但不意味着此步骤全部发生在步骤S1/S2之后，例如对测试结构进行直流测试获得直流测试数据的步骤，可以在步骤S1中对辅助结构的测试之前或之后进行，不影响本发明技术方案的实施和技术效果的实现。
以及，本领域技术人员应当理解，本发明的着眼点主要在于对直流测试数据的优化，并不影响测试结构按其设计原意所进行的相应非直流参数的测试，也不影响其他测试结构的正常测试。也就是说，本发明中所采用的、进行直流测试的测试结构仍然会进行相应非直流参数的测试，而其他测试结构也仍然会进行各自的测试。则步骤S3中对测试结构进行直流测试获得直流测试数据的步骤可在各非直流参数的测试之前或之后进行，不影响本发明技术方案的实施和技术效果的实现。
作为一个较佳实施例，由于测试结构在进行相应非直流参数测试的过程中，可能会包括在施加直流偏置条件下进行的测试，这样所获得的非直流参数的测试数据就会与半导体器件的直流性能发生关联，并且存在误差，因此若实现对其修正将获得更佳的技术效果。本优选实施例即可实现对选定测试结构的直流偏置条件的优化，包括基于直流等效子电路模型来校正对该测试结构测试相应非直流参数时所施加的直流偏置条件。
其中，此处的直流偏置条件是与所获得的S参数对应的直流偏置条件，其中S参数为去嵌后S参数，具体去嵌方法不在本发明讨论范围之内。
以上对本发明所提供的半导体器件的测试优化方法进行了说明。本领域技术人员可以理解，本发明直接借助非直流参数的测试结构进行直流数据测试，且无需增加新的结构来去除测试结构的寄生影响，并实现对半导体器件直流特性的校正，使得直流测试数据和相应参数测试数据所表征的半导体器件趋向一致，从而对半导体器件特性的评估更为准确，也为半导体器件建模提供了可靠的数据。
为了帮助本领域技术人员更为清楚的理解本发明的技术方案，以下将以具体实施例和具体的运算处理进行进一步说明。在本实施例中，以一颗NMOS器件作为DUT，其宽度W＝5um，长度l＝0.04um，叉指数NF＝16。
(1)选择测试结构类型。在本实施例中，采用优选的S参数测试结构。半导体器件通过测试S参数，并借助去嵌入来获取本征器件的相关性能，在这一过程中可以区分本征器件部分和器件的寄生部分。本发明借助这一测试结构，采取以下操作来获取本征器件的直流性能，即去除S参数测试结构所带来的寄生元素的影响。
(2)选择具体测试结构。在本实施例中，采用GSGpad结构作为S参数测试的具体实现结构。这种情况下，NMOS器件的源(source)、衬底(bulk)短接至ground pad，栅(gate)、漏(drain)分别连接至GSGpad的两个Signal pad。
当测试结构确定后，我们能够获得测试结构的寄生网络模型，即可以抽取测试结构引入的寄生因素。在S参数测试结构情况下，就是构建去嵌平面。本实施例中，选择gate、drain两端口的去嵌平面为M3(CMOS工艺中第三层金属)，source、bulk端的去嵌平面为M1(CMOS工艺中第一层金属连线)，该去嵌平面所定义了本征器件的范围。当然，具体选择哪一层金属连线是技术人员根据自己对本征器件的定义而灵活确定的，这里选择M1、M3仅作为一个实际实例加以说明，技术人员完全可以根据需要而采取其他选择。在表达上，本示例的寄生网络模型可以沿用图3的示意，即Yp1、Yp1、Yp1为测试结构所引入的并联寄生元素，Zl1、Zl2、Zl3为测试结构所引入的串联寄生元素，中间为本征器件。
(3)构建open、short辅助结构，并分别对上述open、short辅助结构进行S参数测试。
在GSGpad测试结构下，open辅助结构是在DUT结构基础上，去除待测器件形成：首先选择去嵌平面，比如在DUT结构中确定去嵌平面的位置，将去嵌平面以内的器件结构去除，构成open辅助结构。在open辅助结构基础上，将gate、drain、source、bulk端使用金属线短接形成short辅助结构。
(4)将open辅助结构测试的S参数转化为Y参数(导纳参数)，使用 如图6所示的寄生网络模型，基于Y参数可求得并联寄生因素Yp3,Yp1,Yp2的导纳值：
Yp3＝-Y12
Yp1＝Y11+Y12
Yp2＝Y22+Y12
接下来，分别求取Yp3,Yp1,Yp2的实部，并取倒数，作为GSGpad的并联寄生电阻，即：
Rp3＝1/real(Yp3)
Rp1＝1/real(Yp1)
Rp2＝1/real(Yp2)
(5)将short辅助结构测试的S参数转化为Y参数，使用如图7所示的寄生网络模型，由Yp3,Yp1,Yp2构成的pi型网络和由Zl1,Zl2,Zl3构成的T型网络并联，所以有T型网络的Y参数为：
YT＝Yshort-Ypi＝Yshort-Yopen
将T型网络的Y参数转化为Z参数(阻抗参数)，求解Zl1,Zl2,Zl3可得：
ZL1＝ZT11-ZT12
ZL2＝ZT12
ZL3＝ZT22-ZT12
分别求取Zl1,Zl2,Zl3的实部，作为GSGpad的串联寄生电阻，即：
Rl1＝real(Zl1)
Rl2＝real(Zl2)
Rl3＝real(Zl3)
(6)构建测试结构的直流等效子电路模型，沿用图8所示，即在本征器件基础上栅极串联寄生电阻R1，漏极串联寄生电阻R2，源极串联寄生电阻R3，以及栅漏极之间并联寄生电阻R4，栅源极之间并联寄生电阻R5，源漏极之间并联寄生电阻R6。
其中，本实施例采用将低频段电阻做线性拟合外推至零频点的办法，确定上述阻值。具体地，S参数的测试最低频率为50Mhz，因此可以选取50Mhz～2GHz之间，以一定间距分别计算对应的电阻点，然后做频率的线性拟合，读取拟合后对应0hz的点作为直流寄生电阻：图7中R1的值取Rl1的零频拟合值，R2取Rl2的零频拟合值，R3取Rl3的零频拟合值，R4取Rp3的零频拟合值，R5取Rp1的零频拟合值，R6取Rp2的零频拟合值。
(7)对NMOS的S参数测试结构，即GSGpad，施加一组直流偏置条件进行直流测试，获得直流测试数据例如半导体器件的IV曲线。
有必要说明的是，本部分(7)的处理，与(3)的处理步骤不存在次序要求，即(7)可以在(3)之前或之后进行；以及，本部分(7)的处理，同样可以在对于DUT进行S参数测试和其他非直流参数测试的之前、之后进行。
(8)基于直流等效子电路模型，求解节点电压电流方程，校正直流测试数据。
Figure PCTCN2017087282-appb-000001
Figure PCTCN2017087282-appb-000002
Figure PCTCN2017087282-appb-000003
其中：Vds,Vgs为施加在测试结构上的，半导体器件漏极和栅极相对于源极的电压，Vds',Vgs'为经过校正后实际施加在半导体器件漏极和栅极相对于源 极的电压，Ids'为经过校准后的漏极电流。
根据上述计算结果，半导体器件的IV特性曲线得到修正，在本实施例中为IdVd曲线和IdVg曲线。
图9a示出了校正前后的IdVd数据，其实线部分为未校正前所测试的IdVd数据，符号部分为校正后数据，可以看出由于寄生电阻影响IV特性已发生偏移。图9b示出了5条IdVd曲线对应的栅压偏置Vgs，对于每条曲线，未校正前为我们设定的常数如实线所示，校正后随Vds增大而逐步偏离设定值如符号部分所示。
图10a示出了校正前后的IdVg数据，其实线部分为未校正前测试IdVg数据，符号部分为校正后数据，可以看出由于寄生电阻影响IV特性已发生偏移。图10b示出了5条IdVg曲线对应的漏压偏置Vds，对于每条曲线，未校正前为我们设定的常数如实线所示，校正后随Vgs增大逐步偏离设定值如符号部分所示。
(9)在对测试结构进行S参数测试过程中施加另一组直流偏置条件。
例如，漏源电压Vds扫描0.05～1.1V的5个点，步长为0.2625V，同时Vgs也扫描0.05～1.1V的5个点，步长为0.2625V，这样可获得25组直流偏置条件下的器件S参数。可以看出，此处直流偏置条件的施加是为了进行S参数的相关测试而非进行直流测试，因此其采样数目要远低于如图9a和图10a所示的情况。
但基于与直流测试数据校正同样的计算方式，可以对其直流偏置条件进行校正。
如图11a所示，为S参数S22分量在上述25组偏置条件下得到的25条 曲线，每条曲线都对应一组施加的直流偏置电压信息，
图11b则示出了对于直流偏置条件的校正，反映了校正前后每条曲线对应的直流偏置电压的差异。具体的，其圆圈为我们设定的器件S参数的25组偏置条件，星号为校正后的器件S参数对应的实际偏置条件，可以看出随偏置电压的增大，误差变大。
与以上所描述的半导体器件的测试优化方法相应，本发明还提供了半导体器件的测试优化系统01，其基于测试特定非直流参数的测试结构，如图12所示，包括直流测试/优化单元11。
其中，该直流测试/优化单元11包括：
辅助结构测试模块111，用于对所构建的测试结构的辅助结构进行该非直流参数的测试，并基于辅助结构的寄生网络模型和测试结果来计算测试结构02的并联寄生电阻和串联寄生电阻；
直流等效子电路构建模块112，用于对并联寄生电阻和串联寄生电阻进行线性拟合，获得零频拟合值作为测试结构的直流寄生电阻，并构建测试结构的直流等效子电路模型；
直流测试模块113，用于对测试结构进行直流测试获得直流测试数据，并基于直流等效子电路模型来校正直流测试数据。
作为优选实施例，该系统01还包括特定非直流参数测试/优化单元12，其具体包括主导进行相应非直流参数测试的特定非直流参数测试模块121，以及直流偏置条件校正模块122。该直流偏置条件校正模块122用于基于112提供的直流等效子电路模型，实现对测试结构测试该非直流参数时所施加的直流偏置条件的校正。
此外，本领域技术人员可以理解，本系统01当然可以包括其他非直流参数测试单元13.
由于已经在前述对半导体器件的测试优化方法部分进行了详细的阐述，其处理方法同样适用于本系统01的各相应模块，因此在本部分不再赘述。
基于前述所提供的半导体器件的测试优化方案，本发明还提供了半导体器件的建模优化方案。
该半导体器件的建模优化方法包括：对于特定非直流参数的测试结构，执行本发明所提供的半导体器件的测试优化方法获得建模数据；以及进行建模。
其中，建模数据至少包括直流测试数据和相应非直流参数的测试数据，当然还可以包括其他非直流参数的测试数据。此外，直流测试和该非直流参数测试的进行不分先后，即直流测试可以发生在该非直流参数的测试之前、之后。当然，与其他非直流参数的测试同样不分先后。
该半导体器件的建模优化系统如图12所示，包括：建模数据获取单元02，用于对于测试特定非直流参数的测试结构，从本发明所提供的半导体器件的测试优化系统01获得建模数据；以及，建模单元03，用于进行建模。
其中，建模数据同样至少包括直流测试数据和测试结构测试相应非直流参数的测试数据。
以上所述的仅为本发明的实施例，所述实施例并非用以限制本发明专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明的保护范围内。

Claims (10)

  1. 一种半导体器件的测试优化方法，其特征在于，基于测试特定非直流参数的测试结构，执行以下步骤：
    构建所述测试结构的辅助结构并进行所述非直流参数的测试，基于所述辅助结构的寄生网络模型和测试结果来计算所述测试结构的并联寄生电阻和串联寄生电阻；
    对所述并联寄生电阻和所述串联寄生电阻进行线性拟合，获得零频拟合值作为所述测试结构的直流寄生电阻，并构建所述测试结构的直流等效子电路模型；
    对所述测试结构进行直流测试获得直流测试数据，并基于所述直流等效子电路模型来校正所述直流测试数据。
  2. 根据权利要求1所述的方法，其特征在于，还包括基于所述直流等效子电路模型来校正对所述测试结构测试所述非直流参数时所施加的直流偏置条件。
  3. 根据权利要求1所述的方法，其特征在于，所述辅助结构包括open辅助结构和short辅助结构；
    则所述计算所述测试结构的并联寄生电阻和串联寄生电阻的步骤包括：
    对所述open辅助结构进行所述非直流参数的测试，基于所述open辅助结构的寄生网络模型和测试结果来计算所述并联寄生电阻；
    对所述short辅助结构进行所述非直流参数的测试，基于所述short辅助结构的寄生网络模型和测试结果来计算所述串联寄生电阻。
  4. 根据权利要求3所述的方法，其特征在于，所述open辅助结构的寄生网络模型为三元素的pi型网络，则计算所述并联寄生电阻的步骤包括：对所述open辅助结构进行所述非直流参数的测试，基于测试结果计算所述pi型网络中每一个元素的导纳，并取每个元素导纳的实部的倒数作为所述并联 寄生电阻。
  5. 根据权利要求3所述的方法，其特征在于，所述short辅助结构的寄生网络模型为三元素的pi型网络和三元素的T型网络之并联，则计算所述串联寄生电阻的步骤包括：对所述short辅助结构进行所述非直流参数的测试，基于测试结果计算所述T型网络中每一个元素的阻抗，并取每个元素阻抗的实部作为所述串联寄生电阻；其中所述pi型网络由所述open辅助结构的寄生网络模型确定。
  6. 根据权利要求1所述的方法，其特征在于，所述构建所述测试结构的直流等效子电路模型包括：将所述半导体器件拟态为场效应管，串联寄生电阻包括R1、R2、R3，并联寄生电阻包括R4、R5、R6；所述场效应管的栅、漏、源极分别串联R1、R2、R3；所述场效应管的栅漏极之间、栅源极之间、源漏极之间分别并联R4、R5、R6。
  7. 根据权利要求1-6任一所述的方法，其特征在于，所述非直流参数为S参数。
  8. 一种半导体器件的测试优化系统，其特征在于，基于测试特定非直流参数的测试结构，包括：
    辅助结构测试模块，用于对所构建的所述测试结构的辅助结构进行所述非直流参数的测试，基于所述辅助结构的寄生网络模型和测试结果来计算所述测试结构的并联寄生电阻和串联寄生电阻；
    直流等效子电路构建模块，用于对所述并联寄生电阻和所述串联寄生电阻进行线性拟合，获得零频拟合值作为所述测试结构的直流寄生电阻，并构建所述测试结构的直流等效子电路模型；
    直流测试模块，用于对所述测试结构进行直流测试获得直流测试数据，并基于所述直流等效子电路模型来校正所述直流测试数据。
  9. 一种半导体器件的建模优化方法，其特征在于，包括：
    对于测试特定非直流参数的测试结构，执行如权利要求1-7任一所述的方法获得建模数据；
    进行建模；
    其中，所述建模数据至少包括直流测试数据和所述测试结构测试所述非直流参数的测试数据。
  10. 一种半导体器件的建模优化系统，其特征在于，包括：
    建模数据获取单元，用于对于测试特定非直流参数的测试结构，从如权利要求8所述的半导体器件的测试优化系统获得建模数据；
    建模单元，用于进行建模；
    其中，所述建模数据至少包括直流测试数据和所述测试结构测试所述非直流参数的测试数据。
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