WO2018041080A1 - 用于提升静电放电保护能力的半导体装置及其版图结构 - Google Patents

用于提升静电放电保护能力的半导体装置及其版图结构 Download PDF

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WO2018041080A1
WO2018041080A1 PCT/CN2017/099380 CN2017099380W WO2018041080A1 WO 2018041080 A1 WO2018041080 A1 WO 2018041080A1 CN 2017099380 W CN2017099380 W CN 2017099380W WO 2018041080 A1 WO2018041080 A1 WO 2018041080A1
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electrostatic discharge
line width
characteristic line
discharge protection
region
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PCT/CN2017/099380
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English (en)
French (fr)
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汪广羊
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无锡华润上华科技有限公司
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Priority to US16/329,665 priority Critical patent/US11088132B2/en
Publication of WO2018041080A1 publication Critical patent/WO2018041080A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H01L27/0274—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the field effect transistor, e.g. gate coupled transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H01L27/0277—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base of said parasitic bipolar transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection

Definitions

  • the present invention relates to semiconductor design and fabrication processes, and more particularly to a layout structure for enhancing electrostatic discharge protection capabilities.
  • Electrostatic discharge is a natural phenomenon that prevails in our lives.
  • the large current generated in a short period of time during electrostatic discharge can cause fatal damage to integrated circuits, which is an important problem causing failure in integrated circuit production applications.
  • electrostatic discharge phenomena occurring on the human body it usually occurs within a few hundred nanoseconds, and the maximum current peak may reach several amps.
  • electrostatic discharge occurs for a shorter period of time and the current is larger.
  • Such a large current flows through the integrated circuit in a short period of time, and the power consumption generated can seriously exceed the maximum value that the integrated circuit can withstand, thereby causing serious physical damage to the integrated circuit and causing its final failure.
  • a layout structure for improving electrostatic discharge protection capability is provided.
  • a layout structure for improving electrostatic discharge protection capability comprising: an electrostatic discharge protection device; and a device having a small characteristic line width, located on the same well region as the electrostatic discharge protection device, wherein the feature line width is small Located in the middle portion, the electrostatic discharge protection device is disposed on both sides of the device having a small feature line width.
  • a layout structure of a semiconductor device for improving electrostatic discharge protection capability comprising: an electrostatic discharge protection device; and a device having a small characteristic line width, located above the same well region as the electrostatic discharge protection device
  • the device having a small characteristic line width is located at an intermediate portion, and the electrostatic discharge protection device is disposed on both sides of the device having a small feature line width;
  • the well region is provided with the a device having a small characteristic line width and the electrostatic discharge protection device, wherein the device having a small characteristic line width is located at an intermediate portion, and the electrostatic discharge protection device is disposed on both sides of the device having a small feature line width;
  • the layout structure includes:
  • each gate poly is a strip-shaped structure, and each of the gate polysilicon is laterally spaced Arranging, the width direction of the gate poly is the lateral direction;
  • a metal layer comprising: a first metal layer, an interdigitated structure for connecting an N-type source region of the ESD protection device and an N-type source region of the device having a small characteristic line width; and a second The metal layer is an interdigitated structure for connecting the N-type drain region of the ESD protection device and the N-type drain region of the device having a small characteristic line width.
  • FIG. 1 is a schematic cross-sectional view of a GGNMOS in an ESD protection technique in an embodiment
  • FIG. 2 is a schematic diagram of a layout structure corresponding to the ESD protection circuit of FIG. 1;
  • FIG. 3 is a schematic diagram of a layout structure corresponding to an ESD protection circuit in an embodiment
  • FIG. 4 is a schematic diagram showing the flow direction of a discharge current when an electrostatic discharge protection test is performed on the layout structure of FIG. 3 in an embodiment.
  • Spatial relationship terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., may be used herein for convenience of description. The relationship of one element or feature shown in the figures to the other elements or features is thus described. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned “on” or “below” or “below” or “under” the element or feature is to be “on” the other element or feature.
  • the exemplary terms “below” and “include” can include both the above and the The device may be otherwise oriented (rotated 90 degrees or other orientation) and the spatial descriptors used herein interpreted accordingly.
  • composition and/or “comprising”, when used in the specification, is used to determine the presence of the features, integers, steps, operations, components and/or components, but does not exclude one or more The presence or addition of features, integers, steps, operations, components, components, and/or groups.
  • the term “and/or” includes any of the items listed. And all combinations.
  • Electrostatic discharge can create a transient high voltage inside the IC that will cause breakdown of the gate oxide and cause the IC to malfunction.
  • the electrostatic discharge protection circuit commonly used in the prior art is GGNMOS.
  • the decreasing gate oxide thickness is increasingly sensitive to the effects of electrostatic discharge.
  • the source S and the gate G are grounded, the pickup region is also grounded, and the NPN junction formed between each pair of the source S and the drain D is picked up.
  • the resistances formed between the regions are R1, R2, R3, and R4, respectively, wherein the NPN junction formed between each pair of source S and drain D is referred to as a finger.
  • each finger in the GGNMOS simultaneously turns on electrostatic discharge protection.
  • the width of the MOS should not be too large, otherwise it will affect the frequency of the clock circuit.
  • a device having a small characteristic line width is often used as a port circuit, such as a redundant MOS, and then a GGNMOS or other electrostatic discharge protection circuit similar to the working principle of the GGNMOS is connected in parallel.
  • Devices with small feature line widths typically have a linewidth of less than 100 microns, depending on the specific needs of the layout design.
  • the electrostatic discharge protection device 201 and the device 202 having a small characteristic line width are respectively located on different well regions.
  • the portion between the ESD protection device 201 and the device 202 having a small characteristic line width has an isolation structure such as field oxide or shallow trench isolation, and the isolation structure and other devices may exist.
  • the gate of the device 202 having a small characteristic line width is connected to the control terminal of the internal circuit, the trigger voltage is low, and in the occurrence of electrostatic discharge, the energy generated by the electrostatic discharge is basically released through the device having a small characteristic line width, due to the electrostatic discharge protection device.
  • the devices with small characteristic line widths are respectively located on different well regions, and the two are separated by the isolation structure, and the generated substrate current cannot effectively trigger the electrostatic discharge protection device, thereby causing the device with small characteristic line width to be very
  • the ESD failure occurs at low ESD levels, and the ESD protection device in parallel with devices with a small characteristic line width does not protect.
  • an electrostatic discharge protection device is located in the same well region as a device 300 having a small characteristic line width to be protected.
  • the device 300 having a small characteristic line width is located at the intermediate portion, and electrostatic discharge protection devices are disposed on both sides thereof, thereby saving the layout area and improving the electrostatic discharge protection capability of the device 300 having a small characteristic line width.
  • the electrostatic discharge protection device and the protected redundant MOS are located on the same well region instead of being respectively located on different well regions, thereby thereby Partial isolation structure to save layout area.
  • the protected redundant MOS is located in the middle portion, and electrostatic discharge protection devices such as GGNMOS are disposed on both sides of the protected redundant MOS.
  • the layout designer can adjust the ESD protection device and the protected device by modifying the pattern size of the lithography mask according to actual needs.
  • the size ratio of the device 300 with a small characteristic line width is relatively flexible, and there is no need to redesign the layout.
  • the semiconductor device further includes an active region, wherein the redundant MOS, the GGNMOS and the well region are disposed in the active region, and the redundant MOS is located in the middle portion of the active region, and the GGNMOS is disposed in the same active region in the redundant MOS lateral direction (ie, Both sides in the left and right direction in Fig. 4).
  • the well region is a P well
  • the N-doped region SN of the GGNMOS and the N-type doped region SN of the redundant MOS are disposed in the P well (the N-doped region of the GGNMOS and the N-doped region of the redundant MOS are in the figure) 4 is represented by SN).
  • the semiconductor device further includes a P-type doping region SP drawn as a substrate, and the P-type doping region SP is disposed outside the GGNMOS in the active region, see FIG. 4, that is, a P-type including a left side of the GGNMOS disposed on the left side.
  • the P-type doped region is disposed in the P-well, and the doping concentration of the P-type doped region is greater than the doping concentration of the P-well.
  • the device 300 having a small characteristic line width is protected (corresponding to the device 300 having a small characteristic line width to be protected in FIG.
  • the cross-sectional structure has a low trigger voltage, and the energy generated by the electrostatic discharge is first released through the drain end of the device 300 having a small characteristic line width.
  • the gate of the device 300 with a small feature line width is in an off state, and does not function under normal operation. Since there is no barrier structure between the two, the subsequent substrate current will quickly trigger static electricity.
  • a parasitic bipolar transistor (BJT) in the discharge protection device improves the electrostatic discharge protection capability.
  • the device 300 having a small characteristic line width is located at the middle portion, and the electrostatic discharge protection device is disposed on both sides thereof, so that the components of the electrostatic discharge protection device are mirror-symmetrically distributed around the device 300 having a small characteristic line width, thereby shortening the substrate current pair.
  • the triggering time of the components of the ESD protection device is located at the middle portion, and the electrostatic discharge protection device is disposed on both sides thereof, so that the components of the electrostatic discharge protection device are mirror-symmetrically distributed around the device 300 having a small characteristic line width, thereby shortening the substrate current pair.
  • the channel length of the device having a small feature line width is greater than the channel length of the electrostatic discharge protection device.
  • the channel length L of the device 300 having a small characteristic line width to be protected and the channel length Ld of the ESD protection device such that L is larger than Ld, an increase in the channel resistance increases the device 300 having a small characteristic line width to be protected.
  • the trigger voltage enhances the leakage conduction capability of the drain, thereby further enhancing Electrostatic discharge protection.
  • the device 300 and the ESD protection device having a small characteristic line width are double-gate structure, a source is shared between the gates, the source is doped with an N+ impurity, and the N+ impurity includes phosphorus.
  • SN represents an N-type doped region doped with an N+ type impurity
  • SP represents a pick-up, and is doped with a P+ type impurity
  • the P+ type impurity includes boron, aluminum, gallium, indium, germanium. Wait.
  • the distance between the drain terminal and the gate of the device 300 having a small feature line width is generally greater than the distance between the drain terminal and the gate of the ESD protection device.
  • the gate and the source of the ESD protection device are connected together to be connected to the ground, and the source of the device 300 having the small characteristic line width is connected to the ground, and the device 300 having the characteristic line width is protected.
  • the gate is connected to the internal circuit control terminal.
  • the drain of the ESD protection device and the drain of the device 300 having a small feature line width being protected are connected to the I/O port.
  • an electrostatic discharge protection device is disposed on both sides of the device 300 having a small characteristic line width, and the device 300 having a small characteristic line width can be effectively electrostatically discharged, and at the same time, the cost and the circuit are reduced. Design difficulty and increase the flexibility of circuit design.
  • the layout structure includes A plurality of gate polysilicon, a plurality of N-type doped regions, and a metal layer.
  • Each of the gate polysilicon has a long strip structure, including a gate 403 of the ESD protection device and a gate 303 of the device having a small characteristic line width, and each gate polysilicon is laterally (ie, a channel length of the ESD protection device)
  • the direction or the line width of the small device is arranged in a channel length direction, and the width direction of the gate polysilicon of the elongated structure is also the channel length direction of the electrostatic discharge protection device or the channel length direction of the device having a small feature width.
  • the channel length direction of the device having a small characteristic line width is the current direction between the source and the drain of the device having a small characteristic line width, and the channel length direction of the ESD protection device is between the source and the drain of the ESD protection device. Current direction.
  • the device 300 having a small characteristic line width may be a redundant MOS, and the electrostatic discharge protection device may be a GGNMOS.
  • An N-type doping region is disposed between adjacent gate polysilicon and gate polysilicon; the N-type doping region package An N-type source region 401 as an electrostatic discharge protection device, an N-type drain region 402 as an electrostatic discharge protection device, an N-type source region 301 as a device having a small characteristic line width, and a device N-type drain region as a feature line width. 302.
  • the N-type source region 401 as an electrostatic discharge protection device and the N-type drain region 402 as an electrostatic discharge protection device are laterally distributed.
  • the N-type source region 301 of the device 300 having a small feature line width and the N-type drain region 302 as the device 300 having a small feature line width are laterally distributed.
  • the metal layer includes a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer are both interdigitated structures, wherein the first metal layer is used for the N-type source region 401 and the characteristic line width of the electrostatic discharge protection device
  • the N-type source regions 301 of the small device 300 are connected together, and the second metal layer is used to connect the N-type drain region 402 of the ESD protection device and the device N-type drain region 302 having a small characteristic line width.
  • the layout structure further includes a contact hole including a contact hole for extracting each of the N-type doping regions and a contact hole for drawing the gate polysilicon of each of the ESD protection devices; and an N-type source region 401 of the ESD protection device And the N-type source region 301 of the device 300 having a small characteristic line width is electrically connected to the first metal layer through the corresponding contact hole, and the N-type drain region 402 of the ESD protection device and the device N-type drain region 302 having a small characteristic line width pass through The corresponding contact hole is electrically connected to the second metal layer, and the gate polysilicon of the electrostatic discharge protection device is electrically connected to the first metal layer through the corresponding contact hole.
  • the ESD protection device is located on the same well region as the device 300 having a small characteristic line width to be protected, and the ESD protection device and the device 300 having a small characteristic line width to be protected, a similar layout structure is adopted, both of which are on the layout.
  • the only difference is the contact hole/metal layer, so the layout designer can adjust the pattern size of the metal/metal contact mask according to the actual needs to adjust the electrostatic discharge protection device and the protected feature line width.
  • the device 300's size ratio is flexible and does not require redesigning the layout.

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Abstract

一种用于提升静电放电保护能力的半导体装置，静电放电保护器件与被保护的特征线宽小的器件（300）位于同一阱区之上，特征线宽小的器件（300）位于中间部分，特征线宽小的器件（300）的两侧布置静电放电保护器件。

Description

用于提升静电放电保护能力的半导体装置及其版图结构 技术领域
本发明涉及半导体设计与制造工艺，特别涉及一种用于提升静电放电保护能力的版图结构。
背景技术
静电放电(ESD)是在我们生活中普遍存在的自然现象，但静电放电时在短时间内产生的大电流，会对集成电路产生致命的损伤，是集成电路生产应用中造成失效的重要问题。例如，对于发生在人体上的静电放电现象，通常发生在几百个纳秒内，最大的电流峰值可能达到几个安培，其它模式静电放电发生的时间更短，电流也更大。如此大的电流在短时间内通过集成电路，产生的功耗会严重超过集成电路所能承受的最大值，从而对集成电路产生严重的物理损伤并导致其最终失效。
目前在电路方面，主要是增加集成电路本身的静电放电耐受能力，例如增加额外的静电保护器件或者电路来保护集成电路内部电路不被静电放电损害。
发明内容
根据本申请的各实施例，提供一种用于提升静电放电保护能力的版图结构。
一种用于提升静电放电保护能力的版图结构，包括：静电放电保护器件；及特征线宽小的器件，与所述静电放电保护器件位于同一阱区之上，所述特征线宽小的器件位于中间部分，所述特征线宽小的器件的两侧布置所述静电放电保护器件。
还提供一种用于提升静电放电保护能力的半导体装置的版图结构，所述半导体装置包括：静电放电保护器件；及特征线宽小的器件，与所述静电放电保护器件位于同一阱区之上，所述特征线宽小的器件位于中间部分，所述特征线宽小的器件的两侧布置所述静电放电保护器件；所述阱区上设有所述 特征线宽小的器件与所述静电放电保护器件，所述特征线宽小的器件位于中间部分，所述特征线宽小的器件的两侧布置所述静电放电保护器件；
所述版图结构包括：
多个栅极多晶硅，包括所述静电放电保护器件的栅极和所述特征线宽小的器件的栅极，每个栅极多晶硅为长条状结构，各所述栅极多晶硅在横向上间隔排列，所述栅极多晶硅的宽度方向为所述横向；
多个N型掺杂区，设于相邻的栅极多晶硅与栅极多晶硅之间，作为所述静电放电保护器件的N型源区和作为所述静电放电保护器件的N型漏区在横向上间隔分布；
金属层，包括：第一金属层，为叉指结构，用于将所述静电放电保护器件的N型源区以及所述特征线宽小的器件的N型源区连接在一起；以及第二金属层，为叉指结构，用于将静电放电保护器件的N型漏区以及所述特征线宽小的器件N型漏区连接在一起。
本发明的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中的ESD保护技术中的GGNMOS的示意性剖面图；
图2为图1中ESD保护电路所对应的版图结构的示意图；
图3为一实施例中ESD保护电路所对应的版图结构的示意图；
图4为一实施例中对图3的版图结构进行静电放电保护测试时放电电流流向的示意图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在…上”、“与…相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在…上”、“与…直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在…下”、“在…下面”、“下面的”、“在…之下”、“在…之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在…下面”和“在…下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何 及所有组合。
当集成电路(IC)开始工作时，来自外部的高能量施加给IC，在IC中会出现瞬间发生的静电放电现象。静电放电会在IC内部产生瞬时高压，其将导致栅氧化物的击穿，使IC出现故障。现有技术中常用的静电放电保护电路为GGNMOS。随着MOS器件的特征尺寸的不断减小，不断减小的栅氧化物厚度对静电放电的冲击越来越敏感。如图1所示，在GGNMOS的NMOS区中，源极S和栅极G接地，拾取区(Pickup)也接地，在每对源极S和漏极D之间形成的NPN结与所述拾取区之间形成的电阻分别为R1、R2、R3和R4，其中每对源极S和漏极D之间形成的NPN结称为指(finger)。当发生静电放电时，GGNMOS中的每个指同时开启静电放电保护。
在时钟电路应用中，MOS的宽度不能太大，否则会影响时钟电路的频率。在现有的静电放电电路保护方案中，经常是采用特征线宽小的器件作为端口电路，例如冗余MOS，然后并联GGNMOS或者其它与GGNMOS的工作原理类似的静电放电保护电路。特征线宽小的器件的线宽通常小于100微米，具体大小根据版图设计的具体需要而定。
由于GGNMOS或者其它与GGNMOS的工作原理类似的静电放电保护电路的结构较为复杂，占用的版图面积较大，因此，如图2所示，在现有的静电放电电路保护方案所对应的版图结构中，静电放电保护器件201和特征线宽小的器件202分别位于不同的阱区之上。静电放电保护器件201和特征线宽小的器件202之间的部分存在场氧或者浅沟槽隔离之类的隔离结构，也可能存在所述隔离结构和其它器件。
由于特征线宽小的器件202的栅极连接内部电路的控制端，触发电压低，在出现静电放电时，静电放电产生的能量基本上都会经由特征线宽小的器件释放，由于静电放电保护器件和特征线宽小的器件分别位于不同的阱区之上，而二者之间受到隔离结构的阻隔，产生的衬底电流不能有效触发静电放电保护器件，从而造成特征线宽小的器件在很低的静电放电等级下失效，而与特征线宽小的器件并联的静电放电保护器件没有起到保护作用。
为了解决上述问题，提出一种用于提升静电放电保护能力的半导体装置，如图3所示，在一个实施例中，静电放电保护器件与被保护的特征线宽小的器件300位于同一阱区之上。特征线宽小的器件300位于中间部分，其两侧布置静电放电保护器件，由此可以节省版图面积，同时又提高了对特征线宽小的器件300的静电放电保护能力。
以属于特征线宽小的器件300的冗余MOS为例，静电放电保护器件与被保护的冗余MOS位于同一阱区之上，而不是分别位于不同的阱区之上，由此可以通过省去部分隔离结构来节省版图面积。被保护的冗余MOS位于中间部分，被保护的冗余MOS的两侧布置静电放电保护器件，例如GGNMOS。
由于静电放电保护器件与被保护的特征线宽小的器件300位于同一阱区之上，版图设计人员根据实际需要通过修改光刻掩膜板的图案尺寸就可以调节静电放电保护器件与被保护的特征线宽小的器件300的尺寸比例，比较灵活，无需重新设计版图。
半导体装置还包括有源区，其中冗余MOS、GGNMOS及阱区设于有源区内，且冗余MOS位于有源区的中间部分，GGNMOS设于同一有源区内冗余MOS横向(即图4中的左右方向)两侧。阱区为P阱，GGNMOS的N型掺杂区SN和冗余MOS的N型掺杂区SN设于P阱内(GGNMOS的N型掺杂区和冗余MOS的N型掺杂区在图4中均以SN表示)。
半导体装置还包括作为衬底引出的P型掺杂区SP，P型掺杂区SP设于有源区内GGNMOS的更外侧，参见图4，即包括设于左边的GGNMOS的左侧的P型掺杂区SP、和设于右边的GGNMOS的右侧的P型掺杂区SP。
在一个实施例中，P型掺杂区设于P阱内，P型掺杂区的掺杂浓度大于P阱的掺杂浓度。
如图4所示，对如图3所示的版图结构进行静电放电保护测试时，由于被保护的特征线宽小的器件300(对应于图3中的被保护的特征线宽小的器件300的剖面结构)的触发电压低，静电放电产生的能量会先通过被保护的特征线宽小的器件300的漏端释放。此时，被保护的特征线宽小的器件300的栅极处于关断状态，正常工作下不起作用，由于二者之间不存在隔离结构的阻隔，随后产生的衬底电流会快速触发静电放电保护器件中的寄生双极型三极管(BJT)，进而提高静电放电保护能力。
特征线宽小的器件300位于中间部分，其两侧布置静电放电保护器件，可以使静电放电保护器件的组成部分以特征线宽小的器件300为中心呈镜面对称分布，从而缩短衬底电流对静电放电保护器件的组成部分的触发时间。
一个实施例中，特征线宽小的器件的沟道长度大于静电放电保护器件的沟道长度。通过调整被保护的特征线宽小的器件300的沟道长度L和静电放电保护器件的沟道长度Ld，使L大于Ld，沟道电阻的增大会提升被保护的特征线宽小的器件300的触发电压，增强其漏端导通能力，从而进一步提升 静电放电保护能力。一个实施例中，被保护的特征线宽小的器件300和静电放电保护器件均为双栅结构，栅极之间共用一个源极，源极掺杂有N+型杂质，N+型杂质包括磷、氮、砷、锑、铋等。在图4中，SN代表N型掺杂区，掺杂有N+型杂质，SP代表拾取区(pick-up)，掺杂有P+型杂质，P+型杂质包括硼、铝、镓、铟、铊等。
一个实施例中，特征线宽小的器件300的漏端与栅极之间的距离通常大于静电放电保护器件的漏端与栅极之间的距离。
一个实施例中，静电放电保护器件的栅极和源极接在一起连接接地端，被保护的特征线宽小的器件300的源极连接接地端，被保护的特征线宽小的器件300的栅极连接内部电路控制端。
一个实施例中，静电放电保护器件的漏极和被保护的特征线宽小的器件300的漏极均连接I/O端口。
上述用于提升静电放电保护能力的半导体装置，特征线宽小的器件300的两侧布置静电放电保护器件，可以对特征线宽小的器件300进行有效的静电放电保护，同时，降低成本和电路设计难度，增加电路设计的灵活性。
还提出一种用于提升静电放电保护能力的半导体装置的版图结构，该半导体装置可为如上任意一个实施例中的用于提升静电放电保护能力的半导体装置；如图3所示，版图结构包括多个栅极多晶硅、多个N型掺杂区以及金属层。
其中每个栅极多晶硅为长条状结构，包括静电放电保护器件的栅极403和特征线宽小的器件的栅极303，各栅极多晶硅在横向上(即静电放电保护器件的沟道长度方向或特征线宽小器件的沟道长度方向)间隔排列，长条状结构的栅极多晶硅的宽度方向也是静电放电保护器件的沟道长度方向或特征线宽小器件的沟道长度方向。特征线宽小的器件的沟道长度方向为特征线宽小的器件的源极与漏极间的电流方向，静电放电保护器件的沟道长度方向为静电放电保护器件的源极与漏极间的电流方向。
其中特征线宽小的器件300可为冗余MOS，静电放电保护器件可为GGNMOS。
N型掺杂区设于相邻的栅极多晶硅与栅极多晶硅之间；该N型掺杂区包 括作为静电放电保护器件的N型源区401、作为静电放电保护器件的N型漏区402、作为特征线宽小的器件的N型源区301以及作为特征线宽小的器件N型漏区302。作为静电放电保护器件的N型源区401和作为静电放电保护器件的N型漏区402在横向上间隔分布。作为特征线宽小的器件300的N型源区301和作为特征线宽小的器件300的N型漏区302在横向上间隔分布。
金属层包括第一金属层以及第二金属层，第一金属层和第二金属层均为叉指结构，其中第一金属层用于将静电放电保护器件的N型源区401以及特征线宽小的器件300的N型源区301连接在一起，第二金属层用于将静电放电保护器件的N型漏区402以及特征线宽小的器件N型漏区302连接在一起。
一个实施例中，该版图结构还包括接触孔，接触孔包括引出各N型掺杂区的接触孔以及引出各静电放电保护器件栅极多晶硅的接触孔；静电放电保护器件的N型源区401以及特征线宽小的器件300的N型源区301通过对应的接触孔与第一金属层电连接，静电放电保护器件的N型漏区402以及特征线宽小的器件N型漏区302通过对应的接触孔与第二金属层电连接，静电放电保护器件的栅极多晶硅通过对应的接触孔与第一金属层电连接。
由于静电放电保护器件与被保护的特征线宽小的器件300位于同一阱区之上，并且静电放电保护器件与被保护的特征线宽小的器件300采用类似的版图结构，二者在版图上的区别仅在于接触孔/金属层，因此版图设计人员根据实际需要修改金属层(Metal)/接触孔的光刻掩膜板的图案尺寸就可以调节静电放电保护器件与被保护的特征线宽小的器件300的尺寸比例，比较灵活，无需重新设计版图。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进， 这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种用于提升静电放电保护能力的半导体装置，包括：
    静电放电保护器件；及
    特征线宽小的器件，与所述静电放电保护器件位于同一阱区之上，所述特征线宽小的器件位于中间部分，所述特征线宽小的器件的两侧布置所述静电放电保护器件。
  2. 根据权利要求1所述的半导体装置，其特征在于，所述特征线宽小的器件为冗余MOS，所述静电放电保护器件为GGNMOS。
  3. 根据权利要求1所述的半导体装置，其特征在于，通过修改光刻掩膜板的图案尺寸来调节所述特征线宽小的器件和所述静电放电保护器件的尺寸比例。
  4. 根据权利要求1所述的半导体装置，其特征在于，所述特征线宽小的器件的沟道长度大于所述静电放电保护器件的沟道长度。
  5. 根据权利要求1所述的半导体装置，其特征在于，所述特征线宽小的器件和所述静电放电保护器件为双栅结构，栅极之间共用一个源极。
  6. 根据权利要求5所述的半导体装置，其特征在于，所述源极掺杂有N+型杂质，所述N+型杂质是磷、氮、砷、锑或铋中的至少一种。
  7. 根据权利要求1的所述的半导体装置，其特征在于，所述静电放电保护器件的栅极和源极接在一起连接接地端。
  8. 根据权利要求1的所述的半导体装置，其特征在于，所述特征线宽小的器件的源极连接接地端。
  9. 根据权利要求1的所述的半导体装置，其特征在于，所述特征线宽小的器件的漏极和所述静电放电保护器件的漏极均连接I/O端口。
  10. 根据权利要求1的所述的半导体装置，其特征在于，所述特征线宽小的器件的线宽小于100微米。
  11. 根据权利要求2的所述的半导体装置，其特征在于，包括有源区，所述冗余MOS、所述GGNMOS及所述阱区设于所述有源区内，所述阱区为P阱，所述GGNMOS的N型掺杂区和所述冗余MOS的N型掺杂区设于所述P阱内。
  12. 根据权利要求11的所述的半导体装置，其特征在于，还包括作为衬底引出的P型掺杂区，所述P型掺杂区设于两侧的所述GGNMOS的更外侧。
  13. 根据权利要求12的所述的半导体装置，其特征在于，所述P型掺杂 区设于所述P阱内，所述P型掺杂区的掺杂浓度大于所述P阱的掺杂浓度。
  14. 一种用于提升静电放电保护能力的半导体装置的版图结构，所述半导体装置包括：
    静电放电保护器件；及
    特征线宽小的器件，与所述静电放电保护器件位于同一阱区之上，所述特征线宽小的器件位于中间部分，所述特征线宽小的器件的两侧布置所述静电放电保护器件；所述版图结构包括：
    多个栅极多晶硅，包括所述静电放电保护器件的栅极和所述特征线宽小的器件的栅极，每个栅极多晶硅为长条状结构，各所述栅极多晶硅在横向上间隔排列，所述栅极多晶硅的宽度方向为所述横向；
    多个N型掺杂区，设于相邻的栅极多晶硅与栅极多晶硅之间，作为所述静电放电保护器件的N型源区和作为所述静电放电保护器件的N型漏区在横向上间隔分布；
    金属层，包括：
    第一金属层，为叉指结构，用于将所述静电放电保护器件的N型源区以及所述特征线宽小的器件的N型源区连接在一起；以及
    第二金属层，为叉指结构，用于将静电放电保护器件的N型漏区以及所述特征线宽小的器件N型漏区连接在一起。
  15. 根据权利要求14所述的版图结构，还包括接触孔，所述接触孔包括引出各N型掺杂区的接触孔以及引出各静电放电保护器件栅极多晶硅的接触孔；所述静电放电保护器件的N型源区以及所述特征线宽小的器件的N型源区通过对应的接触孔与所述第一金属层电连接，所述静电放电保护器件的N型漏区以及所述特征线宽小的器件N型漏区通过对应的接触孔与所述第二金属层电连接，各静电放电保护器件的栅极多晶硅通过对应的接触孔与所述第一金属层电连接。
  16. 根据权利要求14所述的版图结构，其特征在于，所述特征线宽小的器件为冗余MOS，所述静电放电保护器件为GGNMOS。
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