WO2018032918A1 - 薄膜晶体管及其制备方法、显示基板及显示装置 - Google Patents

薄膜晶体管及其制备方法、显示基板及显示装置 Download PDF

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WO2018032918A1
WO2018032918A1 PCT/CN2017/092748 CN2017092748W WO2018032918A1 WO 2018032918 A1 WO2018032918 A1 WO 2018032918A1 CN 2017092748 W CN2017092748 W CN 2017092748W WO 2018032918 A1 WO2018032918 A1 WO 2018032918A1
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gate
substrate
layer
semiconductor layer
insulating layer
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PCT/CN2017/092748
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English (en)
French (fr)
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秦纬
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京东方科技集团股份有限公司
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Priority to US15/765,473 priority Critical patent/US10707353B2/en
Publication of WO2018032918A1 publication Critical patent/WO2018032918A1/zh

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    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Definitions

  • the present disclosure relates to the field of transistors, and in particular, to a thin film transistor (TFT), a method for fabricating the same, a display substrate, and a display device.
  • TFT thin film transistor
  • a TFT is a field effect semiconductor device including several important components such as a substrate, a gate, a gate insulating layer, an active layer, and a source and drain.
  • the active layer has a critical impact on device performance and manufacturing processes.
  • the liquid crystal display device with TFT as the driving unit has been rapidly developed due to its small size, light weight and high quality, and has become a mainstream information display terminal.
  • amorphous silicon has the disadvantages of low field effect mobility, strong photosensitivity, and opaque materials.
  • the large-area fabrication process of polysilicon TFTs is complicated, and low-temperature processes are difficult to achieve.
  • Embodiments of the present disclosure provide a thin film transistor including a substrate, a gate, a gate insulating layer, a semiconductor layer, and a source and a drain, wherein the gate has a rough surface on a side facing the semiconductor layer .
  • the thin film transistor has a bottom gate structure.
  • the gate is disposed on the substrate, the gate insulating layer covers the gate and the substrate, the semiconductor layer is disposed on the gate insulating layer, and the semiconductor layer is in the A projection on the substrate is located within the projection of the gate on the substrate, and the source and drain are disposed on the semiconductor layer.
  • the thin film transistor has a top gate structure.
  • the semiconductor layer is disposed on the substrate, the source and the drain are disposed on the semiconductor layer, and the gate insulating layer covers the source and drain, the semiconductor layer, and the lining a gate, the gate is disposed on the gate insulating layer, and a projection of the semiconductor layer on the substrate is located within a projection of the gate on the substrate.
  • the surface of the gate insulating layer facing the gate is rough.
  • the semiconductor layer includes a metal oxide, a-Si, or p-Si.
  • the gate has a rough surface on a side facing the semiconductor layer.
  • the rough surface of the gate has a surface roughness of about 20 to 100 nm.
  • the thin film transistor further includes a buffer layer disposed between the gate electrode and the gate insulating layer.
  • the buffer layer comprises a conductive material.
  • the embodiment of the present disclosure further provides a display substrate including the thin film transistor described in the above embodiments.
  • the embodiment of the present disclosure further provides a display device including the display substrate described in the above embodiments.
  • Embodiments of the present disclosure provide a method of fabricating a thin film transistor including forming a gate, a gate insulating layer, a semiconductor layer, and a source and a drain on a substrate, wherein the step of forming the gate includes forming in a front direction One side of the semiconductor layer has a gate with a rough surface.
  • the steps of forming the gate, the gate insulating layer, the semiconductor layer, and the source and the drain include: forming the gate on the substrate; forming a surface covering the gate and the substrate a gate insulating layer; forming the semiconductor layer on the gate insulating layer, wherein a projection of the semiconductor layer on the substrate is within a projection of the gate on the substrate; The source and drain are formed on the semiconductor layer.
  • the step of forming the gate on the substrate includes: depositing a gate metal layer on the substrate; performing a microetching treatment on the gate metal layer to form a rough surface on a side facing away from the substrate
  • the surface roughness of the surface is about 20 to 100 nm; and the gate metal layer is patterned to form a gate having a rough surface on a side facing away from the substrate.
  • the method further includes forming a buffer layer covering the gate.
  • the step of forming the gate and the buffer layer includes: depositing a gate metal layer on the substrate; performing a microetching treatment on the gate metal layer such that the gate metal layer is separated from the gate metal layer a surface of one side of the substrate is rough; a layer of conductive material is deposited on a surface of the gate metal layer; and a patterning process is performed on the gate metal layer and the conductive material layer to form the gate and the cover The buffer layer of the gate.
  • the step of performing a microetching treatment on the gate metal layer includes etching the surface of the gate metal layer away from the substrate side using a weakly acidic solution or an oxidizing agent.
  • the step of the microetching treatment includes etching the gate metal layer with hydrogen peroxide having a mass concentration of about 1 to 3%, and the etching time is about 10 seconds to 10 minutes.
  • the steps of forming the gate, the gate insulating layer, the semiconductor layer, and the source and the drain include: forming the semiconductor layer on the substrate; forming the source and the semiconductor layer a drain; forming the gate insulating layer covering the source and drain, the semiconductor layer, and the substrate; and forming the gate on the gate insulating layer, wherein the semiconductor layer A projection on the substrate is located within a projection of the gate on the substrate.
  • the method further includes: treating the gate insulating layer with a plasma gas such that the gate insulating layer is away from the substrate The surface is rough.
  • FIG. 1 is a schematic structural view of a TFT according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a TFT according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of incidence and reflection of light when a backlight illuminates a TFT according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural view of a conductive metal material layer deposited on a gate metal layer according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural view of a gate electrode and a buffer layer formed by patterning a gate metal layer and a conductive material layer according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a TFT according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of incidence and reflection of light when a backlight illuminates a TFT according to an embodiment of the present disclosure
  • FIG. 8A is a view showing a result of a TFT stability test prepared in an embodiment of the present disclosure
  • Fig. 8B is a graph showing the results of a known TFT stability test.
  • Reference numerals 1 backlight; 2 light; 3 substrate; 4 gate insulating layer; 5 gate; 6 source or drain; 7 semiconductor layer; 8 gate rough surface; 9 buffer layer; Rough surface of the insulating layer; 11 light shielding layer.
  • a backlight illuminates a TFT
  • light emitted from the backlight passes through the substrate and the transparent gate insulating layer, and directly illuminates the source or the drain.
  • Light that strikes the source or drain is reflected onto the gate.
  • Light is subjected to continuous reflection between the source or the drain and the gate to illuminate the semiconductor layer.
  • the semiconductor layer is sensitive to light. Especially when the semiconductor material is a metal oxide, the oxide semiconductor layer is very sensitive to light. After the semiconductor layer is exposed to light for a long time, the performance of the TFT is significantly degraded. Accordingly, embodiments of the present disclosure are directed to alleviating or eliminating one or more of these problems.
  • Embodiments of the present disclosure disclose a TFT including a substrate, a gate, a gate insulating layer, a semiconductor layer, and a source and a drain.
  • the gate has a rough surface toward a side of the semiconductor layer.
  • the TFT is a bottom gate structure and includes a substrate; a gate disposed on the substrate; a side of the gate facing away from the substrate having a rough surface; a gate insulating layer; disposed on the gate insulating layer a semiconductor layer having a projection on the substrate within a projection of the gate on the substrate; and a source and a drain disposed on the semiconductor layer.
  • FIG. 1 is a schematic structural diagram of a TFT according to an embodiment of the present disclosure.
  • the substrate 3 is, for example, a glass substrate.
  • the gate insulating layer 4 includes a silicon oxide material and is light transmissive.
  • the gate 5 includes a metal material.
  • the source or drain 6 comprises a metallic material.
  • the semiconductor layer 7 includes indium gallium zinc oxide or indium zinc oxide or the like.
  • the grid 5 has a rough surface 8.
  • the TFT is a bottom gate structure.
  • the TFT includes a substrate 3; a gate 5 disposed on the substrate 3; a side of the gate 5 facing away from the substrate 3 having a rough surface 8; a gate insulating layer 4; disposed on the gate insulating layer 4.
  • a semiconductor layer 7, the projection of the semiconductor layer 7 on the substrate 3 is located within the projection of the gate 5 on the substrate 4; and a source and a drain 6 disposed on the semiconductor layer 7.
  • Embodiments of the present disclosure provide a TFT, a method for fabricating the same, a display substrate, and a display device, which effectively reduce a reflectance of a gate, reduce a frequency at which a semiconductor layer is irradiated with light, and improve a TFT. Stability and extend the life of the display device.
  • the gate 5 is modified, which has a rough surface 8 toward the side of the semiconductor layer 7.
  • the gate 5 has a rough surface toward the side of the semiconductor layer 7, that is, the side facing away from the substrate 3.
  • the rough surface is a rugged structure and is characterized, for example, by surface roughness.
  • the rough surface 8 has a surface roughness Ra of about 20 to 100 nm.
  • the rough surface 8 has poor performance in reflecting light, and is effective in preventing light from being reflected onto the semiconductor layer 7 by reflection.
  • the metal used for the gate 5 is a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or an alloy of these metals, and the present disclosure is not particularly limited.
  • the gate is for example copper.
  • the rough surface of the gate is obtained, for example, by a microetching process.
  • the microetching treatment is performed, for example, by etching a surface of the gate metal layer away from the substrate side using a weakly acidic solution or an oxidizing agent.
  • the etching solution selected in the microetching treatment is selected according to the specific material of the gate metal as long as the uneven surface can be formed.
  • copper is used as the gate, and the gate is etched using hydrogen peroxide having a mass concentration of about 1 to 3%, and the etching time is about 10 seconds to 10 minutes.
  • FIG. 2 is a schematic view showing the structure of an oxide TFT in an embodiment of the present disclosure.
  • the embodiment shown in Fig. 2 differs from the embodiment shown in Fig. 1 in that a buffer layer 9 is also provided above the rough surface 8 of the grid 5.
  • a buffer layer 9 is further disposed between the gate 5 and the gate insulating layer 4. The buffer layer 9 effectively prevents metal ions of the gate 5 from entering the gate insulating layer 4 and the semiconductor layer 7.
  • the buffer layer 9 comprises, for example, a conductive material, in particular a transparent conductive material.
  • the buffer layer 9 comprises indium gallium zinc oxide, indium tin oxide or indium zinc oxide.
  • FIG. 3 is a schematic diagram of incidence and reflection of light when a backlight illuminates a TFT according to an embodiment of the present disclosure.
  • Figure 3 is an enlarged view of the area of the broken line frame in Figure 2.
  • the semiconductor layer described in the embodiments of the present disclosure uses, for example, an oxide semiconductor, a-Si, or p-Si. Since the oxide semiconductor is relatively sensitive to light, the embodiment of the present disclosure is more effective in improving the stability of the TFT having the oxide semiconductor as the semiconductor layer.
  • the substrate of the TFT is, for example, glass, quartz or a flexible substrate such as polyimide or the like.
  • the gate insulating layer is made of, for example, silicon oxide or an organic resin material. The use of an organic resin as the gate insulating layer forms a flatter upper surface, preventing the oxide semiconductor layer from being affected by the surface roughness of the gate surface.
  • a flexible display device is prepared by using an organic resin as a gate insulating layer.
  • the source and drain electrodes provided on the oxide semiconductor layer are, for example, metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, and W, and alloys of these metals.
  • the source/drain metal layer is, for example, a single layer structure or a multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, or the like.
  • the embodiment of the present disclosure further discloses a method for fabricating a TFT, comprising: providing a substrate; forming a gate having a rough surface on the substrate, the rough surface being located on a side facing away from the substrate; preparing a gate insulating a layer; a semiconductor layer is prepared on the gate insulating layer, a projection of the semiconductor layer on the substrate is located in a projection of the gate on the substrate; a source and a drain are prepared to obtain a TFT.
  • forming a gate having a rough surface on the substrate includes the steps of: depositing a gate metal layer on the substrate; performing a microetching treatment on the gate metal layer to form a gate having a rough surface facing away from the side of the substrate a metal layer having a surface roughness Ra of about 20 to 100 nm; and a patterning process of the gate metal layer to form a gate having a rough surface facing away from the side of the substrate.
  • the method of depositing a gate metal layer on the substrate is physical sputtering or other deposition methods known to those skilled in the art.
  • the thickness of the gate metal layer is, for example, about 300 to 400 nm.
  • the microetching treatment includes, for example, etching a surface of the gate metal layer away from the substrate side using a weakly acidic solution or an oxidizing agent.
  • the etching solution selected in the microetching treatment is selected according to the specific material of the gate metal as long as a rough surface having unevenness can be formed.
  • copper is used as the gate, and the gate is etched using hydrogen peroxide having a mass concentration of about 1 to 3%.
  • the etching time is about 10 seconds to 10 minutes, for example, about 1 to 2 minutes.
  • the present disclosure controls the surface roughness of the gate surface by controlling the solution used in the microetching process and the etching time to achieve a better effect of avoiding light reflection.
  • a buffer layer is also formed on the semiconductor layer. That is, before the gate insulating layer is prepared, the method further includes: forming a buffer layer covering the gate.
  • forming the gate and the buffer layer comprises: depositing a gate metal layer on the substrate; performing a micro-etching treatment on the gate metal layer to form a gate metal layer having a rough surface on a side facing away from the substrate; Depositing a conductive material layer on a surface of the metal layer; and patterning the gate metal layer and the conductive material layer to form the gate and the buffer layer covering the gate.
  • the conductive material layer is formed, for example, of a transparent conductive material such as indium gallium zinc oxide, indium tin oxide or indium zinc oxide.
  • FIG. 4 is a schematic view showing the structure of a conductive metal material layer deposited on a gate metal layer. As shown, a gate metal layer is deposited on the substrate 3, the gate metal layer is microetched to form a gate 5 having a rough surface 8, and a buffer layer 9 covering the gate 5 is formed.
  • FIG. 5 is a schematic structural view of a gate electrode and a buffer layer formed by patterning a gate metal layer and a conductive material layer. As shown, the structure shown in FIG. 4 is patterned to form a gate 5 having a rough surface 8 and a buffer layer 9 covering the gate 5.
  • the semiconductor layer is, for example, an oxide semiconductor, a-Si or p-Si.
  • the method of the present disclosure is not particularly limited to a method of preparing a gate insulating layer, a semiconductor layer, and a source and a drain, according to a method known to those skilled in the art.
  • the TFT of the bottom gate structure is taken as an example for description. It should be noted that the concepts of the present disclosure are also applicable to TFTs of a top gate structure.
  • Fig. 6 schematically shows a TFT of a top gate structure.
  • the TFT includes a substrate 3; a semiconductor layer 7 sequentially disposed on the substrate 3; a source and a drain 6 disposed on the semiconductor layer 7, and a gate covering the source and drain electrodes 6 and the semiconductor layer 7. a pole insulating layer 4; and a gate 5 disposed on the gate insulating layer 4, the gate 5 having a rough surface toward a side of the semiconductor layer 7.
  • a light shielding layer 11 is further disposed between the substrate 3 and the semiconductor layer 7.
  • the light shielding layer 11 is typically an opaque metal layer. The light shielding layer 11 blocks the light of the backlight from directly irradiating to the semiconductor layer.
  • the TFT further includes, for example, a buffer layer (not shown) disposed between the rough surface 10 of the gate insulating layer 4 and the gate 5.
  • This buffer layer effectively prevents metal ions in the subsequently formed gate from entering the gate insulating layer 4, and thus enters the semiconductor layer 7.
  • the method for preparing the TFT includes: providing a substrate 3; sequentially preparing a light-shielding metal layer 11 and a semiconductor layer 7 on the substrate 3; preparing a source and a drain 6 on the semiconductor layer 7; A gate insulating layer 4 is formed on the source and drain electrodes 6 and the semiconductor layer 7, the gate insulating layer 4 having a rough surface 10 away from the substrate 3 side; and on the gate insulating layer 4 having the rough surface 10 A gate 5 is prepared.
  • the gate electrode 5 has a rough surface (not shown) which is located on the side facing the semiconductor layer 7.
  • an opaque metal layer and a semiconductor layer are sequentially deposited on the substrate 3, and then a laminate of the light shielding layer 11 and the semiconductor layer 7 is formed by one patterning process.
  • a gate electrode deposited on the gate insulating layer has a rough surface by preparing a gate insulating layer having a rough surface.
  • a method of specifically preparing a rough surface for example, by a plasma gas treatment or the like.
  • FIG. 7 is a schematic diagram of incidence and reflection of light when a backlight illuminates a TFT according to an embodiment of the present disclosure.
  • Figure 7 is an enlarged view of the area of the broken line frame in Figure 6.
  • the present disclosure also discloses a display substrate including the TFT described in the above embodiments.
  • the present disclosure also discloses a display device including the display substrate described in the above embodiments.
  • TFTs of the embodiments of the present disclosure and the preparation method thereof are described in detail below with reference to the embodiments, and the scope of the present disclosure is not limited by the following embodiments.
  • a method of fabricating a TFT includes the following steps 11-16.
  • Step 11 Provide a substrate.
  • the base substrate may be glass or quartz.
  • Step 12 Form a gate on the substrate. Specifically, a gate metal layer having a thickness of about 300 to 400 nm is deposited on the substrate on which the step 11 is completed by sputtering or thermal evaporation, and the gate metal layer is Cu.
  • Step 13 Etching the gate metal layer with hydrogen peroxide having a mass concentration of 3%, the etching time is 2 minutes, and forming a surface of the gate metal layer having a rugged structure on the surface facing away from the substrate side, the surface roughness Ra of the surface is about 20 to 100 nm.
  • Step 14 Form a gate insulating layer on the substrate on which the step 13 is completed.
  • a gate insulating layer is deposited on the substrate on which the step 13 is completed by using a plasma enhanced chemical vapor deposition (PECVD) method, and the gate insulating layer is made of an oxide, a nitride or an oxynitride, and the corresponding reaction gas is SiH 4 . , NH 3 and N 2 , or SiH 2 Cl 2 , NH 3 and N 2 .
  • PECVD plasma enhanced chemical vapor deposition
  • Step 15 Depositing an oxide semiconductor layer on the substrate on which the step 14 is completed.
  • the oxide semiconductor is, for example, indium zinc oxide, zinc tin oxide or indium gallium zinc oxide.
  • Step 16 Form a pattern of the data line, the source electrode, and the drain electrode on the substrate on which the step 15 is completed.
  • a source/drain metal layer is deposited on the substrate on which the step 15 is completed by magnetron sputtering, thermal evaporation or other film forming methods, and the source and drain metal layers are, for example, Cu, Al, Ag, Mo, Cr, Nd, Metals such as Ni, Mn, Ti, Ta, and W, and alloys of these metals.
  • the source/drain metal layer is, for example, a single layer structure or a multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, or the like.
  • a photoresist is coated on the source/drain metal layer, and the photoresist is exposed by using a mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist retention region Corresponding to the region where the pattern of the source electrode, the drain electrode and the data line is located, the photoresist unretained region corresponds to the region other than the above-mentioned pattern; the development process, the photoresist in the unreserved region of the photoresist is completely removed, and the photoresist is completely removed.
  • the thickness of the photoresist in the remaining area remains unchanged; the source and drain metal layers of the unretained region of the photoresist are completely etched away by the etching process, and the remaining photoresist is stripped to form a drain electrode, a source electrode, and a data line.
  • a method of fabricating a TFT includes the following steps 21-26.
  • Step 21 Provide a substrate.
  • the base substrate may be glass or quartz.
  • Step 22 Form a gate on the substrate. Specifically, a gate metal layer having a thickness of about 300 to 400 nm is deposited on the substrate on which the step 21 is completed by sputtering or thermal evaporation, and the gate metal layer is Cu.
  • Step 23 etching the gate metal layer with hydrogen peroxide having a mass concentration of 1%, and etching time is 1 minute, forming a surface of the gate metal layer having a surface having a rugged surface, the surface roughness Ra of the surface is about 20 to 100 nm.
  • a transparent conductive layer is deposited on the surface of the gate metal layer having a rough surface, and the transparent conductive layer is made of indium tin oxide. The gate metal layer and the transparent conductive layer are patterned to form a gate having a rough surface and the buffer layer covering the gate.
  • Step 24 Form a gate insulating layer on the substrate on which the step 23 is completed.
  • a gate insulating layer is deposited on the substrate on which the step 23 is completed by PECVD, and the gate insulating layer is made of an oxide, a nitride or an oxynitride, and the corresponding reaction gases are SiH 4 , NH 3 and N 2 , or SiH. 2 Cl 2 , NH 3 and N 2 .
  • Step 25 Depositing an oxide semiconductor layer on the substrate on which the step 24 is completed.
  • the oxide semiconductor is, for example, indium zinc oxide, zinc tin oxide or indium gallium zinc oxide.
  • Step 26 forming a pattern of data lines, source electrodes, and drain electrodes on the substrate on which step 25 is completed.
  • a source/drain metal layer is deposited on the substrate on which the step 25 is completed by magnetron sputtering, thermal evaporation or other film formation methods, and the source/drain metal layers are, for example, Cu, Al, Ag, Mo, Metals such as Cr, Nd, Ni, Mn, Ti, Ta, and W, and alloys of these metals.
  • the source/drain metal layer is, for example, a single layer structure or a multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, or the like.
  • a photoresist is coated on the source/drain metal layer, and the photoresist is exposed by using a mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist retention region Corresponding to the region where the pattern of the source electrode, the drain electrode and the data line is located, the photoresist unretained region corresponds to the region other than the above-mentioned pattern; the development process, the photoresist in the unreserved region of the photoresist is completely removed, and the photoresist is completely removed.
  • the thickness of the photoresist in the remaining area remains unchanged; the source and drain metal layers of the unretained region of the photoresist are completely etched away by the etching process, and the remaining photoresist is stripped to form a drain electrode, a source electrode, and a data line.
  • the TFT stability was tested and tested for TFTs with backlights illuminated for 0, 10, 100, 1000, 2000, and 3000 seconds, respectively.
  • the result is shown in Fig. 8A, which is a transfer characteristic of the TFT.
  • the experimental results show that the source and drain currents of the TFTs after the backlight illumination for different times are basically the same at the same gate voltage. It can be seen that the TFT prepared by the embodiment of the present disclosure has a small characteristic shift amount and high stability even when irradiated for a long time.
  • TFT characteristics were tested on a conventional TFT whose gate surface was flat.
  • the TFTs were irradiated with backlights of 0 seconds, 10 seconds, 100 seconds, 1000 seconds, 2000 seconds, and 3000 seconds, respectively.
  • the TFTs at different gate voltages especially above 0 V, increase the source-drain current.
  • the experimental results show that the existing amorphous silicon or polycrystalline silicon TFT has a large characteristic shift, and its stability is inferior to that of the TFT of the embodiment of the present disclosure.
  • a method of fabricating a TFT includes the following steps 31-36.
  • the base substrate may be a flexible substrate such as polyimide.
  • Step 32 forming a gate on the substrate. Specifically, a gate metal layer having a thickness of about 300 to 400 nm is deposited on the substrate on which the step 31 is completed by sputtering or thermal evaporation, and the gate metal layer is Cu.
  • Step 33 etching the gate metal layer with hydrogen peroxide having a mass concentration of 1.5%, and etching time is 1 minute, forming a surface of the gate metal layer having a rugged structure on a surface facing away from the substrate side, the surface roughness Ra of the surface being about 20 to 100 nm.
  • a transparent conductive layer is deposited on the surface of the gate metal layer having a rough surface, and the transparent conductive layer is made of indium tin oxide. The gate metal layer and the transparent conductive layer are patterned to form a gate having a rough surface and the buffer layer covering the gate.
  • Step 34 forming a gate insulating layer on the substrate on which the step 33 is completed.
  • a gate insulating layer is deposited on the substrate on which the step 33 is completed by using PECVD.
  • the gate insulating layer is, for example, an oxide, a nitride or an oxynitride, and the corresponding reaction gas is SiH 4 , NH 3 , N 2 or SiH. 2 Cl 2 , NH 3 , N 2 .
  • Step 35 depositing an oxide semiconductor layer on the substrate on which the step 34 is completed.
  • the oxide semiconductor is, for example, indium zinc oxide, zinc tin oxide or indium gallium zinc oxide.
  • Step 36 forming a pattern of data lines, source electrodes, and drain electrodes on the substrate on which step 35 is completed.
  • a source/drain metal layer is deposited on the substrate on which the step 35 is completed by magnetron sputtering, thermal evaporation or other film forming methods, and the source/drain metal layers are, for example, Cu, Al, Ag, Mo, Cr, Nd, Metals such as Ni, Mn, Ti, Ta, and W, and alloys of these metals.
  • the source/drain metal layer is, for example, a single layer structure or a multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, or the like.
  • a photoresist is coated on the source/drain metal layer, and the photoresist is exposed by using a mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist retention region Corresponding to the region where the pattern of the source electrode, the drain electrode and the data line is located, the photoresist unretained region corresponds to the region other than the above-mentioned pattern; the development process, the photoresist in the unreserved region of the photoresist is completely removed, and the photoresist is completely removed.
  • the thickness of the photoresist in the remaining area remains unchanged; the source and drain metal layers of the unretained region of the photoresist are completely etched away by the etching process, and the remaining photoresist is stripped to form a drain electrode, a source electrode, and a data line.
  • Embodiments of the present disclosure provide a TFT, a method of fabricating the same, a display substrate, and a display device.
  • the TFT of the embodiment of the present disclosure has a gate having a rough surface. Due to the unevenness of the surface of the gate, the light reflected to the surface of the gate is not reflected again, or is directly scattered to other directions, so that the incident light of the backlight can no longer be irradiated onto the semiconductor layer by continuous reflection, thereby reducing the semiconductor layer.
  • the frequency to be irradiated with light particularly when the semiconductor material is a metal oxide, can reduce the frequency at which the light-sensitive metal oxide semiconductor is irradiated with light, and delays degradation. Since the TFT having this structure has a relatively stable semiconductor layer, its own stability is improved.

Abstract

公开了一种TFT及其制备方法、显示基板及显示装置。该TFT包括衬底、栅极、栅极绝缘层、半导体层、以及源极和漏极。所述栅极在朝向所述半导体层的一侧具有粗糙表面。由于栅极表面的凹凸不平，使得反射到栅极表面的光线不会再进行反射，或者直接散射到其他方向。这使得背光源的入射光线无法再通过连续反射照射到半导体层上，减少半导体层被光照射的频率，并且提升TFT的稳定性。

Description

薄膜晶体管及其制备方法、显示基板及显示装置
相关专利申请
本申请主张于2016年8月19日提交的中国专利申请No.201610698433.8的优先权，其全部内容通过引用结合于此。
技术领域
本公开涉及晶体管领域，特别涉及一种薄膜晶体管(thin film transistor，TFT)及其制备方法、显示基板及显示装置。
背景技术
TFT是一种场效应半导体器件，包括衬底、栅极、栅极绝缘层、有源层和源漏极等几个重要组成部分。其中有源层对于器件性能和制造工艺具有至关重要的影响。在近十几年时间，以硅材料TFT为驱动单元的液晶显示器件以其体积小、重量轻、品质高等优点获得了迅速发展，并成为主流的信息显示终端。然而，非晶硅存在场效应迁移率低、光敏性强以及材料不透明等缺点，而多晶硅TFT大面积制作工艺复杂，低温工艺难以实现。
然而，目前TFT中作为有源层的氧化物半导体在光照的情况下，存在退化现象。在背光源照射下，光线穿过基板照射到源漏极金属层后，通过反射照射到栅极金属层上，这样连续的反射会使得光线照射到半导体层上。由于半导体层对于光非常敏感，长时间照射后，TFT的特性会出现明显的退化。
发明内容
本公开实施例提供了一种薄膜晶体管，包括衬底、栅极、栅极绝缘层、半导体层、以及源极和漏极，其中所述栅极在朝向所述半导体层的一侧具有粗糙表面。
例如，所述薄膜晶体管具有底栅结构。所述栅极设置于所述衬底上，所述栅极绝缘层覆盖所述栅极和所述衬底，所述半导体层设置于所述栅极绝缘层上，所述半导体层在所述衬底上的投影位于所述栅极在所述衬底上的投影内，并且所述源极和漏极设置于所述半导体层上。
例如，所述薄膜晶体管具有顶栅结构。所述半导体层设置于所述衬底上，所述源极和漏极设置于所述半导体层上，所述栅极绝缘层覆盖所述源极和漏极、所述半导体层以及所述衬底，所述栅极设置于所述栅极绝缘层上，并且所述半导体层在所述衬底上的投影位于所述栅极在所述衬底上的投影内。
例如，所述栅极绝缘层的面向所述栅极的表面是粗糙的。
例如，所述半导体层包括金属氧化物、a-Si或者p-Si。
所述栅极在朝向所述半导体层的一侧具有粗糙表面。
例如，所述栅极的粗糙表面具有约20～100nm的表面粗糙度。
例如，所述薄膜晶体管还包括设置在所述栅极和所述栅极绝缘层之间的缓冲层。
例如，所述缓冲层包括导电材料。
本公开实施例还提供一种显示基板，包括上述实施例所述的薄膜晶体管。
本公开实施例还提供了一种显示装置，包括上述实施例所述的显示基板。
本公开实施例提供了一种薄膜晶体管的制备方法，包括在衬底上形成栅极、栅极绝缘层、半导体层、以及源极和漏极，其中形成所述栅极的步骤包括形成在朝向所述半导体层的一侧具有粗糙表面的栅极。
例如，形成所述栅极、栅极绝缘层、半导体层、以及源极和漏极的步骤包括：在所述衬底上形成所述栅极；形成覆盖所述栅极和所述衬底的所述栅极绝缘层；在所述栅极绝缘层上形成所述半导体层，其中所述半导体层在所述衬底上的投影位于所述栅极在所述衬底上的投影内；以及在所述半导体层上形成所述源极和漏极。
例如，在所述衬底上形成所述栅极的步骤包括：在所述衬底上沉积栅金属层；对所述栅金属层进行微蚀处理，在背离所述衬底一侧形成粗糙表面，所述表面的表面粗糙度为约20～100nm；以及对所述栅金属层进行构图工艺，形成背离所述衬底一侧具有粗糙表面的栅极。
例如，在形成所述栅极绝缘层之前，所述方法还包括：形成覆盖所述栅极的缓冲层。
例如，形成所述栅极和所述缓冲层的步骤包括：在衬底上沉积栅金属层；对所述栅金属层进行微蚀处理，使得所述栅金属层的背离所 述衬底的一侧的表面是粗糙的；在所述栅金属层的表面沉积导电材料层；以及对所述栅金属层和所述导电材料层进行构图工艺，形成所述栅极和覆盖所述栅极的所述缓冲层。
例如，所述对栅金属层进行微蚀处理的步骤包括：使用弱酸性溶液或氧化剂腐蚀所述栅金属层背离所述衬底一侧的表面。
例如，所述微蚀处理的步骤包括：使用质量浓度为约1～3％的双氧水腐蚀所述栅金属层，并且腐蚀时间为约10秒～10分钟。
例如，形成所述栅极、栅极绝缘层、半导体层、以及源极和漏极的步骤包括：在所述衬底上形成所述半导体层；在所述半导体层上形成所述源极和漏极；形成覆盖所述源极和漏极、所述半导体层以及所述衬底的所述栅极绝缘层；以及在所述栅极绝缘层上形成所述栅极，其中所述半导体层在所述衬底上的投影位于所述栅极在所述衬底上的投影内。
例如，在形成所述栅极绝缘层之后，并且在形成所述栅极之前，该方法还包括：利用等离子气体处理所述栅极绝缘层，使得所述栅极绝缘层的远离所述衬底的表面是粗糙的。
附图说明
图1为本公开一实施例中TFT的结构示意图；
图2为本公开一实施例中TFT的结构示意图；
图3为本公开一实施例中背光源照射TFT时，光线的入射及反射示意图；
图4为本公开一实施例中栅金属层沉积导电材料层的结构示意图；
图5为本公开一实施例中栅金属层和导电材料层经构图后形成的栅极和缓冲层的结构示意图；
图6为本公开一实施例中TFT的结构示意图；
图7为本公开一实施例中背光源照射TFT时，光线的入射及反射示意图；
图8A表示本公开一实施例中制备的TFT稳定性测试的结果图；以及
图8B表示已知TFT稳定性测试的结果图。
具体实施方式
下面结合实施例对本公开示例性实施方案进行描述，但是应当理解，这些描述只是为进一步说明本公开的特征和优点，而不是对本公开保护范围的限制。
附图标记：1背光源；2光线；3衬底；4栅极绝缘层；5栅极；6源极或漏极；7半导体层；8栅极的粗糙表面；9缓冲层；10栅极绝缘层的粗糙表面；11遮光层。
在已知TFT中，背光源照射TFT时，背光源发出的光线穿过衬底和透明的栅极绝缘层，直接照射到源极或漏极上。照射到源极或漏极的光线被反射到栅极上。光线在源极或漏极和栅极之间经历连续反射而照射到半导体层上。半导体层对于光线比较敏感。特别是半导体材料为金属氧化物时，氧化物半导体层对光线非常敏感。半导体层受光线长时间照射后，TFT的性能会发生明显的退化。因此，本公开实施例旨在减轻或消除一个或多个这些问题。
本公开实施例公开了一种TFT，包括衬底、栅极、栅极绝缘层、半导体层、以及源极和漏极。该栅极朝向该半导体层的一侧具有粗糙表面。
例如，TFT为底栅结构，并且包括衬底；设置于该衬底上的栅极；该栅极背离该衬底的一侧具有粗糙表面；栅极绝缘层；设置于该栅极绝缘层上的半导体层，该半导体层在该衬底上的投影位于该栅极在该衬底上的投影内；以及设置于该半导体层上的源极和漏极。
图1为本公开一实施例中的TFT的结构示意图。衬底3例如为玻璃衬底。栅极绝缘层4包括氧化硅材料，并且是透光的。栅极5包括金属材料。源极或漏极6包括金属材料。半导体层7包括氧化铟镓锌或氧化铟锌等。栅极5具有粗糙表面8。
在图1所示实施例中，TFT为底栅结构。TFT包括衬底3；设置于该衬底3上的栅极5；该栅极5背离该衬底3的一侧具有粗糙表面8；栅极绝缘层4；设置于该栅极绝缘层4上的半导体层7，该半导体层7在该衬底3上的投影位于该栅极5在该衬底4上的投影内；以及设置于该半导体层7上的源极和漏极6。
本公开实施例提供一种TFT及其制备方法、显示基板及显示装置，其有效降低栅极的反射率，减少半导体层被光照射的频率，改善TFT 的稳定性，并且延长显示装置的寿命。
根据本公开实施例，改进了栅极5，该栅极5朝向半导体层7一侧具有粗糙表面8。对于图1所示的底栅结构的TFT，该栅极5朝向半导体层7一侧，即背离衬底3的一侧具有粗糙表面。该粗糙表面即为凹凸不平的结构，并且例如用表面粗糙度表征。例如，该粗糙表面8的表面粗糙度Ra为约20～100nm。粗糙表面8反射光线的性能差，可有效避免光线经过反射照射到半导体层7上。
例如，该栅极5采用的金属为Cu、Al、Ag、Mo、Cr、Nd、Ni、Mn、Ti、Ta、W等金属以及这些金属的合金，本公开不做特别限制。在一示例中，该栅极例如采用铜。
该栅极的粗糙表面例如经过微蚀处理得到。该微蚀处理的方法例如为：使用弱酸性溶液或氧化剂腐蚀栅金属层背离该衬底一侧的表面。该微蚀处理中选用的腐蚀溶液根据栅金属的具体材料进行选择，只要能够出现凹凸不平的表面即可。在一示例中，选用铜作为栅极，使用质量浓度为约1～3％的双氧水腐蚀栅极，腐蚀时间为约10秒～10分钟。
图2为表示本公开一实施例中的氧化物TFT的结构示意图。图2所示实施例与图1所示实施例区别在于，栅极5的粗糙表面8上方还设置有缓冲层9。
由于栅极5具有粗糙表面8，栅极5中的离子可能进入栅极绝缘层4和半导体层7中，从而影响TFT的性能。因此，该栅极5和该栅极绝缘层4之间还设置有缓冲层9。该缓冲层9有效避免了栅极5的金属离子进入栅极绝缘层4和半导体层7中。
该缓冲层9例如包括导电材料，特别是透明的导电材料。在一示例中，该缓冲层9包括氧化铟镓锌、氧化铟锡或氧化铟锌。
图3为本公开实施例中背光源照射TFT时，光线的入射及反射示意图。图3为图2中虚线框区域的放大图。当光线2通过栅极绝缘层4照射到栅极5上时，由于栅极5的表面具有粗糙表面8，从而避免了光线的反射，减少了光线照射到半导体层7的可能性，有助于提高TFT的稳定性。
本公开实施例所述的半导体层例如采用氧化物半导体、a-Si或者p-Si。由于氧化物半导体对于光比较敏感，所以本公开实施例对于以氧化物半导体作为半导体层的TFT的稳定性提高，效果更为明显。
该TFT的衬底例如为玻璃、石英或者柔性衬底，如聚酰亚胺等。该栅极绝缘层例如由氧化硅或者有机树脂材料制成。采用有机树脂作为栅极绝缘层形成更平坦的上表面，避免氧化物半导体层受到栅极表面的表面粗糙度的影响。采用有机树脂作为栅极绝缘层，制备得到柔性显示装置。
设置于氧化物半导体层上的源极和漏极例如是Cu、Al、Ag、Mo、Cr、Nd、Ni、Mn、Ti、Ta、W等金属以及这些金属的合金。源漏金属层例如是单层结构或者多层结构，多层结构比如Cu\Mo、Ti\Cu\Ti、Mo\Al\Mo等。
本公开实施例还公开了一种TFT的制备方法，包括：提供一衬底；在该衬底上形成具有粗糙表面的栅极，该粗糙表面位于背离该衬底的一侧；制备栅极绝缘层；在该栅极绝缘层上制备半导体层，该半导体层在该衬底上的投影位于该栅极在该衬底上的投影内；制备源极和漏极，得到TFT。
进一步的，在该衬底上形成具有粗糙表面的栅极包括以下步骤：在衬底上沉积栅金属层；对栅金属层进行微蚀处理，形成背离该衬底一侧的具有粗糙表面的栅金属层，该表面的表面粗糙度Ra为约20～100nm；以及对该栅金属层进行构图工艺，形成背离该衬底一侧的具有粗糙表面的栅极。
在形成具有粗糙表面的栅极时，在衬底上沉积栅金属层的方法为物理溅射或者本领域普通技术人员知晓的其他沉积方法。该栅金属层的厚度例如为约300～400纳米。
该微蚀处理例如包括：使用弱酸性溶液或氧化剂腐蚀栅金属层背离该衬底一侧的表面。该微蚀处理中选用的腐蚀溶液根据栅金属的具体材料进行选择，只要能够出现凹凸不平的粗糙表面即可。在一示例中，选用铜作为栅极，使用质量浓度为约1～3％的双氧水腐蚀栅极，腐蚀时间为约10秒～10分钟，例如为约1～2分钟。本公开通过控制微蚀处理时使用的溶液以及腐蚀时间控制栅极表面的表面粗糙度，以达到较好的避免光线反射的效果。
为了防止粗糙表面的栅极金属离子进入栅极绝缘层和半导体层，例如还在半导体层上制备缓冲层。即：制备栅极绝缘层之前，该方法还包括：形成覆盖该栅极的缓冲层。
进一步的，形成该栅极和该缓冲层包括：在衬底上沉积栅金属层；对栅金属层进行微蚀处理，形成背离该衬底的一侧具有粗糙表面的栅金属层；在该栅金属层的表面沉积导电材料层；以及对该栅金属层和该导电材料层进行构图工艺，形成该栅极和覆盖该栅极的该缓冲层。
该导电材料层例如采用透明导电材料形成，如氧化铟镓锌、氧化铟锡或氧化铟锌。
图4为栅金属层沉积导电材料层的结构示意图。如所示，在衬底3沉积栅金属层，对栅金属层进行微蚀处理以形成具有粗糙表面8的栅极5，以及形成覆盖栅极5的缓冲层9。
图5为栅金属层和导电材料层经构图后形成的栅极和缓冲层的结构示意图。如所示，对图4所示结构进行构图工艺，形成具有粗糙表面8的栅极5以及覆盖栅极5的缓冲层9。
在本公开实施例的制备方法中，该半导体层例如采用氧化物半导体、a-Si或者p-Si。本公开实施例对于制备栅极绝缘层、半导体层、以及源极和漏极的方法没有特殊的限制，按照本领域普通技术人员知晓的方法即可。
在上述实施例中以底栅结构的TFT为例进行描述。应指出，本公开的构思也可适用于顶栅结构的TFT。
图6示意性示出一种顶栅结构的TFT。如所示，该TFT包括衬底3；依次设置在衬底3上的半导体层7；设置在半导体层7上的源极和漏极6；覆盖源极和漏极6以及半导体层7的栅极绝缘层4；以及设置在栅极绝缘层4上的栅极5，该栅极5朝向该半导体层7的一侧具有粗糙表面。
在一实施例中，衬底3和半导体层7之间还设置有遮光层11。遮光层11通常为不透明的金属层。遮光层11阻挡背光源的光线直接照射到半导体层。
与图2所示实施例类似，该TFT例如还包括设置在栅极绝缘层4的粗糙表面10和栅极5之间的缓冲层(未图示)。该缓冲层有效避免了后续形成的栅极中的金属离子进入栅极绝缘层4，并且因此进入半导体层7中。
该TFT的制备方法包括：提供一衬底3；在该衬底3上依次制备遮光金属层11和半导体层7；在该半导体层7上制备源极和漏极6； 在该源极和漏极6以及半导体层7上形成栅极绝缘层4，该栅极绝缘层4远离衬底3一侧具有粗糙表面10；以及在具有粗糙表面10的栅极绝缘层4上制备栅极5。该栅极5具有粗糙表面(未图示)，该粗糙表面位于朝向该半导体层7的一侧。
在一实施例中，在衬底3上依次沉积不透明的金属层和半导体层，随后通过一次构图工艺，形成遮光层11和半导体层7的叠层。
在该制备方法中，通过制备具有粗糙表面的栅极绝缘层，使得在该栅极绝缘层上沉积的栅极具有粗糙表面。具体制备粗糙表面的方法，例如采用等离子气体处理等方法制备。
图7为本公开一实施例中背光源照射TFT时，光线的入射及反射示意图。图7为图6中虚线框区域的放大图。当光线2通过栅极绝缘层4照射到栅极5上时，由于栅极5的表面具有粗糙表面，从而避免了光线的反射，减少了光线照射到半导体层7的可能性，有助于提高TFT的稳定性。
本公开还公开了一种显示基板，包括上述实施例所述的TFT。
本公开还公开了一种显示装置，包括上述实施例所述的显示基板。
下面结合实施例对本公开实施例的TFT及其制备方法行详细说明，本公开的保护范围不受以下实施例的限制。
在本公开一实施例中，TFT的制备方法包括下述步骤11-16。
步骤11、提供一衬底。衬底基板可为玻璃或石英。
步骤12、在上述衬底上形成栅极。具体地，采用溅射或热蒸发的方法在完成步骤11的基板上沉积厚度约为300～400纳米的栅金属层，栅金属层是Cu。
步骤13、使用质量浓度为3％的双氧水腐蚀栅金属层，腐蚀时间为2分钟，形成背离该衬底一侧的表面包括凹凸不平的结构的栅金属层，该表面的表面粗糙度Ra为约20～100nm。
步骤14、在完成步骤13的衬底上形成栅极绝缘层。具体地，采用等离子体增强化学气相沉积(PECVD)方法在完成步骤13的衬底上沉积栅极绝缘层，栅极绝缘层选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH4、NH3和N2，或者SiH2Cl2、NH3和N2。
步骤15、在完成步骤14的衬底上沉积形成氧化物半导体层。氧化物半导体例如为氧化铟锌、氧化锌锡或氧化铟镓锌。
步骤16、在完成步骤15的衬底上形成数据线、源电极和漏电极的图形。具体地，在完成步骤15的衬底上采用磁控溅射、热蒸发或其它成膜方法沉积一层源漏金属层，源漏金属层例如是Cu、Al、Ag、Mo、Cr、Nd、Ni、Mn、Ti、Ta、W等金属以及这些金属的合金。源漏金属层例如是单层结构或者多层结构，多层结构比如Cu\Mo、Ti\Cu\Ti、Mo\Al\Mo等。在源漏金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于源电极、漏电极和数据线的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的源漏金属层，剥离剩余的光刻胶，形成漏电极、源电极以及数据线。
在本公开一实施例中，TFT的制备方法包括下述步骤21-26。
步骤21、提供一衬底。衬底基板可为玻璃或石英。
步骤22、在上述衬底上形成栅极。具体地，采用溅射或热蒸发的方法在完成步骤21的基板上沉积厚度约为300～400纳米的栅金属层，栅金属层是Cu。
步骤23、使用质量浓度为1％的双氧水腐蚀栅金属层，腐蚀时间为1分钟，形成背离该衬底一侧的表面包括凹凸不平的结构的栅金属层，该表面的表面粗糙度Ra为约20～100nm。在具有粗糙表面的栅金属层的表面沉积透明导电层，该透明导电层采用氧化铟锡。对该栅金属层和该透明导电层进行构图工艺，形成具有粗糙表面的栅极和覆盖该栅极的该缓冲层。
步骤24、在完成步骤23的衬底上形成栅极绝缘层。具体地，采用PECVD在完成步骤23的衬底上沉积栅极绝缘层，栅极绝缘层选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH4、NH3和N2，或者SiH2Cl2、NH3和N2。
步骤25、在完成步骤24的衬底上沉积形成氧化物半导体层。氧化物半导体例如为氧化铟锌、氧化锌锡或氧化铟镓锌。
步骤26、在完成步骤25的衬底上形成数据线、源电极和漏电极的图形。具体地，在完成步骤25的衬底上采用磁控溅射、热蒸发或其它成膜方法沉积一层源漏金属层，源漏金属层例如是Cu、Al、Ag、Mo、 Cr、Nd、Ni、Mn、Ti、Ta、W等金属以及这些金属的合金。源漏金属层例如是单层结构或者多层结构，多层结构比如Cu\Mo、Ti\Cu\Ti、Mo\Al\Mo等。在源漏金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于源电极、漏电极和数据线的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的源漏金属层，剥离剩余的光刻胶，形成漏电极、源电极以及数据线。
对TFT稳定性进行测试，分别对于背光源照射了0秒、10秒、100秒、1000秒、2000秒、3000秒的TFT进行测试。结果如图8A所示，图中为TFT的转移特性。实验结果表明，背光源照射不同时间后的TFT在相同栅极电压下，其源漏极电流也基本一致。由此可见，本公开实施例制备的TFT即使长时间照射，其特性偏移量也较小，稳定性高。
在一比较例中，对栅极表面平整的常规TFT进行TFT特性测试。分别对于背光源照射了0秒、10秒、100秒、1000秒、2000秒、3000秒的TFT进行测试。结果如图8B所示，背光源照射不同时间后的TFT在相同栅极电压下，特别是高于0V以后，源漏极电流变化加大。实验结果表明：现有的非晶硅或者多晶硅TFT特性偏移较大，其稳定性差于本公开实施例的TFT。
在本公开一实施例中，TFT的制备方法包括下述步骤31-36。
步骤31、提供一衬底。衬底基板可为柔性衬底，如聚酰亚胺。
步骤32、在上述衬底上形成栅极。具体地，采用溅射或热蒸发的方法在完成步骤31的基板上沉积厚度约为300～400纳米的栅金属层，栅金属层是Cu。
步骤33、使用质量浓度为1.5％的双氧水腐蚀栅金属层，腐蚀时间为1分钟，形成背离该衬底一侧的表面包括凹凸不平的结构的栅金属层，该表面的表面粗糙度Ra为约20～100nm。在具有粗糙表面的栅金属层的表面沉积透明导电层，该透明导电层采用氧化铟锡。对该栅金属层和该透明导电层进行构图工艺，形成具有粗糙表面的栅极和覆盖该栅极的该缓冲层。
步骤34、在完成步骤33的衬底上形成栅极绝缘层。具体地，采用 PECVD在完成步骤33的衬底上沉积栅极绝缘层，栅极绝缘层例如选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH4、NH3、N2或SiH2Cl2、NH3、N2。
步骤35、在完成步骤34的衬底上沉积形成氧化物半导体层。氧化物半导体例如为氧化铟锌、氧化锌锡或氧化铟镓锌。
步骤36、在完成步骤35的衬底上形成数据线、源电极和漏电极的图形。具体地，在完成步骤35的衬底上采用磁控溅射、热蒸发或其它成膜方法沉积一层源漏金属层，源漏金属层例如是Cu、Al、Ag、Mo、Cr、Nd、Ni、Mn、Ti、Ta、W等金属以及这些金属的合金。源漏金属层例如是单层结构或者多层结构，多层结构比如Cu\Mo、Ti\Cu\Ti、Mo\Al\Mo等。在源漏金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于源电极、漏电极和数据线的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的源漏金属层，剥离剩余的光刻胶，形成漏电极、源电极以及数据线。
本公开实施例提供了一种TFT及其制备方法、显示基板及显示装置。本公开实施例的TFT具有表面粗糙的栅极。由于栅极表面的凹凸不平，使得反射到栅极表面的光线不会再进行反射，或者直接散射到其他方向，从而使背光源的入射光线无法再通过连续反射照射到半导体层上，减少半导体层被光照射的频率，特别是半导体材料为金属氧化物时，能够减少对光敏感的金属氧化物半导体被光照射的频率，延缓退化。具有该结构的TFT由于具有了较为稳定的半导体层，因此其自身稳定性得到提升。
对所公开的实施例的上述说明，使本领域普通技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域普通技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (19)

  1. 一种薄膜晶体管，包括衬底、栅极、栅极绝缘层、半导体层、以及源极和漏极，其中所述栅极在朝向所述半导体层的一侧具有粗糙表面。
  2. 根据权利要求1所述的薄膜晶体管，其中所述栅极设置于所述衬底上，所述栅极绝缘层覆盖所述栅极和所述衬底，所述半导体层设置于所述栅极绝缘层上，所述半导体层在所述衬底上的投影位于所述栅极在所述衬底上的投影内，并且所述源极和漏极设置于所述半导体层上。
  3. 根据权利要求1所述的薄膜晶体管，其中所述半导体层设置于所述衬底上，所述源极和漏极设置于所述半导体层上，所述栅极绝缘层覆盖所述源极和漏极、所述半导体层以及所述衬底，所述栅极设置于所述栅极绝缘层上，并且所述半导体层在所述衬底上的投影位于所述栅极在所述衬底上的投影内。
  4. 根据权利要求3所述的薄膜晶体管，其中所述栅极绝缘层的面向所述栅极的表面是粗糙的。
  5. 根据权利要求1所述的薄膜晶体管，其中所述半导体层包括金属氧化物、a-Si或者p-Si。
  6. 根据权利要求1所述的薄膜晶体管，其中所述栅极的粗糙表面具有约20～100nm的表面粗糙度。
  7. 根据权利要求1所述的薄膜晶体管，还包括设置在所述栅极和所述栅极绝缘层之间的缓冲层。
  8. 根据权利要求7所述的薄膜晶体管，其中所述缓冲层包括导电材料。
  9. 一种显示基板，包括如权利要求1-8中任一项所述的薄膜晶体管。
  10. 一种显示装置，包括如权利要求9所述的显示基板。
  11. 一种制备薄膜晶体管的方法，包括在衬底上形成栅极、栅极绝缘层、半导体层、以及源极和漏极，其中形成所述栅极的步骤包括形成在朝向所述半导体层的一侧具有粗糙表面的栅极。
  12. 根据权利要求11所述的方法，其中形成所述栅极、栅极绝缘层、半导体层、以及源极和漏极的步骤包括：
    在所述衬底上形成所述栅极；
    形成覆盖所述栅极和所述衬底的所述栅极绝缘层；
    在所述栅极绝缘层上形成所述半导体层，其中所述半导体层在所述衬底上的投影位于所述栅极在所述衬底上的投影内；以及
    在所述半导体层上形成所述源极和漏极。
  13. 根据权利要求12所述的方法，其中在所述衬底上形成所述栅极的步骤包括：
    在所述衬底上沉积栅金属层；
    对所述栅金属层进行微蚀处理，在背离所述衬底一侧形成粗糙表面，所述表面的表面粗糙度为约20～100nm；以及
    对所述栅金属层进行构图工艺，形成背离所述衬底一侧具有粗糙表面的栅极。
  14. 根据权利要求11所述的方法，其中在形成所述栅极绝缘层之前，所述方法还包括：形成覆盖所述栅极的缓冲层。
  15. 根据权利要求14所述的方法，其中形成所述栅极和所述缓冲层的步骤包括：
    在衬底上沉积栅金属层；
    对所述栅金属层进行微蚀处理，使得所述栅金属层的背离所述衬底的一侧的表面是粗糙的；
    在所述栅金属层的表面沉积导电材料层；以及
    对所述栅金属层和所述导电材料层进行构图工艺，形成所述栅极和覆盖所述栅极的所述缓冲层。
  16. 根据权利要求13-15中任意一项所述的方法，其中所述对栅金属层进行微蚀处理的步骤包括：
    使用弱酸性溶液或氧化剂腐蚀所述栅金属层背离所述衬底一侧的表面。
  17. 根据权利要求16所述的方法，其中所述微蚀处理的步骤包括：使用质量浓度为约1～3％的双氧水腐蚀所述栅金属层，并且腐蚀时间为约10秒～10分钟。
  18. 根据权利要求11所述的方法，其中形成所述栅极、栅极绝缘层、半导体层、以及源极和漏极的步骤包括：
    在所述衬底上形成所述半导体层；
    在所述半导体层上形成所述源极和漏极；
    形成覆盖所述源极和漏极、所述半导体层以及所述衬底的所述栅极绝缘层；以及
    在所述栅极绝缘层上形成所述栅极，其中所述半导体层在所述衬底上的投影位于所述栅极在所述衬底上的投影内。
  19. 根据权利要求18所述的方法，其中在形成所述栅极绝缘层之后，并且在形成所述栅极之前，该方法还包括：
    利用等离子气体处理所述栅极绝缘层，使得所述栅极绝缘层的远离所述衬底的表面是粗糙的。
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