WO2018020729A1 - 半導体モジュールおよび半導体モジュールの製造方法 - Google Patents

半導体モジュールおよび半導体モジュールの製造方法 Download PDF

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Publication number
WO2018020729A1
WO2018020729A1 PCT/JP2017/010990 JP2017010990W WO2018020729A1 WO 2018020729 A1 WO2018020729 A1 WO 2018020729A1 JP 2017010990 W JP2017010990 W JP 2017010990W WO 2018020729 A1 WO2018020729 A1 WO 2018020729A1
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Prior art keywords
electrode
semiconductor module
module according
semiconductor
wiring layer
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PCT/JP2017/010990
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English (en)
French (fr)
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鈴木　智久
健 寺崎
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株式会社日立製作所
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Priority to JP2018529354A priority Critical patent/JP6643481B2/ja
Priority to US16/318,194 priority patent/US10937731B2/en
Priority to EP17833740.8A priority patent/EP3474325A4/en
Publication of WO2018020729A1 publication Critical patent/WO2018020729A1/ja

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    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other

Definitions

  • the present invention relates to a semiconductor module and a method for manufacturing the semiconductor module, and more particularly to a technique effective when applied to a SiC power module.
  • SiC power devices can operate at a high temperature of 200 ° C or higher, and have the merit of being able to achieve a significant reduction in size and weight.
  • ⁇ Power devices are evaluated for durability against thermal stress by a temperature cycle test.
  • thermal strain caused by the difference in linear expansion coefficient between members is concentrated and broken mainly at the joint portion of the power device.
  • Patent Document 1 In order to efficiently cool the power device, for example, a double-sided cooling structure as shown in Patent Document 1 has been studied. Moreover, in order to reduce the thermal distortion in the junction part of a power device, for example in patent document 2, the level
  • Patent Document 1 relates to a module structure with an improved waterproofing effect in a water-cooled semiconductor module. Although the cooling efficiency of the entire semiconductor module is improved, it is locally generated at the joint portion of the power device as described above. No consideration is given to thermal strain.
  • Patent Document 2 describes a technique for reducing distortion by providing a thin portion on the outer periphery of the heat sink.
  • a highly rigid heat sink is provided immediately above the chip center position where the temperature is highest.
  • a sufficient strain reduction effect cannot be obtained.
  • an object of the present invention is to provide a semiconductor module capable of effectively reducing thermal strain generated at a joint portion between a semiconductor chip and another conductor member with a relatively simple structure.
  • Another object of the present invention is to provide a method for manufacturing a semiconductor module that can effectively reduce thermal strain generated at a joint between a semiconductor chip and another conductor member without using a complicated process. There is to do.
  • the present invention provides a first wiring layer, a semiconductor element bonded to the first wiring layer via a first bonding layer, and a second wiring on the semiconductor element.
  • a first electrode bonded via a bonding layer; a second electrode connected on the first electrode; and a second wiring layer connected on the second electrode;
  • the width of the second electrode in the short direction is wider than the thickness of the first electrode, and the second electrode is disposed at a position away from the center position of the semiconductor element.
  • the present invention also includes (a) a step of bonding a semiconductor element on a first wiring layer via a first bonding layer, and (b) a first step on the semiconductor element via a second bonding layer. (C) a step of disposing a second electrode and a spacer on the first electrode, (d) a step of forming a second wiring layer on the second electrode and the spacer, (E) a method of manufacturing a semiconductor module including a step of applying pressure from above the second wiring layer, wherein the width of the second electrode in the short direction is wider than the thickness of the first electrode; The second electrode is disposed at a position deviating from a center position of the semiconductor element.
  • FIG. 2A It is a figure which shows the distortion reduction effect of a semiconductor module. It is a figure which shows the chip temperature of a semiconductor module. It is a figure which shows a part of manufacturing process of the semiconductor module which concerns on one Embodiment of this invention. It is sectional drawing of the semiconductor module which concerns on one Embodiment of this invention. It is a top view of the semiconductor module which concerns on one Embodiment of this invention. It is sectional drawing of the semiconductor module which concerns on one Embodiment of this invention.
  • FIG. 1 is a cross-sectional view of a main part of a double-sided cooling type semiconductor module, showing a wiring structure of a semiconductor element 3 mounted between upper and lower cooling members 10a and 10b.
  • FIG. 2A is a plan view of the semiconductor module of FIG. 1 as viewed from above, and shows the positional relationship of the semiconductor element 3, the first electrode 5, and the second electrode 6.
  • 2B is a modification of FIG. 2A, and the second electrode 6 in FIG. 2A has a slit shape, whereas in FIG. 2B, the second electrode 6 has a plurality of vias (here, three vias). ).
  • the semiconductor module of this embodiment includes at least a first wiring layer 1, a first bonding layer 2, a semiconductor element 3, a second bonding layer 4, and a first electrode 5 in order from the lower layer.
  • the second electrode 6 and the second wiring layer 7 are stacked.
  • the first electrode 5 and the second electrode 6 constitute an electrode 50.
  • a gap between the first wiring layer 1 and the second wiring layer 7 is filled with a sealing member 8 and sealed.
  • a cooling member 10a is provided on the lower layer (outside) of the first wiring layer 1 via an insulating member 9a, and the cooling member 10b is provided on the upper layer (outer side) of the second wiring layer 7 via an insulating member 9b. Is provided.
  • the first wiring layer 1, the second wiring layer 7, the first electrode 5, and the second electrode 6 are made of a conductive material such as copper (Cu) or aluminum (Al).
  • the first bonding layer 2 and the second bonding layer 4 are made of a bonding material such as solder, sintered silver, sintered copper, or sintered gold.
  • the semiconductor element 3 is made of a semiconductor material such as Si, SiC, or gallium nitride (GaN).
  • GaN gallium nitride
  • an insulating material for sealing such as sealing resin, ceramic, glass, gas or the like is used.
  • the insulating members 9a and 9b are made of an insulating material such as aluminum nitride (AlN), silicon nitride (SiN), aluminum oxide (Al 2 O 3 ), or a resin sheet.
  • the cooling members 10a and 10b are made of a material having high thermal conductivity such as Al and Cu.
  • the semiconductor element 3 is preferably a wide band gap semiconductor such as SiC or GaN, and the bonding layer is preferably composed of sintered silver or sintered copper having a high melting point and high heat resistance.
  • the second bonding layer 4 is made of sintered copper and the first electrode 5 and the second electrode 6 are made of Cu, the difference in linear expansion coefficient between members is eliminated and strain is reduced. It is.
  • the first electrode 5 is preferably about the same thickness as the second bonding layer 4.
  • the second electrode 6 is provided in a form deviated from the semiconductor element center position of the semiconductor element 3. As described above, by providing the second electrode 6 so as to avoid the central position where the temperature of the semiconductor element becomes the highest, it is possible to suppress the influence of the thermal strain generated by the thermal expansion of the second electrode 6. .
  • FIG. 3 shows a comparison result in which the distribution of the equivalent plastic strain at the evaluation position B of the structure in which the peripheral part is provided as in Patent Document 2 and the structure of this example (FIG. 2A) is calculated by finite element analysis. .
  • the horizontal axis in FIG. 3 indicates the position from the left end of the semiconductor element 3, and the vertical axis indicates the strength of the equivalent plastic strain.
  • the conventional structure 1 the structure of Patent Document 2
  • distortion occurs over the entire semiconductor element.
  • the strain is relaxed as a whole, and it can be seen that there is almost no strain particularly in the vicinity of the center position of the semiconductor element.
  • the strain generated in the bonding layer can be effectively reduced.
  • the width b (FIG. 2A) of the second electrode 6 needs to be provided wider than at least the thickness t (FIG. 1) of the first electrode 5.
  • FIG. 4 shows the result of comparing the temperatures at the evaluation position A (FIG. 2A) of the semiconductor element 3 when the relationship between the thickness t of the first electrode 5 and the thickness t of the first electrode 5 is b> t.
  • the horizontal axis of FIG. 4 indicates the position from the left end of the semiconductor element 3, and the vertical axis indicates the temperature of the semiconductor element 3. It can be seen that the temperature of the structure of this example (the present invention) is lower than that of the conventional structure 2 (the structure of Patent Document 3).
  • the second electrode 6 may be formed by a plurality of vias as shown in FIG. 2B instead of being provided in a slit shape as shown in FIG. 2A. Even in this case, the width b of the second electrode 6, that is, the via diameter b needs to be larger than the thickness t (FIG. 1) of the first electrode 5.
  • the number of vias to be provided is preferably determined after preliminarily calculating the temperature and strain of the semiconductor element by simulation or the like.
  • the manufacturing method of the semiconductor module of a present Example is demonstrated.
  • the electrode 50 including the first electrode 5 and the second electrode 6, the first electrode 5, the second electrode 6, and the second wiring layer 7 are formed separately, and each member is separated from each other. It is set as the structure connected by a joining member. That is, the first electrode 5 and the second electrode 6 are connected by the third bonding layer, and the second electrode 6 and the second wiring layer 7 are connected by the fourth bonding layer.
  • the first electrode 5, the second electrode 6, and the second wiring layer 7 are made of Cu, and a joining member between the members is sintered copper. Even when Cu cannot be used for the second wiring layer 7, at least the first electrode 5 and the second electrode 6, which have a high temperature, are made of Cu, and the joining member between them is made of sintered copper. Is preferable for reducing thermal strain.
  • the second wiring layer 7 and the second electrode 6 may be formed as a single body by molten metal or shaving. At this time, if the first electrode 5 can also be formed integrally, it is more preferable because there is no joint.
  • a pressurizing process is generally required.
  • a non-bonded spacer 11 may be sandwiched between the first electrode 5 and the second wiring layer 7 as shown in FIG.
  • the spacer 11 is preferably the same member as the second electrode 6 and is removed after bonding.
  • the second electrode 6 is formed of Cu
  • the spacer 11 may be made of the same member as the sealing member 8 and molded as it is.
  • the first wiring layer 1 to the first electrode 5 may be pressure bonded once, and then the second electrode 6 and the second wiring layer 7 may be pressure bonded.
  • FIGS. 6A and 6B are modifications of the semiconductor module shown in FIGS. 1 and 2A.
  • FIG. 6A shows a laminated structure from the first wiring layer 1 to the second wiring layer 7.
  • the first electrode 5 and the second wiring layer 7 are connected by one second electrode 6.
  • two second electrodes 6 are provided at both ends of the first electrode 5 across the chip center position, and the first electrode 5 and the second wiring layer 7 are connected.
  • Yes. 6B is a plan view of FIG. 6A as viewed from above.
  • FIG. 7A is a cross-sectional view of a semiconductor module in which a plurality of semiconductor devices 3 are arranged between the first wiring layer 1 and the second wiring layer 7.
  • FIG. 7B is a plan view of FIG. 7A as viewed from above.
  • 8A and 8B are modified examples of FIGS. 7A and 7B, showing an example in which the position of each second electrode 6 with respect to each semiconductor device 3 is different.
  • the second electrodes 6 on the semiconductor device 3 disposed in the left and right regions of the center position of the module are disposed so as to be symmetric with respect to the center position of the module.
  • the second electrodes 6 on the semiconductor device 3 respectively disposed in the left and right regions of the center position of the module are disposed symmetrically within the same region.
  • the first electrode 5 and the second electrode 6 are structured as described in the first embodiment and the second embodiment to improve heat dissipation, and as shown in FIGS. 7A to 8B, the second electrode 6 is formed.
  • the second electrode 6 is arranged symmetrically in the left and right regions of the center position of the module, thereby further reducing the uneven distribution of thermal strain in the semiconductor module.
  • a structure in which a third electrode is provided between the second electrode 6 and the second wiring layer 7 and a plurality of second electrodes are connected to the third electrode may be employed.
  • the second electrode 6 and the third electrode may be connected via the fifth bonding layer, and the third electrode and the second wiring layer 7 are connected via the sixth bonding layer. It is good also as a structure.

Abstract

比較的簡単な構造で、半導体チップと他の導体部材との接合部に生じる熱ひずみを効果的に低減することが可能な半導体モジュールを提供する。第１の配線層と、前記第１の配線層上に第１の接合層を介して接合された半導体素子と、前記半導体素子上に第２の接合層を介して接合された第１の電極と、前記第１の電極上に接続された第２の電極と、前記第２の電極上に接続された第２の配線層と、を備え、前記第２の電極の短手方向の幅は、前記第１の電極の厚さよりも広く、前記第２の電極は前記半導体素子の中心位置から外れた位置に配置されることを特徴とする。

Description

半導体モジュールおよび半導体モジュールの製造方法
　本発明は、半導体モジュールおよび半導体モジュールの製造方法に関し、特に、SiCパワーモジュールに適用して有効な技術に関する。
　近年、ハイブリッド自動車や鉄道用途を中心として、インバータなどの電力制御機器に用いられるパワーデバイスの市場拡大が続いている。環境保護や省エネに対する意識の高まりを背景として、パワーデバイスにはさらなる高効率化が求められている。しかし、従来のシリコン（Si）を用いたパワーデバイスの性能は限界に近づいており、より高効率な炭化ケイ素（SiC）を用いた次世代パワーデバイスの開発が進められている。SiCパワーデバイスでは200℃以上の高温動作が可能となり、大幅な小型・軽量化が実現できるメリットがある。
　しかし、200℃以上の高温環境下では、従来チップ接合材として使用されてきた鉛フリーはんだは、再溶融の問題から使用できない。また、現在はRoHS（Restriction of Hazardous Substances）指令から除外されている鉛含有率85％以上の高融点はんだは、将来的にRoHSの対象項目となることが予想され、代替材料の開発が急務である。これらの代替材料として、ナノやマイクロメートルオーダーの金属粒子を焼結させた焼結金属材料が期待されており、焼結銀や焼結銅による接合に関して開発が進められている。
　パワーデバイスは、温度サイクル試験によって、熱的ストレスに対する耐久性が評価される。温度サイクル試験では、主にパワーデバイスの接合部に、部材間の線膨脹係数の差に起因する熱ひずみが集中し破壊する。
　パワーデバイスを効率的に冷却するために、例えば特許文献１に示すような両面冷却構造が検討されている。また、パワーデバイスの接合部における熱ひずみを低減するために、例えば特許文献２では、ヒートシンク部に段差を設けて薄肉部を形成している。また、特許文献３では、半導体チップの上部面に検査用の板状導体部材が設けられた構造が記載されている。
特開２０１５－２３０９１３号公報 特開２００２－１１０８９３号公報 特開２０１２－２３８７４９号公報
　200℃以上の高温動作においては、接合部材に発生する熱ひずみが大きくなり、接合部材の破壊がこれまで以上に問題になると考えられる。特許文献１は、水冷方式の半導体モジュールにおいて、防水効果を高めたモジュール構造に関するものであるが、半導体モジュール全体の冷却効率は向上するものの、上記のようなパワーデバイスの接合部に発生する局所的な熱ひずみについては考慮されていない。
　また、特許文献２では、ヒートシンクの外周に薄肉部を設けることでひずみを低減する手法が記載されているが、最も温度の高くなるチップ中心位置の直上に剛性の高いヒートシンクを設けていることから、200℃以上の高温状態を想定した場合には十分なひずみ低減効果は得られない。
　また、特許文献３に示されるような板状の導体部材をヒートシンクとの接続に用いることも考えられるが、この場合、放熱パスが細いため放熱性が低く、冷却性能は不十分となる。
　そこで、本発明の目的は、比較的簡単な構造で、半導体チップと他の導体部材との接合部に生じる熱ひずみを効果的に低減することが可能な半導体モジュールを提供することにある。
　また、本発明の別の目的は、複雑なプロセスを用いることなく、半導体チップと他の導体部材との接合部に生じる熱ひずみを効果的に低減することが可能な半導体モジュールの製造方法を提供することにある。
　上記課題を解決するために、本発明は、第１の配線層と、前記第１の配線層上に第１の接合層を介して接合された半導体素子と、前記半導体素子上に第２の接合層を介して接合された第１の電極と、前記第１の電極上に接続された第２の電極と、前記第２の電極上に接続された第２の配線層と、を備え、前記第２の電極の短手方向の幅は、前記第１の電極の厚さよりも広く、前記第２の電極は前記半導体素子の中心位置から外れた位置に配置されることを特徴とする。
　また、本発明は、（ａ）第１の配線層上に第１の接合層を介して半導体素子を接合する工程、（ｂ）前記半導体素子上に第２の接合層を介して第１の電極を接合する工程、（ｃ）前記第１の電極上に第２の電極およびスペーサーを配置する工程、（ｄ）前記第２の電極および前記スペーサー上に第２の配線層を形成する工程、（ｅ）前記第２の配線層上から加圧する工程、を含む半導体モジュールの製造方法であって、前記第２の電極の短手方向の幅は、前記第１の電極の厚さよりも広く、前記第２の電極は前記半導体素子の中心位置から外れた位置に配置されることを特徴とする。
　本発明によれば、比較的簡単な構造で、半導体チップと他の導体部材との接合部に生じる熱ひずみを効果的に低減することが可能な半導体モジュールを実現できる。
　また、本発明によれば、複雑なプロセスを用いることなく、半導体チップと他の導体部材との接合部に生じる熱ひずみを効果的に低減することが可能な半導体モジュールの製造方法を実現することができる。
　上記した以外の課題、構成及び効果は、以下の実施形態の説明により明らかにされる。
本発明の一実施形態に係る半導体モジュールの断面図である。 本発明の一実施形態に係る半導体モジュールの平面図である。 図２Ａの変形例である。 半導体モジュールのひずみ低減効果を示す図である。 半導体モジュールのチップ温度を示す図である。 本発明の一実施形態に係る半導体モジュールの製造過程の一部を示す図である。 本発明の一実施形態に係る半導体モジュールの断面図である。 本発明の一実施形態に係る半導体モジュールの平面図である。 本発明の一実施形態に係る半導体モジュールの断面図である。 本発明の一実施形態に係る半導体モジュールの平面図である。 本発明の一実施形態に係る半導体モジュールの断面図である。 本発明の一実施形態に係る半導体モジュールの平面図である。
　以下、本発明に係る実施形態について、図面を参照しながら詳細に説明する。ただし、本発明は、ここで取り上げた実施形態に限定されることはなく、発明の技術的思想を逸脱しない範囲で適宜組み合わせや改良が可能ある。
　図１から図２Ｂを参照して、本実施例の半導体モジュールについて説明する。図１は両面冷却型の半導体モジュールの要部断面図であり、上下の冷却部材１０ａ，１０ｂの間に実装された半導体素子３の配線構造を示している。図２Ａは図１の半導体モジュールを上面から見た平面図であり、半導体素子３、第１の電極５、第２の電極６の位置関係を示している。また、図２Ｂは図２Ａの変形例であり、図２Ａの第２の電極６がスリット状であるのに対し、図２Ｂでは第２の電極６が複数のビア（ここでは、３本のビア）で構成される例を示している。
　本実施例の半導体モジュールは、図１に示すように、下層から順に、少なくとも第１の配線層１、第１の接合層２、半導体素子３、第２の接合層４、第1の電極５、第２の電極６、第２の配線層７を備える積層構造となっている。第1の電極５および第２の電極６により電極５０が構成されている。第１の配線層１と第２の配線層７の間の空隙には封止部材８が充填されて封止されている。第１の配線層１の下層（外側）には絶縁部材９ａを介して冷却部材１０ａが設けられており、第２の配線層７の上層（外側）には絶縁部材９ｂを介して冷却部材１０ｂが設けられている。
　第１の配線層１や第２の配線層７、第1の電極５、第２の電極６は、銅（Cu）やアルミニウム（Al）等の導電材料により構成されている。また、第1の接合層２、第２の接合層４は、はんだや焼結銀、焼結銅、焼結金などの接合材料により構成されている。半導体素子３は、SiやSiC、窒化ガリウム（GaN）などの半導体材料により構成されている。封止部材８には、封止樹脂、セラミック、ガラス、気体などの封止用の絶縁材料が用いられる。絶縁部材９ａ，９ｂは、窒化アルミニウム（AlN）や窒化シリコン（SiN）、酸化アルミニウム（Al2O3）、樹脂シートなどの絶縁材料によって構成される。冷却部材１０a，１０ｂは、Al、Cuなどの熱伝導率の高い材料によって構成される。
　半導体モジュールを高温で動作させる場合、半導体素子３は、SiCやGaNなどのワイドバンドギャップ半導体が好ましく、接合層は融点が高く高耐熱な焼結銀や焼結銅によって構成されることが好ましい。また、第２の接合層４を焼結銅、第１の電極５および第２の電極６をCuによって構成することで、部材間の線膨脹係数差が無くなりひずみが低減されるため、より好適である。また、第１の電極５は、第２の接合層４と同等程度の膜厚であることが好ましい。
　図１および図２Ａに示すように、第２の電極６は、半導体素子３の半導体素子中心位置から外れた形で設けられる。このように、半導体素子の温度が最も高くなる中心位置を避ける形で第２の電極６を設けることで、第２の電極６の熱膨張によって発生する熱ひずみの影響を抑えることが可能となる。
　特許文献２のように周辺部に薄肉部を設けた構造と、本実施例の構造（図２Ａ）の評価位置Ｂにおける相当塑性ひずみの分布を有限要素解析によって計算した比較結果を図３に示す。図３の横軸は半導体素子３の左端からの位置を示し、縦軸は相当塑性ひずみの強度を示している。従来構造１（特許文献２の構造）では半導体素子全体に渡って、ひずみが生じている。一方、本実施例（本発明）の構造では、全体的にひずみが緩和されており、特に半導体素子の中心位置付近ではひずみがほとんど無いことが分かる。このように、本発明によれば接合層に発生するひずみを効果的に低減することができる。
　また、第２の電極６の幅ｂ（図２Ａ）は、少なくとも第１の電極５の厚さｔ（図１）よりも広く設ける必要がある。第２の電極６の幅ｂを第１の電極５の厚さｔより広くすることで、放熱パスが広がり、放熱性を向上させるメリットがある。
　特許文献３のように第１導体部材の変形部の幅ｂと接合部の厚さｔの関係をｂ＝ｔとした場合と、本実施例の構造のように第２の電極６の幅ｂと第１の電極５の厚さｔの関係をｂ＞tとした場合において、半導体素子３の評価位置Ａ（図２Ａ）における温度を比較した結果を図４に示す。図４の横軸は半導体素子３の左端からの位置を示し、縦軸は半導体素子３の温度を示している。本実施例（本発明）の構造は、従来構造２（特許文献３の構造）に比べて、温度が低いことが分かる。このように、本発明によれば、半導体モジュールの冷却性能を保ちながら、半導体素子と他の導体部材との接合部のひずみを低減することが可能となる。これにより、半導体モジュールの信頼性を向上することができる。
　なお、第２の電極６を図２Ａのようにスリット状に設けるのではなく、図２Ｂのように複数のビアで形成してもよい。この場合においても、第２の電極６の幅ｂ、すなわちビア径ｂを第１の電極５の厚さｔ（図１）よりも広く設ける必要がある。また、設けるビアの数は、シミュレーションなどにより半導体素子の温度やひずみを予め算出したうえで決定するのが望ましい。
　図１および図５を参照して、本実施例の半導体モジュールの製造方法について説明する。第１の電極５および第２の電極６からなる電極５０の製造方法としては、第１の電極５、第２の電極６、第２の配線層７がそれぞれ別々に形成され、各部材間を接合部材で接続する構成としている。つまり、第１の電極５と第２の電極６は第３の接合層で接続され、第２の電極６と第２の配線層７は第４の接合層で接続される。
　この際に第１の電極５、第２の電極６、第２の配線層７はCuで形成し、各部材間の接合部材は焼結銅であることが好ましい。第２の配線層７にCuを用いることができない場合でも、少なくとも、温度の高くなる第1の電極５と第２の電極６はCuで形成し、その間の接合部材は焼結銅とするのが熱ひずみ低減のために好ましい。
　また、第２の配線層７や第２の電極６は溶湯や削りだしなどによって一体物として形成してもよい。この際に第１の電極５も一体で形成可能であれば接合部がなくなるためより好ましい。
　なお、焼結金属によって部材同士を接合する場合、一般的に加圧プロセスが必要となる。この際に、均一に圧力を加えるために図５に示すように非接合のスペーサー１１を第１の電極５と第２の配線層７の間に挟んでもよい。この場合、スペーサー１１は第２の電極６と同じ部材であることが好ましく、接合後に除去される。例えば第２の電極６をCuで形成する場合は、スペーサー１１にもCuを用いるのが望ましい。同じ材料を用いることで、均一に圧力を加えることができ、各部材間により信頼性の高い接合を形成することができる。
　なお、スペーサー１１を封止部材８と同じ部材で構成しておきそのままモールドしてもよい。また、第1の配線層１から第１の電極５までを一度加圧接合しておき、その後第２の電極６と第２の配線層７を加圧接合してもよい。
　図６Ａ，図６Ｂは、図１，図２Ａに示す半導体モジュールの変形例である。図６Ａは第１の配線層１から第２の配線層７までの積層構造を示しており、図１では第１の電極５と第２の配線層７を１つの第２の電極６で接続しているのに対し、図６Ａではチップ中心位置を挟んで第１の電極５の両端に２つの第２の電極６を設けて第１の電極５と第２の配線層７を接続している。図６Ｂは図６Ａを上面から見た平面図である。
　図６Ａ，図６Ｂに示すように、チップ中心位置を挟んで第１の電極５の両端に２つの第２の電極６を設けて第１の電極５と第２の配線層７を接続する構造とすることで、焼結金属によって部材同士を接合する場合に、より均一に加圧することが可能になる。また、この場合、第１の電極５からの放熱パスが２倍になるため、より効果的に熱ひずみを低減することができる。
　本実施例によれば、SiCなどを利用したパワーデバイスが高温動作した場合においても、焼結金属接合部に発生する熱ひずみを低減することが可能となり、接合の信頼性を向上することができる。
　図７Ａから図８Ｂを参照して、本実施例の半導体モジュールについて説明する。図７Ａは、第１の配線層１と第２の配線層７の間に複数の半導体装置３を配置した半導体モジュールの断面図である。図７Ｂは図７Ａを上面から見た平面図である。また、図８Ａ，図８Ｂは図７Ａ，図７Ｂの変形例であり、各半導体装置３に対する各々の第２の電極６の位置が異なる例を示している。
　図７Ａ，図７Ｂの半導体モジュールでは、モジュールの中心位置の左右の領域に配置される半導体装置３上の第２の電極６が、モジュールの中心位置に対して対称になるように配置されている。また、図８Ａ，図８Ｂの半導体モジュールでは、モジュールの中心位置の左右の領域に各々配置される半導体装置３上の第２の電極６を同じ領域内で対称になるように配置している。
　半導体素子としてSiCを用いる場合、素子の欠陥の問題からチップ（半導体装置）を大型化できないため、一般に図７Ａから図８Ｂのように、複数のチップを並列接続して使用する場合が多い。この際に、第１の電極５と第２の電極６を実施例１や実施例２で説明した構造として放熱性を高め、さらに、図７Ａから図８Ｂのように、第２の電極６を半導体モジュールの中心位置に対して対称に配置して半導体モジュール内の熱ひずみの偏在を低減することで、半導体モジュール全体の反り変形の偏りを抑制することが可能となる。これにより、半導体モジュールの信頼性が向上する。
　また、図８Ａ，図８Ｂのように、モジュールの中心位置の左右各々の領域内において第２の電極６を対称に配置することで、半導体モジュール内の熱ひずみの偏在がさらに低減される。
　また、第２の電極６と第２の配線層７の間に第３の電極を設け、第３の電極に複数の第２の電極が接続される構造としても良い。この場合、第２の電極６と第３の電極を第５の接合層を介して接続しても良く、第３の電極と第２の配線層７を第６の接合層を介して接続する構造としても良い。
　なお、上記した実施例は、本発明の理解を助けるために具体的に説明したものであり、本発明は、説明した全ての構成を備えることに限定されるものではない。例えば、ある実施例の構成の一部を他の実施例の構成に置き換えることが可能であり、また、ある実施例の構成に他の実施例の構成を加えることも可能である。さらに、各実施例の構成の一部について、削除・他の構成に置換・他の構成の追加をすることが可能である。
　１…第１の配線層、２…第1の接合層、３…半導体素子、４…第２の接合層、５…第1の電極、６…第２の電極、７…第２の配線層、８…封止部材、９ａ，９ｂ…絶縁部材、１０ａ，１０ｂ…冷却部材、１１…スペーサー、５０…電極。

Claims (20)

  1. 　第１の配線層と、
    　前記第１の配線層上に第１の接合層を介して接合された半導体素子と、
    　前記半導体素子上に第２の接合層を介して接合された第１の電極と、
    　前記第１の電極上に接続された第２の電極と、
    　前記第２の電極上に接続された第２の配線層と、を備え、
    　前記第２の電極の短手方向の幅は、前記第１の電極の厚さよりも広く、
    　前記第２の電極は前記半導体素子の中心位置から外れた位置に配置されることを特徴とする半導体モジュール。
  2. 　請求項１に記載の半導体モジュールであって、
    　前記第２の電極は、スリット状の電極であることを特徴とする半導体モジュール。
  3. 　請求項２に記載の半導体モジュールであって、
    　前記第２の電極は、前記半導体素子の中心位置を挟んで前記第１の電極の両端に各々１つずつ接続されることを特徴とする半導体モジュール。
  4. 　請求項１に記載の半導体モジュールであって、
    　前記第２の電極は、複数個のビアからなり、
    　前記短手方向の幅は、前記ビアのビア径であることを特徴とする半導体モジュール。
  5. 　請求項１から４のいずれか１項に記載の半導体モジュールであって、
    　前記第１の接合層および前記第２の接合層のうち、少なくともいずれか一方は金属粒子を焼結させた焼結金属であることを特徴とする半導体モジュール。
  6. 　請求項１から４のいずれか１項に記載の半導体モジュールであって、
    　前記第１の電極は銅を主成分とする導電部材からなり、
    　前記第２の接合層は焼結銅であることを特徴とする半導体モジュール。
  7. 　請求項１から６のいずれか１項に記載の半導体モジュールであって、
    　前記第１の電極と前記第２の電極は、第３の接合層を介して接続されることを特徴とする半導体モジュール。
  8. 　請求項１に記載の半導体モジュールであって、
    　前記第１の電極と前記第２の電極は、一体の導電部材からなることを特徴とする半導体モジュール。
  9. 　請求項１から８のいずれか１項に記載の半導体モジュールであって、
    　前記第２の電極と前記第２の配線層は、第４の接合層を介して接続されることを特徴とする半導体モジュール。
  10. 　請求項１から９のいずれか１項に記載の半導体モジュールであって、
    　前記半導体素子が同一半導体モジュール内に複数個配置されていることを特徴とする半導体モジュール。
  11. 　請求項１０に記載の半導体モジュールであって、
    　前記第２の電極は、前記半導体モジュールの長手方向の中心位置を対称軸として線対称となるように設けられることを特徴とする半導体モジュール。
  12. 　請求項１１に記載の半導体モジュールであって、
    　前記対称軸により２分割される一方の領域の前記第２の電極は、前記半導体モジュールの長手方向において隣接する他の第２の電極と線対称になるように設けられることを特徴とする半導体モジュール。
  13. 　請求項１０に記載の半導体モジュールであって、
    　前記第２の電極と前記第２の配線層の間に第３の電極を有し、
    　前記第３の電極には少なくとも２つ以上の第２の電極が接続されることを特徴とする半導体モジュール。
  14. 　請求項１３に記載の半導体モジュールであって、
    　前記第２の電極と前記第３の電極は、第５の接合層を介して接続されることを特徴とする半導体モジュール。
  15. 　請求項１４に記載の半導体モジュールであって、
    　前記第３の電極と前記第２の配線層は、第６の接合層を介して接続されることを特徴とする半導体モジュール。
  16. 　（ａ）第１の配線層上に第１の接合層を介して半導体素子を接合する工程、
    　（ｂ）前記半導体素子上に第２の接合層を介して第１の電極を接合する工程、
    　（ｃ）前記第１の電極上に第２の電極およびスペーサーを配置する工程、
    　（ｄ）前記第２の電極および前記スペーサー上に第２の配線層を形成する工程、
    　（ｅ）前記第２の配線層上から加圧する工程、
    　を含む半導体モジュールの製造方法であって、
    　前記第２の電極の短手方向の幅は、前記第１の電極の厚さよりも広く、
    　前記第２の電極は前記半導体素子の中心位置から外れた位置に配置されることを特徴とする半導体モジュールの製造方法。
  17. 　請求項１６に記載の半導体モジュールの製造方法であって、
    　前記（ｅ）工程の後、（ｆ）前記スペーサーを除去する工程、をさらに有することを特徴とする半導体モジュールの製造方法。
  18. 　請求項１７に記載の半導体モジュールの製造方法であって、
    　前記第２の電極および前記スペーサーは同じ材料であることを特徴とする半導体モジュールの製造方法。
  19. 　請求項１６に記載の半導体モジュールの製造方法であって、
    　前記スペーサーは、前記第１の配線層と前記第２の配線層間の空隙を封止する封止部材と同じ材料であることを特徴とする半導体モジュールの製造方法。
  20. 　請求項１６から１９のいずれか１項に記載の半導体モジュールの製造方法であって、
    　前記第１の接合層および前記第２の接合層のうち、少なくともいずれか一方は金属粒子を焼結させた焼結金属であることを特徴とする半導体モジュールの製造方法。
PCT/JP2017/010990 2016-07-27 2017-03-17 半導体モジュールおよび半導体モジュールの製造方法 WO2018020729A1 (ja)

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WO2023026599A1 (ja) * 2021-08-27 2023-03-02 株式会社日立パワーデバイス パワー半導体ユニット、パワー半導体ユニットの製造方法
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