WO2018016829A1 - Flexible circuit board and manufacturing method therefor - Google Patents

Flexible circuit board and manufacturing method therefor Download PDF

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Publication number
WO2018016829A1
WO2018016829A1 PCT/KR2017/007669 KR2017007669W WO2018016829A1 WO 2018016829 A1 WO2018016829 A1 WO 2018016829A1 KR 2017007669 W KR2017007669 W KR 2017007669W WO 2018016829 A1 WO2018016829 A1 WO 2018016829A1
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WO
WIPO (PCT)
Prior art keywords
heat dissipation
layer
protective layer
base film
conductive pattern
Prior art date
Application number
PCT/KR2017/007669
Other languages
French (fr)
Korean (ko)
Inventor
손동은
이재문
Original Assignee
스템코 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 스템코 주식회사 filed Critical 스템코 주식회사
Priority to JP2019502734A priority Critical patent/JP2019521528A/en
Priority to CN201780044647.6A priority patent/CN109804717A/en
Publication of WO2018016829A1 publication Critical patent/WO2018016829A1/en

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203Cooling of mounted components
    • H05K1/0209External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/118Printed elements for providing electric connections to or between printed circuits specially for flexible printed circuits, e.g. using folded portions
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/189Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/281Applying non-metallic protective coatings by means of a preformed insulating foil
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00Constructional details common to different types of electric apparatus
    • H05K7/20Modifications to facilitate cooling, ventilating, or heating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00Constructional details common to different types of electric apparatus
    • H05K7/20Modifications to facilitate cooling, ventilating, or heating
    • H05K7/2039Modifications to facilitate cooling, ventilating, or heating characterised by the heat transfer by conduction from the heat generating element to a dissipating body

Definitions

  • the present invention relates to a flexible circuit board and a method of manufacturing the same.
  • FPDs flat panel displays
  • LCDs liquid crystal displays
  • OLED organic light emitting diode
  • the conductive pattern formed on the flexible circuit board connects the circuit elements and transfers electrical signals transmitted at high speed.
  • high integration of flexible circuit boards and conductive patterns formed thereon has also been progressed. Due to integration and precision, problems of malfunction of circuit elements due to heat generated on conductive patterns have arisen. have.
  • the technical problem to be solved by the present invention is to provide a flexible circuit board having good heat dissipation characteristics, including a heat dissipation layer containing a heat dissipation material on the protective layer covering the conductive pattern.
  • Another technical problem to be solved by the present invention is to provide a method for manufacturing a flexible circuit board on which a heat dissipation layer containing a heat dissipation material is formed on a protective layer covering the conductive pattern.
  • a flexible circuit board may include a base film, a plurality of first conductive patterns formed on one surface of the base film, and a plurality of first conductive patterns formed to cover the plurality of first conductive patterns.
  • the height of the top surface of the first protective layer from the base film may be equal to or higher than the height of the top surfaces of the plurality of conductive patterns from the base film.
  • the top surface of the first heat dissipation layer may be substantially flat.
  • the ratio of the thickness of the first protective layer and the first heat dissipation layer may be 2: 8 to 8: 2.
  • the thickness of the first protective layer is 1 ⁇ m to 30 ⁇ m
  • the thickness of the first heat dissipating layer is 1 ⁇ m to 30 ⁇ m
  • the thickness of the first protective layer and the first heat dissipating layer may be 2 ⁇ m to 60 ⁇ m.
  • the base material may include the same material as the material constituting the first protective layer.
  • a plurality of second conductive patterns formed on the other surface of the base film opposite to the one surface thereof, a second protective layer formed to cover the plurality of second conductive patterns, and the second protective layer may be covered. It may further include a second heat dissipation layer including a heat dissipation material therein.
  • the first passivation layer is formed along a profile of the plurality of first conductive patterns, and an upper surface of the first passivation layer is formed on the first surface of the first conductive pattern and the first passivation layer. And a second surface between the surfaces, wherein a height of the first surface from the base film may be higher than a height of the second surface from the base film.
  • the first heat dissipation layer may be formed along a profile of the upper surface of the first protective layer.
  • the semiconductor device may further include a plating layer interposed between the first conductive pattern and the first protective layer.
  • a method of manufacturing a flexible circuit board provides a base film having a plurality of conductive patterns formed on at least one surface thereof, and forms a protective layer to cover the plurality of conductive patterns. And forming a heat dissipation layer including a heat dissipation material mixed therein on the protective layer.
  • forming the heat dissipation layer may include forming a height of the heat dissipation layer from the base film to be higher than a top surface of the conductive pattern.
  • a heat radiation layer including a heat radiation material is formed on the base film, so that heat generated from the conductive pattern can be effectively released.
  • the protective layer interposed between the heat dissipation layer and the conductive pattern is formed so as to completely cover the conductive pattern, thereby preventing the electrical reliability deterioration due to the heat dissipation material included in the heat dissipation layer.
  • FIG. 1 is a cross-sectional view of a flexible circuit board according to an embodiment of the present invention.
  • FIG. 2 is an enlarged view enlarging a part of FIG. 1.
  • FIG 3 is a cross-sectional view of a flexible circuit board according to another embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of a flexible circuit board according to another embodiment of the present invention.
  • FIG. 5 is a flowchart illustrating a method of manufacturing a flexible circuit board according to an embodiment of the present invention.
  • spatially relative terms below “, “ beneath “, “ lower”, “ above “, “ upper” It may be used to easily describe the correlation of a device or components with other devices or components. Spatially relative terms are to be understood as including terms in different directions of the device in use or operation in addition to the directions shown in the figures. For example, when flipping a device shown in the figure, a device described as “below” or “beneath” of another device may be placed “above” of another device. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device can also be oriented in other directions, so that spatially relative terms can be interpreted according to orientation.
  • first, second, etc. are used to describe various elements or components, these elements or components are of course not limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, the first device or component mentioned below may be a second device or component within the technical idea of the present invention.
  • FIG. 1 is a cross-sectional view of a flexible circuit board according to an exemplary embodiment of the present invention
  • FIG. 2 is an enlarged view of a portion of FIG. 1.
  • a flexible circuit board may include a base film 10, a first conductive pattern 20, a first protective layer 30, and a first heat dissipation layer 40. It may include.
  • the base film 10 may be formed of a flexible material and may be included as the substrate in the flexible circuit board 1 to allow the flexible circuit board 1 to be bent or folded.
  • the base film 10 may be, for example, a polyimide film.
  • the base film 10 may be a PET film, polyethylene naphthalate film, polycarbonate film or insulating metal foil.
  • the base film 10 will be described as being a polyimide film.
  • the first conductive pattern 20 may be formed on the base film 10.
  • the first conductive pattern 110 may have at least one strip-shaped conductive line having a predetermined width.
  • the first conductive pattern 20 may transfer electrical signals between the circuit elements mounted on the base film 10 and the electronic devices to which the flexible circuit board 1 is connected.
  • the first conductive pattern 20 may include, for example, a conductive material such as copper, but the present invention is not limited thereto. Specifically, the first conductive pattern 20 may be made of a material having electrical conductivity, such as gold and aluminum.
  • the first passivation layer 30 may be formed to cover the first conductive pattern 20.
  • the first protective layer 30 may include an insulating material, and the insulating material may be, for example, a solder resist. Alternatively, the first protective layer 30 may include a coverlay film.
  • the first passivation layer 30 may completely cover the first conductive pattern 20. That is, the level of the upper surface 35 of the first protective layer 30 may be equal to or higher than the level of the uppermost surface 25 of the first conductive pattern 20. Therefore, the height of the upper surface 35 of the first protective layer 30 from the base film 10 may be equal to or higher than the height of the uppermost surface 25 of the first conductive pattern 20 from the base film 10.
  • an additional plating layer may be formed between the first conductive pattern 20 and the first protective layer 30 to cover the surface of the first conductive pattern 20.
  • the plating layer may be formed by plating a material such as copper, tin, nickel, palladium, gold, or an alloy thereof on the first conductive pattern 20.
  • the upper surface 35 of the first protective layer 30 may be substantially flat.
  • Substantially flat herein may include a case where some unevenness is formed on an upper surface of the first protective layer 30.
  • the height difference between the uppermost part and the lowermost part of the upper surface of the first protective layer 30 can be negligible compared to the overall thickness of the first protective layer 30.
  • the first protective layer 30 is formed.
  • the process of planarizing the upper surface of the may be added.
  • the first heat dissipation layer 40 may be formed on the first protective layer 30.
  • the first heat dissipation layer 40 may be formed to cover the top surface of the first passivation layer 30. As shown in FIG. 1, the first heat dissipation layer 40 may be formed to completely cover the surface of the first protective layer 30, but the present invention is not limited thereto.
  • the first heat dissipation layer 40 may be formed so as to cover only an area on the first protective layer 30 overlapping the first conductive pattern 20.
  • the first passivation layer 30 may be covered.
  • the height of the lower surface 41 of the first heat dissipation layer 40 may also be equal to or higher than the height of the uppermost surface 25 of the first conductive pattern 20.
  • the ratio of the thickness of the first protective layer 30 and the first heat dissipation layer 40 may be 2: 8 to 8: 2.
  • the thickness of the first protective layer 30 refers to the height from the top surface of the first conductive pattern 20 to the top surface 35 of the first protective layer 30, the thickness of the first heat dissipation layer 40 The height from the lower surface 41 of the first heat dissipation layer 40 on the upper surface 35 of the first protective layer 30 to the uppermost surface of the first heat dissipation layer 40 is referred to.
  • the heat dissipation effect of the first conductive pattern 20 by the first heat dissipation layer 40 may be insufficient. have.
  • the thickness of the first protective layer 30 is too thin compared to the first heat dissipation layer 40, there is a fear that the insulating property is lowered, compared to the thickness of the first protective layer 30, the first heat dissipation layer
  • the thickness of 40 is formed more than necessary, the manufacturing cost of the flexible circuit board 1 may be excessively increased compared with the increase in the heat radiation effect.
  • the thickness of the first protective layer 30 may be 1 ⁇ m to 30 ⁇ m
  • the thickness of the first heat dissipation layer 40 may be 1 ⁇ m to 30 ⁇ m
  • the first protective layer 30 may be used.
  • the thickness of the first heat dissipation layer 40 may be 2 ⁇ m to 60 ⁇ m.
  • the first heat dissipation layer 40 may include a base material and a heat dissipation member 45.
  • the base material may include, for example, a solder resist or coverlay film.
  • the base material of the first heat dissipation layer 40 may include the same material as the first protective layer 30.
  • the heat dissipation member 45 as the heat dissipation material included in the first heat dissipation layer 40 may include a material having good thermal conductivity, and for example, a metallic material such as aluminum or copper or a carbon material such as graphene or carbon nanotubes. It may include or may contain a compound thereof.
  • the heat dissipation member 45 may include a spherical heat dissipation ball, but the present invention is not limited thereto.
  • the heat dissipation member 45 may have a polyhedron shape such as a hexahedron, and may be mixed with the base material of the first heat dissipation layer 40 so as to transfer heat generated in the first conductive pattern 20 to the air without limitation in shape. It can be applied to the invention.
  • the heat generated from the first conductive pattern 20 is discharged to the outside by the heat radiating material 45 included in the first heat radiating layer 40. I can promote it. Therefore, the circuit element and the electronic device mounted on the first conductive pattern 20 by the first heat dissipation layer 40 reduce the influence of heat received from the heat generated in the first conductive pattern 20, and the flexible circuit board 1 Operating reliability) may be increased.
  • first heat dissipation layer 40 on the first protective layer 30 may be advantageous in terms of production process and production cost rather than forming a separate metal tape on the back surface of the base film 10. Can be.
  • the first heat dissipation layer 40 may be spaced apart from the first conductive pattern 20 due to the first protective layer 30.
  • the height of the upper surface 35 of the first protective layer 30 is equal to or higher than the height of the uppermost surface of the first conductive pattern 25, the first heat dissipation between the plurality of first conductive patterns 20.
  • the heat dissipation member 45 included in the layer 40 and the first heat dissipation layer 40 is not located.
  • the heat dissipation member 45 reacts with moisture, and the like. Due to the leakage current formed to flow between the patterns 20, the insulation effect between the plurality of first conductive patterns 20 may be reduced. Therefore, the operation reliability of the flexible circuit board 1 can also be lowered.
  • the first heat dissipation layer 40 of the flexible circuit board 1 may include the first heat dissipation layer 40 and the first heat dissipation layer 40 between the plurality of first conductive patterns 20. Since the heat dissipation member 45 included in the 40 is not positioned, even when the heat dissipation member 45 in the first heat dissipation layer 40 reacts with moisture, a leakage current is generated between the first conductive patterns 20. Can be prevented and effectively insulated between the first conductive patterns 20.
  • FIG. 3 is a cross-sectional view of a flexible circuit board according to another embodiment of the present invention.
  • the description of the parts in common with the above-described embodiments will be omitted and the differences will be mainly described.
  • the flexible circuit board 2 differs in shape of the flexible circuit board and the first protective layer 130 and the first heat dissipation layer 140 in the above-described embodiment. Can be.
  • the upper surface 135 of the first protective layer 130 may be formed along the profile of the upper surface of the first conductive pattern 20. That is, the upper surface 135 of the first protective layer 130 includes a first surface 136 on the first conductive pattern 20 and a second surface 137 between the first surface 136, the base The height of the first face 136 from the film 10 is higher than the height of the second face 137.
  • the top surface 135 of the first passivation layer 130 is formed along the profile of the top surface of the first conductive pattern 20, it may still be equal to or higher than the height of the top surface of the first conductive pattern 20. have. That is, the level of the second surface 137 that is lower than the height of the first surface 136 of the upper surface 135 of the first protective layer 130 is still equal to or higher than the level of the uppermost surface of the first conductive pattern 20.
  • the heat dissipation material included in the first heat dissipation layer 140 and the first heat dissipation layer 40 may be prevented from being disposed between the first conductive patterns 20. Therefore, despite the shape of the upper surface 135 of the deformed first passivation layer 130, the insulation effect between the first passivation layer 130 and the first conductive pattern 20 due to the first heat dissipation layer 140 remains the same. Can be maintained.
  • the shape of the first heat dissipation layer 140 covering the first passivation layer 130 is also defined by the first passivation layer 130. It can be formed along the profile of). Accordingly, the upper surface of the first heat dissipation layer 140 may include a first surface 141 on the first conductive pattern 20 and a second surface 142 between the first surface, and the first surface 141. The height of may be higher than the height of the second surface 142.
  • the height of the bottom surface of the first heat dissipation layer 140 may be equal to or higher than the height of the top surface of the first conductive pattern 20.
  • the first protective layer 130 is formed along the profile of the surface of the first conductive pattern 20, the upper surface 135 of the curved first protective layer 130 is formed. ), The surface area of the top surface 135 of the first protective layer 130 may increase.
  • the contact area between the first passivation layer 130 and the first heat dissipation layer 140 may also increase due to the increased surface area of the upper surface 135 of the first passivation layer 130. Therefore, the heat transfer efficiency of the first conductive pattern 20 transferred to the first heat dissipation layer 140 through the first protective layer 130 may increase.
  • first passivation layer 130 is formed along the profile of the first conductive pattern 20, after forming the first passivation layer 130, planarizing the top surface of the first passivation layer 130. This may not be done.
  • FIG. 4 is a cross-sectional view of a flexible circuit board according to another embodiment of the present invention.
  • the flexible circuit board 3 may include a second conductive pattern 120 and a second conductive pattern 120 formed on a surface opposite to the first conductive pattern 20 of the base film 10.
  • the via layer 51 may further include a via 51 penetrating the protective layer 230, the second heat dissipating layer 240, and the base film 10.
  • the second conductive pattern 120 may be formed on an opposite surface of one surface on which the first conductive pattern 20 of the base film 10 is formed. Like the first conductive pattern 20, the second conductive pattern 120 may include at least one or more conductive wires having a predetermined width.
  • the second conductive pattern 120 may be electrically connected to the first conductive pattern 20 through the via 51 penetrating the substrate.
  • the via 51 may fill the via hole 50 formed through the base film 10.
  • the via 51 may include a conductive material such as copper or gold, or an alloy thereof.
  • one or more additional metal layers may be included between the inner wall of the via hole 50 and the via 51.
  • first conductive pattern 20 and the second conductive pattern 120 are formed at positions corresponding to the base film 10, but the present invention is not limited thereto. It will be apparent to those skilled in the art that the arrangement of the first and second conductive patterns 20 may vary according to the design of the flexible circuit board 1 and the arrangement of the circuit elements mounted thereon. .
  • the second protective layer 230 may be formed to cover the second conductive pattern 120. Like the first passivation layer 30, the second passivation layer 230 may be formed to completely cover the second conductive pattern 120. Therefore, the height of the upper surface of the second protective layer 230 from the other surface of the base film 10 may be equal to or higher than the height of the uppermost surface of the second conductive pattern 120.
  • the second heat dissipation layer 240 may be formed on the second protective layer 230.
  • the second heat dissipation layer 240 may include a base material which is an insulating material and a heat dissipation material contained in the base material.
  • the first heat dissipation layer 40 and the second heat dissipation layer 240 may include the same material. That is, the base material and the heat dissipation layer constituting the first heat dissipation layer 40 and the second heat dissipation layer 240 may include the same material.
  • the second heat dissipation layer 240 may be formed to completely cover the second protective layer 230.
  • the second heat dissipation layer 240 may include the second conductive pattern 120. It may be formed to cover only the upper surface of the second protective layer 230 on the formed region.
  • the second heat dissipation layer 240 is not interposed between the second conductive patterns 120. This is the same as the description associated with the first heat dissipation layer 40. Therefore, the shape of the second heat dissipation layer 240 helps to release heat generated in the second conductive pattern 120 into the air, and at the same time, a leakage current is generated between the second conductive pattern 120 and the heat dissipating material, thereby providing a flexible circuit. It is possible to prevent reducing the operating reliability of the substrate 3.
  • FIG. 5 is a flowchart illustrating a method of manufacturing a flexible circuit board according to an embodiment of the present invention.
  • a method of manufacturing a flexible circuit board provides a base film having a plurality of conductive patterns formed on at least one surface thereof (S10), and forming the plurality of conductive patterns.
  • a first protective layer is formed to cover (S20), and a heat radiation layer having a heat dissipating material formed therein is formed on the first protective layer (S30).
  • the first conductive pattern 20 may be formed by, for example, a semi additive process of forming a resist on the base film 10 and performing plating in an electrolytic or non-electrolytic manner.
  • a conductive layer may be formed on the layer 10 and may be formed by an etching process of etching the conductive layer.
  • Forming the first protective layer 30 to cover the plurality of first conductive patterns 20 may include forming a solder resist or coverlay film on the first conductive pattern 20 by printing or laminating. Can be.
  • the first protective layer 30 needs to be sufficiently formed so that the level of the upper surface of the first protective layer 30 can be higher than the level of the uppermost surface of the first conductive pattern 20.
  • Flattening the upper surface of the first protective layer 30 may include, for example, pressing the upper surface of the first protective layer 30 with a press.
  • Forming the first heat dissipation layer 40 to cover the first passivation layer 30 may include printing or laminating a solder resist or coverlay film including the heat dissipation material 45 on the first passivation layer 30. It may include forming into.

Abstract

A flexible circuit board and a manufacturing method therefor are provided. A flexible circuit board comprises: a base film; a plurality of first conductive patterns formed on one surface of the base film; a first protection layer formed to cover the plurality of first conductive patterns; and a first heat dissipation layer covering the first protection layer, wherein the first heat dissipation layer includes a base material and a heat dissipation material contained in the base material.

Description

연성 회로 기판 및 그 제조 방법Flexible circuit board and its manufacturing method
본 발명은 연성 회로 기판 및 그 제조 방법에 관한 것이다.The present invention relates to a flexible circuit board and a method of manufacturing the same.
최근 전자 기기에 소형화 추세에 따라 연성 회로 기판을 이용한 칩 온 필름(Chip On Film: COF) 패키지 기술이 사용되고 있다. 연성 회로 기판 및 이를 이용한 COF 패키지 기술은 예를 들어, 액정 표시 장치(Liquid Crystal Display; LCD), 유기 발광 다이오드(Organic Light Emitting Diode) 디스플레이 장치 등과 같은 평판 표시 장치(Flat Panel Display; FPD)에 이용된다.Recently, according to the trend of miniaturization in electronic devices, chip on film (COF) packaging technology using a flexible circuit board is being used. Flexible circuit boards and COF package technology using the same are used in flat panel displays (FPDs), such as liquid crystal displays (LCDs), organic light emitting diode (OLED) display devices, and the like. do.
연성 회로 기판 상에 형성된 도전 패턴은 회로 소자 간을 연결하고, 고속으로 전송되는 전기적 신호를 전달한다. 한편, 연성 회로 기판이 실장되는 전자 장치의 소형화에 따라 연성 회로 기판 및 이에 형성된 도전 패턴의 고집적화 또한 진행되고 있는데, 집적화 및 정밀화로 인해 도전 패턴 상에서 발생하는 열에 의한 회로 소자의 동작 불량 문제가 대두되고 있다.The conductive pattern formed on the flexible circuit board connects the circuit elements and transfers electrical signals transmitted at high speed. On the other hand, with the miniaturization of electronic devices on which flexible circuit boards are mounted, high integration of flexible circuit boards and conductive patterns formed thereon has also been progressed. Due to integration and precision, problems of malfunction of circuit elements due to heat generated on conductive patterns have arisen. have.
도전 패턴으로부터 발생하는 열을 효과적으로 방출하기 위하여, 도전 패턴의 두께를 증가시키거나, 도전 패턴이 형성된 베이스 필름의 이면에 알루미늄 또는 구리 재질의 메탈 테이프를 부착하여 방열 특성을 높이는 방식이 도입되었다. 그러나 이러한 방식은 연성 회로 기판의 미세화의 구현이 어려워지거나, 추가적인 공정을 필요로 하여 생산 비용 증가 등의 문제를 야기할 수 있다.In order to effectively dissipate heat generated from the conductive pattern, a method of increasing the thickness of the conductive pattern or attaching a metal tape made of aluminum or copper to the back surface of the base film on which the conductive pattern is formed has been introduced. However, such a method may make it difficult to realize the miniaturization of the flexible circuit board, or may require an additional process and cause problems such as an increase in production cost.
본 발명이 해결하고자 하는 기술적 과제는 도전 패턴을 덮는 보호층 상에, 방열재를 함유한 방열층을 포함하여 방열 특성이 좋은 연성 회로 기판을 제공하는 것이다.The technical problem to be solved by the present invention is to provide a flexible circuit board having good heat dissipation characteristics, including a heat dissipation layer containing a heat dissipation material on the protective layer covering the conductive pattern.
본 발명이 해결하고자 하는 다른 기술적 과제는 도전 패턴을 덮는 보호층 상에, 방열재를 함유한 방열층이 형성된 연성 회로 기판의 제조 방법을 제공하는 것이다.Another technical problem to be solved by the present invention is to provide a method for manufacturing a flexible circuit board on which a heat dissipation layer containing a heat dissipation material is formed on a protective layer covering the conductive pattern.
본 발명의 기술적 과제들은 이상에서 언급한 기술적 과제로 제한되지 않으며, 언급되지 않은 또 다른 기술적 과제들은 아래의 기재로부터 당업자에게 명확하게 이해될 수 있을 것이다.Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.
본 발명의 기술적 과제들은 이상에서 언급한 기술적 과제들로 제한되지 않으며, 언급되지 않은 또 다른 기술적 과제들은 아래의 기재로부터 통상의 기술자에게 명확하게 이해될 수 있을 것이다.The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.
상기 기술적 과제를 달성하기 위한 본 발명의 일 실시예에 따른 연성 회로 기판은, 베이스 필름, 상기 베이스 필름의 일면 상에 형성된 복수의 제1 도전 패턴, 상기 복수의 제1 도전 패턴을 덮도록 형성된 제1 보호층 및 상기 제1 보호층을 덮는 방열층으로, 상기 방열층은 베이스 물질 및 상기 베이스 물질에 포함된 방열재를 포함하는 제1 방열층을 포함한다.According to an aspect of the present disclosure, a flexible circuit board may include a base film, a plurality of first conductive patterns formed on one surface of the base film, and a plurality of first conductive patterns formed to cover the plurality of first conductive patterns. A heat dissipation layer covering the first protective layer and the first protective layer, wherein the heat dissipation layer includes a first heat dissipation layer including a base material and a heat dissipation material included in the base material.
본 발명의 몇몇 실시예에서, 상기 베이스 필름으로부터 상기 제1 보호층의 최상면의 높이는, 상기 베이스 필름으로부터 상기 복수의 도전 패턴의 최상면의 높이와 같거나 높을 수 있다.In some embodiments of the present disclosure, the height of the top surface of the first protective layer from the base film may be equal to or higher than the height of the top surfaces of the plurality of conductive patterns from the base film.
본 발명의 몇몇 실시예에서, 상기 제1 방열층의 상면은 실질적으로 평탄할 수 있다.In some embodiments of the present invention, the top surface of the first heat dissipation layer may be substantially flat.
본 발명의 몇몇 실시예에서, 상기 제1 보호층과 제1 방열층의 두께의 비는, 2:8 내지 8:2일 수 있다.In some embodiments of the present invention, the ratio of the thickness of the first protective layer and the first heat dissipation layer may be 2: 8 to 8: 2.
본 발명의 몇몇 실시예에서, 상기 제1 보호층의 두께는 1㎛ 내지 30㎛이고, 상기 제1 방열층의 두께는 1㎛ 내지 30㎛이고, 상기 제1 보호층 및 제1 방열층의 두께의 합이 2㎛ 내지 60㎛일 수 있다.In some embodiments of the present invention, the thickness of the first protective layer is 1 μm to 30 μm, the thickness of the first heat dissipating layer is 1 μm to 30 μm, and the thickness of the first protective layer and the first heat dissipating layer. The sum may be 2 μm to 60 μm.
본 발명의 몇몇 실시예에서, 상기 베이스 물질은 상기 제1 보호층을 구성하는 물질과 동일한 물질을 포함할 수 있다.In some embodiments of the present invention, the base material may include the same material as the material constituting the first protective layer.
본 발명의 몇몇 실시예에서, 상기 베이스 필름의 상기 일면과 대향되는 타면에 형성된 복수의 제2 도전 패턴, 상기 복수의 제2 도전 패턴을 덮도록 형성된 제2 보호층 및 상기 제2 보호층을 덮고, 내부에 방열재를 포함하는 제2 방열층을 더 포함할 수 있다.In some embodiments of the present disclosure, a plurality of second conductive patterns formed on the other surface of the base film opposite to the one surface thereof, a second protective layer formed to cover the plurality of second conductive patterns, and the second protective layer may be covered. It may further include a second heat dissipation layer including a heat dissipation material therein.
본 발명의 몇몇 실시예에서, 상기 제1 보호층은 상기 복수의 제1 도전 패턴의 프로파일을 따라 형성되고, 상기 제1 보호층의 상면은 상기 제1 도전 패턴 상의 제1 면과, 상기 제1 면 사이의 제2 면을 포함하고, 상기 베이스 필름으로부터 상기 제1 면의 높이는 상기 베이스 필름으로부터 상기 제2 면의 높이보다 높을 수 있다.In some embodiments of the present disclosure, the first passivation layer is formed along a profile of the plurality of first conductive patterns, and an upper surface of the first passivation layer is formed on the first surface of the first conductive pattern and the first passivation layer. And a second surface between the surfaces, wherein a height of the first surface from the base film may be higher than a height of the second surface from the base film.
본 발명의 몇몇 실시예에서, 상기 제1 방열층은 상기 제1 보호층의 상면의 프로파일을 따라 형성될 수 있다.In some embodiments of the present disclosure, the first heat dissipation layer may be formed along a profile of the upper surface of the first protective layer.
본 발명의 몇몇 실시예에서, 상기 제1 도전 패턴과 상기 제1 보호층 사이에 개재되는 도금층을 더 포함할 수 있다.In some embodiments of the present disclosure, the semiconductor device may further include a plating layer interposed between the first conductive pattern and the first protective layer.
상기 기술적 과제를 달성하기 위한 본 발명의 일 실시예에 따른 연성 회로 기판의 제조 방법은, 적어도 일면 상에 복수의 도전 패턴이 형성된 베이스 필름을 제공하고, 복수의 도전 패턴을 덮도록 보호층을 형성하고, 상기 보호층 상에, 내부에 혼합된 방열재를 포함하는 방열층을 형성하는 것을 포함한다.According to one or more exemplary embodiments, a method of manufacturing a flexible circuit board provides a base film having a plurality of conductive patterns formed on at least one surface thereof, and forms a protective layer to cover the plurality of conductive patterns. And forming a heat dissipation layer including a heat dissipation material mixed therein on the protective layer.
본 발명의 몇몇 실시예에서, 상기 방열층을 형성하는 것은, 상기 베이스 필름으로부터 상기 방열층의 높이가 상기 도전 패턴의 최상면보다 높게 형성하는 것을 포함할 수 있다.In some embodiments of the present disclosure, forming the heat dissipation layer may include forming a height of the heat dissipation layer from the base film to be higher than a top surface of the conductive pattern.
본 발명의 실시예들에 따른 연성 회로 기판에 따르면, 베이스 필름 상에 방열재를 포함한 방열층을 형성하여, 도전 패턴으로부터 발생하는 열을 효과적으로 방출할 수 있도록 한다.According to the flexible circuit board according to the embodiments of the present invention, a heat radiation layer including a heat radiation material is formed on the base film, so that heat generated from the conductive pattern can be effectively released.
또한, 방열층과 도전 패턴 사이에 개재되는 보호층은 도전 패턴을 완전히 덮도록 형성되고, 따라서 방열층에 포함된 방열재로 인한 전기적 신뢰성 저하를 방지할 수 있다.In addition, the protective layer interposed between the heat dissipation layer and the conductive pattern is formed so as to completely cover the conductive pattern, thereby preventing the electrical reliability deterioration due to the heat dissipation material included in the heat dissipation layer.
본 발명의 효과들은 이상에서 언급한 효과들로 제한되지 않으며, 언급되지 않은 또 다른 효과들은 청구범위의 기재로부터 당업자에게 명확하게 이해될 수 있을 것이다.The effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.
도 1은 본 발명의 일 실시예에 따른 연성 회로 기판의 단면도이다.1 is a cross-sectional view of a flexible circuit board according to an embodiment of the present invention.
도 2는 도 1의 일부를 확대한 확대도이다.FIG. 2 is an enlarged view enlarging a part of FIG. 1. FIG.
도 3은 본 발명의 다른 실시예에 따른 연성 회로 기판의 단면도이다.3 is a cross-sectional view of a flexible circuit board according to another embodiment of the present invention.
도 4는 본 발명의 또 다른 실시예에 따른 연성 회로 기판의 단면도이다.4 is a cross-sectional view of a flexible circuit board according to another embodiment of the present invention.
도 5는 본 발명의 일 실시예에 따른 연성 회로 기판의 제조 방법을 설명하기 위한 순서도이다.5 is a flowchart illustrating a method of manufacturing a flexible circuit board according to an embodiment of the present invention.
본 발명의 이점 및 특징, 그리고 그것들을 달성하는 방법은 첨부되는 도면과 함께 상세하게 후술되어 있는 실시예들을 참조하면 명확해질 것이다. 그러나 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명은 청구항의 범주에 의해 정의될 뿐이다. 도면에서 표시된 구성요소의 크기 및 상대적인 크기는 설명의 명료성을 위해 과장된 것일 수 있다. 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성 요소를 지칭하며, "및/또는"은 언급된 아이템들의 각각 및 하나 이상의 모든 조합을 포함한다.Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. The size and relative size of the components shown in the drawings may be exaggerated for clarity of explanation. Like reference numerals refer to like elements throughout the specification, and "and / or" includes each and every combination of one or more of the mentioned items.
소자(elements) 또는 층이 다른 소자 또는 층의 "위(on)" 또는 "상(on)"으로 지칭되는 것은 다른 소자 또는 층의 바로 위뿐만 아니라 중간에 다른 층 또는 다른 소자를 개재한 경우를 모두 포함한다. 반면, 소자가 "직접 위(directly on)" 또는 "바로 위"로 지칭되는 것은 중간에 다른 소자 또는 층을 개재하지 않은 것을 나타낸다.When elements or layers are referred to as "on" or "on" of another element or layer, intervening other elements or layers as well as intervening another layer or element in between. It includes everything. On the other hand, when a device is referred to as "directly on" or "directly on" indicates that no device or layer is intervened in the middle.
공간적으로 상대적인 용어인 "아래(below)", "아래(beneath)", "하부(lower)", "위(above)", "상부(upper)" 등은 도면에 도시되어 있는 바와 같이 하나의 소자 또는 구성 요소들과 다른 소자 또는 구성 요소들과의 상관관계를 용이하게 기술하기 위해 사용될 수 있다. 공간적으로 상대적인 용어는 도면에 도시되어 있는 방향에 더하여 사용시 또는 동작시 소자의 서로 다른 방향을 포함하는 용어로 이해되어야 한다. 예를 들면, 도면에 도시되어 있는 소자를 뒤집을 경우, 다른 소자의 "아래(below)" 또는 "아래(beneath)"로 기술된 소자는 다른 소자의 "위(above)"에 놓여질 수 있다. 따라서, 예시적인 용어인 "아래"는 아래와 위의 방향을 모두 포함할 수 있다. 소자는 다른 방향으로도 배향될 수 있고, 이에 따라 공간적으로 상대적인 용어들은 배향에 따라 해석될 수 있다.The spatially relative terms " below ", " beneath ", " lower ", " above ", " upper " It may be used to easily describe the correlation of a device or components with other devices or components. Spatially relative terms are to be understood as including terms in different directions of the device in use or operation in addition to the directions shown in the figures. For example, when flipping a device shown in the figure, a device described as "below" or "beneath" of another device may be placed "above" of another device. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in other directions, so that spatially relative terms can be interpreted according to orientation.
본 명세서에서 사용된 용어는 실시예들을 설명하기 위한 것이며 본 발명을 제한하고자 하는 것은 아니다. 본 명세서에서, 단수형은 문구에서 특별히 언급하지 않는 한 복수형도 포함한다. 명세서에서 사용되는 "포함한다(comprises)" 및/또는 "포함하는(comprising)"은 언급된 구성요소 외에 하나 이상의 다른 구성요소의 존재 또는 추가를 배제하지 않는다.The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, "comprises" and / or "comprising" does not exclude the presence or addition of one or more other components in addition to the mentioned components.
비록 제1, 제2 등이 다양한 소자나 구성요소들을 서술하기 위해서 사용되나, 이들 소자나 구성요소들은 이들 용어에 의해 제한되지 않음은 물론이다. 이들 용어들은 단지 하나의 소자나 구성요소를 다른 소자나 구성요소와 구별하기 위하여 사용하는 것이다. 따라서, 이하에서 언급되는 제1 소자나 구성요소는 본 발명의 기술적 사상 내에서 제2 소자나 구성요소 일 수도 있음은 물론이다.Although the first, second, etc. are used to describe various elements or components, these elements or components are of course not limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, the first device or component mentioned below may be a second device or component within the technical idea of the present invention.
다른 정의가 없다면, 본 명세서에서 사용되는 모든 용어(기술 및 과학적 용어를 포함)는 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 공통적으로 이해될 수 있는 의미로 사용될 수 있을 것이다. 또 일반적으로 사용되는 사전에 정의되어 있는 용어들은 명백하게 특별히 정의되어 있지 않는 한 이상적으로 또는 과도하게 해석되지 않는다.Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.
도 1은 본 발명의 일 실시예에 따른 연성 회로 기판의 단면도이고, 도 2는 도 1의 일부를 확대한 확대도이다.1 is a cross-sectional view of a flexible circuit board according to an exemplary embodiment of the present invention, and FIG. 2 is an enlarged view of a portion of FIG. 1.
도 1 및 도 2를 참조하면, 본 발명의 일 실시예에 따른 연성 회로 기판은 베이스 필름(10), 제1 도전 패턴(20), 제1 보호층(30), 제1 방열층(40)을 포함할 수 있다.1 and 2, a flexible circuit board according to an embodiment of the present invention may include a base film 10, a first conductive pattern 20, a first protective layer 30, and a first heat dissipation layer 40. It may include.
베이스 필름(10)은 유연성이 있는 재질로 형성될 수 있으며, 연성 회로 기판(1)에 기재로서 포함되어 연성 회로 기판(1)이 벤딩되거나 접히도록 할 수 있다. 베이스 필름(10)은 예를 들어, 폴리이미드 필름일 수 있다. 이와 달리, 베이스 필름(10)은 PET 필름, 폴리에틸렌 나프탈레이트 필름, 폴리카보네이트 필름 또는 절연금속 호일일 수도 있다. 본 발명의 일 실시예에 따른 연성 회로 기판(1)에서, 베이스 필름(10)은 폴리이미드 필름인 것으로 설명한다.The base film 10 may be formed of a flexible material and may be included as the substrate in the flexible circuit board 1 to allow the flexible circuit board 1 to be bent or folded. The base film 10 may be, for example, a polyimide film. Alternatively, the base film 10 may be a PET film, polyethylene naphthalate film, polycarbonate film or insulating metal foil. In the flexible circuit board 1 according to the embodiment of the present invention, the base film 10 will be described as being a polyimide film.
제1 도전 패턴(20)은 베이스 필름(10) 상에 형성될 수 있다. 제1 도전 패턴(110)은 예를 들어, 일정한 폭을 갖는 띠 형상인 도선이 적어도 하나 이상 형성된 것일 수 있다. 제1 도전 패턴(20)은 베이스 필름(10) 상에 실장되는 회로 소자 및 연성 회로 기판(1)이 접속되는 전자 장치들 간의 전기적 신호를 전달할 수 있다.The first conductive pattern 20 may be formed on the base film 10. For example, the first conductive pattern 110 may have at least one strip-shaped conductive line having a predetermined width. The first conductive pattern 20 may transfer electrical signals between the circuit elements mounted on the base film 10 and the electronic devices to which the flexible circuit board 1 is connected.
제1 도전 패턴(20)은 예를 들어, 구리와 같은 도전성 물질을 포함할 수 있으나 본 발명이 이에 제한되는 것은 아니다. 구체적으로, 제1 도전 패턴(20)은 금, 알루미늄 등의 전기 전도성을 가진 물질로 이루어질 수 있다. The first conductive pattern 20 may include, for example, a conductive material such as copper, but the present invention is not limited thereto. Specifically, the first conductive pattern 20 may be made of a material having electrical conductivity, such as gold and aluminum.
제1 도전 패턴(20)을 덮도록 제1 보호층(30)이 형성될 수 있다. 제1 보호층(30)은 절연 물질을 포함할 수 있고, 절연 물질은 예를 들어 솔더 레지스트일 수 있다. 또는 제1 보호층(30)은 커버레이 필름을 포함할 수도 있다.The first passivation layer 30 may be formed to cover the first conductive pattern 20. The first protective layer 30 may include an insulating material, and the insulating material may be, for example, a solder resist. Alternatively, the first protective layer 30 may include a coverlay film.
제1 보호층(30)은 제1 도전 패턴(20)을 완전히 덮을 수 있다. 즉, 제1 보호층(30)의 상면(35)의 레벨은 제1 도전 패턴(20)의 최상면(25)의 레벨과 같거나 높을 수 있다. 따라서 베이스 필름(10)으로부터 제1 보호층(30)의 상면(35)의 높이는, 베이스 필름(10)으로부터 제1 도전 패턴(20)의 최상면(25)의 높이와 같거나 높을 수 있다.The first passivation layer 30 may completely cover the first conductive pattern 20. That is, the level of the upper surface 35 of the first protective layer 30 may be equal to or higher than the level of the uppermost surface 25 of the first conductive pattern 20. Therefore, the height of the upper surface 35 of the first protective layer 30 from the base film 10 may be equal to or higher than the height of the uppermost surface 25 of the first conductive pattern 20 from the base film 10.
도 1에 도시되지는 않았지만, 제1 도전 패턴(20)과 제1 보호층(30)의 사이에, 제1 도전 패턴(20)의 표면을 덮도록 추가적인 도금층이 형성될 수도 있다. 이러한 도금층은 예를 들어, 제1 도전 패턴(20) 상에 구리, 주석, 니켈, 팔라듐, 금 등의 물질 또는 이들의 합금을 도금시켜 형성할 수 있다.Although not shown in FIG. 1, an additional plating layer may be formed between the first conductive pattern 20 and the first protective layer 30 to cover the surface of the first conductive pattern 20. For example, the plating layer may be formed by plating a material such as copper, tin, nickel, palladium, gold, or an alloy thereof on the first conductive pattern 20.
본 발명의 일 실시예에 따른 연성 회로 기판(1)에서, 제1 보호층(30)의 상면(35)은 실질적으로 평탄할 수 있다. 여기서 실질적으로 평탄하다는 것은, 제1 보호층(30)의 상면에 다소의 요철이 형성된 경우를 포함할 수 있다. 그러나 이와 같은 요철에도 불구하고 제1 보호층(30)의 전체 두께에 비교할 때, 제1 보호층(30)의 상면의 최상부와 최하부의 높이 차이는 극히 적어 무시할 수 있다.In the flexible circuit board 1 according to the exemplary embodiment of the present invention, the upper surface 35 of the first protective layer 30 may be substantially flat. Substantially flat herein may include a case where some unevenness is formed on an upper surface of the first protective layer 30. However, in spite of the irregularities, the height difference between the uppermost part and the lowermost part of the upper surface of the first protective layer 30 can be negligible compared to the overall thickness of the first protective layer 30.
본 발명의 몇몇 실시예에서, 상면이 평탄한 제1 보호층(30)을 형성하기 위하여 제1 도전 패턴(20) 상에 제1 보호층(30)을 형성한 후, 제1 보호층(30)의 상면을 평탄화하는 공정이 추가될 수 있다.In some embodiments of the present invention, after forming the first protective layer 30 on the first conductive pattern 20 to form the first protective layer 30 having a flat top surface, the first protective layer 30 is formed. The process of planarizing the upper surface of the may be added.
제1 보호층(30) 상에, 제1 방열층(40)이 형성될 수 있다. 제1 방열층(40)은 제1 보호층(30)의 상면을 덮도록 형성될 수 있다. 도 1에 도시된 것과 같이, 제1 방열층(40)은 제1 보호층(30)의 표면을 완전히 덮도록 형성될 수 있으나 본 발명이 이에 제한되는 것은 아니다. 제1 방열층(40)은 제1 도전 패턴(20)과 오버랩되는 제1 보호층(30) 상의 영역 만을 덮도록 형성될 수도 있다.The first heat dissipation layer 40 may be formed on the first protective layer 30. The first heat dissipation layer 40 may be formed to cover the top surface of the first passivation layer 30. As shown in FIG. 1, the first heat dissipation layer 40 may be formed to completely cover the surface of the first protective layer 30, but the present invention is not limited thereto. The first heat dissipation layer 40 may be formed so as to cover only an area on the first protective layer 30 overlapping the first conductive pattern 20.
앞서 설명한 것과 같이 제1 보호층(30)의 상면(35)의 높이는 제1 도전 패턴(20)의 최상면(25)의 높이와 같거나 높게 형성될 수 있으므로, 제1 보호층(30)을 덮는 제1 방열층(40)의 하면(41)의 높이 또한 제1 도전 패턴(20)의 최상면(25)의 높이와 같거나 높게 형성될 수 있다.As described above, since the height of the upper surface 35 of the first passivation layer 30 may be the same as or higher than the height of the top surface 25 of the first conductive pattern 20, the first passivation layer 30 may be covered. The height of the lower surface 41 of the first heat dissipation layer 40 may also be equal to or higher than the height of the uppermost surface 25 of the first conductive pattern 20.
본 발명의 몇몇 실시예에서, 제1 보호층(30)과 제1 방열층(40)의 두께의 비는 2:8 내지 8:2일 수 있다. 여기서, 제1 보호층(30)의 두께는 제1 도전 패턴(20)의 상면으로부터 제1 보호층(30)의 상면(35)까지의 높이를 말하며, 제1 방열층(40)의 두께는 제1 보호층(30)의 상면(35) 상의 제1 방열층(40)의 하면(41)으로부터 제1 방열층(40)의 최상면까지의 높이를 말한다. 제1 보호층(30)의 두께에 비하여 제1 방열층(40)의 두께가 너무 얇게 형성되는 경우, 제1 방열층(40)에 의한 제1 도전 패턴(20)의 방열 효과가 불충분할 수 있다. 반면, 제1 방열층(40)에 비해 제1 보호층(30)의 두께가 너무 얇게 형성되는 경우, 절연성이 저하될 우려가 있고, 제1 보호층(30)의 두께에 비하여 제1 방열층(40)의 두께가 필요 이상으로 형성되는 경우, 방열 효과의 증가에 비해 연성 회로 기판(1)의 제조 비용이 과도하게 증가할 수 있다.In some embodiments of the present invention, the ratio of the thickness of the first protective layer 30 and the first heat dissipation layer 40 may be 2: 8 to 8: 2. Here, the thickness of the first protective layer 30 refers to the height from the top surface of the first conductive pattern 20 to the top surface 35 of the first protective layer 30, the thickness of the first heat dissipation layer 40 The height from the lower surface 41 of the first heat dissipation layer 40 on the upper surface 35 of the first protective layer 30 to the uppermost surface of the first heat dissipation layer 40 is referred to. When the thickness of the first heat dissipation layer 40 is too thin compared to the thickness of the first protective layer 30, the heat dissipation effect of the first conductive pattern 20 by the first heat dissipation layer 40 may be insufficient. have. On the other hand, when the thickness of the first protective layer 30 is too thin compared to the first heat dissipation layer 40, there is a fear that the insulating property is lowered, compared to the thickness of the first protective layer 30, the first heat dissipation layer When the thickness of 40 is formed more than necessary, the manufacturing cost of the flexible circuit board 1 may be excessively increased compared with the increase in the heat radiation effect.
본 발명의 몇몇 실시예에서, 제1 보호층(30)의 두께는 1㎛ 내지 30㎛, 제1 방열층(40)의 두께는 1㎛ 내지 30㎛로 할 수 있으며, 제1 보호층(30) 및 제1 방열층(40)의 두께의 합은 2㎛ 내지 60㎛로 형성할 수 있다.In some embodiments of the present invention, the thickness of the first protective layer 30 may be 1 μm to 30 μm, the thickness of the first heat dissipation layer 40 may be 1 μm to 30 μm, and the first protective layer 30 may be used. ) And the thickness of the first heat dissipation layer 40 may be 2 μm to 60 μm.
제1 방열층(40)은 베이스 물질과, 방열재(45)를 포함할 수 있다. 베이스 물질은 예를 들어, 솔더 레지스트 또는 커버레이 필름을 포함할 수 있다. 본 발명의 몇몇 실시예에서, 제1 방열층(40)의 베이스 물질은 제1 보호층(30)과 동일한 물질을 포함할 수 있다.The first heat dissipation layer 40 may include a base material and a heat dissipation member 45. The base material may include, for example, a solder resist or coverlay film. In some embodiments of the present invention, the base material of the first heat dissipation layer 40 may include the same material as the first protective layer 30.
제1 방열층(40)에 포함된 방열재로서의 방열재(45)는 열전도율이 좋은 물질을 포함할 수 있으며, 예를 들어 알루미늄, 구리 등의 금속성 물질 또는 그래핀, 탄소나노튜브 등의 탄소 물질을 포함하거나, 이들의 화합물을 포함할 수도 있다.The heat dissipation member 45 as the heat dissipation material included in the first heat dissipation layer 40 may include a material having good thermal conductivity, and for example, a metallic material such as aluminum or copper or a carbon material such as graphene or carbon nanotubes. It may include or may contain a compound thereof.
본 발명의 몇몇 실시예에서, 방열재(45)는 구형의 방열볼을 포함할 수 있으나 본 발명이 이에 제한되지는 않는다. 방열재(45)는 육면체 등 다면체 형상을 가질 수 있으며, 제1 방열층(40)의 베이스 물질과 섞여 제1 도전 패턴(20)에서 발생한 열을 공기 중으로 전달할 수 있는 물질이라면 형상의 제한 없이 본 발명에 적용할 수 있다.In some embodiments of the present invention, the heat dissipation member 45 may include a spherical heat dissipation ball, but the present invention is not limited thereto. The heat dissipation member 45 may have a polyhedron shape such as a hexahedron, and may be mixed with the base material of the first heat dissipation layer 40 so as to transfer heat generated in the first conductive pattern 20 to the air without limitation in shape. It can be applied to the invention.
본 발명의 일 실시예에 따른 연성 회로 기판(1)에서, 제1 방열층(40)에 포함된 방열재(45)에 의하여, 제1 도전 패턴(20)으로부터 발생한 열이 외부로 방출되는 것을 촉진할 수 있다. 따라서 제1 방열층(40)에 의해 제1 도전 패턴(20) 상에 실장되는 회로 소자 및 전자 장치가 제1 도전 패턴(20)에서 발생한 열로부터 받는 열의 영향을 감소시키고, 연성 회로 기판(1)의 동작 신뢰성이 증가할 수 있다.In the flexible circuit board 1 according to an embodiment of the present invention, the heat generated from the first conductive pattern 20 is discharged to the outside by the heat radiating material 45 included in the first heat radiating layer 40. I can promote it. Therefore, the circuit element and the electronic device mounted on the first conductive pattern 20 by the first heat dissipation layer 40 reduce the influence of heat received from the heat generated in the first conductive pattern 20, and the flexible circuit board 1 Operating reliability) may be increased.
또한, 이와 같이 제1 방열층(40)을 제1 보호층(30) 상에 형성하는 것은, 별도의 메탈 테이프를 베이스 필름(10)의 이면에 형성하는 경우보다 생산 공정 및 생산 단가 측면에서 유리할 수 있다.In addition, forming the first heat dissipation layer 40 on the first protective layer 30 in this way may be advantageous in terms of production process and production cost rather than forming a separate metal tape on the back surface of the base film 10. Can be.
한편, 본 발명의 일 실시예에 따른 연성 회로 기판(1)에서, 제1 방열층(40)은 제1 보호층(30)으로 인해 제1 도전 패턴(20)과 이격될 수 있다. 뿐만 아니라, 제1 보호층(30)의 상면(35)의 높이는 제1 도전 패턴(25)의 최상면의 높이와 같거나 높게 형성되므로, 복수의 제1 도전 패턴(20)들 사이에 제1 방열층(40) 및 제1 방열층(40)에 포함된 방열재(45)가 위치하지 않는다.Meanwhile, in the flexible circuit board 1 according to the exemplary embodiment, the first heat dissipation layer 40 may be spaced apart from the first conductive pattern 20 due to the first protective layer 30. In addition, since the height of the upper surface 35 of the first protective layer 30 is equal to or higher than the height of the uppermost surface of the first conductive pattern 25, the first heat dissipation between the plurality of first conductive patterns 20. The heat dissipation member 45 included in the layer 40 and the first heat dissipation layer 40 is not located.
베이스 필름(10) 상의 제1 도전 패턴(20)들 사이에 방열재(45)가 함유된 제1 방열층(40)이 개재되는 경우, 방열재(45)와 습기 등이 반응하여 제1 도전 패턴(20)들 사이를 흐르도록 형성된 누설 전류로 인해 복수의 제1 도전 패턴(20) 사이의 절연 효과가 감소할 수 있다. 따라서 연성 회로 기판(1)의 동작 신뢰성 또한 저하될 수 있다.When the first heat dissipation layer 40 containing the heat dissipation member 45 is interposed between the first conductive patterns 20 on the base film 10, the heat dissipation member 45 reacts with moisture, and the like. Due to the leakage current formed to flow between the patterns 20, the insulation effect between the plurality of first conductive patterns 20 may be reduced. Therefore, the operation reliability of the flexible circuit board 1 can also be lowered.
그러나 본 발명의 일 실시예에 따른 연성 회로 기판(1)의 제1 방열층(40)은, 복수의 제1 도전 패턴(20)들 사이에 제1 방열층(40) 및 제1 방열층(40)에 포함된 방열재(45)가 위치하지 않으므로, 제1 방열층(40) 내의 방열재(45)가 수분과 반응하는 경우에도, 제1 도전 패턴(20) 사이에 누설 전류가 발생하는 것을 방지하고, 제1 도전 패턴(20)들 사이를 효과적으로 절연시킬 수 있다.However, the first heat dissipation layer 40 of the flexible circuit board 1 according to the exemplary embodiment of the present invention may include the first heat dissipation layer 40 and the first heat dissipation layer 40 between the plurality of first conductive patterns 20. Since the heat dissipation member 45 included in the 40 is not positioned, even when the heat dissipation member 45 in the first heat dissipation layer 40 reacts with moisture, a leakage current is generated between the first conductive patterns 20. Can be prevented and effectively insulated between the first conductive patterns 20.
도 3은 본 발명의 다른 실시예에 따른 연성 회로 기판의 단면도이다. 이하 앞서 설명한 실시예와 공통되는 부분의 설명은 생략하고 차이점을 위주로 설명하기로 한다.3 is a cross-sectional view of a flexible circuit board according to another embodiment of the present invention. Hereinafter, the description of the parts in common with the above-described embodiments will be omitted and the differences will be mainly described.
도 3을 참조하면, 본 발명의 다른 실시예에 따른 연성 회로 기판(2)은 앞서 설명한 실시예에서의 연성 회로 기판과 제1 보호층(130) 및 제1 방열층(140)의 형상이 다를 수 있다.Referring to FIG. 3, the flexible circuit board 2 according to another embodiment of the present invention differs in shape of the flexible circuit board and the first protective layer 130 and the first heat dissipation layer 140 in the above-described embodiment. Can be.
제1 보호층(130)의 상면(135)은 제1 도전 패턴(20)의 상면의 프로파일을 따라 형성될 수 있다. 즉, 제1 보호층(130)의 상면(135)은 제1 도전 패턴(20) 상의 제1 면(136)과, 제 1면(136) 사이의 제2 면(137)을 포함하고, 베이스 필름(10)으로부터 제1 면(136)의 높이는 제2 면(137)의 높이보다 높다.The upper surface 135 of the first protective layer 130 may be formed along the profile of the upper surface of the first conductive pattern 20. That is, the upper surface 135 of the first protective layer 130 includes a first surface 136 on the first conductive pattern 20 and a second surface 137 between the first surface 136, the base The height of the first face 136 from the film 10 is higher than the height of the second face 137.
한편, 제1 보호층(130)의 상면(135)은 제1 도전 패턴(20)의 상면의 프로파일을 따라 형성됨에도 불구하고, 여전히 제1 도전 패턴(20)의 최상면의 높이와 같거나 높을 수 있다. 즉, 제1 보호층(130)의 상면(135) 중 제1 면(136)의 높이보다 낮은 제2 면(137)의 레벨은 여전히 제1 도전 패턴(20)의 최상면의 레벨과 같거나 높게 형성되어, 제1 도전 패턴(20) 사이에 제1 방열층(140) 및 제1 방열층(40)에 포함된 방열재가 제1 도전 패턴(20) 사이에 위치하는 것을 방지할 수 있다. 따라서 변형된 제1 보호층(130)의 상면(135)의 형상에도 불구하고, 제1 보호층(130) 및 제1 방열층(140)으로 인한 제1 도전 패턴(20) 간의 절연 효과는 그대로 유지될 수 있다.Meanwhile, although the top surface 135 of the first passivation layer 130 is formed along the profile of the top surface of the first conductive pattern 20, it may still be equal to or higher than the height of the top surface of the first conductive pattern 20. have. That is, the level of the second surface 137 that is lower than the height of the first surface 136 of the upper surface 135 of the first protective layer 130 is still equal to or higher than the level of the uppermost surface of the first conductive pattern 20. The heat dissipation material included in the first heat dissipation layer 140 and the first heat dissipation layer 40 may be prevented from being disposed between the first conductive patterns 20. Therefore, despite the shape of the upper surface 135 of the deformed first passivation layer 130, the insulation effect between the first passivation layer 130 and the first conductive pattern 20 due to the first heat dissipation layer 140 remains the same. Can be maintained.
제1 보호층(130)이 제1 도전 패턴(20)의 상면의 프로파일을 따라 형성됨에 따라, 제1 보호층(130)을 덮는 제1 방열층(140)의 형상 또한 제1 보호층(130)의 프로파일을 따라 형성될 수 있다. 따라서 제1 방열층(140)의 상면은 제1 도전 패턴(20) 상의 제1 면(141)과, 제1 면 사이의 제2 면(142)를 포함할 수 있고, 제1 면(141)의 높이는 제2 면(142)의 높이보다 높을 수 있다.As the first passivation layer 130 is formed along the profile of the top surface of the first conductive pattern 20, the shape of the first heat dissipation layer 140 covering the first passivation layer 130 is also defined by the first passivation layer 130. It can be formed along the profile of). Accordingly, the upper surface of the first heat dissipation layer 140 may include a first surface 141 on the first conductive pattern 20 and a second surface 142 between the first surface, and the first surface 141. The height of may be higher than the height of the second surface 142.
한편, 전술한 실시예의 경우와 같이 제1 방열층(140)의 하면의 높이는 제1 도전 패턴(20)의 최상면의 높이와 같거나 높을 수 있다.Meanwhile, as in the case of the above-described embodiment, the height of the bottom surface of the first heat dissipation layer 140 may be equal to or higher than the height of the top surface of the first conductive pattern 20.
본 실시예에 따른 연성 회로 기판(2)은, 제1 보호층(130)이 제1 도전 패턴(20)의 표면의 프로파일을 다라 형성되므로, 굴곡진 제1 보호층(130)의 상면(135)의 형상으로 인해 제1 보호층(130)의 상면(135)의 표면적이 증가할 수 있다. 또한, 증가한 제1 보호층(130)의 상면(135)의 표면적으로 인해 제1 보호층(130)과 제1 방열층(140) 간의 접촉 면적도 그만큼 증가할 수 있다. 따라서, 제1 보호층(130)을 통해 제1 방열층(140)으로 전달되는 제1 도전 패턴(20)의 열 전달 효율이 증가할 수 있다.In the flexible circuit board 2 according to the present exemplary embodiment, since the first protective layer 130 is formed along the profile of the surface of the first conductive pattern 20, the upper surface 135 of the curved first protective layer 130 is formed. ), The surface area of the top surface 135 of the first protective layer 130 may increase. In addition, the contact area between the first passivation layer 130 and the first heat dissipation layer 140 may also increase due to the increased surface area of the upper surface 135 of the first passivation layer 130. Therefore, the heat transfer efficiency of the first conductive pattern 20 transferred to the first heat dissipation layer 140 through the first protective layer 130 may increase.
한편, 제1 보호층(130)이 제1 도전 패턴(20)의 프로파일을 따라 형성되는 경우, 제1 보호층(130)을 형성한 후, 제1 보호층(130)의 상면을 평탄화시키는 공정이 수행되지 않을 수 있다.Meanwhile, when the first passivation layer 130 is formed along the profile of the first conductive pattern 20, after forming the first passivation layer 130, planarizing the top surface of the first passivation layer 130. This may not be done.
도 4는 본 발명의 또 다른 실시예에 따른 연성 회로 기판의 단면도이다.4 is a cross-sectional view of a flexible circuit board according to another embodiment of the present invention.
도 4를 참조하면, 본 발명의 또 다른 실시예에 따른 연성 회로 기판(3)은 베이스 필름(10)의 제1 도전 패턴(20)과 반대면에 형성된 제2 도전 패턴(120), 제2 보호층(230) 및 제2 방열층(240) 및 베이스 필름(10)을 관통하는 비아(51)를 더 포함할 수 있다.Referring to FIG. 4, the flexible circuit board 3 according to another exemplary embodiment may include a second conductive pattern 120 and a second conductive pattern 120 formed on a surface opposite to the first conductive pattern 20 of the base film 10. The via layer 51 may further include a via 51 penetrating the protective layer 230, the second heat dissipating layer 240, and the base film 10.
제2 도전 패턴(120)은 베이스 필름(10)의 제1 도전 패턴(20)이 형성된 일면의 반대면에 형성될 수 있다. 제2 도전 패턴(120)은 제1 도전 패턴(20)과 마찬가지로 일정한 폭을 가진 띠 형상인 도선을 적어도 하나 이상 포함할 수 있다. The second conductive pattern 120 may be formed on an opposite surface of one surface on which the first conductive pattern 20 of the base film 10 is formed. Like the first conductive pattern 20, the second conductive pattern 120 may include at least one or more conductive wires having a predetermined width.
제2 도전 패턴(120)은 제1 도전 패턴(20)과 기판을 관통하는 비아(51)를 통해 전기적으로 연결될 수 있다. 비아(51)는 베이스 필름(10)을 관통하여 형성된 비아홀(50)을 채울 수 있다. 비아(51)는 제1 및 제2 도전 패턴(120)과 마찬가지로 구리, 금 등의 도전성 물질 또는 이들의 합금을 포함할 수 있다. 도 4에 도시되지는 않았지만 비아홀(50)의 내측벽과 비아(51) 사이에는 하나 이상의 추가적인 금속층을 포함할 수도 있다.The second conductive pattern 120 may be electrically connected to the first conductive pattern 20 through the via 51 penetrating the substrate. The via 51 may fill the via hole 50 formed through the base film 10. Like the first and second conductive patterns 120, the via 51 may include a conductive material such as copper or gold, or an alloy thereof. Although not shown in FIG. 4, one or more additional metal layers may be included between the inner wall of the via hole 50 and the via 51.
도 4는 제1 도전 패턴(20)과 제2 도전 패턴(120)이 베이스 필름(10)을 중심으로 대응되는 위치에 형성된 것으로 도시되었으나 본 발명이 이에 제한되지는 않는다. 연성 회로 기판(1)의 설계 및 이에 실장되는 회로 소자의 배치에 따라 제1 및 제2 도전 패턴(20)의 배치는 이와 달라질 수 있음은 본 발명이 속하는 기술 분야의 통상의 기술자에게 자명할 것이다.4 illustrates that the first conductive pattern 20 and the second conductive pattern 120 are formed at positions corresponding to the base film 10, but the present invention is not limited thereto. It will be apparent to those skilled in the art that the arrangement of the first and second conductive patterns 20 may vary according to the design of the flexible circuit board 1 and the arrangement of the circuit elements mounted thereon. .
제2 도전 패턴(120)을 덮도록, 제2 보호층(230)이 형성될 수 있다. 제2 보호층(230)은 제1 보호층(30)과 마찬가지로, 제2 도전 패턴(120)을 완전히 덮도록 형성될 수 있다. 따라서, 베이스 필름(10)의 타면으로부터 제2 보호층(230)의 상면의 높이는, 제2 도전 패턴(120)의 최상면의 높이와 같거나 높을 수 있다.The second protective layer 230 may be formed to cover the second conductive pattern 120. Like the first passivation layer 30, the second passivation layer 230 may be formed to completely cover the second conductive pattern 120. Therefore, the height of the upper surface of the second protective layer 230 from the other surface of the base film 10 may be equal to or higher than the height of the uppermost surface of the second conductive pattern 120.
제2 보호층(230) 상에 제2 방열층(240)이 형성될 수 있다. 제2 방열층(240)은 절연 물질인 베이스 물질과, 베이스 물질 내에 함유된 방열재를 포함할 수 있다. 제1 방열층(40)과 제2 방열층(240)은 동일한 물질을 포함할 수 있다. 즉, 제1 방열층(40)과 제2 방열층(240)을 구성하는 베이스 물질과 방열층은 서로 동일한 물질을 포함할 수 있다.The second heat dissipation layer 240 may be formed on the second protective layer 230. The second heat dissipation layer 240 may include a base material which is an insulating material and a heat dissipation material contained in the base material. The first heat dissipation layer 40 and the second heat dissipation layer 240 may include the same material. That is, the base material and the heat dissipation layer constituting the first heat dissipation layer 40 and the second heat dissipation layer 240 may include the same material.
도 4에 도시된 것과 같이, 제2 방열층(240)은 제2 보호층(230)을 완전히 덮도록 형성될 수 있으며, 이와는 달리 제2 방열층(240)은 제2 도전 패턴(120)이 형성된 영역 상의 제2 보호층(230)의 상면 만을 덮도록 형성될 수도 있다.As shown in FIG. 4, the second heat dissipation layer 240 may be formed to completely cover the second protective layer 230. In contrast, the second heat dissipation layer 240 may include the second conductive pattern 120. It may be formed to cover only the upper surface of the second protective layer 230 on the formed region.
제2 보호층(230)의 상면이 제2 도전 패턴(120)의 상면의 레벨과 같거나 높도록 형성됨에 따라, 제2 방열층(240)이 제2 도전 패턴(120) 사이에 개재되지 않는 것은 제1 방열층(40)과 관련된 설명과 같다. 따라서 이러한 제2 방열층(240)의 형상은 제2 도전 패턴(120)에서 발생한 열을 공기 중으로 방출시키는 것을 도움과 동시에, 제2 도전 패턴(120)과 방열재 간에 누설 전류가 발생하여 연성 회로 기판(3)의 동작 신뢰성을 감소시키는 것을 방지할 수 있다.As the upper surface of the second protective layer 230 is formed to be equal to or higher than the level of the upper surface of the second conductive pattern 120, the second heat dissipation layer 240 is not interposed between the second conductive patterns 120. This is the same as the description associated with the first heat dissipation layer 40. Therefore, the shape of the second heat dissipation layer 240 helps to release heat generated in the second conductive pattern 120 into the air, and at the same time, a leakage current is generated between the second conductive pattern 120 and the heat dissipating material, thereby providing a flexible circuit. It is possible to prevent reducing the operating reliability of the substrate 3.
도 5는 본 발명의 일 실시예에 따른 연성 회로 기판의 제조 방법을 설명하기 위한 순서도이다.5 is a flowchart illustrating a method of manufacturing a flexible circuit board according to an embodiment of the present invention.
도 5와 도 1을 참조하면, 본 발명의 일 실시예에 따른 연성 회로 기판의 제조 방법은, 적어도 일면 상에 복수의 도전 패턴이 형성된 베이스 필름을 제공하고(S10), 상기 복수의 도전 패턴을 덮도록 제1 보호층을 형성하고(S20), 제1 보호층 상에 내부에 방열재가 형성된 방열층을 형성한다(S30).5 and 1, a method of manufacturing a flexible circuit board according to an embodiment of the present disclosure provides a base film having a plurality of conductive patterns formed on at least one surface thereof (S10), and forming the plurality of conductive patterns. A first protective layer is formed to cover (S20), and a heat radiation layer having a heat dissipating material formed therein is formed on the first protective layer (S30).
제1 도전 패턴(20)은 예를 들어, 베이스 필름(10) 상에 레지스트를 형성하고, 전해 또는 비전해 방식으로 도금을 수행하는 세미 애디티브(semi additive) 공정으로 형성될 수 있으며, 베이스 필름(10) 상에 도전층을 형성하고, 상기 도전층을 식각하는 에칭(etching) 공정으로도 형성될 수 있다.The first conductive pattern 20 may be formed by, for example, a semi additive process of forming a resist on the base film 10 and performing plating in an electrolytic or non-electrolytic manner. A conductive layer may be formed on the layer 10 and may be formed by an etching process of etching the conductive layer.
복수의 제1 도전 패턴(20)을 덮도록, 제1 보호층(30)을 형성하는 것은, 솔더 레지스트 또는 커버레이 필름을 제1 도전 패턴(20) 상에 인쇄 또는 라미네이팅으로 형성하는 것을 포함할 수 있다. 제1 보호층(30)은, 제1 보호층(30)의 상면의 레벨이 제1 도전 패턴(20)의 최상면의 레벨보다 높아질 수 있도록 충분히 형성될 필요가 있다.Forming the first protective layer 30 to cover the plurality of first conductive patterns 20 may include forming a solder resist or coverlay film on the first conductive pattern 20 by printing or laminating. Can be. The first protective layer 30 needs to be sufficiently formed so that the level of the upper surface of the first protective layer 30 can be higher than the level of the uppermost surface of the first conductive pattern 20.
여기서, 제1 보호층(30)의 상면의 레벨을 실질적으로 평탄하게 유지하기 위해 제1 보호층(30)을 형성한 후 상면을 평탄화하는 공정이 추가될 수 있다. 제1 보호층(30)의 상면을 평탄화하는 것은 예를 들어, 제1 보호층(30)의 상면을 프레스로 가압하는 것을 포함할 수 있다.Here, in order to maintain the level of the upper surface of the first protective layer 30 substantially flat, a process of forming the first protective layer 30 and then flattening the upper surface may be added. Flattening the upper surface of the first protective layer 30 may include, for example, pressing the upper surface of the first protective layer 30 with a press.
제1 보호층(30)을 덮도록, 제1 방열층(40)을 형성하는 것은, 방열재(45)가 포함된 솔더 레지스트 또는 커버레이 필름을 제1 보호층(30) 상에 인쇄 또는 라미네이팅으로 형성하는 것을 포함할 수 있다.Forming the first heat dissipation layer 40 to cover the first passivation layer 30 may include printing or laminating a solder resist or coverlay film including the heat dissipation material 45 on the first passivation layer 30. It may include forming into.
이상 첨부된 도면을 참조하여 본 발명의 실시예들을 설명하였으나, 본 발명은 상기 실시예들에 한정되는 것이 아니라 서로 다른 다양한 형태로 제조될 수 있으며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자는 본 발명의 기술적 사상이나 필수적인 특징을 변경하지 않고서 다른 구체적인 형태로 실시될 수 있다는 것을 이해할 수 있을 것이다. 그러므로 이상에서 기술한 실시예들은 모든 면에서 예시적인 것이며 한정적이 아닌 것으로 이해해야만 한다.Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments but may be manufactured in various forms, and having ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

Claims (12)

  1. 베이스 필름;Base film;
    상기 베이스 필름의 일면 상에 형성된 복수의 제1 도전 패턴;A plurality of first conductive patterns formed on one surface of the base film;
    상기 복수의 제1 도전 패턴을 덮도록 형성된 제1 보호층; 및A first protective layer formed to cover the plurality of first conductive patterns; And
    상기 제1 보호층을 덮는 방열층으로, 상기 방열층은 베이스 물질 및 상기 베이스 물질에 포함된 방열재를 포함하는 제1 방열층을 포함하는 연성 회로 기판.A heat dissipation layer covering the first protective layer, wherein the heat dissipation layer includes a first heat dissipation layer including a base material and a heat dissipation material included in the base material.
  2. 제 1항에 있어서,The method of claim 1,
    상기 베이스 필름으로부터 상기 제1 보호층의 최상면의 높이는, 상기 베이스 필름으로부터 상기 복수의 제1 도전 패턴의 최상면의 높이와 같거나 높은 연성 회로 기판.And a height of a top surface of the first protective layer from the base film is equal to or higher than a height of a top surface of the plurality of first conductive patterns from the base film.
  3. 제 1항에 있어서, The method of claim 1,
    상기 제1 방열층의 상면은 실질적으로 평탄한 연성 회로 기판.And a top surface of the first heat dissipation layer is substantially flat.
  4. 제 1항에 있어서,The method of claim 1,
    상기 제1 보호층과 상기 제1 방열층의 두께의 비는, 2:8 내지 8:2인 연성 회로 기판.The ratio of the thickness of a said 1st protective layer and a said 1st heat radiation layer is a flexible circuit board of 2: 8-8: 2.
  5. 제 1항에 있어서,The method of claim 1,
    상기 제1 보호층의 두께는 1㎛ 내지 30㎛이고,The thickness of the first protective layer is 1 ㎛ to 30 ㎛,
    상기 제1 방열층의 두께는 1㎛ 내지 30㎛이고,The thickness of the first heat dissipation layer is 1 ㎛ to 30 ㎛,
    상기 제1 보호층 및 제1 방열층의 두께의 합이 2㎛ 내지 60㎛인 연성 회로 기판.The sum of the thicknesses of the first protective layer and the first heat dissipation layer is 2 μm to 60 μm.
  6. 제 1항에 있어서,The method of claim 1,
    상기 베이스 물질은 상기 제1 보호층을 구성하는 물질과 동일한 물질을 포함하는 연성 회로 기판.And the base material includes the same material as the material constituting the first protective layer.
  7. 제 1항에 있어서,The method of claim 1,
    상기 베이스 필름의 상기 일면과 대향되는 타면에 형성된 복수의 제2 도전 패턴;A plurality of second conductive patterns formed on the other surface opposite to the one surface of the base film;
    상기 복수의 제2 도전 패턴을 덮도록 형성된 제2 보호층; 및A second protective layer formed to cover the plurality of second conductive patterns; And
    상기 제2 보호층을 덮고, 내부에 방열재를 포함하는 제2 방열층을 더 포함하는 연성 회로 기판.And a second heat dissipation layer covering the second protective layer and including a heat dissipation material therein.
  8. 제 1항에 있어서,The method of claim 1,
    상기 제1 보호층은 상기 복수의 제1 도전 패턴의 프로파일을 따라 형성되고,The first protective layer is formed along the profile of the plurality of first conductive patterns,
    상기 제1 보호층의 상면은 상기 제1 도전 패턴 상의 제1 면과, 상기 제1 면 사이의 제2 면을 포함하고,An upper surface of the first protective layer includes a first surface on the first conductive pattern and a second surface between the first surface,
    상기 베이스 필름으로부터 상기 제1 면의 높이는 상기 베이스 필름으로부터 상기 제2 면의 높이보다 높은 연성 회로 기판.The height of the first surface from the base film is higher than the height of the second surface from the base film.
  9. 제 8항에 있어서,The method of claim 8,
    상기 제1 방열층은 상기 제1 보호층의 상면의 프로파일을 따라 형성되는 연성 회로 기판.The first heat dissipation layer is formed along the profile of the upper surface of the first protective layer.
  10. 제 1항에 있어서,The method of claim 1,
    상기 제1 도전 패턴과 상기 제1 보호층 사이에 개재되는 도금층을 더 포함하는 연성 회로 기판.The flexible circuit board further comprises a plating layer interposed between the first conductive pattern and the first protective layer.
  11. 적어도 일면 상에 복수의 도전 패턴이 형성된 베이스 필름을 제공하고,Providing a base film having a plurality of conductive patterns formed on at least one surface thereof,
    복수의 도전 패턴을 덮도록 보호층을 형성하고,A protective layer is formed to cover the plurality of conductive patterns,
    상기 보호층 상에, 내부에 혼합된 방열재를 포함하는 방열층을 형성하는 것을 포함하되,On the protective layer, including forming a heat dissipation layer including a heat dissipating material mixed therein,
    상기 베이스 필름으로부터 상기 보호층의 높이는, 상기 베이스 필름으로부터 상기 복수의 도전 패턴의 최상면의 높이보다 높은 연성 회로 기판의 제조 방법.The height of the said protective layer from the said base film is a manufacturing method of the flexible circuit board higher than the height of the uppermost surface of the said some conductive pattern from the said base film.
  12. 제 11항에 있어서,The method of claim 11,
    상기 방열층을 형성하는 것은, 상기 베이스 필름으로부터 상기 방열층의 높이가 상기 도전 패턴의 최상면보다 높게 형성하는 것을 포함하는 연성 회로 기판의 제조 방법.Forming the heat dissipation layer includes forming a height of the heat dissipation layer higher than the uppermost surface of the conductive pattern from the base film.
PCT/KR2017/007669 2016-07-20 2017-07-17 Flexible circuit board and manufacturing method therefor WO2018016829A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114333592A (en) * 2021-12-31 2022-04-12 湖北长江新型显示产业创新中心有限公司 Display device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110972386A (en) * 2018-09-28 2020-04-07 深圳正峰印刷有限公司 Circuit board suitable for printed electronic component
KR102335624B1 (en) * 2020-05-20 2021-12-07 주식회사 코닉에스티 Stiffener and camera module having the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110117928A (en) * 2010-04-22 2011-10-28 이성규 Cover film for circuit board and circuit board assembly having the same
KR101211732B1 (en) * 2006-09-30 2012-12-12 엘지이노텍 주식회사 Flexible Printed Circuit Board with excellent radiant heat property
KR101292643B1 (en) * 2011-10-26 2013-08-02 성균관대학교산학협력단 Electromagnetic noise suppressing film comprising graphene and electronic device comprising the same
JP2014207315A (en) * 2013-04-12 2014-10-30 船井電機株式会社 Flexible substrate and display apparatus
KR101547500B1 (en) * 2014-12-15 2015-08-26 스템코 주식회사 Flexible printed circuit boards and electronic device comprising the same and method for manufacturing the flexible printed circuit boards

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05327192A (en) * 1992-05-15 1993-12-10 Cmk Corp Manufacture of flexible printed circuit board
EP0891127A3 (en) * 1997-07-11 2000-03-22 Lexmark International, Inc. TAB circuit protective coating
JP2003338579A (en) * 2002-05-22 2003-11-28 Kyocera Corp Wiring board with radiator plate
JP2004211060A (en) * 2002-12-16 2004-07-29 Ceramission Kk Emulsion composition, coating film formed therefrom and cooling structure using the coating film
TWI355214B (en) * 2004-09-27 2011-12-21 Canon Kk Method of producing light emitting device
CN101684181B (en) * 2008-09-26 2011-12-14 比亚迪股份有限公司 Photosensitive polyimide and flexible printed circuit board thereof
JP2011199090A (en) * 2010-03-23 2011-10-06 Shindo Denshi Kogyo Kk Method of manufacturing flexible printed wiring board, method of manufacturing semiconductor device, method of manufacturing display device, flexible printed wiring board, semiconductor device, and display device
CN104823276A (en) * 2013-11-21 2015-08-05 东部Hitek株式会社 Cof-type semiconductor package and method of manufacturing same
JP6623513B2 (en) * 2013-12-03 2019-12-25 東洋インキScホールディングス株式会社 Electronic elements and sheet materials

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101211732B1 (en) * 2006-09-30 2012-12-12 엘지이노텍 주식회사 Flexible Printed Circuit Board with excellent radiant heat property
KR20110117928A (en) * 2010-04-22 2011-10-28 이성규 Cover film for circuit board and circuit board assembly having the same
KR101292643B1 (en) * 2011-10-26 2013-08-02 성균관대학교산학협력단 Electromagnetic noise suppressing film comprising graphene and electronic device comprising the same
JP2014207315A (en) * 2013-04-12 2014-10-30 船井電機株式会社 Flexible substrate and display apparatus
KR101547500B1 (en) * 2014-12-15 2015-08-26 스템코 주식회사 Flexible printed circuit boards and electronic device comprising the same and method for manufacturing the flexible printed circuit boards

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114333592A (en) * 2021-12-31 2022-04-12 湖北长江新型显示产业创新中心有限公司 Display device
CN114333592B (en) * 2021-12-31 2023-08-25 湖北长江新型显示产业创新中心有限公司 display device

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