WO2012133990A1 - Method for manufacturing high heat-dissipation circuit board appropriate for mounting light emitting diode - Google Patents
Method for manufacturing high heat-dissipation circuit board appropriate for mounting light emitting diode Download PDFInfo
- Publication number
- WO2012133990A1 WO2012133990A1 PCT/KR2011/005016 KR2011005016W WO2012133990A1 WO 2012133990 A1 WO2012133990 A1 WO 2012133990A1 KR 2011005016 W KR2011005016 W KR 2011005016W WO 2012133990 A1 WO2012133990 A1 WO 2012133990A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- base
- substrate
- pad
- circuit board
- Prior art date
Links
- 230000017525 heat dissipation Effects 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000010410 layers Substances 0.000 claims abstract description 159
- 239000000758 substrates Substances 0.000 claims abstract description 74
- 239000000126 substances Substances 0.000 claims abstract description 19
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 229910052751 metals Inorganic materials 0.000 claims description 40
- 239000002184 metals Substances 0.000 claims description 40
- 238000007747 plating Methods 0.000 claims description 37
- 239000010950 nickel Substances 0.000 claims description 28
- 238000009713 electroplating Methods 0.000 claims description 18
- 239000010931 gold Substances 0.000 claims description 18
- 239000010944 silver (metal) Substances 0.000 claims description 18
- 229910052782 aluminium Inorganic materials 0.000 claims description 16
- 229910052802 copper Inorganic materials 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 15
- 239000004593 Epoxy Substances 0.000 claims description 13
- 239000011248 coating agents Substances 0.000 claims description 13
- 238000000576 coating method Methods 0.000 claims description 13
- 125000003700 epoxy group Chemical group 0.000 claims description 13
- 229910052737 gold Inorganic materials 0.000 claims description 13
- 239000007788 liquids Substances 0.000 claims description 12
- 229910052759 nickel Inorganic materials 0.000 claims description 12
- 239000002952 polymeric resin Substances 0.000 claims description 12
- 229910052709 silver Inorganic materials 0.000 claims description 12
- 239000011135 tin Substances 0.000 claims description 12
- 229910052718 tin Inorganic materials 0.000 claims description 12
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol Chemical compound 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OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 claims description 10
- 229920000728 polyesters Polymers 0.000 claims description 10
- 239000000919 ceramics Substances 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound 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[Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000004020 conductors Substances 0.000 claims description 8
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group 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C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 claims description 7
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N al2o3 Chemical compound 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[O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 6
- 239000004033 plastics Substances 0.000 claims description 6
- 229920003023 plastics Polymers 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminum Chemical compound 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[Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 239000000203 mixtures Substances 0.000 claims description 4
- 239000011347 resins Substances 0.000 claims description 4
- 229920005989 resins Polymers 0.000 claims description 4
- 229910017083 AlN Inorganic materials 0.000 claims description 3
- -1 C(=O)(C=C)* Chemical group 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C(=O)(C=C)* 0.000 claims description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N aluminum nitride Chemical compound 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[Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 3
- 229910003726 AI2O3 Inorganic materials 0.000 claims 1
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052593 corundum Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 239000007791 liquid phases Substances 0.000 claims 1
- 229910052904 quartz Inorganic materials 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicium dioxide Chemical compound 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Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/053—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an inorganic insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
- H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10106—Light emitting diode [LED]
Abstract
Description
본 발명은 LED 실장에 적합한 고방열성 회로기판 제조방법에 관한 것으로서, 특히 얇고 유연한 것부터 두껍고 견고한 여러가지 형태의 베이스기판에 회로를 구성하여 방열효율이 더 향상될 뿐만 아니라 제조비용이 적게 들어 종래에 비하여 고출력 LED의 실장에 더 적합한 고방열성 회로기판 제조방법을 제공하는 데 있다. The present invention relates to a method for manufacturing a high heat dissipation circuit board suitable for LED mounting, in particular, by configuring a circuit in various types of base boards from thin and flexible to thick and rigid, not only improves heat dissipation efficiency, but also reduces manufacturing cost, resulting in high output. It is to provide a high heat dissipation circuit board manufacturing method more suitable for the mounting of the LED.
LED 소자는 얼마 전까지만 해도 주로 표시용(display)으로 사용되어 고방열(高放熱)이 필요하지 않았기 때문에 LED를 탑재하는 회로기판으로 수지계 기판이 사용되어 왔다. 그러나 최근 들어 조명분야에의 응용이 두드러지면서 고출력 LED를 실장한 제품에 대한 방열대책이 부각되고 있으며, 열로 인한 LED 광효율 및 수명의 저하가 커다란 과제로 떠오르고 있다. 특히 LED 모듈이 소형화되고 출력은 높아지는 추세에 있기 때문에 그에 따른 열은 더욱 많이 발생될 수 밖에 없으므로 이러한 방열대책이 매우 절실히 요구되고 있다. Since LED devices have been used mainly for displays until recently, high heat dissipation was not required, resin-based substrates have been used as circuit boards on which LEDs are mounted. However, in recent years, as the application in the lighting field is prominent, heat dissipation measures for products equipped with high-power LEDs have been highlighted, and deterioration of LED light efficiency and lifetime due to heat has emerged as a big problem. In particular, since LED modules are becoming smaller and have a higher output, heat generation is inevitably generated. Therefore, such heat dissipation measures are urgently required.
도 1은 LED용 회로기판을 설명하기 위한 도면이다. 도 1에 도시된 바와 같이, LED 칩(20)에서 발생한 열은 LED 패키지(30) 및 회로기판(10)을 통해서 공기 중으로 방열된다. 예전에는 LED 출력이 작기 때문에 LED 소자를 탑재한 회로기판(10)으로는 글라스 에폭시 기판(FR-4) 등과 같은 수지계 기판이 사용되어 왔다. 그러나 조명용도로 사용되는 고출력 LED의 경우 발광효율이 20-30%로 낮고 또한 칩 사이즈가 작기 때문에 전체적인 소비전력이 낮음에도 불구하고 단위면적당 발열량이 매우 크다.1 is a view for explaining a circuit board for the LED. As shown in FIG. 1, heat generated in the LED chip 20 is radiated to the air through the LED package 30 and the circuit board 10. In the past, since the LED output was small, a resin substrate such as a glass epoxy substrate (FR-4) or the like was used as the circuit board 10 having the LED element. However, high output LEDs used for lighting use have a low luminous efficiency of 20-30% and a small chip size, so that the amount of heat generated per unit area is very high despite the low overall power consumption.
따라서 고출력 LED용 회로기판의 고방열성이 불가피하게 되었고, 수지 기판 대신에 금속 베이스 기판 및 세라믹 기판 등이 사용되었다. 회로기판의 방열성은 LED의 성능 및 수명에 큰 영향을 미치기 때문에 고출력의 LED 제품을 설계함에 있어 회로기판은 매우 중요한 요소로 작용한다. Therefore, high heat dissipation of the high output LED circuit board is inevitable, and a metal base substrate and a ceramic substrate are used instead of the resin substrate. Since the heat dissipation of the circuit board has a great influence on the performance and life of the LED, the circuit board is an important factor in designing a high output LED product.
도 2는 종래의 중출력 LED용 방열회로기판(100)을 설명하기 위한 도면이다. 도 2를 참조하면, 종래의 방열회로기판(100)은 구리 또는 알루미늄으로 이루어진 금속기판(110)에 에폭시와 세라믹 등이 혼합되어 이루어진 절연층(120)과 구리 등으로 이루어진 금속배선층(131)이 순차적으로 적층된 구조를 갖는다. 방열회로기판(100) 상에는 일반적인 LED 패키지(30)나 COB형 LED 패키지(31)가 탑재되며, 그 내부의 LED(20)는 금속배선층(131)에 전기적으로 연결된다.2 is a view illustrating a conventional heat dissipation circuit board 100 for a medium output LED. Referring to FIG. 2, the conventional heat dissipation circuit board 100 includes an insulating layer 120 made of a mixture of epoxy and ceramic and a metal wiring layer 131 made of copper or the like on a metal substrate 110 made of copper or aluminum. It has a structure laminated sequentially. A general LED package 30 or a COB type LED package 31 is mounted on the heat dissipation circuit board 100, and the LED 20 therein is electrically connected to the metal wiring layer 131.
도 3은 도 2의 방열회로기판(100)을 제조하는 과정을 설명하기 위한 도면이다. 도 3에 도시된 바와 같이, 이러한 종래의 방열회로기판(100)은 금속기판(110) 상에 절연층(120)과 금속층(130)을 순차적으로 적층한 후 이를 열합착(hot press)하고 금속층(130)을 패터닝함으로써 얻어진다. 3 is a view for explaining a process of manufacturing the heat radiation circuit board 100 of FIG. As shown in FIG. 3, the conventional heat dissipation circuit board 100 sequentially laminates the insulating layer 120 and the metal layer 130 on the metal substrate 110, and then hot-bonds the metal layer 110. It is obtained by patterning 130.
그러나, 상술한 종래의 방열회로기판(100)은 열합착 공정을 거쳐서 제조되기 때문에 열팽창 및 열수축에 의하여 금속기판(110)이 휠 수 있기 때문에 금속기판(110)을 얇게 할 수 없어 방열회로기판(100)에 유연성(flexibility)을 부여하기에 한계가 있을 뿐만 아니라 절연층(120)이 에폭시와 세라믹 등이 혼합되어 이루어져 있기 때문에 고출력 LED 제품의 적용에는 방열성의 한계를 가지고 있다. 따라서 다양하고 창의적인 LED 조명의 구현이 어렵다. However, since the above-described conventional heat dissipation circuit board 100 is manufactured through a thermal bonding process, the metal substrate 110 may be bent due to thermal expansion and thermal contraction, and thus the metal substrate 110 may not be thinned. In addition to providing flexibility to 100, the insulating layer 120 is made of a mixture of epoxy and ceramic, and thus has a heat dissipation limit in the application of a high power LED product. Therefore, it is difficult to implement a variety of creative LED lighting.
따라서 본 발명이 해결하려는 과제는, 열합착 방법이 아닌 다른 방법을 사용함으로써 얇고 유연한 것부터 두껍고 견고한 여러가지 형태의 베이스기판에 회로를 구성하여 방열효율이 더 향상될 뿐만 아니라 제조비용이 적게 들어 종래에 비하여 고출력 LED의 실장에 더 적합한 고방열성 회로기판 제조방법을 제공하는 데 있다. Therefore, the problem to be solved by the present invention, by using a method other than the thermal bonding method by configuring a circuit in various types of base boards from thin and flexible to thick and rigid, not only improves the heat dissipation efficiency but also the manufacturing cost is low compared to the conventional The present invention provides a method of manufacturing a high heat dissipation circuit board that is more suitable for mounting high power LEDs.
상기 과제를 달성하기 위한 본 발명에 따른 고방열성 회로기판 제조방법은,The high heat dissipation circuit board manufacturing method according to the present invention for achieving the above object,
베이스 기판 상에 상기 베이스 기판의 소정영역을 노출시키도록 비도전성의 회로 베이스층을 형성하는 단계;Forming a non-conductive circuit base layer on the base substrate to expose a predetermined region of the base substrate;
상기 회로 베이스층에 의해 노출되는 베이스 기판 상에 도전성의 패드 베이스층을 채우는 단계; Filling a conductive pad base layer on the base substrate exposed by the circuit base layer;
상기 회로 베이스층과 패드 베이스층 상에 화학도금층을 형성한 후에 상기 화학도금층 상에 전기도금층을 형성하여 화학도금층과 전기도금층이 순차적으로 적층되는 도금층을 형성하는 단계; After forming a chemical plating layer on the circuit base layer and the pad base layer, forming an electroplating layer on the chemical plating layer to form a plating layer in which the chemical plating layer and the electroplating layer are sequentially stacked;
상기 도금층 상에 도전성의 본딩 패드층을 형성하는 단계; 및 Forming a conductive bonding pad layer on the plating layer; And
상기 회로 베이스층이 노출되도록 상기 도금층과 상기 본딩 패드층을 패터닝하여 상기 패드 베이스층 상부를 포함하는 소정영역에 도금층 패턴과 본딩패드가 순차적으로 적층된 구조를 형성하는 단계; 를 포함하여 이루어지는 것을 특징으로 한다. Patterning the plating layer and the bonding pad layer to expose the circuit base layer to form a structure in which a plating layer pattern and a bonding pad are sequentially stacked on a predetermined region including an upper portion of the pad base layer; Characterized in that comprises a.
상기 베이스 기판으로는, 윗면에 절연층이 형성된 금속기판, 표면에 산화알루미늄층이 형성된 알루미늄 기판, 또는 열도전성의 세라믹이 함유된 절연성 방열 플라스틱 기판을 사용할 수 있다. The base substrate may be a metal substrate having an insulating layer formed thereon, an aluminum substrate having an aluminum oxide layer formed thereon, or an insulating heat-dissipating plastic substrate containing a thermally conductive ceramic.
상기 베이스 기판으로서 상기 금속기판을 사용하는 경우에는, 상기 절연층이 상기 금속기판의 소정영역을 노출시키도록 형성되며, 상기 회로 베이스층은 상기 금속기판이 노출되도록 상기 절연층 상에 형성되며, 상기 패드 베이스층은 상기 절연층 및 회로 베이스층에 의해 노출되는 금속기판 상에 채워지도록 형성될 수 있다. 이 때 상기 패드 베이스층은 Au, Ag, Al, Cu, Sn 또는 Ni 을 포함하여 이루어지는 금속을 전기도금시킴으로써 형성될 수 있다. In the case where the metal substrate is used as the base substrate, the insulating layer is formed to expose a predetermined region of the metal substrate, and the circuit base layer is formed on the insulating layer to expose the metal substrate. The pad base layer may be formed to be filled on the metal substrate exposed by the insulating layer and the circuit base layer. In this case, the pad base layer may be formed by electroplating a metal including Au, Ag, Al, Cu, Sn, or Ni.
상기 절연층은 실리콘, 에폭시, 페놀, 아크릴, 또는 폴리에스테르를 포함하여 이루어지는 고분자 수지의 액상도료, 또는 여기에 Al2O3, AlN, BN, Si, 또는 SiO2 를 포함하여 이루어지는 세라믹이 혼합된 액상도료를 인쇄방식으로 상기 금속기판 상에 코팅하여 경화시킴으로써 형성될 수 있다. The insulating layer is a liquid coating of a polymer resin containing silicon, epoxy, phenol, acrylic, or polyester, or a liquid coating mixed with a ceramic containing Al 2 O 3, AlN, BN, Si, or SiO 2 is printed thereon. It can be formed by coating and curing on the metal substrate in a manner.
상기 회로 베이스층은 Au, Ag, Al, Cu, Sn, 또는 Ni를 포함하여 이루어지는 금속과 실리콘, 에폭시, 페놀, 아크릴, 또는 폴리에스테르를 포함하여 이루어지는 고분자 수지가 혼합된 액상의 비도전성 재료를 상기 베이스 기판 상에 인쇄방식으로 코팅하여 경화시킴으로써 형성될 수 있다. The circuit base layer may include a liquid non-conductive material in which a metal including Au, Ag, Al, Cu, Sn, or Ni is mixed with a polymer resin including silicon, epoxy, phenol, acrylic, or polyester. It may be formed by coating and curing the printing method on the base substrate.
상기 패드 베이스층은 Au, Ag, Al, Cu, Sn 또는 Ni 을 포함하여 이루어지는 금속과 실리콘, 에폭시, 페놀, 아크릴, 또는 폴리에스테르를 포함하여 이루어지는 고분자 수지가 혼합된 액상의 도전성 재료를 상기 베이스 기판 상에 인쇄방식으로 코팅하여 경화시킴으로써 형성될 수 있다. The pad base layer may include a liquid conductive material in which a metal including Au, Ag, Al, Cu, Sn, or Ni and a polymer resin including silicon, epoxy, phenol, acrylic, or polyester is mixed with the base substrate. It may be formed by coating and curing on a printing method.
상기 도금층은 상기 화학도금층보다 상기 전기도금층의 두께가 더 두꺼운 것이 바람직하다. 상기 본딩 패드층은 Ni 및 Au가 순차적으로 밑에서 위로 적층된 Ni/Au나 Ni 및 Ag가 순차적으로 밑에서 위로 적층된 Ni/Ag로 이루어지는 것일 수 있다. The plating layer is preferably thicker than the chemical plating layer of the electroplating layer. The bonding pad layer may include Ni / Au in which Ni and Au are sequentially stacked from the bottom up, or Ni / Ag in which Ni and Ag are sequentially stacked from the bottom up.
본 발명은 열합착 방법을 사용하지 않기 때문에 열팽창 및 열수축에 따른 기판의 휨현상을 고려할 필요가 없어 고방열성 회로기판(200)을 얇게 만들 수 있을 뿐만 아니라 두껍고 견고한 여러 가지 형태의 베이스 기판을 사용할 수도 있어, 다양하고 창의적인 LED 조명이 구현이 가능하고, 또한 방열 및 배광특성을 종래보다 더 극대화할 수 있다. 그리고 제조비용도 절감할 수 있다. Since the present invention does not use the thermal bonding method, there is no need to consider the warpage of the substrate due to thermal expansion and thermal contraction, and thus, the high heat dissipation circuit board 200 can be made thin, and various types of base substrates that are thick and rigid can be used. In addition, various and creative LED lightings can be implemented, and heat dissipation and light distribution can be maximized more than before. And manufacturing costs can be reduced.
도 1은 LED용 회로기판을 설명하기 위한 도면; 1 is a view for explaining a circuit board for the LED;
도 2는 종래의 중출력 LED용 방열회로기판(100)을 설명하기 위한 도면; 2 is a view for explaining a conventional heat dissipation circuit board 100 for mid-power LED;
도 3은 도 2의 방열회로기판(100)을 제조하는 과정을 설명하기 위한 도면; 3 is a view for explaining a process of manufacturing the heat radiation circuit board 100 of FIG.
도 4는 본 발명의 제1실시예에 따른 고방열성 회로기판(200)의 제조방법을 설명하기 위한 도면; 4 is a view for explaining a method of manufacturing a high heat dissipation circuit board 200 according to a first embodiment of the present invention;
도 5는 본 발명의 제2실시예에 따른 고방열성 회로기판(200)의 제조방법을 설명하기 위한 도면; 5 is a view for explaining a manufacturing method of a high heat radiation circuit board 200 according to a second embodiment of the present invention;
도 6은 본 발명의 제3실시예에 따른 고방열성 회로기판(200)의 제조방법을 설명하기 위한 도면; 6 is a view for explaining a manufacturing method of a high heat radiation circuit board 200 according to a third embodiment of the present invention;
도 7은 본 발명의 제4실시예에 따른 고방열성 회로기판(200)의 제조방법을 설명하기 위한 도면; 7 is a view for explaining a manufacturing method of a high heat radiation circuit board 200 according to a fourth embodiment of the present invention;
도 8은 본 발명의 잇점을 설명하기 위한 도면이다. 8 is a view for explaining the advantages of the present invention.
[도면의 주요 부호에 대한 설명][Description of Major Symbols in Drawing]
200: 고방열성 회로기판200: high heat radiation circuit board
210, 310, 410: 베이스 기판210, 310, 410: base substrate
211: 금속기판211: metal substrate
212: 절연층212: insulation layer
230: 회로 베이스층230: circuit base layer
240: 패드 베이스층240: pad base layer
250: 화학도금층250: chemical plating layer
255: 전기도금층255: electroplating layer
260: 도금층260: plating layer
261: 도금층 패턴261: plating layer pattern
270: 본딩 패드층270: bonding pad layer
271: 본딩 패드271: bonding pads
280: 감광막 패턴280: photoresist pattern
311: 알루미늄 기판311: aluminum substrate
312: 산화알루미늄층312: aluminum oxide layer
이하에서, 본 발명의 바람직한 실시예를 첨부한 도면들을 참조하여 상세히 설명한다. 아래의 실시예는 본 발명의 내용을 이해하기 위해 제시된 것일 뿐이며 당 분야에서 통상의 지식을 가진 자라면 본 발명의 기술적 사상 내에서 많은 변형이 가능할 것이다. 따라서 본 발명의 권리범위가 이러한 실시예에 한정되는 것으로 해석돼서는 안 된다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail. The following examples are only presented to understand the content of the present invention, and those skilled in the art will be capable of many modifications within the technical spirit of the present invention. Therefore, the scope of the present invention should not be construed as limited to these embodiments.
[제1실시예][First Embodiment]
도 4는 본 발명의 제1실시예에 따른 고방열성 회로기판(200)의 제조방법을 설명하기 위한 도면이다. 구체적으로, 도 4a에 도시된 바와 같이, 10um~10mm의 두께를 갖는 Al, Cu, Mg, Fe 등의 금속기판(211) 상에 내열성 및 절연성이 우수한 실리콘, 에폭시, 페놀, 아크릴, 폴리에스테르 등의 고분자 수지의 액상도료 또는 여기에 Al2O3, AlN, BN, Si, SiO2 등의 높은 열전도도를 가지는 세라믹을 혼합한 액상도료를 인쇄방식으로 30~300um 두께로 코팅하여 100~200℃에서 경화시킴으로써 절연층(212)을 형성시켜 베이스 기판(210)을 준비한다. 4 is a view for explaining a method of manufacturing a high heat radiation circuit board 200 according to a first embodiment of the present invention. Specifically, as shown in Figure 4a, on the metal substrate 211, such as Al, Cu, Mg, Fe having a thickness of 10um ~ 10mm excellent silicon, epoxy, phenol, acrylic, polyester, etc. 100 ~ 200 ℃ by coating 30 ~ 300um thick liquid coating material of polymer resin or liquid coating material mixed with ceramic having high thermal conductivity such as Al 2 O 3 , AlN, BN, Si, SiO 2 By curing at, an insulating layer 212 is formed to prepare a base substrate 210.
다음에, 도 4b에 도시된 바와 같이, Au, Ag, Al, Cu, Sn, Ni 등의 금속과 내열성 및 절연성이 우수한 실리콘, 에폭시, 페놀, 아크릴, 폴리에스테르 등의 고분자 수지가 혼합된 액상의 비도전성 재료를 절연층(212) 상에 인쇄방식으로 5~30um의 두께로 코팅하여 100~200℃에서 경화시킴으로써 회로 베이스층(230)을 형성한다. 회로 베이스층(230)은 LED칩이나 패키지의 패드부가 놓이는 영역에 있는 베이스 기판(210)은 노출되도록 베이스 기판(210) 상에 형성된다. 회로 베이스층(230)은 비록 금속이 포함되기는 하지만 고분자 수지가 더 많은 경우 이렇게 비도전성이 될 수 있다. Next, as shown in Figure 4b, a liquid mixture of a metal such as Au, Ag, Al, Cu, Sn, Ni and a polymer resin such as silicon, epoxy, phenol, acrylic, polyester excellent in heat resistance and insulation The non-conductive material is coated on the insulating layer 212 with a thickness of 5 to 30 μm by a printing method and cured at 100 to 200 ° C. to form the circuit base layer 230. The circuit base layer 230 is formed on the base substrate 210 so that the base substrate 210 in the area where the pad portion of the LED chip or the package is placed is exposed. The circuit base layer 230 may be non-conductive if there are more polymer resins, although metals are included.
이어서 도 4c에 도시된 바와 같이, 회로 베이스층(230)에 의해 노출된 베이스 기판(210) 상에 Au, Ag, Al, Cu, Sn, Ni 등의 금속과 내열성이 우수한 실리콘, 에폭시, 페놀, 아크릴, 폴리에스테르 등의 고분자 수지를 혼합하여 높은 열전도도를 가지는 액상의 도전성 재료를 인쇄방식으로 채워 넣어 100~200℃에서 경화시킴으로서 패드 베이스층(240)을 형성한다. 금속의 양을 많이 하고 고분자 수지의 양을 적게 하면 회로 베이스층(230)의 경우와 달리 패드 베이스층(240)이 이와 같이 전도성을 가질 수 있다.Subsequently, as shown in FIG. 4C, metals such as Au, Ag, Al, Cu, Sn, and Ni, silicon, epoxy, phenol, and the like, which are excellent in heat resistance, are exposed on the base substrate 210 exposed by the circuit base layer 230. The pad base layer 240 is formed by mixing a polymer resin such as acrylic or polyester, filling a liquid conductive material having high thermal conductivity by printing, and curing at 100 to 200 ° C. If the amount of the metal is increased and the amount of the polymer resin is reduced, the pad base layer 240 may have conductivity as described above, unlike the circuit base layer 230.
그리고 회로 베이스층(230)과 패드 베이스층(240) 상에 화학도금방식으로 0.1~6um의 Cu, Ni , Sn 등을 도금하여 화학도금층(250)을 형성한다. 그리고 도 4d에 도시된 바와 같이, 화학도금층(250) 상에 전기도금방식으로 5~100um의 Cu, Ni 또는 Sn 등을 도금하여 전기도금층(255)을 형성함으로써, 화학도금층(250)과 전기도금층(255)이 순차적으로 적층되어 이루어진 도금층(260)을 형성한다. 회로 베이스층(230)이 비전도성이기 때문에 화학도금을 먼저 행하는 것이며, 이후에 전기도금을 행하는 이유는 전기도금이 화학도금에 비하여 두껍게 형성하는데 더 유리하기 때문이다.In addition, the chemical plating layer 250 is formed by plating 0.1 to 6 μm of Cu, Ni, and Sn on the circuit base layer 230 and the pad base layer 240 by a chemical plating method. As shown in FIG. 4D, the electroplating layer 250 and the electroplating layer are formed by plating 5 to 100 μm of Cu, Ni, Sn, or the like on the chemical plating layer 250 by electroplating. A plating layer 260 formed by sequentially stacking 255 is formed. Since the circuit base layer 230 is non-conductive, the chemical plating is performed first, and the electroplating is performed later because the electroplating is more advantageous to form thicker than the chemical plating.
다음에, 도 4e에 도시된 바와 같이, 전기도금방식으로 Ni/Au 나 Ni/Ag를 도금층(260) 상에 전기도금하여 와이어 본딩을 위한 본딩 패드층(270)을 형성한다. 본딩 패드층(270)은 LED칩을 패키지화하는 실장공정중 와이어 본딩시 접착력을 강화시키는 것이기도 하지만 LED 빛의 반사율을 높이기 위한 것이기도 하다. 여기서, Ni/Au는 Ni층이 먼저 형성되고 그 위에 Au층이 형성된 것을 말하며, Ni은 1~10um, Au는 0.1~5um이고, Ni/Ag는 Ni층이 먼저 형성되고 그 위에 Ag층이 형성된 것을 말하며, Ni은 1~10um, Ag은 1~10um의 두께를 가지는 것이 바람직하다.Next, as illustrated in FIG. 4E, Ni / Au or Ni / Ag is electroplated on the plating layer 260 to form a bonding pad layer 270 for wire bonding. The bonding pad layer 270 enhances the adhesive strength during wire bonding during the packaging process of packaging the LED chip, but also improves the reflectance of the LED light. Here, Ni / Au refers to the Ni layer is formed first, the Au layer is formed thereon, Ni is 1 ~ 10um, Au is 0.1 ~ 5um, Ni / Ag is Ni layer is formed first, Ag layer formed thereon That is, Ni preferably has a thickness of 1 ~ 10um, Ag 1 ~ 10um.
계속해서, 도 4f에서와 같이 감광막 패턴(280)을 본딩 패드층(270) 상에 형성한 후, 도 4g에서와 같이, 이를 식각마스크로 하여 회로 베이스층(230)이 노출될 때까지 본딩 패드층(270)과 도금층(260)을 순차적으로 식각한 후 감광막 패턴(280)을 제거함으로써 도금층 패턴(261) 및 본딩패드(271)를 형성하여 본 발명의 제1실시예에 따른 고방열성 회로기판(200)을 완성한다. Subsequently, after the photoresist pattern 280 is formed on the bonding pad layer 270 as shown in FIG. 4F, as shown in FIG. 4G, the bonding pad is exposed until the circuit base layer 230 is exposed using the etching mask as an etching mask. After etching the layer 270 and the plating layer 260 sequentially, the photoresist layer pattern 280 is removed to form the plating layer pattern 261 and the bonding pads 271 to form a high heat-dissipating circuit board according to the first embodiment of the present invention. Complete 200.
감광막 패턴(280)은 패드 베이스층(240) 상부와 함께 와이어 본딩될 위치에 존재해야 한다. 그래야, 패드 베이스층(240) 상부 및 그 밖에 와이어 본딩될 위치에 도금층 패턴(261) 및 본딩패드(271)가 순차적으로 적층된 상태에서 존재할 수 있기 때문이다. The photoresist pattern 280 should be present at a position to be wire bonded together with the pad base layer 240. This is because the plating layer pattern 261 and the bonding pads 271 may be sequentially stacked on the pad base layer 240 and other positions to be wire bonded.
한편, 도 4h에서와 같이 애초부터 뒷면에 요철부(A)가 형성된 금속기판(211)을 사용함으로써 방열효율을 더 향상시킬 수도 있다. 이 경우 베이스 기판(410)의 두께가 어느 정도 두꺼워질 수 밖에 없을 것이다. On the other hand, as shown in Figure 4h from the beginning by using the metal substrate 211 is formed in the concave-convex portion (A) on the back can further improve the heat dissipation efficiency. In this case, the thickness of the base substrate 410 may be increased to some extent.
본 발명의 제1실시예에 의하면, 열합착 방법이 아닌 도금 및 인쇄방법을 취함으로써 베이스 기판(210)의 두께를 매우 얇게 할 수 있기 때문에 기판에 유연성(flexibility)을 부여할 수 있다. 물론 종래와 같이 두껍고 견고한 여러 가지 형태의 베이스 기판(210)을 사용할 수도 있다. 따라서 다양하고 창의적인 LED 조명을 구현할 수 있고, 제조비용 측면에서도 유리하며, 방열효율도 향상된다. According to the first embodiment of the present invention, since the thickness of the base substrate 210 can be made very thin by using the plating and printing method instead of the thermal bonding method, flexibility can be given to the substrate. Of course, various types of base substrate 210 may be used that are thick and rigid as in the prior art. Therefore, it is possible to realize a variety of creative LED lighting, it is advantageous in terms of manufacturing cost, and also improve the heat dissipation efficiency.
[제2실시예]Second Embodiment
도 5는 본 발명의 제2실시예에 따른 고방열성 회로기판(200)의 제조방법을 설명하기 위한 도면이다. 도 4의 경우는 패드 베이스층(240)이 절연층(212) 상에 형성되었지만 도 5의 경우는 패드 베이스층(240)이 금속기판(211)에 직접 형성되는 것을 차이점으로 한다. 5 is a view for explaining a method of manufacturing a high heat radiation circuit board 200 according to a second embodiment of the present invention. In FIG. 4, the pad base layer 240 is formed on the insulating layer 212. However, in FIG. 5, the pad base layer 240 is directly formed on the metal substrate 211.
구체적으로, 도 5a에 도시된 바와 같이, 금속기판(211) 상에 절연층(212)을 형성시켜 베이스 기판(210)을 준비한다. 이 때 절연층(212)은 LED칩이나 패키지의 패드부가 놓이는 영역에 있는 금속기판(211)은 노출되도록 인쇄방식으로 형성된다. 그리고 도 5b에 도시된 바와 같이, 절연층(212)과 같은 인쇄방식으로 절연층(212) 상에만 회로 베이스층(230)을 형성한다. Specifically, as shown in FIG. 5A, the base substrate 210 is prepared by forming an insulating layer 212 on the metal substrate 211. At this time, the insulating layer 212 is formed by a printing method so that the metal substrate 211 in the region where the pad portion of the LED chip or the package is placed is exposed. As shown in FIG. 5B, the circuit base layer 230 is formed only on the insulating layer 212 using the same printing method as the insulating layer 212.
이어서 도 5c에 도시된 바와 같이, 노출된 금속기판(211) 상에 Au, Ag, Al, Cu, Sn, Ni 등의 금속과 내열성이 우수한 실리콘, 에폭시, 페놀, 아크릴, 폴리에스테르 등의 고분자 수지를 혼합하여 높은 열전도도를 가지는 액상의 도전성 재료를 인쇄방식으로 채워 넣어 100~200℃에서 경화시킴으로서 패드 베이스층(240)을 형성하거나, Au, Ag, Al, Cu, Sn, Ni 등을 전기도금방식으로 노출된 금속기판(211) 상에 채워넣어 패드 베이스층(240)을 형성시키다. 노출된 금속기판(211)은 전기가 통하지만 맨 위에 있는 회로 베이스층(230)은 비전도성이기 때문에 전기도금하는 경우 노출된 금속기판(211) 상에만 패드 베이스층(240)이 형성되어 채워진다.Subsequently, as shown in FIG. 5C, polymers such as Au, Ag, Al, Cu, Sn, and Ni and polymers having excellent heat resistance on the exposed metal substrate 211 and polymer resins such as silicone, epoxy, phenol, acryl, and polyester By mixing the liquid conductive material having a high thermal conductivity by printing method to harden at 100 ~ 200 ℃ to form a pad base layer 240, or electroplating Au, Ag, Al, Cu, Sn, Ni, etc. The pad base layer 240 is formed by filling the exposed metal substrate 211 in a manner. Since the exposed metal substrate 211 is electrically conductive, but the uppermost circuit base layer 230 is non-conductive, the pad base layer 240 is formed and filled only on the exposed metal substrate 211 when electroplating.
계속해서, 도 5d에 도시된 바와 같이 회로 베이스층(230)과 패드 베이스층(240) 상에 화학도금층(250)을 형성하고, 도 5e에 도시된 바와 같이 전기도금층(255)을 순차적으로 형성하여 화학도금층(250)과 전기도금층(255)이 순차적으로 적층되어 이루어진 도금층(260)을 형성한다. 다음에, 도 5f에서와 같이 본딩 패드층(270)을 형성하고, 도 5g 및 도 5h 에서처럼 패터닝 공정을 진행하여 제2실시예에 따른 고방열성 회로기판(200)을 완성한다. 이러한 패터닝 공정은 제1실시예의 경우와 동일하게 진행된다. Subsequently, the chemical plating layer 250 is formed on the circuit base layer 230 and the pad base layer 240 as shown in FIG. 5D, and the electroplating layer 255 is sequentially formed as shown in FIG. 5E. The chemical plating layer 250 and the electroplating layer 255 are sequentially stacked to form a plating layer 260. Next, the bonding pad layer 270 is formed as shown in FIG. 5F, and the patterning process is performed as shown in FIGS. 5G and 5H to complete the high heat dissipation circuit board 200 according to the second embodiment. This patterning process proceeds in the same manner as in the first embodiment.
[제3실시예]Third Embodiment
도 6은 본 발명의 제3실시예에 따른 고방열성 회로기판(200)의 제조방법을 설명하기 위한 도면으로서, 제1실시예의 경우와 달리 베이스 기판(310)으로서 알루미늄 기판(311)의 표면이 양극산화처리(anodizing)되어 30~200um의 산화알루미늄층(312)으로 둘러싸인 것을 사용하는 것이 특징이다. 산화알루미늄층(312)은 도 4의 절연층(212)에 대응되며 그 후속공정은 제1실시예(도 4)와 동일하다. 산화알루미늄층(312)은 열전도도가 60W/mk 정도로서 나쁘지 않기 때문에 굳이 제거할 필요까지는 없다.FIG. 6 is a view for explaining a method of manufacturing a high heat dissipation circuit board 200 according to a third embodiment of the present invention. Unlike the first embodiment, the surface of the aluminum substrate 311 is formed as the base substrate 310. Anodizing (anodizing) is characterized by using a 30 ~ 200um surrounded by an aluminum oxide layer 312. The aluminum oxide layer 312 corresponds to the insulating layer 212 of FIG. 4, and the subsequent process is the same as that of the first embodiment (FIG. 4). The aluminum oxide layer 312 does not need to be removed because the thermal conductivity is not bad as about 60 W / mk.
[제4실시예]Fourth Embodiment
도 7은 본 발명의 제4실시예에 따른 고방열성 회로기판(200)의 제조방법을 설명하기 위한 도면으로서, 제1실시예의 경우와 달리 베이스 기판(410)으로서 방열플라스틱 기판을 사용하는 것이 특징이다. 방열 플라스틱은 플라스틱에 높은 열전도성의 세라믹을 혼합하여 방열성과 절연성을 가지도록 한 것을 말한다. 방열 플라스틱은 가볍고 싸기 때문에 비용적인 측면에서 특히 바람직하며 유연성 면에서도 더욱 유리하다. FIG. 7 is a view for explaining a method of manufacturing a high heat dissipation circuit board 200 according to a fourth embodiment of the present invention. Unlike the first embodiment, a heat dissipation plastic substrate is used as the base substrate 410. to be. Heat dissipation plastic refers to a material having high heat conductivity ceramic mixed with plastic to have heat dissipation and insulation. Heat dissipation plastics are particularly advantageous in terms of cost because they are light and inexpensive, and more advantageous in terms of flexibility.
도 8은 본 발명의 잇점을 설명하기 위한 도면이다. 8 is a view for explaining the advantages of the present invention.
본 발명은 열합착 방법을 사용하지 않기 때문에 열팽창 및 열수축에 따른 기판의 휨현상을 고려할 필요가 없어 고방열성 회로기판(200)을 얇게 만들 수 있을 뿐만 아니라 두껍고 견고한 여러 가지 형태의 베이스 기판을 사용할 수도 있어, 다양하고 창의적인 LED 조명이 구현이 가능하고, 또한 방열 및 배광특성을 종래보다 더 극대화할 수 있다. 그리고 제조비용도 절감할 수 있다. Since the present invention does not use the thermal bonding method, there is no need to consider the warpage of the substrate due to thermal expansion and thermal contraction, and thus, the high heat dissipation circuit board 200 can be made thin, and various types of base substrates that are thick and rigid can be used. In addition, various and creative LED lightings can be implemented, and heat dissipation and light distribution can be maximized more than before. And manufacturing costs can be reduced.
Claims (11)
- 베이스 기판 상에 상기 베이스 기판의 소정영역을 노출시키도록 비도전성의 회로 베이스층을 형성하는 단계;Forming a non-conductive circuit base layer on the base substrate to expose a predetermined region of the base substrate;상기 회로 베이스층에 의해 노출되는 베이스 기판 상에 도전성의 패드 베이스층을 채우는 단계; Filling a conductive pad base layer on the base substrate exposed by the circuit base layer;상기 회로 베이스층과 패드 베이스층 상에 화학도금층을 형성한 후에 상기 화학도금층 상에 전기도금층을 형성하여 화학도금층과 전기도금층이 순차적으로 적층되는 도금층을 형성하는 단계; After forming a chemical plating layer on the circuit base layer and the pad base layer, forming an electroplating layer on the chemical plating layer to form a plating layer in which the chemical plating layer and the electroplating layer are sequentially stacked;상기 도금층 상에 도전성의 본딩 패드층을 형성하는 단계; 및Forming a conductive bonding pad layer on the plating layer; And상기 회로 베이스층이 노출되도록 상기 도금층과 상기 본딩 패드층을 패터닝하여 상기 패드 베이스층 상부를 포함하는 소정영역에 도금층 패턴과 본딩패드가 순차적으로 적층된 구조를 형성하는 단계; 를 포함하여 이루어지는 것을 특징으로 하는 고방열성 회로기판 제조방법. Patterning the plating layer and the bonding pad layer to expose the circuit base layer to form a structure in which a plating layer pattern and a bonding pad are sequentially stacked on a predetermined region including an upper portion of the pad base layer; A high heat dissipation circuit board manufacturing method comprising a.
- 제1항에 있어서, 상기 베이스 기판은 윗면에 절연층이 형성된 금속기판인 것을 특징으로 하는 고방열성 회로기판 제조방법. The method of claim 1, wherein the base substrate is a metal substrate having an insulating layer formed on an upper surface thereof.
- 제1항에 있어서, 상기 베이스 기판은 표면에 산화알루미늄층이 형성된 알루미늄 기판인 것을 특징으로 하는 고방열성 회로기판 제조방법. The method of claim 1, wherein the base substrate is an aluminum substrate having an aluminum oxide layer formed on a surface thereof.
- 제1항에 있어서, 상기 베이스 기판은 열도전성의 세라믹이 함유된 절연성 방열 플라스틱 기판인 것을 특징으로 하는 고방열성 회로기판 제조방법. The method of claim 1, wherein the base substrate is an insulating heat-dissipating plastic substrate containing a thermally conductive ceramic.
- 제2항에 있어서, 상기 절연층이 상기 금속기판의 소정영역을 노출시키도록 형성되며, 상기 회로 베이스층은 상기 금속기판이 노출되도록 상기 절연층 상에 형성되며, 상기 패드 베이스층은 상기 절연층 및 회로 베이스층에 의해 노출되는 금속기판 상에 채워지도록 형성되는 것을 특징으로 하는 고방열성 회로기판 제조방법.The method of claim 2, wherein the insulating layer is formed to expose a predetermined region of the metal substrate, the circuit base layer is formed on the insulating layer so that the metal substrate is exposed, the pad base layer is the insulating layer And filling the metal substrate exposed by the circuit base layer.
- 제2항에 있어서, 상기 절연층이 실리콘, 에폭시, 페놀, 아크릴, 또는 폴리에스테르를 포함하여 이루어지는 고분자 수지의 액상도료이거나, 여기에 Al2O3, AlN, BN, Si, 또는 SiO2 를 포함하여 이루어지는 세라믹이 혼합된 액상도료를 인쇄방식으로 상기 금속기판 상에 코팅하여 경화시킴으로써 형성되는 것을 특징으로 하는 고방열성 회로기판 제조방법. 3. The method of claim 2, wherein the insulating layer is a liquid coating of a polymer resin comprising silicon, epoxy, phenol, acryl, or polyester, or a ceramic comprising Al2O3, AlN, BN, Si, or SiO2. The method of manufacturing a high heat dissipation circuit board, characterized in that formed by coating the cured liquid coating on the metal substrate by a printing method.
- 제1항에 있어서, 상기 회로 베이스층이 Au, Ag, Al, Cu, Sn, 또는 Ni를 포함하여 이루어지는 금속과 실리콘, 에폭시, 페놀, 아크릴, 또는 폴리에스테르를 포함하여 이루어지는 고분자 수지가 혼합된 액상의 비도전성 재료를 상기 베이스 기판 상에 인쇄방식으로 코팅하여 경화시킴으로써 형성되는 것을 특징으로 하는 고방열성 회로기판 제조방법.The liquid phase of claim 1, wherein the circuit base layer comprises a metal comprising Au, Ag, Al, Cu, Sn, or Ni and a polymer resin comprising silicon, epoxy, phenol, acryl, or polyester. The non-conductive material of the method of manufacturing a high heat dissipation circuit board, characterized in that formed by coating on the base substrate by curing.
- 제1항에 있어서, 상기 패드 베이스층은 Au, Ag, Al, Cu, Sn 또는 Ni 을 포함하여 이루어지는 금속과 실리콘, 에폭시, 페놀, 아크릴, 또는 폴리에스테르를 포함하여 이루어지는 고분자 수지가 혼합된 액상의 도전성 재료를 상기 베이스 기판 상에 인쇄방식으로 코팅하여 경화시킴으로써 형성되는 것을 특징으로 하는 고방열성 회로기판 제조방법.The method of claim 1, wherein the pad base layer is a liquid mixture of a metal resin containing Au, Ag, Al, Cu, Sn or Ni and a polymer resin comprising silicon, epoxy, phenol, acrylic or polyester. A method of manufacturing a high heat dissipation circuit board, wherein the conductive material is formed by coating and curing the conductive material on the base substrate.
- 제5항에 있어서, 상기 패드 베이스층은 Au, Ag, Al, Cu, Sn 또는 Ni 을 포함하여 이루어지는 금속을 전기도금시킴으로써 형성되는 것을 특징으로 하는 고방열성 회로기판 제조방법. The method of claim 5, wherein the pad base layer is formed by electroplating a metal including Au, Ag, Al, Cu, Sn, or Ni.
- 제1항에 있어서, 상기 도금층은 상기 화학도금층보다 상기 전기도금층의 두께가 더 두꺼운 것을 특징으로 하는 고방열성 회로기판 제조방법.The method of claim 1, wherein the plating layer is thicker in thickness than the chemical plating layer in the electroplating layer.
- 제1항에 있어서, 상기 본딩 패드층은 Ni 및 Au가 순차적으로 밑에서 위로 적층된 Ni/Au나 Ni 및 Ag가 순차적으로 밑에서 위로 적층된 Ni/Ag로 이루어지는 것을 특징으로 하는 고방열성 회로기판 제조방법. The method of claim 1, wherein the bonding pad layer is formed of Ni / Au in which Ni and Au are sequentially stacked from the bottom up, or Ni / Ag in which Ni and Ag are sequentially stacked from the bottom up. .
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