WO2018000495A1

WO2018000495A1 - Chip single-event effect detection method and device

Info

Publication number: WO2018000495A1
Application number: PCT/CN2016/092256
Authority: WO
Inventors: 李慧云; 邵翠萍; 刘玢玢
Original assignee: 中国科学院深圳先进技术研究院
Priority date: 2016-06-27
Filing date: 2016-07-29
Publication date: 2018-01-04
Also published as: CN106199392A; CN106199392B

Abstract

A chip single-event effect detection method and device, the method comprising: placing a to-be-detected chip in a testing machine, and triggering the to-be-detected chip to generate a single-event effect; randomly turning off a scanning register for the to-be-detected chip, and forming a random observation matrix; providing an input testing vector for the to-be-detected chip so as to obtain an output testing vector of the to-be-detected chip, and obtaining an error total vector according to the output testing vector; and carrying out compressed sensing signal reconstruction on the error total vector, and determining an internal sensitive region of the to-be-detected chip. The method may be used to efficiently and conveniently detect the single-event effect of a chip.

Description

Chip single particle effect detecting method and device

Technical field

The present invention relates to the field of integrated circuit technology, and in particular, to a chip single particle effect detecting method and apparatus.

Background technique

The importance of integrated circuit reliability research is highlighted by the rapid advancement of the semiconductor industry. The new small package, high speed, low power high performance chip is greatly sensitive to particle radiation and can generate many semiconductor ionizing radiation effects, also known as single particle effect. FIG. 1 is a schematic diagram of a semiconductor single-particle effect caused by incident high-energy particles in the prior art. As shown in FIG. 1 , a single-particle effect causes an electronic device to deviate from normal functions and performance, resulting in a decrease in chip reliability or even failure.

In addition to space ray can lead to single-particle effect of the chip, modern integrated circuit chip manufacturing process also introduces a large number of processing steps of radiation damage, such as ion implantation, dry etching, electron beam or X-ray lithography, plasma enhanced chemical vapor deposition , ion milling, barrier layer and metal layer construction. The source of ionizing radiation in the chip packaging process is alpha particles, such as lead-based isotopes in flip-chip solder balls, radioactive impurities such as uranium and thorium. These sources of radiation will seriously threaten the reliability of the single-particle effect on the chip.

With the development of space technology and nuclear technology, single-particle effects are further classified, such as Single event latch-up (SEL), Single event upset (SEU), single-event function interrupt (Single) Event functional interrupt (SEFI) and single event burnout (SEB). According to the single-particle effect on the electronic components can be restored, single-event effects can be divided into unrecoverable errors and recoverable errors. "Unrecoverable error", or "hard error", refers to an error that causes a fatal permanent damage to the device or system, such as SEB; "recoverable error", or "soft error", means restarting Methods such as device or rewriting of data can restore normal errors such as SEU, SET, SED, etc. Among them, the single-particle latch SEL and the single-event flip SEU are two single-particle effects with high frequency of occurrence.

Single-event effects pose a serious threat to the reliability of deep sub-micron integrated circuits, especially for orbiting spacecraft or other avionics. According to the statistics of the National Geophysical Data Center (NGDC) of the United States, from 1971 to 1986, 39 synchronous satellites launched abroad had 1589 faults during the flight, and 1129 faults caused by space radiation, accounting for the total number of faults. 71%, and in the failure caused by radiation, the single-event effect caused 621 failures, accounting for 55% of the total failure caused by radiation. A similar situation has occurred in spacecraft launched in China. China Academy of Space Technology counts six communications satellites of the Dongfanghong II series from 1984 to 2000 The fault, in which the space environment effect caused by the fault accounted for 40% of the total number of faults. From 2007 to 2010, the statistics of single-event effect faults of spacecraft in China show that the single-particle effect dominates the radiation effect of space environment, and the damage to spacecraft is becoming more and more serious.

Irradiation studies using high-energy ion beams require expensive specialized equipment, typically including particle accelerators, terminal beam machines, and oscilloscopes. Only a few universities and research institutions can carry out such experiments. Scientists have discovered that pulsed lasers can be used to simulate the single-particle effects of space cosmic ray heavy ions in microelectronic devices and integrated circuits. In 1994, JSMelinger et al. studied the experiment and basic mechanism of laser single-particle effect, and carried out a detailed analysis of the interaction process between laser and electronic device materials, arguing that although the electron-hole-to-plasma structure and heavy ions generated by laser The generated electron-holes have large differences in the plasma track structure, but they can still be used as an important evaluation tool in the laboratory for single-event effect testing. And in engineering design applications, the laser single-event effect test method is more practical than the particle accelerator. The process of single-particle effects caused by pulsed laser irradiation, especially soft errors, is called "fault injection". However, even the use of pulsed lasers to test the reliability of single-particle effects faces inefficiencies and cumbersome problems.

Summary of the invention

Embodiments of the present invention provide a chip single-event effect detecting method for efficiently and conveniently detecting a single-particle effect of a chip, and the method includes:

Putting the chip to be tested into the test machine, triggering the single chip effect of the chip to be tested;

Randomly turning off the scan register of the chip to be tested to form a random observation matrix;

Providing an input test vector to the chip to be tested, obtaining an output test vector of the chip to be tested, and obtaining an error total vector according to the output test vector;

The compressed sensing signal is reconstructed from the total number of errors to determine the sensitive area inside the chip to be tested.

The embodiment of the invention further provides a chip single-event effect detecting device for detecting the single-particle effect of the chip efficiently and conveniently, and the device comprises:

a test machine for placing a chip to be tested, the chip to be tested comprising a scan register;

a triggering device for triggering a single particle effect of the chip to be tested;

a random observation matrix forming unit for randomly turning off a scan register of the chip to be tested to form a random observation matrix;

The test machine is further configured to provide an input test vector to the chip to be tested, obtain an output test vector of the chip to be tested, obtain an error total vector according to the output test vector, perform a compressed sensing signal reconstruction on the total error vector, and determine a chip to be tested. Internal sensitive area.

In the embodiment of the present invention, the chip to be tested is placed in the test machine, triggering the chip to be tested to generate a single particle effect; randomly scanning the scan register of the chip to be tested to form a random observation matrix; providing an input test vector to the chip to be tested, The output test vector of the chip to be tested obtains the error total vector according to the output test vector; performs compression sensing signal reconstruction on the total error vector to determine the sensitive internal area of the chip to be tested; and can efficiently and efficiently make the internal change of the chip due to fault injection The results are reflected in the output, and reduce the understanding of the chip design and the dependence on the test experience; the observation and signal reconstruction can be performed efficiently with less observation cost, less test time.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work. In the drawing:

1 is a schematic view showing a semiconductor single particle effect caused by incident high energy particles in the prior art;

2 is a schematic diagram of a method for detecting a single particle effect of a chip according to an embodiment of the present invention;

3 is a block diagram of a signal observation and reconstruction method for detecting a SEU inside a chip by using compressed sensing in an embodiment of the present invention;

4 is a schematic diagram of scanning irradiation of a chip in an embodiment of the present invention;

FIG. 5 is a schematic diagram of a signal reconstruction process of a SEE sensitive point X according to an embodiment of the present invention; FIG.

6 is a schematic diagram of a chip single particle effect detecting device according to an embodiment of the present invention;

7 is a schematic diagram of a logic unit in each irradiation required to match a randomly enabled scan register in an embodiment of the present invention;

FIG. 8 is a schematic diagram of tasks and cooperation of a fault injection device and a compression sensing test machine according to an embodiment of the present invention.

detailed description

The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. The illustrative embodiments of the present invention and the description thereof are intended to explain the present invention, but are not intended to limit the invention.

The inventors have found that the use of pulsed lasers to test the reliability of single-event effects in the prior art faces inefficiencies and cumbersome problems, because the radiation effect test of existing chips requires test engineers to repeatedly scan and scan chips under laser irradiation for a long time. The output is used to analyze and judge the internal reliability of the chip. Even if you get the wrong result, you need to combine the fault analysis method (Fault Analysis) to analyze the data to find the vulnerability in the chip. This aspect is due to the fact that the laser irradiation must be synchronized with the key instruction processing inside the chip in time, and the fault injection tool must be spatially focused on the chip sensitive register area, which requires a long-term exploration by a tester with deep professional knowledge. Such test methods are time-consuming and laborious, are prone to false detections, and do not effectively help defend the design. Another reason for the cumbersome and inefficient operation of the existing chip radiation effect reliability test method is that the number of input and output pins of the chip is limited, so that the internal changes caused by the fault injection are not quickly and effectively reflected in the output result. Even with DFT (Design for Test) technology, it is impossible to observe the response of each logic gate. There are currently reports that nuclear microprobes that focus on high-energy photons or helium ions, or built-in edge detectors, can be used to investigate, but none of them can effectively detect the condition of all internal nodes.

The modern semiconductor process has adopted the 45nm node process on a large scale, and the 22nm node and 16nm node process into the chip is just around the corner. Under such deep submicron process conditions, variations in process parameters in manufacturing necessarily result in reduced reliability of the radiation effect. It is an inevitable trend to perform accurate and comprehensive fault injection on the chip and perform system analysis on the response.

In order to solve the disadvantages of the existing single-event effect reliability testing method, the embodiment of the present invention provides a method for detecting a single-particle effect of a chip by using a compressed sensing theory, which has the characteristics of losslessness and high efficiency. 2 is a schematic diagram of a method for detecting a single-particle effect of a chip according to an embodiment of the present invention. As shown in FIG. 2, the method may include:

Step 201: Put the chip to be tested into the testing machine, and trigger the chip to be tested to generate a single particle effect;

Step 202: Randomly turn off the scan register of the chip to be tested to form a random observation matrix;

Step 203, providing an input test vector to the chip to be tested, obtaining an output test vector of the chip to be tested, and obtaining an error total vector according to the output test vector;

Step 204: Perform compression sensing signal reconstruction on the error total vector to determine a sensitive area inside the chip to be tested.

It can be seen from the flow shown in FIG. 2 that in the embodiment of the present invention, by placing the chip to be tested into the testing machine, the chip to be tested is triggered to generate a single particle effect, and the scanning register of the chip to be tested is randomly turned off to form a random observation matrix. Providing an input test vector to the chip to be tested, obtaining an output test vector of the chip to be tested, and obtaining an error total according to the output test vector The number vector enables testability design and automated test vectors, so it can efficiently and efficiently reflect the internal changes caused by fault injection in the output of the chip, and reduce the understanding of the chip design and the dependence on the test experience. By compressing the perceptual signal reconstruction of the total number of errors, the sensitive area inside the chip to be tested is determined, so that observation and signal reconstruction can be performed efficiently with less observation cost and less test time.

The embodiment of the present invention studies the testability design and the corresponding test method based on the compressed sensing theory. The overall design idea is as follows: 1) Insert the register into the scan chain during the chip design process (if it is a cryptographic chip, it can only contain no key) The information register is inserted into the scan chain), and then a radiation effect reliability test vector is generated to avoid key related information leakage due to the insertion of the scan chain. Control each scan register for establishing a random observation matrix during testing; 2) Using the fault injection in the test phase after the chip is manufactured, based on the compressed sensing theory, control the shutdown scan register on the test machine to form a random observation matrix. By outputting the test vector to obtain the error total vector, and then obtaining the internal sensitive points through the signal reconstruction algorithm, the security level of the cryptographic chip or the SEE reliability of the avionics can be quickly determined.

The single-event effect detection method of the embodiment of the invention can combine the compression sensing, high-precision fault injection technology and DFT (Design for Test) technology to form an observation matrix, which greatly reduces the number of sensors or detectors required in the existing method. FIG. 3 is a block diagram showing the principle of signal observation and reconstruction used by the compressed sensing for detecting the internal SEU of the chip in the embodiment of the present invention. As shown in FIG. 3, in the embodiment of the present invention, the SEU sensitive point original signal of the chip is randomly observed and compressed, and the SEU sensitive point signal can be reconstructed.

In the implementation, the chip to be tested is first placed in the test machine, which triggers the single-particle effect of the chip to be tested. In a specific embodiment, the chip to be tested is placed in the test machine, triggering the single-particle effect of the chip to be tested, and the laser fault injection technology can be used. Of course, in addition to the fault injection by the laser beam irradiation, other single particles can be used. Effect triggering methods, such as heavy ion beam irradiation, or other radiation environments.

In the embodiment, the compressive sensing theory and the fault injection technology can be combined to perform the testability design and the corresponding test process, randomly turn off the scan register of the chip to be tested, form a random observation matrix, and provide an input test vector to the chip to be tested. The output test vector of the chip to be tested obtains the error total vector according to the output test vector; the compressed sensing signal is reconstructed for the total error vector to determine the sensitive area inside the chip to be tested.

The realization of the theory of compressed sensing contains three key elements: sparsity, uncorrelated observation, and nonlinear optimization reconstruction. The sparseness of the signal is a necessary condition for the compressed sensing. The uncorrelated observation is the key to the compressed sensing. The nonlinear optimization is the means of compressing the perceived signal. For the non-correlated observation, assume X is the internal SEE sensitive area of the chip to be tested, X is

Array. If x _ji =0, it indicates that the logic unit G _i has SEE reliability under the jth irradiation, x _ji =1, indicating that the logic unit G _i is an SEE sensitive area under the jth irradiation. Put it in a certain set of N-dimensional orthogonal bases

Expand on, ie:

If written in matrix form, we can get: X = Ψ θ, where Ψ = [ψ ₁ , ψ ₂ ..., ψ _N ] is an orthogonal basis matrix, satisfying ΨΨ ^T = Ψ ^T Ψ = I; expansion coefficient vector θ = [ θ ₁ , θ ₂ ..., θ _N ] ^T . Assuming that the coefficient vector θ is K-sparse, and the number of non-zero sparse K<<N, then another observation matrix Φ that is not related to the orthogonal base dictionary Φ: M×N (M<<N), Perform a compression observation on signal X to get:

Y=ΦX

or

Where y _j (j∈1, 2, ..., M) represents the total number of faults after each irradiation. In this way, M results y ∈ R ^M can be obtained, and X can be reconstructed based on the M results.

In the application of uncorrelated observations, an unrelated observation matrix Φ: M × N (M < < N) is designed, so that the signal energy is not destroyed when the internal fault point X is reduced from N to M dimensions. Using the method of randomly turning off the scan register, the random observation matrix can be obtained as follows:

Where Φ is a random observation matrix, wherein the element a _ji =0 indicates that the scan register corresponding to the i-th irradiated logic unit is turned off at the jth irradiation, j∈1, 2, ..., M , i∈1, 2,...,N. For example, in the jth irradiation, only a few to tens of logic cells are irradiated (the number depends on the size of the semiconductor process and the size of the laser focus spot), and the switch matrix is controlled to randomly turn off its associated scan register. If the scan register corresponding to the i-th logical unit is turned off, a _ji =0. The error caused by the SEE sensitivity of this logical unit is not reflected in the total number of errors y _{j of the jth} irradiation. As in the compressed sensing imaging technique, the light of the pixel is not counted in the observation matrix. Otherwise a _ji =1. Thus, after M-irradiation, it is possible to recover whether the i-th logical unit is SEE-sensitive by compressing the perceptual signal reconstruction, that is, x _i =0 or 1. x _i =0, indicating that the logic unit G _i has SEE reliability under irradiation, x _i =1, indicating that the logic unit G _i is an SEE sensitive area under irradiation.

In each irradiation process of the test, the scanning unit is established according to the laser beam or the heavy ion microbeam focusing size. FIG. 4 is a schematic diagram of the scanning irradiation of the chip in the embodiment of the present invention, as shown in FIG. 4, wherein the ALU The (arithmetic logic unit) and decoder (decoder) regions are the key irradiation ranges, taking the laser beam irradiation as an example. The small frame in Fig. 4 is the primary beam focusing range (only the illustration, the actual ratio is smaller than the illustration), The circular extent of the beam is approximated by a square in Figure 4. Taking the 0.18 μm process as an example, the experimental data shows that the irradiation spot diameter is about 3.7 μm, covering about 10 to 15 logic cells (also called logic gates). When the process node is reduced to 28 nm, the 3.7 μm laser spot covers 160-240 logic gates, and so on. It is also possible to use a technique in which the spot focus radius is small, such as a femtosecond laser. Therefore, in the embodiment, triggering the chip to be tested to generate a single particle effect may include: performing a fault injection on the chip to be tested by using a laser beam or a heavy ion microbeam. Using the laser beam or heavy ion microbeam irradiation to perform fault injection on the chip to be tested may include: establishing a scanning unit according to the laser beam or the heavy ion microbeam irradiation aggregation size during each irradiation of the test. When a laser beam or a heavy ion microbeam is irradiated to the test chip for fault injection, the arithmetic logic unit and the decoder region of the chip to be tested may be irradiated by laser beam or heavy ion microbeam irradiation.

Figure 4 shows the different logic cells covered by the chip under two exposures. Assuming that the logical unit (G ₁ , G ₄ , G ₆ , G ₉ , ...) of the p-th irradiation, the SEE sensitivity signals are [x ₁ , x ₄ , x ₆ , x ₉ , .. .], then the random observation matrix needs to be controlled so that the coefficient a _pi of the array x _pi in the formula (1), that is, some coefficients of [a _p1 , a _p4 , a _p6 , a _p9 ,...] are 1, and the rest are 0; the logical gates of the qth irradiation (G ₃ , G ₅ , G ₇ , G ₈ , ...), whose SEE sensitivity signals are [x ₃ , x ₅ , x ₇ , x ₈ , .. .], the random observation matrix needs to be controlled so that some coefficients in the array [a _q3 , a _q5 , a _q7 , a _q8 ,...] are 1 and the rest are 0.

Specifically, when the randomization matrix is formed by randomly turning off the scan register of the chip to be tested by using the enable signal, the method may include: forming a random observation matrix switch array by the serial-parallel decoder, and outputting to the enable port of the scan register of the chip to be tested. Enable the signal, randomly turn off the scan register of the chip to be tested, and form a random observation matrix; or, by controlling the input test vector, randomly turn off the scan register of the chip to be tested to form a random observation matrix, that is, randomly controlled by the input test vector Whether the error result that may occur in a scan register is included in the total number of errors to form a random observation matrix. In the embodiment, the scan register of the chip to be tested is randomly turned off, and when the random observation matrix is formed, the two-dimensional movement of the chip to be tested by the two-dimensional stage of the microscope may be further included, and the scan register that is randomly turned off each time is The logic cells of the chip under test that trigger the single-particle effect are matched.

FIG. 5 is a schematic diagram of a signal reconstruction process of a SEE sensitive point X according to an embodiment of the present invention. The design of the reconstruction algorithm directly affects the quality of signal reconstruction. In the implementation, the compressed sensing signal reconstruction of the total number of errors is performed to determine the sensitive area inside the chip to be tested, which may include: performing a compressed sensing signal reconstruction on the total number of errors using a linear programming algorithm or a nonlinear algorithm to determine the internal sensitivity of the chip to be tested. region. The nonlinear computing property can be, for example, a greedy algorithm. The greedy algorithm has low computational complexity and can simplify hardware integration. After repeated iterations, the greedy algorithm can gradually reduce the error, and finally complete the signal reconstruction of the SEE sensitive point X, and obtain the SEU reliability fault inside the chip. In an embodiment, a combination of a linear programming algorithm and a nonlinear algorithm may be used to perform compressed sensing signal reconstruction on the error total vector, or other related algorithms.

FIG. 6 is a schematic diagram of a single-particle effect detecting device for a chip according to an embodiment of the present invention. As shown in FIG. 6, the device may include:

a test machine 601, configured to put a chip to be tested, the chip to be tested includes a scan register;

The triggering device 602 is configured to trigger a single particle effect of the chip to be tested;

The random observation matrix forming unit 603 is configured to randomly turn off the scan register of the chip to be tested to form a random observation matrix;

The test machine 601 is further configured to provide an input test vector to the chip to be tested, obtain an output test vector of the chip to be tested, obtain an error total vector according to the output test vector, and perform compression sensing signal reconstruction on the total error vector to determine the internal chip to be tested. Sensitive area.

As previously mentioned, in an embodiment the triggering device may be a fault injecting device, such as a laser, such as a nanosecond laser, a picosecond laser or a femtosecond laser; or may be a heavy ion microbeam generator or the like. In an embodiment the laser or heavy ion microbeam generator can be further used to irradiate the arithmetic logic unit and decoder region of the chip under test.

In a specific example, the random observation matrix forming unit may include a random observation matrix switch array formed by a parallel-parallel decoder, and the random observation matrix switch array is configured to output an enable signal to an enable port of a scan register of the chip to be tested, The scan register of the chip to be tested is randomly turned off to form a random observation matrix; or, the random observation matrix forming unit may be further configured to randomly turn off the scan register of the chip to be tested by controlling the input test vector to form a random observation matrix.

In a specific example, the test machine may further include a two-dimensional stage of the microscope for performing two-dimensional movement of the chip to be tested, and each of the scan registers that are randomly turned off and the logic of the chip to be tested that are triggered to generate a single particle effect The units match.

In a specific example, the random observation matrix forming unit is further used to form a random observation matrix as follows:

Where Φ is the random observation matrix, wherein the element a _ji =0 indicates that the scan register corresponding to the i-th irradiated logic unit is turned off at the jth irradiation, j∈1, 2, .. .,M,i∈1,2,...,N.

In a specific example, the test machine is further configured to perform a compression observation on the signal X to obtain:

Where y _j (j∈1, 2, ..., M) represents the total number of faults after each irradiation; X is the internal SEE sensitive area of the chip to be tested, X is

An array of x _ji =0 indicates that the logical unit G _i has SEE reliability under the jth irradiation, and x _ji =1 indicates that the logical unit G _i is an SEE sensitive region under the jth irradiation.

In practice, the hardware implementation complexity of the observation matrix should also be considered. FIG. 7 is a schematic diagram of the logic unit under each irradiation in the embodiment of the present invention matched with the randomly enabled scan register. Figure 7 shows the random observation matrix switch array and the chip mother board to be tested on the test machine. The random observation matrix switch array is connected to the scan register enable port of the chip to be tested, and the scan register is randomly turned off by the enable signal. Due to the huge internal signal point data, considering the switching speed, the random observation matrix Φ can be obtained by the method of serial-parallel decoder.

Secondary development using laser and microscope software to control laser intensity and synchronization strategy. As shown in FIG. 7, the random observation matrix switch array data on the device is reconstructed by compressing the sensing signal, and the two-dimensional movement of the chip is realized by the two-dimensional stage of the microscope, so that each time the matrix array array is randomly observed, the array is enabled. The scan register is matched to the irradiated chip logic unit. In the embodiment, the sample displacement control command can be used to control the laser injection of the chip and return to the control state signal.

In a specific embodiment, the integrated circuit to be tested can be unsealed and then placed in a test machine for reconstructing the compressed sensing signal, and combined with the fault injection device (trigger device), the corresponding test vector and test protocol are input. Until the next irradiation. FIG. 8 is a schematic diagram of tasks and cooperation between a fault injection device and a compression sensing test machine according to an embodiment of the present invention. As shown in FIG. 8 , the fault injection device and the compression sensing test machine are synchronously controlled, and the fault injection device controls the p. The sub-laser irradiation range, the test machine performs image processing, compares the chip back layout (Layout), obtains the irradiated logic unit list G _pi , controls the random shutdown [a _pi ], establishes the equation Y=ΦX, and controls The mobile station continues to move for the next irradiation process.

In this way, after each irradiation test, the total number of faults after each irradiation can be obtained with a high test coverage with less test vectors y _j (j∈1, 2,..., M) And reconstruct the signal by nonlinear optimization formula (1)

Indicates that the logic unit has SEE reliability under irradiation, x _i =1, indicating that the logic sheet belongs to the SEE sensitive area under irradiation. Therefore, the SEU reliability fault inside the chip is obtained.

It can be seen from the above embodiments that in the embodiment of the present invention, the single-particle effect (SEE) sensitive point in the chip is analogized to the signal to be observed with sparsity, so the method of compressed sensing can be used to perform the detection without loss and high efficiency. At present, the radiation effect reliability test of the chip requires the test engineer to repeatedly scan the sampling chip for a long time, and analyze and judge the internal reliability of the chip only by the output result. Even if you get the wrong result, you need to combine the fault analysis method (Fault Analysis) to analyze the data to find the vulnerability in the chip. How to perform the radiation effect reliability test on the chip and efficiently and efficiently reflect the internal change caused by the fault injection on the output result is one of the key problems to be solved by the embodiment of the present invention. The embodiment of the present invention combines the random observation matrix under irradiation based on the compressed sensing theory, and combines with the testability design test to obtain the number of errors after each irradiation, and then through nonlinear optimization, with less observation cost and less The test time efficiently and efficiently reflects the internal changes caused by the fault injection of the chip in the output.

The traditional fault injection must be synchronized with the key instruction processing inside the chip. In space, the fault injection tool must be focused on the chip sensitive register area. This requires a deep knowledge of the tester to perform a white box test. In the embodiment of the present invention, the laser can accurately focus the fault injection time and region of the chip to be tested, and the scanning register covered by the focused spot is used to control the enable port of the scan register by using a random switch to form a random observation matrix. To establish a stochastic observation matrix of compressed sensing.

In the embodiment of the present invention, the total number of errors is obtained by outputting the test vector, and then the internal sensitive point is obtained by the signal reconstruction algorithm, so that the reliability degree of the radiation effect of the chip can be quickly determined. In the embodiment of the present invention, the greedy algorithm is taken as an example for signal reconstruction, and other related algorithms may also be used.

In summary, the embodiment of the present invention can efficiently and effectively reflect the internal changes caused by the fault injection in the output result, and reduce the chip design in the test, because the testability design and the automatic test vector are performed. Understand and rely on testing experience. Due to the theory of compressed sensing, observation and signal reconstruction can be performed efficiently with less observation cost and less test time.

At present, the inventor has initially set up a laser fault injection test platform, using the Mai Tai Deepsee laser from Spectra-Physics of the United States and the A1MP+ series confocal microscope from Nikon. The former can provide adjustable power irradiation in the range of 680nm-1040nm. It adopts ultra-stable regenerative mold technology, the wavelength adjustment and excitation configuration are simple and easy to adjust, the beam direction is stable, the power fluctuation is small, and the wavelength drift is eliminated. The latter directly incorporates a femtosecond laser and has an optical path design that focuses the laser in a 1 μm space. With a suitable objective, the laser beam can be focused in a smaller space. The confocal microscope itself has a two-dimensional motorized stage that enables two-dimensional movement of the sample to achieve a fault injection attack across the entire surface of the electronic chip. The inventors have obtained preliminary results on the experimental platform that the circuit can be irradiated from the front side at a wavelength of around 900 nm, resulting in a stable error.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

The above described specific embodiments of the present invention are further described in detail, and are intended to be illustrative of the embodiments of the present invention. All modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims

A chip single particle effect detecting method, comprising:

Putting the chip to be tested into the test machine, triggering the single chip effect of the chip to be tested;

Randomly turning off the scan register of the chip to be tested to form a random observation matrix;

Providing an input test vector to the chip to be tested, obtaining an output test vector of the chip to be tested, and obtaining an error total vector according to the output test vector;

The compressed sensing signal is reconstructed from the total number of errors to determine the sensitive area inside the chip to be tested.
The method according to claim 1, wherein the triggering the chip to be tested to generate a single particle effect comprises: performing a fault injection on the chip to be tested by using a laser beam or a heavy ion microbeam.
The method according to claim 2, wherein said laser beam or heavy ion microbeam irradiation is used to perform fault injection on the chip to be tested, including: according to the laser beam or heavy ion during each irradiation of the test The microbeam aggregation size establishes a scanning unit.
The method according to claim 2, wherein said using the laser beam or the heavy ion microbeam to irradiate the chip to be tested for fault injection comprises: using a laser beam or a heavy ion microbeam to perform an arithmetic logic unit of the chip to be tested The decoder area is irradiated.
The method of claim 1 wherein said randomly turning off a scan register of the chip under test to form a random observation matrix comprises:

Forming a random observation matrix switch array by a serial-parallel decoder, outputting an enable signal to an enable port of a scan register of the chip to be tested, and randomly turning off a scan register of the chip to be tested to form a random observation matrix;

Or, by controlling the input test vector, the scan register of the chip to be tested is randomly turned off to form a random observation matrix.
The method of claim 1, wherein the randomly turning off the scan register of the chip to be tested to form a random observation matrix further comprises:

The two-dimensional movement of the chip to be tested is performed by the two-dimensional stage of the microscope, and the scan register that is randomly turned off is matched with the logic unit of the chip to be tested that is triggered to generate a single particle effect.
The method of claim 1 wherein said random observation matrix is as follows:

Where Φ is the random observation matrix, wherein the element a ji =0 indicates that the scan register corresponding to the i-th irradiated logic unit is turned off at the jth irradiation, j∈1, 2,... , M, i∈1, 2,..., N.
The method according to claim 7, wherein the input test vector is provided to the chip to be tested, the output test vector of the chip to be tested is obtained, and the error total vector is obtained according to the output test vector, including performing a compression observation on the signal X. ,get:

Where y j (j∈1, 2, ..., M) represents the total number of faults after each irradiation; X is the internal SEE sensitive area of the chip to be tested, X is
An array of x ji =0 indicates that the logical unit G i has SEE reliability under the jth irradiation, and x ji =1 indicates that the logical unit G i is an SEE sensitive region under the jth irradiation.
The method according to claim 1, wherein the reconstructing the perceptual signal vector for the error total vector to determine a sensitive area inside the chip to be tested comprises: compressing the total number of errors by using a linear programming algorithm or a nonlinear algorithm Perceive signal reconstruction to determine the sensitive area inside the chip to be tested.
A chip single-event effect detecting device, comprising:

a test machine for placing a chip to be tested, the chip to be tested comprising a scan register;

a triggering device for triggering a single particle effect of the chip to be tested;

a random observation matrix forming unit for randomly turning off a scan register of the chip to be tested to form a random observation matrix;

The test machine is further configured to provide an input test vector to the chip to be tested, obtain an output test vector of the chip to be tested, obtain an error total vector according to the output test vector, perform a compressed sensing signal reconstruction on the total error vector, and determine a chip to be tested. Internal sensitive area.
The chip single particle effect detecting apparatus according to claim 10, wherein said triggering means is a laser or a heavy ion microbeam generator.
The chip single particle effect detecting apparatus according to claim 11, wherein said laser or heavy ion microbeam generator is further used for irradiating an arithmetic logic unit and a decoder area of a chip to be tested.
The chip single-event effect detecting apparatus according to claim 10, wherein said random observation matrix forming unit comprises a random observation matrix switch array formed by a series-parallel decoder, said random observation matrix switch array being used for The enable port of the scan register of the chip to be tested outputs an enable signal, and randomly turns off the scan register of the chip to be tested to form a random observation matrix;

Alternatively, the random observation matrix forming unit is further configured to randomly turn off the scan register of the chip to be tested by controlling the input test vector to form a random observation matrix.
The chip single-event effect detecting apparatus according to claim 10, wherein the testing machine further comprises a two-dimensional stage of the microscope, wherein the chip to be tested is moved two-dimensionally, and each time the matrix is randomly observed. The scan register that forms the cell turn-off matches the logic cell of the chip under test that is triggered to produce a single particle effect.
The chip single-event effect detecting apparatus according to claim 10, wherein said random observation matrix forming unit is further configured to form a random observation matrix as follows:

Where Φ is the random observation matrix, wherein the element a ji =0 indicates that the scan register corresponding to the i-th irradiated logic unit is turned off at the jth irradiation, j∈1, 2, .. .,M,i∈1,2,...,N.
The chip single-event effect detecting apparatus according to claim 15, wherein the testing machine is further configured to perform a compression observation on the signal X to obtain:

Where y j (j∈1, 2, ..., M) represents the total number of faults after each irradiation; X is the internal SEE sensitive area of the chip to be tested, X is
An array of x ji =0 indicates that the logical unit G i has SEE reliability under the jth irradiation, and x ji =1 indicates that the logical unit G i is an SEE sensitive region under the jth irradiation.