JP2005107733A - Memory controller and memory control system and its method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To minimize the illegal operation of an SDRAM due to the change of a mode register value to be caused by the factor of an SEU(Single Event Upset) or the like. <P>SOLUTION: This SDRAM control system is incorporated in a memory device connected to a control/data bus or the like, and constituted of an SDRAM 103, an SDRAM controller 102 which performs SDRAM access control to the SDRAM 103 and a memory access device 101 which receives an instruction from a CPU or the like through a control/data bus or the like, and issues an SDRAM access instruction to the SDRAM controller 102. The SDRAM controller 102 performs mode register setting just before performing SDRAM access control to the SDRAM 103. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to control of a memory containing a register, and more particularly to control of a memory that copes with the occurrence of SEU.

  The SDRAM has a mode register that determines an operation mode of the SDRAM, such as a latency mode, a wrap type, and a burst length. The value of the mode register can be set by the user, but once set, the SDRAM holds the value of the mode register until the mode register value is reset or the power of the SDRAM is turned off.

  Therefore, conventionally, when the SDRAM is turned on, the mode register is set only once. Unless the user changes the operation mode required for the SDRAM or the SDRAM is turned off and turned on again, the mode register is set. Was never reset.

  Here, a conventional SDRAM control system will be described with reference to the drawings.

  As shown in FIG. 5, in a conventional SDRAM control system, when a user, CPU, or the like instructs SDRAM access (memory read, memory write, etc.), the memory access device outputs an SDRAM access command 301 to the SDRAM control device. . The SDRAM control device that has received the SDRAM access command 301 performs SDRAM control 304 on the SDRAM. The SDRAM control 304 performs SDRAM access control 303.

  When there is an SDRAM access command (“memory read”) from the memory access device, the SDRAM control 304 for the SDRAM access command (memory read command) is activated (ACT) in synchronization with the clock as shown in FIG. The read command (RD) and the precharge command (PRE) are sequentially issued to read data from the SDRAM.

Japanese Patent Application Laid-Open No. 11-213660

  However, when an SDRAM is used in a space device, the mode register value in the SDRAM that determines the operation mode of the SDRAM changes due to the occurrence of SEU (Single Event Upset).

  In SDRAM, since the SDRAM control protocol is performed according to the SDRAM operation mode, the SDRAM performs an illegal operation (an illegal operation means that the SDRAM does not operate in the operation mode expected by the user) due to a change in the mode register value. There was a problem that would not work as expected.

  In addition, since the value of the mode register in the SDRAM cannot generally be monitored from the outside, it is not possible to detect in advance an illegal operation of the SDRAM due to a change in the value of the mode register caused by factors such as SEU. There was no means to effectively solve the problem.

  Accordingly, in order to solve such a problem, a memory control device according to the present invention is a memory control device that receives a memory access command from a memory access device to a memory having a register and performs memory control on the memory. When a memory access command is received from the memory access device, a mode register setting is performed in the memory prior to memory control, and the mode register setting is performed each time a memory access command is received from the memory access device. desirable.

  The memory control system according to the present invention includes a memory having a built-in register, a memory control device that performs memory control on the memory, and a memory access device that issues a memory access command to the memory control device. In the memory control system, when the memory control device receives a memory access command from the memory access device, the memory control device performs mode register setting in the memory prior to memory control, and the mode register setting is transmitted from the memory access device. It is desirable to do this whenever there is a memory access command.

The memory control method according to the present invention is a memory control device that performs memory control on a memory in response to a memory access command from the memory access device.
When a memory access command is received from the memory access device, it is preferable to set a mode register in the memory prior to memory control, and the mode register setting is preferably performed every time there is a memory access command from the memory access device. .

  As described above, according to the present invention, the mode register is set immediately before the access control is performed, so that the mode caused by factors such as SEU is not monitored from the outside without monitoring the value of the mode register in the SDRAM. Unauthorized operation of the SDRAM due to changes in register values can be minimized.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an SDRAM control system according to the present invention.

  The SDRAM control system is built in a memory device connected to a control / data bus or the like, and includes an SDRAM 103, an SDRAM control device 102 for controlling SDRAM access to the SDRAM 103, a CPU (not shown) via the control / data bus, and the like. And a memory access device 101 that receives an instruction from the memory control device 102 and issues an SDRAM access command to the SDRAM control device 102.

  The SDRAM 103 and the memory access device 101 are well-known and perform normal operations, but the SDRAM control device 102 is set to set the mode register for the SDRAM 103 immediately before performing SDRAM access control.

  Next, the operation of the SDRAM control system according to the present invention will be described with reference to the drawings. 2 shows an operation flow of the present invention, FIG. 3 shows a time chart of the first mode, and FIG. 4 shows a time chart of the second mode.

  When a user, CPU, or the like instructs SDRAM access (memory read, memory write, etc.), the memory access device 101 outputs an SDRAM access command 201 to the SDRAM control device 102. The SDRAM access command 201 indicates a memory read command, a memory write command, or the like.

  The SDRAM control device 102 that has received the SDRAM access command 201 performs SDRAM control 204 on the SDRAM 103. The SDRAM control 204 first performs mode register setting 202 for the SDRAM 103, and then performs SDRAM access control 203 as in the conventional case. Actually, the SDRAM control 204 is performed by adding the mode register setting command 202 to the head of the SDRAM access control 203.

  In other words, since the SDRAM access control 203 is performed according to the SDRAM operation mode, by performing the mode register setting 202 immediately before the SDRAM access control 203, the SDRAM access control 203 is performed at the timing when the mode register value change probability due to SEU is the lowest. The access control 203 can be performed.

  Details of the SDRAM control 204 are shown in FIGS.

  FIG. 3 shows a case where the SDRAM access command 201 from the memory access device 101 is once (“memory read”), and FIG. 4 shows a case where the SDRAM access command 201 from the memory access device 101 is multiple times (in this example “memory” "Read" and "Memory write").

  First, an operation when the SDRAM access command 201 is once (“memory read”) will be described.

  As shown in the figure, the SDRAM control 204 in response to the SDRAM access command (memory read command) first issues a mode register setting command in synchronization with the clock to set the mode register of the SDRAM 103, and then activates (ACT). ), A read command (RD), and a precharge command (PRE) are sequentially issued to access the SDRAM.

  Next, the operation when the SDRAM access command 201 is performed a plurality of times (in this example, “memory read” and “memory write” twice) will be described.

  When the first SDRAM access command 201 is output from the memory access device 101 to the SDRAM control device 102, the SDRAM control device 102 sends an SDRAM control 204 with the mode register setting 202 added to the head of the SDRAM access control 203 to the SDRAM 103. Do. The SDRAM control 204 first issues a mode register setting command in synchronization with the clock to set the mode register of the SDRAM, and then activates (ACT), a read command (RD), and a precharge command (PRE). By issuing sequentially, data is read from the SDRAM.

  When the first SDRAM control 204 is completed and the second SDRAM access command 201 is output to the SDRAM control device 102, the SDRAM control device 102 performs the second SDRAM control 204.

  Also in the second SDRAM control 204 at this time, as in the first SDRAM control 204, the mode register setting 203 is performed immediately before the SDRAM access control (write protocol) 203, and thereafter, activation (ACT), Data is written to the SDRAM by sequentially issuing a write command (WR) and a precharge command (PRE).

  In each of the above embodiments, the SDRAM is used as the memory. However, since the present invention deals with a change in the mode register value due to the generation of SEU, the present invention is not limited to the SDRAM. And all of the memories with built-in registers such as flash memory.

1 shows a block diagram of an SDRAM control system according to the present invention. The operation | movement flow of this invention is shown. The time chart of the 1st mode is shown. The time chart of the 2nd mode is shown. The operation | movement flow of the conventional SDRAM control system is shown. The conventional time chart is shown. ;

Explanation of symbols

101: Memory access device 102: SDRAM control device 103: SDRAM
201, 301: SDRAM access command 202: Mode register setting 203, 303: SDRAM access control 204, 304: SDRAM control

Claims (6)

In a memory control device that performs memory control on the memory in response to a memory access command for a memory having a built-in register from the memory access device,
When a memory access command is received from the memory access device, a mode register is set in the memory prior to memory control. 2. The memory control device according to claim 1, wherein the mode register setting is performed every time a memory access command is issued from the memory access device. In a memory control system having a memory incorporating a register, a memory control device that performs memory control on the memory, and a memory access device that issues a memory access command to the memory control device,
The memory control device, when receiving a memory access command from the memory access device, sets a mode register in the memory prior to memory control. 4. The memory control device according to claim 3, wherein the mode register setting is performed every time a memory access command is issued from the memory access device. In a memory control device that performs memory control on a memory in response to a memory access command from the memory access device,
When a memory access command is received from the memory access device, a mode register is set in the memory prior to memory control. 6. The memory control method according to claim 5, wherein the mode register setting is performed every time a memory access command is issued from the memory access device.

Images