WO2018000495A1 - Procédé et dispositif de détection d'effet d'une particule isolée de puce - Google Patents

Procédé et dispositif de détection d'effet d'une particule isolée de puce Download PDF

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Publication number
WO2018000495A1
WO2018000495A1 PCT/CN2016/092256 CN2016092256W WO2018000495A1 WO 2018000495 A1 WO2018000495 A1 WO 2018000495A1 CN 2016092256 W CN2016092256 W CN 2016092256W WO 2018000495 A1 WO2018000495 A1 WO 2018000495A1
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chip
tested
observation matrix
scan register
random observation
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PCT/CN2016/092256
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English (en)
Chinese (zh)
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李慧云
邵翠萍
刘玢玢
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中国科学院深圳先进技术研究院
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Publication of WO2018000495A1 publication Critical patent/WO2018000495A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/308—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
    • G01R31/311—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation of integrated circuits

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  • the present invention relates to the field of integrated circuit technology, and in particular, to a chip single particle effect detecting method and apparatus.
  • FIG. 1 is a schematic diagram of a semiconductor single-particle effect caused by incident high-energy particles in the prior art. As shown in FIG. 1 , a single-particle effect causes an electronic device to deviate from normal functions and performance, resulting in a decrease in chip reliability or even failure.
  • Single event latch-up SEL
  • Single event upset SEU
  • single-event function interrupt Single-event function interrupt
  • SEFI Event functional interrupt
  • SEB single event burnout
  • Unrecoverable error or “hard error” refers to an error that causes a fatal permanent damage to the device or system, such as SEB
  • Recoverable error or “soft error” means restarting Methods such as device or rewriting of data can restore normal errors such as SEU, SET, SED, etc.
  • the single-particle latch SEL and the single-event flip SEU are two single-particle effects with high frequency of occurrence.
  • Embodiments of the present invention provide a chip single-event effect detecting method for efficiently and conveniently detecting a single-particle effect of a chip, and the method includes:
  • the compressed sensing signal is reconstructed from the total number of errors to determine the sensitive area inside the chip to be tested.
  • the embodiment of the invention further provides a chip single-event effect detecting device for detecting the single-particle effect of the chip efficiently and conveniently, and the device comprises:
  • test machine for placing a chip to be tested, the chip to be tested comprising a scan register
  • a triggering device for triggering a single particle effect of the chip to be tested
  • a random observation matrix forming unit for randomly turning off a scan register of the chip to be tested to form a random observation matrix
  • the test machine is further configured to provide an input test vector to the chip to be tested, obtain an output test vector of the chip to be tested, obtain an error total vector according to the output test vector, perform a compressed sensing signal reconstruction on the total error vector, and determine a chip to be tested. Internal sensitive area.
  • the chip to be tested is placed in the test machine, triggering the chip to be tested to generate a single particle effect; randomly scanning the scan register of the chip to be tested to form a random observation matrix; providing an input test vector to the chip to be tested, The output test vector of the chip to be tested obtains the error total vector according to the output test vector; performs compression sensing signal reconstruction on the total error vector to determine the sensitive internal area of the chip to be tested; and can efficiently and efficiently make the internal change of the chip due to fault injection
  • the results are reflected in the output, and reduce the understanding of the chip design and the dependence on the test experience; the observation and signal reconstruction can be performed efficiently with less observation cost, less test time.
  • FIG. 1 is a schematic view showing a semiconductor single particle effect caused by incident high energy particles in the prior art
  • FIG. 2 is a schematic diagram of a method for detecting a single particle effect of a chip according to an embodiment of the present invention
  • FIG. 3 is a block diagram of a signal observation and reconstruction method for detecting a SEU inside a chip by using compressed sensing in an embodiment of the present invention
  • FIG. 4 is a schematic diagram of scanning irradiation of a chip in an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a signal reconstruction process of a SEE sensitive point X according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of a chip single particle effect detecting device according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a logic unit in each irradiation required to match a randomly enabled scan register in an embodiment of the present invention
  • FIG. 8 is a schematic diagram of tasks and cooperation of a fault injection device and a compression sensing test machine according to an embodiment of the present invention.
  • the inventors have found that the use of pulsed lasers to test the reliability of single-event effects in the prior art faces inefficiencies and cumbersome problems, because the radiation effect test of existing chips requires test engineers to repeatedly scan and scan chips under laser irradiation for a long time. The output is used to analyze and judge the internal reliability of the chip. Even if you get the wrong result, you need to combine the fault analysis method (Fault Analysis) to analyze the data to find the vulnerability in the chip.
  • This aspect is due to the fact that the laser irradiation must be synchronized with the key instruction processing inside the chip in time, and the fault injection tool must be spatially focused on the chip sensitive register area, which requires a long-term exploration by a tester with deep professional knowledge.
  • the embodiment of the present invention provides a method for detecting a single-particle effect of a chip by using a compressed sensing theory, which has the characteristics of losslessness and high efficiency.
  • 2 is a schematic diagram of a method for detecting a single-particle effect of a chip according to an embodiment of the present invention. As shown in FIG. 2, the method may include:
  • Step 201 Put the chip to be tested into the testing machine, and trigger the chip to be tested to generate a single particle effect;
  • Step 202 Randomly turn off the scan register of the chip to be tested to form a random observation matrix
  • Step 203 providing an input test vector to the chip to be tested, obtaining an output test vector of the chip to be tested, and obtaining an error total vector according to the output test vector;
  • Step 204 Perform compression sensing signal reconstruction on the error total vector to determine a sensitive area inside the chip to be tested.
  • the chip to be tested is triggered to generate a single particle effect, and the scanning register of the chip to be tested is randomly turned off to form a random observation matrix.
  • the number vector enables testability design and automated test vectors, so it can efficiently and efficiently reflect the internal changes caused by fault injection in the output of the chip, and reduce the understanding of the chip design and the dependence on the test experience.
  • the perceptual signal reconstruction of the total number of errors By compressing the perceptual signal reconstruction of the total number of errors, the sensitive area inside the chip to be tested is determined, so that observation and signal reconstruction can be performed efficiently with less observation cost and less test time.
  • the embodiment of the present invention studies the testability design and the corresponding test method based on the compressed sensing theory.
  • the overall design idea is as follows: 1) Insert the register into the scan chain during the chip design process (if it is a cryptographic chip, it can only contain no key) The information register is inserted into the scan chain), and then a radiation effect reliability test vector is generated to avoid key related information leakage due to the insertion of the scan chain. Control each scan register for establishing a random observation matrix during testing; 2) Using the fault injection in the test phase after the chip is manufactured, based on the compressed sensing theory, control the shutdown scan register on the test machine to form a random observation matrix. By outputting the test vector to obtain the error total vector, and then obtaining the internal sensitive points through the signal reconstruction algorithm, the security level of the cryptographic chip or the SEE reliability of the avionics can be quickly determined.
  • the single-event effect detection method of the embodiment of the invention can combine the compression sensing, high-precision fault injection technology and DFT (Design for Test) technology to form an observation matrix, which greatly reduces the number of sensors or detectors required in the existing method.
  • FIG. 3 is a block diagram showing the principle of signal observation and reconstruction used by the compressed sensing for detecting the internal SEU of the chip in the embodiment of the present invention. As shown in FIG. 3, in the embodiment of the present invention, the SEU sensitive point original signal of the chip is randomly observed and compressed, and the SEU sensitive point signal can be reconstructed.
  • the chip to be tested is first placed in the test machine, which triggers the single-particle effect of the chip to be tested.
  • the chip to be tested is placed in the test machine, triggering the single-particle effect of the chip to be tested, and the laser fault injection technology can be used.
  • the laser fault injection technology can be used.
  • other single particles can be used. Effect triggering methods, such as heavy ion beam irradiation, or other radiation environments.
  • the compressive sensing theory and the fault injection technology can be combined to perform the testability design and the corresponding test process, randomly turn off the scan register of the chip to be tested, form a random observation matrix, and provide an input test vector to the chip to be tested.
  • the output test vector of the chip to be tested obtains the error total vector according to the output test vector; the compressed sensing signal is reconstructed for the total error vector to determine the sensitive area inside the chip to be tested.
  • the realization of the theory of compressed sensing contains three key elements: sparsity, uncorrelated observation, and nonlinear optimization reconstruction.
  • the sparseness of the signal is a necessary condition for the compressed sensing.
  • the uncorrelated observation is the key to the compressed sensing.
  • the nonlinear optimization is the means of compressing the perceived signal.
  • an unrelated observation matrix ⁇ M ⁇ N (M ⁇ ⁇ N) is designed, so that the signal energy is not destroyed when the internal fault point X is reduced from N to M dimensions.
  • the random observation matrix can be obtained as follows:
  • FIG. 4 is a schematic diagram of the scanning irradiation of the chip in the embodiment of the present invention, as shown in FIG. 4, wherein the ALU
  • the (arithmetic logic unit) and decoder (decoder) regions are the key irradiation ranges, taking the laser beam irradiation as an example.
  • the small frame in Fig. 4 is the primary beam focusing range (only the illustration, the actual ratio is smaller than the illustration), The circular extent of the beam is approximated by a square in Figure 4.
  • the experimental data shows that the irradiation spot diameter is about 3.7 ⁇ m, covering about 10 to 15 logic cells (also called logic gates).
  • the 3.7 ⁇ m laser spot covers 160-240 logic gates, and so on.
  • triggering the chip to be tested to generate a single particle effect may include: performing a fault injection on the chip to be tested by using a laser beam or a heavy ion microbeam.
  • Using the laser beam or heavy ion microbeam irradiation to perform fault injection on the chip to be tested may include: establishing a scanning unit according to the laser beam or the heavy ion microbeam irradiation aggregation size during each irradiation of the test.
  • the arithmetic logic unit and the decoder region of the chip to be tested may be irradiated by laser beam or heavy ion microbeam irradiation.
  • Figure 4 shows the different logic cells covered by the chip under two exposures. Assuming that the logical unit (G 1 , G 4 , G 6 , G 9 , ...) of the p-th irradiation, the SEE sensitivity signals are [x 1 , x 4 , x 6 , x 9 , ..
  • the random observation matrix needs to be controlled so that the coefficient a pi of the array x pi in the formula (1), that is, some coefficients of [a p1 , a p4 , a p6 , a p9 ,...] are 1, and the rest are 0; the logical gates of the qth irradiation (G 3 , G 5 , G 7 , G 8 , ...), whose SEE sensitivity signals are [x 3 , x 5 , x 7 , x 8 , .. .], the random observation matrix needs to be controlled so that some coefficients in the array [a q3 , a q5 , a q7 , a q8 ,...] are 1 and the rest are 0.
  • the method may include: forming a random observation matrix switch array by the serial-parallel decoder, and outputting to the enable port of the scan register of the chip to be tested. Enable the signal, randomly turn off the scan register of the chip to be tested, and form a random observation matrix; or, by controlling the input test vector, randomly turn off the scan register of the chip to be tested to form a random observation matrix, that is, randomly controlled by the input test vector Whether the error result that may occur in a scan register is included in the total number of errors to form a random observation matrix.
  • the scan register of the chip to be tested is randomly turned off, and when the random observation matrix is formed, the two-dimensional movement of the chip to be tested by the two-dimensional stage of the microscope may be further included, and the scan register that is randomly turned off each time is The logic cells of the chip under test that trigger the single-particle effect are matched.
  • FIG. 5 is a schematic diagram of a signal reconstruction process of a SEE sensitive point X according to an embodiment of the present invention.
  • the design of the reconstruction algorithm directly affects the quality of signal reconstruction.
  • the compressed sensing signal reconstruction of the total number of errors is performed to determine the sensitive area inside the chip to be tested, which may include: performing a compressed sensing signal reconstruction on the total number of errors using a linear programming algorithm or a nonlinear algorithm to determine the internal sensitivity of the chip to be tested. region.
  • the nonlinear computing property can be, for example, a greedy algorithm.
  • the greedy algorithm has low computational complexity and can simplify hardware integration.
  • the greedy algorithm can gradually reduce the error, and finally complete the signal reconstruction of the SEE sensitive point X, and obtain the SEU reliability fault inside the chip.
  • a combination of a linear programming algorithm and a nonlinear algorithm may be used to perform compressed sensing signal reconstruction on the error total vector, or other related algorithms.
  • FIG. 6 is a schematic diagram of a single-particle effect detecting device for a chip according to an embodiment of the present invention. As shown in FIG. 6, the device may include:
  • a test machine 601 configured to put a chip to be tested, the chip to be tested includes a scan register;
  • the triggering device 602 is configured to trigger a single particle effect of the chip to be tested
  • the random observation matrix forming unit 603 is configured to randomly turn off the scan register of the chip to be tested to form a random observation matrix
  • the test machine 601 is further configured to provide an input test vector to the chip to be tested, obtain an output test vector of the chip to be tested, obtain an error total vector according to the output test vector, and perform compression sensing signal reconstruction on the total error vector to determine the internal chip to be tested. Sensitive area.
  • the triggering device may be a fault injecting device, such as a laser, such as a nanosecond laser, a picosecond laser or a femtosecond laser; or may be a heavy ion microbeam generator or the like.
  • the laser or heavy ion microbeam generator can be further used to irradiate the arithmetic logic unit and decoder region of the chip under test.
  • the random observation matrix forming unit may include a random observation matrix switch array formed by a parallel-parallel decoder, and the random observation matrix switch array is configured to output an enable signal to an enable port of a scan register of the chip to be tested, The scan register of the chip to be tested is randomly turned off to form a random observation matrix; or, the random observation matrix forming unit may be further configured to randomly turn off the scan register of the chip to be tested by controlling the input test vector to form a random observation matrix.
  • the test machine may further include a two-dimensional stage of the microscope for performing two-dimensional movement of the chip to be tested, and each of the scan registers that are randomly turned off and the logic of the chip to be tested that are triggered to generate a single particle effect The units match.
  • the random observation matrix forming unit is further used to form a random observation matrix as follows:
  • test machine is further configured to perform a compression observation on the signal X to obtain:
  • y j (j ⁇ 1, 2, ..., M) represents the total number of faults after each irradiation
  • X is the internal SEE sensitive area of the chip to be tested
  • FIG. 7 is a schematic diagram of the logic unit under each irradiation in the embodiment of the present invention matched with the randomly enabled scan register.
  • Figure 7 shows the random observation matrix switch array and the chip mother board to be tested on the test machine.
  • the random observation matrix switch array is connected to the scan register enable port of the chip to be tested, and the scan register is randomly turned off by the enable signal. Due to the huge internal signal point data, considering the switching speed, the random observation matrix ⁇ can be obtained by the method of serial-parallel decoder.
  • the random observation matrix switch array data on the device is reconstructed by compressing the sensing signal, and the two-dimensional movement of the chip is realized by the two-dimensional stage of the microscope, so that each time the matrix array array is randomly observed, the array is enabled.
  • the scan register is matched to the irradiated chip logic unit.
  • the sample displacement control command can be used to control the laser injection of the chip and return to the control state signal.
  • FIG. 8 is a schematic diagram of tasks and cooperation between a fault injection device and a compression sensing test machine according to an embodiment of the present invention. As shown in FIG. 8 , the fault injection device and the compression sensing test machine are synchronously controlled, and the fault injection device controls the p.
  • the total number of faults after each irradiation can be obtained with a high test coverage with less test vectors y j (j ⁇ 1, 2,..., M)
  • the single-particle effect (SEE) sensitive point in the chip is analogized to the signal to be observed with sparsity, so the method of compressed sensing can be used to perform the detection without loss and high efficiency.
  • the radiation effect reliability test of the chip requires the test engineer to repeatedly scan the sampling chip for a long time, and analyze and judge the internal reliability of the chip only by the output result. Even if you get the wrong result, you need to combine the fault analysis method (Fault Analysis) to analyze the data to find the vulnerability in the chip. How to perform the radiation effect reliability test on the chip and efficiently and efficiently reflect the internal change caused by the fault injection on the output result is one of the key problems to be solved by the embodiment of the present invention.
  • the embodiment of the present invention combines the random observation matrix under irradiation based on the compressed sensing theory, and combines with the testability design test to obtain the number of errors after each irradiation, and then through nonlinear optimization, with less observation cost and less
  • the test time efficiently and efficiently reflects the internal changes caused by the fault injection of the chip in the output.
  • the traditional fault injection must be synchronized with the key instruction processing inside the chip.
  • the fault injection tool In space, the fault injection tool must be focused on the chip sensitive register area. This requires a deep knowledge of the tester to perform a white box test.
  • the laser can accurately focus the fault injection time and region of the chip to be tested, and the scanning register covered by the focused spot is used to control the enable port of the scan register by using a random switch to form a random observation matrix. To establish a stochastic observation matrix of compressed sensing.
  • the total number of errors is obtained by outputting the test vector, and then the internal sensitive point is obtained by the signal reconstruction algorithm, so that the reliability degree of the radiation effect of the chip can be quickly determined.
  • the greedy algorithm is taken as an example for signal reconstruction, and other related algorithms may also be used.
  • the embodiment of the present invention can efficiently and effectively reflect the internal changes caused by the fault injection in the output result, and reduce the chip design in the test, because the testability design and the automatic test vector are performed. Understand and rely on testing experience. Due to the theory of compressed sensing, observation and signal reconstruction can be performed efficiently with less observation cost and less test time.
  • the inventor has initially set up a laser fault injection test platform, using the Mai Tai Deepsee laser from Spectra-Physics of the United States and the A1MP+ series confocal microscope from Nikon.
  • the former can provide adjustable power irradiation in the range of 680nm-1040nm. It adopts ultra-stable regenerative mold technology, the wavelength adjustment and excitation configuration are simple and easy to adjust, the beam direction is stable, the power fluctuation is small, and the wavelength drift is eliminated.
  • the latter directly incorporates a femtosecond laser and has an optical path design that focuses the laser in a 1 ⁇ m space. With a suitable objective, the laser beam can be focused in a smaller space.
  • the confocal microscope itself has a two-dimensional motorized stage that enables two-dimensional movement of the sample to achieve a fault injection attack across the entire surface of the electronic chip.
  • the inventors have obtained preliminary results on the experimental platform that the circuit can be irradiated from the front side at a wavelength of around 900 nm, resulting in a stable error.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

La présente invention concerne un procédé et un dispositif de détection d'effet d'une particule isolée de puce, le procédé comprenant : le placement d'une puce à détecter dans une machine d'essai, et le déclenchement de la puce à détecter pour générer un effet d'une particule isolée ; la désactivation aléatoire d'un registre de balayage pour la puce à détecter, et la formation d'une matrice d'observation aléatoire ; la fourniture d'un vecteur de test d'entrée pour la puce à détecter de façon à obtenir un vecteur de test de sortie de la puce à détecter, et l'obtention d'un vecteur total d'erreur en fonction du vecteur de test de sortie ; et la conduite d'une reconstruction de signal de détection compressé sur le vecteur total d'erreur, et la détermination d'une région sensible interne de la puce à détecter. Le procédé peut être utilisé pour détecter de façon efficace et pratique l'effet d'une particule isolée d'une puce.
PCT/CN2016/092256 2016-06-27 2016-07-29 Procédé et dispositif de détection d'effet d'une particule isolée de puce WO2018000495A1 (fr)

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* Cited by examiner, † Cited by third party
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CN109558649A (zh) * 2018-11-08 2019-04-02 北京控制工程研究所 一种面向宇航芯片的寄存器单粒子效应模拟仿真方法
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CN111680470A (zh) * 2020-05-26 2020-09-18 西北核技术研究院 一种数字信号处理器版图分布定位方法
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040124876A1 (en) * 2002-12-30 2004-07-01 Actel Corporation Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array
JP2005107733A (ja) * 2003-09-29 2005-04-21 Nec Engineering Ltd メモリ制御装置、システム及び方法
CN102854456A (zh) * 2011-06-28 2013-01-02 中国科学院电子学研究所 可编程逻辑器件单粒子辐照性能测试系统
CN103473159A (zh) * 2013-10-13 2013-12-25 西安电子科技大学 基于动态重构的fpga配置信息翻转测试平台及测试方法
WO2015051175A2 (fr) * 2013-10-03 2015-04-09 Orbotech Ltd. Application de sondes à plasma induit par faisceau électronique pour inspection, essai, débogage et modifications de surface
CN104793080A (zh) * 2015-04-16 2015-07-22 西安交通大学 一种片上系统单粒子效应测试方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642725B2 (en) * 2001-06-28 2003-11-04 Chung-Shan Institute Of Science And Technology Method of testing radiation for a SDRAM
CN102402475B (zh) * 2010-09-15 2014-12-03 北京圣涛平试验工程技术研究院有限责任公司 一种宇航用cpu单粒子效应试验方法
CN103021469A (zh) * 2012-11-30 2013-04-03 北京时代民芯科技有限公司 一种存储器电路的通用单粒子效应检测方法
CN104346272B (zh) * 2013-07-24 2018-04-10 无锡华润微电子有限公司 芯片自动仿真验证系统
CN105589780A (zh) * 2014-10-22 2016-05-18 北京圣涛平试验工程技术研究院有限责任公司 Cpu中子单粒子效应试验方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040124876A1 (en) * 2002-12-30 2004-07-01 Actel Corporation Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array
JP2005107733A (ja) * 2003-09-29 2005-04-21 Nec Engineering Ltd メモリ制御装置、システム及び方法
CN102854456A (zh) * 2011-06-28 2013-01-02 中国科学院电子学研究所 可编程逻辑器件单粒子辐照性能测试系统
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