WO2018191837A1

WO2018191837A1 - Method and device for detecting total dose effect

Info

Publication number: WO2018191837A1
Application number: PCT/CN2017/080692
Authority: WO
Inventors: 邵翠萍; 李慧云
Original assignee: 深圳先进技术研究院
Priority date: 2017-04-17
Filing date: 2017-04-17
Publication date: 2018-10-25

Abstract

The invention is applicable to the technical field of electronic information. Provided are a method and device for detecting a total dose effect. The method comprises: carrying out a design for testability on a circuit in a chip to be tested; constructing an original signal of the total dose effect of the chip to be tested to generate an observation matrix of the original signal and a test vector set corresponding to a row vector in the observation matrix; carrying out total dose irradiation on a pre-set number of chips to be tested, and testing a corresponding irradiated chip to be tested using all the test vector sets to determine whether an error occurs in the irradiated chip to be tested; and when an error occurs, generating a compressed sensing equation according to all the test results and the observation matrix, and generating the distribution of logic units sensitive to the total dose effect inside the chip to be tested by means of a pre-set signal reconstruction algorithm and the compressed sensing equation. Thus, in conjunction with the design for testability and the compressed sensing theory, the state of each logic unit inside the chip to be tested after the total dose irradiation is observed, and a logic unit sensitive to the total dose effect inside the chip to be tested is efficiently and accurately positioned.

Description

Method and device for detecting total dose effect

Technical field

The invention belongs to the field of electronic information technology, and in particular relates to a method and a device for detecting total dose effects.

Background technique

The radiation particles in the space radiation environment will have a serious impact on the spacecraft's electronic system, causing various radiation effects. The radiation effects that have the greatest impact on the semiconductor are the total dose effect and the single-particle effect. The total dose effect of the integrated circuit is currently In the space electronics field, the key and difficult problems in the study of irradiation effects, the total dose effect will lead to the drift of the threshold voltage of a single MOS device, and also lead to the circuit speed reduction, electrical parameter drift, power consumption increase and even functional failure of the integrated circuit.

At present, the reliability test method based on total dose effect is mainly based on simulated radiation source for ground test. In-situ test and shift test can be used in the test. For some devices or under certain conditions, annealing test is also required. In the test of dose effect, the changes of electrical parameters and circuit function parameters under certain radiation doses are mainly monitored statistically, and the mechanism of total dose effect of circuits or devices is analyzed according to parameter changes. In the large-scale integrated circuit, limited by the chip test port, this way can not observe the state of each logic unit inside the chip, can not accurately find the critical condition of the circuit function failure, and can not locate the distribution of the failed logic unit, so It is impossible to conduct an accurate and efficient study of the logic unit failure mechanism.

In addition, the total dose effect is a major threat to security for chips used for cryptographic security. The total dose effect can be used as an important attack method for error injection attacks. The accumulation of radiation dose may cause errors in the encryption and decryption operations of the cryptographic circuit, causing leakage of password information. Therefore, it is very important to study the total dose effect of the security chip. urgent. However, the current research on the total dose effect is more concerned with the reliability of the circuit, and does not conduct in-depth research on the security of the cryptographic circuit. The unified test analysis method only evaluates the statistical performance of the overall circuit. It does not test the logic unit that is sensitive to the total dose radiation in the circuit, and can not locate these sensitive units, so it cannot guide the reliability and safety design of the chip. .

Summary of the invention

The object of the present invention is to provide a method and a device for detecting the total dose effect, which aims to solve the problem that the state of each logic unit inside the chip after the total dose irradiation cannot be observed due to the prior art, and the in-chip pair can not be located. The problem of dose-sensitive logic units.

In one aspect, the invention provides a method of detecting a total dose effect, the method comprising the steps of:

Testability design of the circuit in the chip to be tested;

Constructing an original signal of the total dose effect of the chip to be tested, and generating an observation matrix of the original signal;

Generating a corresponding test vector set according to the row vector in the observation matrix;

Performing total dose irradiation on a preset number of the chips to be tested, and testing the corresponding chips to be tested after the irradiation by using all test vector sets to determine whether the chip to be tested after the irradiation is in error;

When it is determined that the irradiated chip to be tested is in error, generating a compressed sensing equation according to the test result of the all test vector sets and the observation matrix, according to the compressed sensing equation and a preset signal reconstruction algorithm, Generating and outputting a distribution of sensitive logic cells for the total dose effect inside the chip to be tested.

In another aspect, the present invention provides a total dose effect detecting device, the device comprising:

a circuit design module for testability design of circuits in the chip to be tested;

a matrix generating module, configured to construct an original signal of the total dose effect of the chip to be tested, and generate an observation matrix of the original signal;

a vector set generation module, configured to generate a corresponding test vector set according to the row vector in the observation matrix;

An irradiation test module is configured to perform total dose irradiation on a preset number of the chips to be tested, and test the corresponding chips to be tested after irradiation by using all test vector sets to determine the to-be-tested after the irradiation Whether the chip is wrong; and

a sensitive output module, configured to generate a compressed sensing equation according to the test result of the test vector set and the observation matrix when determining the error of the chip to be tested after the irradiation, according to the compressed sensing equation and the preset The signal reconstruction algorithm generates and outputs a distribution of sensitive logic units of the total dose effect inside the chip to be tested.

The measurable design of the circuit in the chip to be tested is the original signal of the total dose effect of the chip structure after the measurability design, and according to the compressed sensing theory, the observation matrix of the original signal is generated, and each row of the observation matrix is generated. The test vector set corresponding to the vector, and then performing total dose irradiation on a preset number of identical chips to be tested simultaneously, and testing the corresponding chip to be tested after the irradiation by all the test vector sets, and determining the chip to be tested according to the test result Whether there is an error under irradiation, when an error occurs, according to all the test results and the observation matrix, a compression sensing equation for generating a total dose effect reconstruction signal of the chip to be tested is constructed, and the total internal dose of the chip to be tested can be generated according to the reconstructed signal. The distribution of sensitive logic elements of the effect, so that the internal state of the chip under test in the total dose radiation environment is reflected by the test result corresponding to the test vector set of the subsequent configuration through the controllability and observability of the testability design, through compression Perceptual theory improves signal reconstruction efficiency and reconstruction accuracy, and locates the chip under test efficiently and accurately Effect of total dose sensitive logic, and thus can be quickly determined the relationship between the degree of reliability of the irradiation of the radiation effect and the total dose effect of the chip under test.

DRAWINGS

1 is a flowchart showing an implementation of a method for detecting a total dose effect according to Embodiment 1 of the present invention;

2 is a distribution diagram of a sensitive logic unit of a total dose effect inside a chip to be tested according to Embodiment 1 of the present invention;

3 is a relationship diagram of redundancy ratio and reconstruction accuracy in a process of distributing a sensitive logic unit for generating a total dose effect of a chip to be tested according to Embodiment 1 of the present invention;

4 is a flowchart showing an implementation of a method for detecting a total dose effect according to Embodiment 2 of the present invention;

5 is a schematic structural view of a total dose effect detecting device according to Embodiment 3 of the present invention;

FIG. 6 is a schematic structural view of a detecting device for total dose effect according to Embodiment 4 of the present invention.

detailed description

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The specific implementation of the present invention is described in detail below in conjunction with specific embodiments:

Embodiment 1:

FIG. 1 is a flowchart showing an implementation process of a method for detecting a total dose effect according to Embodiment 1 of the present invention. For convenience of description, only parts related to the embodiment of the present invention are shown, which are described in detail as follows:

In step S101, the circuit in the chip to be tested is designed for testability.

Embodiments of the present invention are applicable to systems or platforms for the distribution of sensitive logic cells that test the total dose effect within the chip. Testability design of the circuit in the chip to be tested, using the controllability and observability of the testability design to pass the internal state of the chip under test under the total dose irradiation through the test result corresponding to the test vector set of the subsequent construction Reacted. Specifically, the number of scan chains may be determined according to the scale of the circuit in the chip to be tested, and then the testable design tool (for example, DFT Compiler) is used to insert the registers in the circuit into the scan chain by full scan.

In step S102, an original signal of the total dose effect of the chip to be tested is constructed, and an observation matrix of the original signal is generated.

In the embodiment of the present invention, the original signal of the total dose effect of the chip to be tested may be constructed according to the sensitivity state of the logic unit to the total dose effect in the chip to be tested, and the sensitivity state of the total internal dose of the chip to be tested may be determined according to the chip to be tested. The properties of the internal logic unit are determined. Specifically, the original signal can be expressed as X=[x ₁ , x ₂ , . . . , x _i , . . . , x _N ] ^Τ , where x _i represents that the logic unit R _i in the chip to be tested is under the total dose effect irradiation Reliable or sensitive, when x _i =0, the logic unit R _i can be considered to have reliability under total dose effect irradiation, and when x _i =1, the logic unit R _i can be considered to be sensitive under total dose effect irradiation. N is the total number of logical units in the chip to be tested.

In the embodiment of the present invention, the number or distribution of the sensitive logic units in the circuit is sparse compared with all the logic units in the circuit, and the original signal is considered to be sparse, so the step of sparsely transforming the original signal in the compressed sensing is omitted. Or, it can be understood that the sparse basis matrix of the original signal is an identity matrix.

In the embodiment of the present invention, the observation matrix of the original signal is constructed, and according to the compressed sensing theory, it can be known that the constraint equidistance or incoherence should be satisfied between the observation matrix and the sparse basis matrix, since any given matrix is combined with a random matrix. It has great incoherence and often uses a random matrix as the observation matrix. In the embodiment of the present invention, the original signal is a 0-1 distributed discrete signal, and the test result is the number of logical units that are internally erroneous after the total dose of the chip to be tested is an integer greater than or equal to 0, and the observation matrix is used to represent the chip to be tested. Whether the corresponding logical unit is measured, so the observation matrix should be an integer of 0-1 distribution. Specifically, a Bernoulli random matrix of 0-1 distribution can be set as an observation matrix of the original signal.

In step S103, a corresponding test vector set is generated according to the row vector in the observation matrix.

In the embodiment of the present invention, each row vector in the observation matrix corresponds to one test vector set, and one test vector set can be used to test a chip to be tested.

Specifically, determining, according to the value of each position in the current row vector of the observation matrix, whether the logical unit corresponding to the location is a unit to be tested, for example, when the value of the location is 1, the corresponding logical unit is a unit to be tested, when When the value of the position is 0, the corresponding logical unit is not the unit to be tested. After the determination, the test vector generation tool in the testability design is used to produce test vectors of all the units to be tested determined by the row vector, and the test vectors constitute a test vector set corresponding to the row vector. In this way, a test vector set corresponding to each row vector in the observation matrix can be generated.

In step S104, a predetermined number of chips to be tested are subjected to total dose irradiation, and the corresponding chips to be tested after the irradiation are tested by all test vector sets to determine whether the chip to be tested after the irradiation is in error.

In the embodiment of the present invention, the time of each total dose effect test is usually more than ten hours, and there are usually hundreds of logic units in the circuit, in order to measure the logic unit in the chip faster and more accurately. The state is monitored, and a preset number of chips identical to the chip to be tested can be placed in a preset total dose radiation environment while performing total dose irradiation. Specifically, the total dose radiation environment can be simulated radiation source For the ground test method, the simulated ray source may be a gamma ray, an electron beam of an electron accelerator, and an X-ray source. The preset number is the number of rows of the observation matrix, and is also the number of test vector sets.

In the embodiment of the present invention, the test unit in the test chip is tested by the test vector in each test vector set, and the test result of each test vector set is the logical unit of the error in the corresponding test chip after irradiation. The number, therefore, the number of error logic units inside the chip to be tested is obtained while determining whether the chip to be tested after the irradiation is in error.

Alternatively, a chip can be irradiated multiple times, each time using a test vector set to test it.

In step S105, when it is determined that the chip to be tested after the irradiation is in error, a compression sensing equation is generated according to the test result and the observation matrix of all the test vector sets, and the compressed sensing equation and the preset signal reconstruction algorithm are generated and output. The distribution of sensitive logic elements for the total dose effect inside the chip to be tested.

In the embodiment of the present invention, when it is determined that the chip to be tested is in error under irradiation, a compression sensing equation for generating a total dose effect reconstruction signal of the chip to be tested may be constructed according to the test result and the observation matrix of all test vector sets, The preset signal reconstruction algorithm nonlinearly optimizes the compressed sensing equation to generate a reconstructed signal of the total dose effect of the chip to be tested. The reconstructed signal is the distribution of sensitive logic elements of the total dose effect of the chip to be tested.

Specifically, the compressed sensing equation can be expressed as:

Y=ΦX', ie

Where Y is the test result, Φ is the observation matrix, X' is the reconstructed signal, and a ₁₁ , a _{12 ,} etc. are the data in the observation matrix. When x _i '= 0 R _i that the logic unit at a total irradiation dose is reliable, when the x _i' = R _i that the logic unit at a total dose of radiation is sensitive to 1. As an example, FIG. 2 is a distribution of sensitive logic cells for the total dose effect inside the chip to be tested, and the dot in FIG. 2 is a logic unit sensitive to the total dose effect inside the chip to be tested.

Preferably, the convex optimization algorithm with high signal recovery accuracy is used to solve the compressed sensing equation, and the reconstruction precision of the reconstructed signal of the total dose effect of the chip under test is effectively improved.

Preferably, as shown in FIG. 3, when the redundancy ratio (the ratio of the number of rows of the observation matrix to the sparsity) is greater than or equal to 4, the total dose effect reconstruction signal of the chip to be tested has the best effect, that is, the reconstruction accuracy. highest. Wherein, the sparsity is the number of 1 in the original signal, the abscissa in FIG. 3 is the redundancy ratio, the ordinate is the reconstruction accuracy, and the reconstruction accuracy is the correct data in the reconstructed signal and the total scale of the reconstructed signal. The ratios, curves 1 to 5 in Fig. 3, sequentially indicate the relationship between the redundancy ratio and the reconstruction accuracy when the number of registers to be observed in one test is 200, 100, 50, 25, and 13, respectively.

In the embodiment of the present invention, the internal state of the chip under test in the total dose radiation environment is reflected by the test result corresponding to the test vector set of the subsequent configuration through the controllability and observability of the testability design, through the compressed sensing The test results of the theoretical and test vector sets, the distribution of sensitive logic units for generating the total dose effect of the chip under test, thereby efficiently and accurately locating the logic unit sensitive to the total dose irradiation inside the chip to be tested, and quickly determining the chip to be tested. The degree of reliability of the radiation effect and the relationship between the irradiation conditions and the irradiation effect.

Embodiment 2:

FIG. 4 is a flowchart showing an implementation process of a method for detecting a total dose effect according to Embodiment 2 of the present invention, which is described in detail as follows:

In step S401, the circuit in the chip to be tested is designed for testability.

In the embodiment of the present invention, the circuit in the chip to be tested is designed for testability, and the internal state of the chip under test under the total dose irradiation is tested by the subsequent structure by using the controllability and observability of the testability design. The test results corresponding to the vector set are reflected.

In step S402, an original signal of the total dose effect of the chip to be tested is constructed, and an observation matrix of the original signal is generated.

In the embodiment of the present invention, the original signal of the total dose effect of the chip to be tested may be constructed according to the sensitivity state of the logic unit to the total dose effect in the chip to be tested. According to the theory of compressed sensing, the observation matrix of the original signal may be a random matrix. Since the original signal is a 0-1 distributed discrete signal in the embodiment of the present invention, the test result is the number of internal logic units after the total dose of the chip to be tested is irradiated. Is an integer greater than or equal to 0. The observation matrix is used to indicate whether the corresponding logical unit in the chip to be tested is the unit to be tested. The measurement matrix should be an integer of 0-1 distribution. Specifically, a Bernoulli random matrix of 0-1 distribution can be set as an observation matrix of the original signal.

In step S403, a corresponding test vector set is generated according to the row vector in the observation matrix.

In the embodiment of the present invention, determining whether the logical unit corresponding to the position is a unit to be tested according to the value of each position in the current row vector of the observation matrix, and using the test vector generation tool in the testability design to produce all the determined by the row vector. Test vectors of the unit to be tested, these test vectors constitute a test vector set corresponding to the row vector, and thus, a test vector set corresponding to each row vector in the observation matrix can be generated.

In step S404, total dose irradiation is performed on a preset number of chips to be tested, and the corresponding chips to be tested after the irradiation are tested through all test vector sets.

In the embodiment of the present invention, a preset number of chips identical to the chip to be tested may be placed in a preset total dose radiation environment while performing total dose irradiation, and the test vector pairs in each test vector set are correspondingly tested. The units to be tested in the chip are tested, and the test result of each test vector set is the number of logical units that are erroneous after irradiation in the corresponding chip to be tested.

In step S405, it is determined whether the chip to be tested after the irradiation is in error.

In the embodiment of the present invention, after testing the unit to be tested in the corresponding chip to be tested by using the test vector in each test vector set, according to the test result, it may be determined whether the chip to be tested after the irradiation is in error, when the chip to be tested is tested. When an error occurs under irradiation, step S406 is performed, and when the chip to be tested is not erroneous under irradiation, step S407 is performed.

In step S406, a compression sensing equation is generated according to the test result and the observation matrix of all test vector sets, and the distribution of sensitive logic elements of the total internal dose effect of the chip to be tested is generated and output according to the compressed sensing equation and the preset signal reconstruction algorithm. .

In the embodiment of the present invention, a compressed sensing equation of a reconstructed signal for generating a total dose effect of a chip to be tested may be constructed according to test results and an observation matrix of all test vector sets, by a preset signal reconstruction algorithm and a compressed sensing equation. And generating a reconstructed signal of a total dose effect inside the chip to be tested, the reconstructed signal being a sensitive logic unit distribution of the total dose effect inside the chip to be tested.

In step S407, the irradiation dose of the total dose irradiation is increased.

In an embodiment of the invention, the total dose effect of the chip under test is increased by increasing the radiation dose of the total dose of radiation. After the irradiation dose is increased, the test chip is re-irradiated and tested until the chip to be tested is erroneous after irradiation, that is, a logic unit in which an error occurs.

In the embodiment of the present invention, the internal state of the chip under test in the total dose radiation environment is reflected by the test result corresponding to the test vector set of the subsequent configuration through the controllability and observability of the testability design, through the compressed sensing The test results of the theoretical and test vector sets, the distribution of sensitive logic units for generating the total dose effect of the chip under test, thereby efficiently and accurately locating the logic unit sensitive to the total dose irradiation inside the chip to be tested, thereby being able to quickly determine the test to be tested The degree of reliability of the radiation effect of the chip and the relationship between the irradiation conditions and the irradiation effect.

One of ordinary skill in the art can understand that all or part of the steps of implementing the above embodiments may be completed by a program instructing related hardware, and the program may be stored in a computer readable storage medium, the storage. Media, such as ROM/RAM, disk, CD, etc.

Embodiment 3:

FIG. 5 shows the structure of a total dose effect detecting device provided by Embodiment 3 of the present invention. For the convenience of description, only parts related to the embodiment of the present invention are shown, including:

The circuit design module 51 is configured to perform testability design on the circuit in the chip to be tested.

The matrix generation module 52 is configured to construct an original signal of the total dose effect of the chip to be tested, and generate an observation matrix of the original signal.

In the embodiment of the present invention, the original signal of the total dose effect of the chip to be tested may be constructed according to the sensitivity state of the logic unit to the total dose effect in the chip to be tested, and the sensitivity state of the total internal dose of the chip to be tested may be determined according to the chip to be tested. The properties of the internal logic unit are determined. Specifically, the original signal can be expressed as X=[x ₁ , x ₂ , . . . , x _i , . . . , x _N ] ^Τ , where x _i represents that the logic unit R _i in the chip to be tested is under the total dose effect irradiation Reliable or sensitive, when x _i =0, the logic unit R _i can be considered to be reliable under total dose effect irradiation, and when x _i =1, the logic unit R _i can be considered to be sensitive under total dose effect irradiation. N is the total number of logical units in the chip to be tested.

In the embodiment of the present invention, the observation matrix of the original signal is constructed, and according to the compressed sensing theory, it can be known that the constraint equidistance or incoherence should be satisfied between the observation matrix and the sparse basis matrix, since any given matrix is combined with a random matrix. It has great incoherence and often uses a random matrix as the observation matrix. In the embodiment of the present invention, the sudden death signal is a 0-1 distributed discrete signal, and the test result is the number of logical units that are erroneous after the total dose of the chip to be tested is an integer greater than or equal to 0, and the observation matrix is used to represent the corresponding in the chip. Whether the logical unit is measured, so the observation matrix should be an integer of 0-1 distribution. Specifically, a Bernoulli random matrix of 0-1 distribution can be set as an observation matrix of the original signal.

The vector set generation module 53 is configured to generate a corresponding test vector set according to the row vector in the observation matrix.

In the embodiment of the present invention, each row vector in the observation matrix corresponds to one test vector set, and one test vector set can be used to test a chip to be tested. Determine whether the logical unit corresponding to the position is a unit to be tested according to the value of each position in the current row vector of the observation matrix. For example, when the value of the position is 1, the corresponding logical unit is the unit to be tested, and the value of the position is When 0, the corresponding logical unit is not the unit to be tested. After the determination, the test vector generation tool in the testability design is used to produce test vectors of all the units to be tested determined by the row vector, and the test vectors constitute a test vector set corresponding to the row vector. In this way, a test vector set corresponding to each row vector in the observation matrix can be generated.

The irradiation test module 54 is configured to perform total dose irradiation on a preset number of chips to be tested, and test the corresponding chips to be tested after the irradiation by using all test vector sets to determine whether the chip to be tested after the irradiation is in error. .

In the embodiment of the present invention, the time of each total dose effect test is usually more than ten hours, There are usually hundreds of logic units in the circuit. In order to monitor the state of the logic unit in the chip to be tested more quickly and accurately, a preset number of chips identical to the chip to be tested can be put into the preset total. The dose radiation environment is simultaneously subjected to total dose irradiation. Then, the test unit in the test chip is tested by the test vector in each test vector set, and the test result of each test vector set is the number of logical units in the corresponding chip to be tested after the irradiation, so the antenna is determined. The number of error logic units inside the chip to be tested is obtained while the chip under test is erroneous.

The sensitive output module 55 is configured to generate a compressed sensing equation according to the test result and the observation matrix of all the test vector sets when determining the error of the chip to be tested after the irradiation, and generate the compressed sensing equation according to the compressed sensing equation and the preset signal reconstruction algorithm. And output the distribution of sensitive logic units of the total dose effect inside the chip to be tested.

Specifically, the compressed sensing equation can be expressed as:

Y=ΦX', ie

Where Y is the test result, Φ is the observation matrix, X' is the reconstructed signal, and a ₁₁ , a _{12 ,} etc. are the data in the observation matrix. When x _i '= 0 R _i that the logic unit at a total irradiation dose is reliable, when the x _i' = R _i that the logic unit at a total dose of radiation is sensitive to 1.

In the embodiment of the present invention, the internal state of the chip under test in the total dose radiation environment is reflected by the test result corresponding to the test vector set of the subsequent configuration through the controllability and observability of the testability design, through the compressed sensing The theoretical and test vector set test results, the total internal dose of the chip to be tested is generated. The sensitive logic unit should be distributed to efficiently and accurately locate the logic unit sensitive to the total dose irradiation inside the chip to be tested, and quickly determine the reliability degree of the radiation effect of the chip to be tested and the relationship between the irradiation condition and the irradiation effect. relationship.

Embodiment 4:

6 shows the structure of a total dose effect detecting device provided by Embodiment 4 of the present invention, which includes:

The circuit design module 61 is configured to perform testability design on the circuit in the chip to be tested.

The matrix generation module 62 is configured to construct an original signal of the total dose effect of the chip to be tested, and generate an observation matrix of the original signal.

In the embodiment of the present invention, the original signal of the total dose effect of the chip to be tested may be constructed according to the sensitivity state of the logic unit to the total dose effect in the chip to be tested. According to the theory of compressed sensing, the observation matrix of the original signal may be a random matrix. Since the original signal is a 0-1 distributed discrete signal in the embodiment of the present invention, the test result is the number of internal logic units after the total dose of the chip to be tested is irradiated. It is an integer greater than or equal to 0. The observation matrix is used to indicate whether the corresponding logical unit in the chip to be tested is the unit to be tested. Therefore, the observation matrix should be an integer of 0-1 distribution. Specifically, a Bernoulli random matrix of 0-1 distribution can be set as an observation matrix of the original signal.

The vector set generation module 63 is configured to generate a corresponding test vector set according to the row vector in the observation matrix.

The irradiation test module 64 is configured to perform total dose irradiation on a preset number of chips to be tested, and pass all The test vector set is tested in the corresponding chip to be tested after the irradiation, and it is determined whether the chip to be tested after the irradiation is in error.

In the embodiment of the present invention, a preset number of chips identical to the chip to be tested may be placed in a preset total dose radiation environment while performing total dose irradiation, and the test vector pairs in each test vector set are correspondingly tested. The units to be tested in the chip are tested, and the test result of each test vector set is the number of logical units that are erroneous after irradiation in the corresponding chip to be tested. Therefore, the number of error logic units inside the chip to be tested is obtained while determining whether the chip to be tested after the irradiation is in error.

The sensitive output module 65 is configured to generate a compressed sensing equation and a preset signal reconstruction algorithm according to the test result and the observation matrix of all the test vector sets when determining the error of the chip to be tested after the irradiation, and generate and output the chip to be tested. Distribution of sensitive logic units for internal total dose effects.

In the embodiment of the present invention, when the chip to be tested is in error under irradiation, the compressed sensing equation can be constructed according to the test result and the observation matrix of all test vector sets, and the preset signal reconstruction algorithm and the compressed sensing equation are generated. The reconstructed signal of the total dose effect inside the chip is measured, and the reconstructed signal is a distribution of sensitive logic units of the total dose effect inside the chip to be tested.

The dose increasing module 66 is configured to increase the irradiation dose of the total dose irradiation when it is determined that the chip to be tested after the irradiation is not faulty.

In an embodiment of the invention, the total dose effect is increased by increasing the irradiation dose of the total dose irradiation. After the irradiation dose is increased, the chip to be tested is irradiated and tested again by the irradiation test module 64 until the chip to be tested is erroneous after irradiation, that is, a logic unit in which an error occurs in the chip to be tested.

Preferably, the matrix generation module 62 includes an original signal construction module 621 and an observation matrix setup module 622, wherein:

The original signal construction module 621 is configured to construct an original signal according to whether the logic unit in the chip to be tested is sensitive to the total dose effect;

The observation matrix setting module 622 is configured to set the preset Bernoulli random matrix as the observation matrix of the original signal.

Preferably, the vector set generation module 63 includes a test vector generation module 631 and a test vector set generation Module 632, wherein:

a test vector generation module 631, configured to sequentially determine, according to each row vector in the observation matrix, a unit to be tested in a logic unit inside the chip to be tested, and generate a test vector of the unit to be tested;

The test vector set generation module 632 is configured to form test vectors of all the units to be tested in the chip to be tested into a test vector set, and each row vector corresponds to one test vector set.

Preferably, the irradiation test module 64 includes an irradiation module 641 and a test module 642, wherein:

An irradiation module 641, configured to irradiate a preset number of chips to be tested in a preset total dose radiation environment;

The test module 642 is configured to test, by using each test vector set, the corresponding chip to be tested after the irradiation, determine whether the chip to be tested after the irradiation is in error, and obtain an error logic unit of the chip to be tested after each irradiation. number.

In the embodiment of the present invention, each unit of the total dose effect detecting device may be implemented by a corresponding hardware or software unit, and each unit may be an independent software and hardware unit, or may be integrated into a soft and hardware unit. Limit the invention.

The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. Within the scope.

Claims

A method for detecting a total dose effect, characterized in that the method comprises the following steps:

Testability design of the circuit in the chip to be tested;

Constructing an original signal of the total dose effect of the chip to be tested, and generating an observation matrix of the original signal;

Generating a corresponding test vector set according to the row vector in the observation matrix;

Performing total dose irradiation on a preset number of the chips to be tested, and testing the corresponding chips to be tested after the irradiation by using all test vector sets to determine whether the chip to be tested after the irradiation is in error;

When it is determined that the irradiated chip to be tested is in error, generating a compressed sensing equation according to the test result of the all test vector sets and the observation matrix, according to the compressed sensing equation and a preset signal reconstruction algorithm, Generating and outputting a distribution of sensitive logic cells for the total dose effect inside the chip to be tested.
The method of claim 1 wherein the method further comprises:

When it is determined that the irradiated chip to be tested is not erroneous, the irradiation dose of the total dose irradiation is increased, and the operation of performing total dose irradiation on a preset number of the chips to be tested is re-executed.
The method according to claim 1, wherein the step of constructing an original signal of the total dose effect of the chip to be tested and generating an observation matrix of the original signal comprises:

Constructing the original signal according to a sensitivity state of a logic unit to a total dose effect in the chip to be tested;

A preset Bernoulli random matrix is set as the observation matrix of the original signal.
The method of claim 1 wherein the step of generating a corresponding set of test vectors based on the row vectors in the observation matrix comprises:

Determining, according to each row vector in the observation matrix, a unit to be tested in a logic unit inside the chip to be tested, and generating a test vector of the unit to be tested;

The test vectors of all the units to be tested in the chip to be tested constitute a test vector set, and each of the row vectors corresponds to one test vector set.
The method according to claim 1, wherein a total dose of the predetermined number of the chips to be tested is irradiated, and the corresponding chips to be tested after the irradiation are tested by all test vector sets to confirm The step of determining whether the chip to be tested after the irradiation is in error includes:

Irradiating the preset number of chips to be tested in a preset total dose radiation environment;

Determining, by the each test vector set, the corresponding chip to be tested after the irradiation, determining whether the irradiated chip to be tested is in error, and obtaining the number of error logic units of the chip to be tested after each irradiation .
A total dose effect detecting device, characterized in that the device comprises:

a circuit design module for testability design of circuits in the chip to be tested;

a matrix generating module, configured to construct an original signal of the total dose effect of the chip to be tested, and generate an observation matrix of the original signal;

a vector set generation module, configured to generate a corresponding test vector set according to the row vector in the observation matrix;

The irradiation test module is configured to perform total dose irradiation on a preset number of the chips to be tested, and test the corresponding chip to be tested after the irradiation by using all the test vector sets to determine the irradiated chip to be tested. Whether it is wrong; and

a sensitive output module, configured to generate a compressed sensing equation according to the test result of the test vector set and the observation matrix when determining the error of the chip to be tested after the irradiation, according to the compressed sensing equation and the preset The signal reconstruction algorithm generates and outputs a distribution of sensitive logic units of the total dose effect inside the chip to be tested.
The device of claim 6 wherein said device further comprises:

And a dose increasing module, configured to increase an irradiation dose of the total dose irradiation when it is determined that the irradiated chip to be tested is not in error.
The apparatus of claim 6, wherein the matrix generation module comprises:

An original signal construction module configured to construct the original signal according to a sensitivity state of a logic unit to a total dose effect in the chip to be tested;

An observation matrix setting module is configured to set a preset Bernoulli random matrix as an observation matrix of the original signal.
The apparatus of claim 6, wherein the vector set generation module comprises:

a test vector generating module, configured to sequentially determine, according to each row vector in the observation matrix, a unit to be tested in a logic unit inside the chip to be tested, and generate a test vector of the unit to be tested;

And a test vector set generating module, configured to form test vectors of all the units to be tested in the chip to be tested into a test vector set, where each row vector corresponds to one test vector set.
The apparatus of claim 6 wherein said irradiation test module comprises:

An irradiation module for irradiating the preset number of chips to be tested in a preset total dose radiation environment;

a test module, configured to test, by using each of the test vector sets, the corresponding chip to be tested after the irradiation, determine whether the irradiated chip to be tested is in error, and obtain a test after each irradiation The number of error logic units in the chip.