WO2017199293A1 - Dispositif de conversion de puissance - Google Patents

Dispositif de conversion de puissance Download PDF

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Publication number
WO2017199293A1
WO2017199293A1 PCT/JP2016/064493 JP2016064493W WO2017199293A1 WO 2017199293 A1 WO2017199293 A1 WO 2017199293A1 JP 2016064493 W JP2016064493 W JP 2016064493W WO 2017199293 A1 WO2017199293 A1 WO 2017199293A1
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WIPO (PCT)
Prior art keywords
phase
voltage
period
control signal
threshold
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PCT/JP2016/064493
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English (en)
Japanese (ja)
Inventor
樹 松永
哲 平良
覚 寺島
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2016/064493 priority Critical patent/WO2017199293A1/fr
Priority to JP2018517937A priority patent/JP6452894B2/ja
Priority to TW105120155A priority patent/TW201742363A/zh
Publication of WO2017199293A1 publication Critical patent/WO2017199293A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present invention relates to a power conversion device that performs power conversion between a plurality of phases of alternating current and direct current.
  • a technology for performing two-phase PWM control of a power conversion device in PWM (Pulse Width Modulation) control of a power conversion device having a main circuit in which a switching element and a diode connected in reverse parallel to the switching element are bridge-connected is disclosed. ing.
  • the switching of the phase is stopped for a certain period in the vicinity of the voltage peak of each phase, the switching is performed in the remaining two phases, and the switching loss is reduced.
  • each phase PWM signal for controlling the switching of each phase of the inverter
  • the phase voltage and the line current are detected for at least one of the phases, and the phase difference (power factor angle) between them is detected.
  • the obtained power factor angle is used to control the generation operation of each phase PWM signal, and the switching stop period of each phase of the inverter is made to follow the vicinity of the peak of the line current flowing through the load of the inverter (see, for example, Patent Document 1). .
  • a power factor is calculated based on an output current and a voltage command value, and a carrier signal having a frequency corresponding to the power factor is generated to control a switching element.
  • a PWM signal is generated (see, for example, Patent Document 2).
  • the power factor is obtained based on the detected load state, and the follow-up control of the switching stop period is performed based on the power factor, so the control is complicated. Further, the switching stop period of each phase of the inverter is limited to the vicinity of the peak of the line current flowing through the load of the inverter, and there is a limit to reducing the switching loss. Moreover, in the power converter device of the said patent document 2, although the suppression effect of a harmonic is acquired, switching of each phase is stopped only near the peak of each phase voltage command value, and reduction of switching loss is similarly performed. There were limits.
  • the present invention has been made to solve the above-described problems, and is effective in easy control in a power conversion device that converts a plurality of phases of AC power into DC power using PWM control.
  • An object of the present invention is to reduce switching loss while suppressing harmonics.
  • a power converter comprises a plurality of switching elements each connected in reverse parallel with a plurality of switching elements that are bridge-connected, a power converter that converts a plurality of phases of AC power into DC power, and the power converter AC voltage detector and AC current detector provided on the AC side of the power converter for detecting AC voltage and AC current, DC voltage detector for detecting DC voltage at the DC terminal of the power converter, and detection results thereof And a control unit for controlling the output of the power converter by PWM control based on the above.
  • the control unit generates a control signal for generating a control signal for controlling the switching of the switching element by generating a phase AC voltage command for controlling the DC voltage, and limits the control signal for each phase.
  • the limiting unit determines a first period that sandwiches positive and negative peaks of each phase voltage in the AC voltage and a second period that sandwiches a zero cross point as the limiting period of each phase, and limits the control signal in the limiting period.
  • a limit signal is generated.
  • the control signal is limited by setting the first period sandwiching the positive and negative peaks of each phase voltage in the AC voltage and the second period sandwiching the zero-cross point as the limit period of each phase. Therefore, switching loss can be reduced while suppressing harmonics effectively with easy control.
  • FIG. 1 shows schematic structure of the power converter device by Embodiment 1 of this invention. It is a circuit diagram which shows the power converter by Embodiment 1 of this invention. It is a block diagram which shows a part of control part by Embodiment 1 of this invention. It is a block diagram which shows a part of control part by Embodiment 1 of this invention. It is a block diagram which shows a part of limit signal generation part by Embodiment 1 of this invention. It is a flowchart explaining the production
  • Embodiment 3 of this invention It is a block diagram which shows a part of control part by Embodiment 3 of this invention. It is a block diagram which shows a part of control part by Embodiment 3 of this invention. It is a flowchart explaining the production
  • FIG. 1 is a schematic configuration diagram of a power conversion device according to Embodiment 1 of the present invention.
  • a power converter 1 includes an AC voltage detector 2, a filter 3, an AC current detector (hereinafter referred to as a current detector) 4, and a power converter that includes a power module. 5, a smoothing capacitor 6 connected to the DC side of the power converter 5, a DC voltage detector 7, and a control unit 8 that controls the power converter 5.
  • the power converter 5 performs power conversion from AC power of three-phase AC (in this case, three-phase AC (R phase, S phase, T phase) to DC power, and the AC side is connected to the AC voltage source via the filter 3.
  • the DC side is connected to a load 11 via a smoothing capacitor 6.
  • the load 11 is composed of, for example, a motor and an inverter that converts DC power into AC power necessary for driving the motor.
  • the AC voltage source 10 is handled including the impedance component and reactance component due to the transformer and wiring on the input side of the power conversion device 1.
  • the power converter 5 is configured by bridge-connecting a plurality (six in this case) of switching elements 52a to 52f to which diodes 51a to 51f are connected in antiparallel.
  • the diodes 51a to 51f constitute a three-phase full-wave rectifier circuit. Details of the connection configuration of the power converter 5 are shown below.
  • the anode of the diode 51 a and the cathode of the diode 51 b are connected to the R phase of the AC voltage source 10 via the current detector 4 and the filter 3.
  • the anode of the diode 51 c and the cathode of the diode 51 d are connected to the S phase of the AC voltage source 10 through the current detector 4 and the filter 3.
  • the anode of the diode 51 e and the cathode of the diode 51 f are connected to the T phase of the AC voltage source 10 via the current detector 4 and the filter 3.
  • connection point between the anode of the diode 51a and the cathode of the diode 51b, the connection point between the anode of the diode 51c and the cathode of the diode 51d, and the connection point of the anode of the diode 51e and the cathode of the diode 51f This is terminal 5a.
  • terminals from each connection point are illustrated as AC terminals 5a.
  • the switching elements 52a to 52f are connected in antiparallel with the diodes 51a to 51f, respectively.
  • the cathode of the diode 51a, the cathode of the diode 51c, the cathode of the diode 51e, and the terminals of the switching elements 52a, 52c, and 52e connected to each other are connected to each other as a high potential side terminal of the DC terminal 5b of the power converter 5.
  • the anode of the diode 51b, the anode of the diode 51d, the anode of the diode 51f, and the terminals of the switching elements 52b, 52d, and 52f connected thereto are connected to each other, and the low potential side of the DC terminal 5b of the power converter 5 Form a terminal.
  • the high potential side terminal and the low potential side terminal of the DC terminal 5b are simply referred to as a DC terminal 5b.
  • the switching elements 52a to 52f are controlled to be either on or off by a control signal (gate signal) Ga output from the control unit 8 to each of the switching elements 52a to 52f.
  • a control signal (gate signal) Ga output from the control unit 8 to each of the switching elements 52a to 52f.
  • the state of the control signal Ga that turns on the switching elements 52a to 52f is referred to as “on”, and the state of the control signal Ga that turns off the switching elements 52a to 52f is referred to as “off”.
  • the switching elements 52a to 52f have a drive circuit (not shown) and are switched on / off.
  • the filter 3 includes, for example, six reactors connected to each phase by two, and three capacitors connected by ⁇ connection or Y connection between the two reactors of each phase.
  • the smoothing capacitor 6 is connected between the DC terminals 5b of the power converter 5 and smoothes the DC voltage.
  • the AC voltage detector 2 is disposed on the side of the AC voltage source 10 of the filter 3 and is an AC voltage between two phases, in this case, an R-phase voltage Vrs for the S-phase, an S-phase voltage Vst for the T-phase, and R A T-phase voltage Vtr with respect to the phase is detected.
  • the detected values of the alternating voltages Vrs, Vst, Vtr are sent to the control unit 8.
  • the detection values of the AC voltages Vrs, Vst, and Vtr are simply referred to as AC voltages Vrs, Vst, and Vtr for convenience. In this embodiment, three AC voltages Vrs, Vst, and Vtr are detected, but only two may be detected.
  • the current detector 4 (4R, 4S, 4T) is disposed between the filter 3 and the power converter 5, and is used for the phase currents Ir, Is, It as the alternating current flowing in the AC terminal 5a of the power converter 5. Detect value.
  • the current detector 4R detects the R-phase phase current Ir
  • the current detector 4S detects the S-phase phase current Is
  • the current detector 4T detects the T-phase phase current It.
  • the detected values of the phase currents Ir, Is, It are sent to the control unit 8.
  • the detected values of the phase currents Ir, Is, It are simply referred to as phase currents Ir, Is, It for convenience.
  • the DC voltage detector 7 is connected between both terminals of the smoothing capacitor 6, that is, between the DC terminals 5b of the power converter 5, and detects the DC voltage Vdc of the smoothing capacitor 6.
  • the DC voltage (detected value) Vdc is sent to the control unit 8.
  • the control unit 8 includes a phase voltage processing unit 81, a limiting signal generation unit 82 as a limiting unit, and a control signal generation unit 83. Details of the control unit 8 are shown in FIGS. As illustrated in FIG. 3, the phase voltage processing unit 81 uses the AC voltages Vrs, Vst, and Vtr input from the AC voltage detector 2 as phase voltage information 810 as phase voltages (phase voltage values) Vr, Vs, Vt and positive and negative peak values (Vrmax, Vrmin), (Vsmax, Vsmin), (Vtmax, Vtmin) of the phase voltage are calculated and output to the limit signal generator 82. Furthermore, the phase voltage processing unit 81 outputs the phase angle ⁇ of the phase voltage to the control signal generation unit 83.
  • phase voltage processing unit 81 uses the AC voltages Vrs, Vst, and Vtr input from the AC voltage detector 2 as phase voltage information 810 as phase voltages (phase voltage values) Vr, Vs, Vt and positive and negative peak values (Vr
  • the positive and negative peak values of the phase voltage are the maximum voltage value (> 0) and the minimum voltage value ( ⁇ 0) of the phase voltage.
  • the AC voltage detector 2 detects only two of the three AC voltages Vrs, Vst, and Vtr, the three-phase voltages Vr, Vs, and Vt are calculated using the two AC voltages.
  • the limit signal generation unit 82 includes a first storage unit 21 that holds the first coefficient K1, a second storage unit 22 that holds the second coefficient K2, an R-phase voltage threshold generation unit 23r, and an S-phase voltage threshold generation unit. 23s, a T-phase voltage threshold generation unit 23t, an R-phase voltage comparison unit 24r, an S-phase voltage comparison unit 24s, and a T-phase voltage comparison unit 24t.
  • the limit signal generation unit 82 outputs an enable signal En (Enr, Ens, Ent) as a limit signal for limiting the control signal of each phase, and the enable signal En is input to the control signal generation unit 83.
  • arbitrary values satisfying K1> K2 ⁇ 0 can be set from the outside. Details of the R-phase voltage threshold generation unit 23r, the S-phase voltage threshold generation unit 23s, and the T-phase voltage threshold generation unit 23t are illustrated in FIG. The operation of the R-phase voltage threshold generation unit 23r will be described below with reference to FIG. The operations of the S-phase voltage threshold generation unit 23s and the T-phase voltage threshold generation unit 23t are the same operations as the R-phase voltage threshold generation unit 23r for the S-phase and the T-phase, and will not be described.
  • the first coefficient K1, the second coefficient K2, and the positive and negative peak values (Vrmax, Vrmin) of the R phase voltage are input to the R phase voltage threshold generation unit 23r, and the positive first threshold Vra , The positive second threshold Vrb, the negative second threshold Vrc, and the negative first threshold Vrd are output as voltage thresholds for the phase voltage Vr.
  • the positive peak value Vrmax is multiplied by the first coefficient K1 in the multiplier 23a, and is multiplied by the second coefficient K2 in the multiplier 23b. Then, the multipliers 23a and 23b generate a positive first threshold value Vra and a positive second threshold value Vrb.
  • the negative peak value Vrmin is multiplied by the second coefficient K2 in the multiplier 23c, and is multiplied by the first coefficient K1 in the multiplier 23d.
  • the multipliers 23c and 23d generate a negative second threshold value Vrc and a negative first threshold value Vrd.
  • the R-phase voltage threshold generation unit 23r, the S-phase voltage threshold generation unit 23s, and the T-phase voltage threshold generation unit 23t set four voltage thresholds for each phase, and set the voltage threshold for each phase. Is input to the R-phase voltage comparison unit 24r, the S-phase voltage comparison unit 24s, and the T-phase voltage comparison unit 24t.
  • Four voltage thresholds for each phase, a total of 12 voltage thresholds, are set as follows.
  • the R phase voltage comparison unit 24r receives the R phase voltage Vr from the phase voltage processing unit 81 (step S1), and detects the sign of the R phase voltage Vr (step S2). If the R-phase voltage Vr is positive, the R-phase voltage Vr and the positive first threshold value Vra are compared (step S3). If the R-phase voltage Vr exceeds the positive first threshold value Vra, the enable signal Enra is Turn it on.
  • the enable signal Enra maintains the on state during the period in which the state in which the R-phase voltage Vr exceeds the positive first threshold value Vra continues (step S4).
  • the enable signal is a signal for selecting one of the on and off states, and outputting the enable signal that is a limiting signal means turning on the enable signal.
  • step S5 If the R-phase voltage Vr is equal to or lower than the positive first threshold value Vra in step S3, the R-phase voltage Vr is compared with the positive second threshold value Vrb (step S5), and the R-phase voltage Vr is determined to be the positive second threshold value. If it is less than Vrb, the enable signal Enrb is turned on. The enable signal Enrb is maintained in the ON state during the period in which the state where the R-phase voltage Vr is positive and less than the positive second threshold value Vrb continues (step S6).
  • step S7 If the R-phase voltage Vr is negative or 0 in step S2, the R-phase voltage Vr is compared with the negative second threshold value Vrc (step S7), and the R-phase voltage Vr exceeds the negative second threshold value Vrc. Then, the enable signal Enrc is turned on. The enable signal Enrc is kept on during the period in which the state where the R-phase voltage Vr exceeds the negative second threshold value Vrc continues (step S8).
  • step S7 if the R-phase voltage Vr is equal to or less than the negative second threshold value Vrc, the R-phase voltage Vr and the negative first threshold value Vrd are compared (step S9), and the R-phase voltage Vr is the negative first threshold value. If it is less than Vrd, the enable signal Enrd is turned on. The enable signal Enrd is maintained in the on state during the period in which the R-phase voltage Vr is negative and is still below the negative first threshold value Vrd (step S10).
  • step S5 If the R-phase voltage Vr is greater than or equal to the positive second threshold value Vrb in step S5, or if the R-phase voltage Vr is greater than or equal to the negative first threshold value Vrd in step S9, all R-phase enable signals Enr (Enra, (Enrb, Enrc, Enrd) are turned off (step S11).
  • the R-phase voltage comparison unit 24r turns on any one of the R-phase enable signals Enr (Enra, Enrb, Enrc, Enrd) using the value of the R-phase voltage Vr and the voltage thresholds Vra to Vrd. Or turn everything off.
  • the control signal generation unit 83 generates a command value storage unit 31 that holds a command value Vdc * of the DC voltage Vdc, a voltage command generation unit 32, and a control signal Ga using a PWM signal.
  • a PWM signal generator 33 and a carrier wave generator 34 are provided.
  • the voltage command generating unit 32 stores the phase angle ⁇ from the phase voltage processing unit 81, the phase currents Ir, Is, It from the current detector 4, the DC voltage Vdc from the DC voltage detector 7, and the command value storage.
  • the command value Vdc * from the unit 31 is input.
  • the voltage command generator 32 generates each phase AC voltage command Vr *, Vs *, Vt * for controlling the DC voltage Vdc to the command value Vdc *, and each phase AC voltage command Vr *, Vs *, Based on Vt *, each phase modulation wave Mr *, Ms *, and Mt * for the power converter 5 is calculated.
  • the carrier wave generator 34 generates a carrier wave for PWM control and outputs it to the PWM signal generator 33.
  • the carrier wave is generally a high-frequency triangular wave or sawtooth wave.
  • the PWM signal generation unit 33 includes an R phase PWM signal generation unit 33r, an S phase PWM signal generation unit 33s, and a T phase PWM signal generation unit 33t.
  • the R-phase PWM signal generation unit 33r receives the R-phase modulation wave Mr * from the voltage command generation unit 32, and further receives the R-phase enable signal Enr from the limit signal generation unit 82.
  • the S-phase PWM signal generator 33s receives the S-phase modulated wave Ms * and the S-phase enable signal Ens
  • the T-phase PWM signal generator 33t receives the T-phase modulated wave Mt * and the T-phase.
  • the enable signal Ent is input.
  • the PWM signal generation units 33r, 33s, and 33t for each phase compare the modulated waves Mr *, Ms *, and Mt * for each phase with the carrier waves, respectively, and the PWM signal G for each phase that becomes a basic control signal, that is, , Gr (Gpr, Gnr), Gs (Gps, Gns), and Gt (Gpt, Gnt).
  • the PWM signals Gpr, Gps, Gpt are generated for the high potential side switching elements 52a, 52c, 52e in the power converter 5, and the PWM signals Gnr, Gns, Gnt are low potentials in the power converter 5. Are generated for the switching elements 52b, 52d, and 52f on the side.
  • the PWM signal generators 33r, 33s, and 33t for each phase limit the on / off switching of the generated PWM signals Gr, Gs, and Gt by the enable signals Enr, Ens, and Ent for each phase, that is, the control signal Ga, , Gra (Gpra, Gnra), Gsa (Gpsa, Gnsa), and Gta (Gpta, Gnta).
  • the operation of the R-phase PWM signal generation unit 33r that generates the control signal Gra (Gpra, Gnra) based on the PWM signal Gr (Gpr, Gnr) and the enable signal Enr will be described below with reference to FIG. Note that the operations of the S-phase PWM signal generation unit 33s and the T-phase PWM signal generation unit 33t are the same operations as those of the R-phase PWM signal generation unit 33r for the S-phase and the T-phase, and will not be described.
  • the R-phase PWM signal generation unit 33r receives the enable signal Enr (Enra, Enrb, Enrc, Enrd) from the R-phase voltage comparison unit 24r (Step SS1), and when the enable signal Enra is on (Step SS2), the control is performed.
  • the signal Gpra is forcibly set to on, and the control signal Gnra is forcibly set to off (step SS3).
  • the enable signal Enrb is on (step SS4)
  • the control signal Gpra is forcibly set to off
  • the control signal Gnra is forcibly set to off (step SS5).
  • step SS6 When the enable signal Enrc is on (step SS6), the control signal Gpra is forcibly set to off and the control signal Gnra is forcibly set to off (step SS7).
  • step SS8 When the enable signal Enrd is on (step SS8), the control signal Gpra is forcibly set to off and the control signal Gnra is forcibly set to on (step SS9).
  • step SS10 When all the enable signals Enr (Enra, Enrb, Enrc, Enrd) are off, the control signal Gpra is set to the PWM signal Gpr, and the control signal Gnra is set to the PWM signal Gnr (step SS10).
  • the R-phase PWM signal generation unit 33r receives the R-phase PWM signal Gr, which is a comparison result between the modulated wave Mr * and the carrier wave, during a period when the enable signal Enr is not input (the off period of the enable signal Enr). Used as R-phase control signal Gra. In a limited period, which is a period during which the enable signal Enr is input (the ON period of the enable signal Enr), the control signal Gra is fixed to ON or OFF, and switching is stopped. The control signal Gra (Gpra, Gnra) is output to the power converter 5 to switch the R-phase switching elements 52a, 52b. For this reason, during the period (limit period) in which the enable signal Enr is input to the R-phase PWM signal generation unit 33r, the on / off switching of the R-phase switching elements 52a and 52b is stopped.
  • FIG. 8 is a waveform diagram showing the relationship between the R-phase voltage Vr, the four voltage thresholds (Vra, Vrb, Vrc, Vrd) for the R-phase voltage Vr, and the period during which the enable signal Enr is output.
  • the A region which is the positive first period
  • the enable signal Enra is output, the control signal Gpra is turned on, and the control signal Gnra is fixed off.
  • the region B that can be generated in the positive second period
  • the enable signal Enrb is output, and both the control signals Gpra and Gnra are fixed off.
  • the enable signal Enrc is output, and both the control signals Gpra and Gnra are fixed off.
  • the D region which is the negative first period
  • the enable signal Enrd is output, the control signal Gpra is fixed to be off, and the control signal Gnra is fixed to be on.
  • the difference between the magnitude of the phase voltage and the DC voltage Vdc of the power converter 5 is small, and switching is switched. Little change in voltage even when stopped.
  • the second period (B region and C region) on the positive side and the negative side across the zero cross point of each phase voltage the current change is small, and the waveform change is small even when switching is stopped.
  • the second period across the zero cross point is configured by combining the positive second period (B region) and the negative second period (C region). For this reason, the number of times of switching can be reduced and harmonic distortion can be suppressed.
  • the switching of the control signal Ga is stopped using the enable signal En generated based on the voltage threshold generated using the positive and negative peak values of the phase voltage. For this reason, switching loss can be reduced while suppressing harmonics effectively with easy control.
  • FIG. 9 and FIG. 10 are waveform diagrams of each part for explaining the operation of the power converter 5.
  • Each phase voltage Vr, Vs, Vt, each phase current Ir, Is, It, and the control signal Gpra for the R phase, Gnra and enable signals Enra, Enrb, Enrc, and Enrd for the R phase are shown.
  • the period during which the enable signal En is output is set shorter than that in the case of FIG.
  • the number of times of switching is 46 per cycle, and the harmonic distortion factor (THD) of each phase current Ir, Is, It is 5.5%.
  • the number of times of switching is 34 times per cycle, and the harmonic distortion factor (THD) of each phase current Ir, Is, It is 12.9%.
  • the period during which the enable signal En is output that is, the limit period during which switching of the control signal Ga is stopped.
  • the switching frequency of the switching elements 52a to 52f can be reduced, and the effect of reducing the switching loss can be increased. If the period during which the enable signal En is output is set short, the switching loss reduction effect is reduced, but the harmonic suppression effect can be increased. For this reason, according to the characteristic requested
  • the value of the first coefficient K1 is desirably 0.86 or less in order to reliably perform the two-phase PWM control.
  • the switching of the control signal Ga is stopped during the period in which the enable signal En is output.
  • the present invention is not limited to this.
  • the number of times of switching may be limited.
  • the negative voltage threshold value may be generated by inverting the polarity of the positive voltage threshold value.
  • FIG. 11 is a schematic configuration diagram of a power conversion device 1A according to Embodiment 2 of the present invention.
  • a power converter 1A includes an AC voltage detector 2, a filter 3, an AC current detector (hereinafter referred to as a current detector) 4, and a power converter. 5, a smoothing capacitor 6 connected to the DC side of the power converter 5, a DC voltage detector 7, and a control unit 8 ⁇ / b> A that controls the power converter 5.
  • the configuration other than the control unit 8A is the same as that of the first embodiment.
  • the control unit 8A includes a phase voltage processing unit 81A, a limiting signal generation unit 82A as a limiting unit, and a control signal generation unit 83A. Details of the control unit 8A are shown in FIGS.
  • the phase voltage processing unit 81A outputs the phase angle ⁇ of the phase voltage to the control signal generation unit 83A using the AC voltages Vrs, Vst, and Vtr input from the AC voltage detector 2.
  • the control signal generation unit 83A includes a command value storage unit 31 that stores a command value Vdc * of the DC voltage Vdc, a voltage command generation unit 32A, a PWM signal generation unit 33 that generates a control signal Ga using a PWM signal, and a carrier. And a wave generator 34.
  • the carrier wave generator 34 and the PWM signal generator 33 are the same as those in the first embodiment.
  • the voltage command generation unit 32A stores a phase angle ⁇ from the phase voltage processing unit 81A, phase currents Ir, Is, It from the current detector 4, a DC voltage Vdc from the DC voltage detector 7, and a command value storage.
  • the command value Vdc * from the unit 31 is input.
  • the voltage command generator 32A generates each phase AC voltage command Vr *, Vs *, Vt * for controlling the DC voltage Vdc to the command value Vdc *, and each phase AC voltage command Vr *, Vs *, Based on Vt *, each phase modulation wave Mr *, Ms *, and Mt * for the power converter 5 is calculated.
  • the limit signal generation unit 82A includes a first storage unit 21 that holds the first coefficient K1, a second storage unit 22 that holds the second coefficient K2, an R-phase voltage threshold generation unit 23r, and an S-phase voltage threshold generation unit. 23s, a T-phase voltage threshold generation unit 23t, an R-phase voltage comparison unit 24r, an S-phase voltage comparison unit 24s, and a T-phase voltage comparison unit 24t. Then, the limit signal generation unit 82A receives the phase voltage command information 830 from the control signal generation unit 83A, and outputs an enable signal En (Enr, Ens, Ent) for each phase. The enable signal En is input to the control signal generation unit 83A.
  • the voltage threshold value generation units 23r, 23s, and 23t for each phase and the voltage comparison units 24r, 24s, and 24t for each phase have the same configurations as those of the first embodiment, but the phase voltage command information 830 Based on the above, a voltage threshold value for each phase AC voltage command Vr *, Vs *, Vt * is generated and compared. That is, in the voltage threshold value generators 23r, 23s, and 23t for each phase, the positive and negative values of the first coefficient K1 and the second coefficient K2 that satisfy K1> K2 ⁇ 0 and the AC voltage commands Vr *, Vs *, and Vt * for each phase.
  • each phase voltage comparison unit 24r, 24s, 24t each phase AC voltage command Vr *, Vs *, Vt * and voltage thresholds (positive first threshold, positive second threshold, negative second threshold, The enable signal En is output by comparing with the negative first threshold).
  • switching is stopped or the number of times is reduced in the first period in which the positive and negative peaks of each phase voltage are sandwiched and the second period in which the zero-cross point is sandwiched, and it is easy as in the first embodiment. Switching loss can be reduced while suppressing harmonics effectively with simple control.
  • FIG. 14 is a schematic configuration diagram of a power conversion device 1B according to Embodiment 3 of the present invention.
  • a power converter 1 ⁇ / b> B includes an AC voltage detector 2, a filter 3, an AC current detector (hereinafter referred to as a current detector) 4, and a power converter that includes a power module. 5, a smoothing capacitor 6 connected to the DC side of the power converter 5, a DC voltage detector 7, and a control unit 8 ⁇ / b> B that controls the power converter 5.
  • the configuration other than the control unit 8B is the same as that of the first embodiment.
  • the control unit 8B includes a phase voltage processing unit 81B, a limiting signal generating unit 82B as a limiting unit, and a control signal generating unit 83. Details of the control unit 8B are shown in FIGS. Note that the control signal generator 83 shown in FIG. 16 has the same configuration as that of the first embodiment. As illustrated in FIG. 15, the phase voltage processing unit 81B calculates the phase voltages Vr, Vs, and Vt using the AC voltages Vrs, Vst, and Vtr input from the AC voltage detector 2, and each phase angle ⁇ r. , ⁇ s, ⁇ t are detected and output as phase voltage information 811 to the limit signal generator 82B.
  • phase voltage processing unit 81B outputs any one of the phase angles ⁇ r, ⁇ s, and ⁇ t to the control signal generation unit 83 as the phase angle ⁇ of the phase voltage.
  • the range of the phase angles ⁇ r, ⁇ s, ⁇ t is from 0 ° to 360 °, and when 360 ° or more, a value obtained by subtracting 360 ° from the phase angle is used.
  • the AC voltage detector 2 detects only two of the three AC voltages Vrs, Vst, and Vtr, the three-phase phase voltage using the two AC voltages is used. Vr, Vs, and Vt are calculated.
  • the limit signal generation unit 82B includes a first storage unit 26 that holds the first reference phase ⁇ 1, a second storage unit 27 that holds the second reference phase ⁇ 2, an R-phase voltage phase comparison unit 28r, and an S-phase voltage phase. A comparison unit 28s and a T-phase voltage phase comparison unit 28t are provided. Then, the limit signal generator 82B outputs the enable signal En (Enr, Ens, Ent) for each phase, and the enable signal En is input to the control signal generator 83.
  • any phase angle value satisfying 0 ° ⁇ ⁇ 2 ⁇ 1 ⁇ 90 ° can be set from the outside.
  • the adder adds 180 degrees based on the first reference phase ⁇ 1 and the second reference phase ⁇ 2, respectively, and four phase angle thresholds ⁇ 1, ⁇ 2, (180 ° + ⁇ 1), (180 ° + ⁇ 2) for each phase. ) Is generated and input to the voltage phase comparators 28r, 28s, and 28t of each phase.
  • the four phase angle threshold values for each phase are the positive first threshold value ⁇ 1, the positive second threshold value ⁇ 2, the negative first threshold value (180 ° + ⁇ 1), and the negative second threshold value (180 ° + ⁇ 2).
  • This is a phase angle corresponding to the voltage values of the four voltage threshold values (Vra, Vrb, Vrd, Vrc) generated in the first embodiment.
  • the A region that is the positive first period has a phase angle range of ⁇ 1 to (180 ° ⁇ 1)
  • the B region that is the positive second period has a phase angle range of 0. It is in the range of ° to ⁇ 2, and (180 ° ⁇ 2) to 180 °.
  • the C region which is the negative second period, has a phase angle range of 180 ° to (180 ° + ⁇ 2) and (360 ° ⁇ 2) to 360 °.
  • the D region which is the first negative period has a phase angle range of (180 ° + ⁇ 1) to (360 ° ⁇ 1).
  • the operation of the R-phase voltage phase comparator 28r will be described below with reference to FIG. 17 and with reference to the waveform diagram of FIG. Note that the operations of the S-phase voltage phase comparison unit 28s and the T-phase voltage phase comparison unit 28t are the same operations as the R-phase voltage phase comparison unit 28r for the S-phase and the T-phase, and the description thereof is omitted.
  • the phase angle ⁇ r of the R phase voltage Vr is input from the phase voltage processing unit 81B (step S1) and the phase angle ⁇ r satisfies 0 ° ⁇ r ⁇ 2 (step S2). Then, the enable signal Enrb is turned on.
  • the enable signal Enrb is maintained in the on state during a period in which the state satisfying 0 ° ⁇ r ⁇ 2 is continued (step S3). If the condition that the phase angle ⁇ r is given in step S2 does not satisfy the condition and ⁇ 1 ⁇ r ⁇ (180 ° ⁇ 1) is satisfied (step S4), the enable signal Enra is turned on. The enable signal Enra maintains the on state while the state satisfying ⁇ 1 ⁇ r ⁇ (180 ° ⁇ 1) continues (step S5).
  • step S6 If the condition that the phase angle ⁇ r is not satisfied in step S4 and (180 ° ⁇ 2) ⁇ r ⁇ 180 ° is satisfied (step S6), the enable signal Enrb is turned on. The enable signal Enrb is maintained in the ON state during a period in which the state satisfying (180 ° ⁇ 2) ⁇ r ⁇ 180 ° is continued (step S7). If the condition where the phase angle ⁇ r is not satisfied in step S6 and 180 ° ⁇ ⁇ r ⁇ (180 ° + ⁇ 2) is satisfied (step S8), the enable signal Enrc is turned on. The enable signal Enrc is kept on during the period in which the state satisfying 180 ° ⁇ ⁇ r ⁇ (180 ° + ⁇ 2) continues (step S9).
  • step S10 If the condition that the phase angle ⁇ r is not satisfied in step S8 satisfies (180 ° + ⁇ 1) ⁇ r ⁇ (360 ° ⁇ 1) (step S10), the enable signal Enrd is turned on.
  • the enable signal Enrd maintains the on state during a period in which the state satisfying (180 ° + ⁇ 1) ⁇ r ⁇ (360 ° ⁇ 1) is continued (step S11). If the condition that the phase angle ⁇ r is not satisfied in step S10 and (360 ° ⁇ 2) ⁇ r ⁇ 360 ° is satisfied (step S12), the enable signal Enrc is turned on.
  • the enable signal Enrc is kept on during the period in which the state satisfying (360 ° ⁇ 2) ⁇ r ⁇ 360 ° is continued (step S13). If the condition that the phase angle ⁇ r is given is not satisfied in step S12, all the R-phase enable signals Enr (Enra, Enrb, Enrc, Enrd) are turned off (step S14).
  • phase angle threshold values ⁇ 1, ⁇ 2, (180 ° + ⁇ 1), (180 ° + ⁇ 2) with respect to the phase angle ⁇ r of the R phase voltage are input to the R phase voltage phase comparison unit 28r, and (180 ° ⁇ 1). ), (180 ° ⁇ 2), (360 ° ⁇ 1), and (360 ° ⁇ 2) are calculated and used by the R phase voltage phase comparison unit 28r as phase angle threshold values.
  • Only the phase angle threshold values ⁇ 1 and ⁇ 2 that can use the first reference phase ⁇ 1 and the second reference phase ⁇ 2 as they are are input to the R phase voltage phase comparison unit 28r, and the remaining phase angle threshold values are input to the R phase voltage phase comparison unit 28r. It is also possible to use it by calculating with.
  • switching is stopped in the first period in which the positive and negative peaks of each phase voltage are sandwiched and in the second period in which the zero cross point is sandwiched, and the harmonics are effectively effectively applied as in the first embodiment.
  • the switching loss can be reduced while suppressing the above.
  • the switching of the control signal Ga is stopped using the enable signal En generated based on the phase angle threshold generated from the first reference phase ⁇ 1 and the second reference phase ⁇ 2. For this reason, switching loss can be reduced while suppressing harmonics effectively with easy control.
  • the period during which the enable signal En is output is set to be long, the switching frequency of the switching elements 52a to 52f can be reduced, and the effect of reducing the switching loss can be increased. If the period during which the enable signal En is output is set short, the switching loss reduction effect is reduced, but the harmonic suppression effect can be increased. For this reason, according to the characteristic requested
  • the value of the first reference phase ⁇ 1 is smaller than 60 °.
  • the second period across the zero cross point may be substantially zero, and in this case, the second reference phase ⁇ 2 is set to 0 °.
  • the switching may be limited to reduce the number of switchings instead of stopping the switching in the period in which the enable signal En is output.
  • FIG. 18 is a schematic configuration diagram of a power conversion device 1C according to the fourth embodiment of the present invention.
  • a power converter 1 ⁇ / b> C includes an AC voltage detector 2, a filter 3, an AC current detector (hereinafter referred to as a current detector) 4, and a power converter that includes a power module. 5, a smoothing capacitor 6 connected to the DC side of the power converter 5, a DC voltage detector 7, and a control unit 8 ⁇ / b> C that controls the power converter 5.
  • the configuration other than the control unit 8C is the same as that in the first embodiment.
  • the control unit 8C includes a phase voltage processing unit 81A, a limiting signal generation unit 82C as a limiting unit, and a control signal generation unit 83C. Details of the control unit 8C are shown in FIGS.
  • the phase voltage processing unit 81A has the same configuration as that of the second embodiment, and uses the AC voltages Vrs, Vst, and Vtr input from the AC voltage detector 2 to determine the phase angle ⁇ of the phase voltage as a control signal generation unit. Output to 83C.
  • the control signal generation unit 83C includes a command value storage unit 31 that stores a command value Vdc * of the DC voltage Vdc, a voltage command generation unit 32C, a PWM signal generation unit 33 that generates a control signal Ga using a PWM signal, and a carrier. And a wave generator 34.
  • the carrier wave generator 34 and the PWM signal generator 33 are the same as those in the first embodiment.
  • the voltage command generation unit 32C stores the phase angle ⁇ from the phase voltage processing unit 81A, the phase currents Ir, Is, It from the current detector 4, the DC voltage Vdc from the DC voltage detector 7, and the command value storage.
  • the command value Vdc * from the unit 31 is input.
  • the voltage command generator 32C generates each phase AC voltage command Vr *, Vs *, Vt * for controlling the DC voltage Vdc to the command value Vdc *, and each phase AC voltage command Vr *, Vs *, Based on Vt *, each phase modulation wave Mr *, Ms *, and Mt * for the power converter 5 is calculated.
  • the phase angle ⁇ r *, ⁇ s *, ⁇ t * of each phase AC voltage command Vr *, Vs *, Vt * is detected and output as phase voltage command information 831 to the limit signal generator 82C.
  • the limit signal generation unit 82C includes a first storage unit 26 that holds the first reference phase ⁇ 1, a second storage unit 27 that holds the second reference phase ⁇ 2, an R-phase voltage phase comparison unit 28r, and an S-phase voltage phase. A comparison unit 28s and a T-phase voltage phase comparison unit 28t are provided. Then, the limit signal generator 82C The phase angle ⁇ r *, ⁇ s *, ⁇ t * as the phase voltage command information 831 is input from the control signal generation unit 83C, and the enable signal En (Enr, Ens, Ent) for each phase is output. The enable signal En is input to the control signal generation unit 83C.
  • the voltage phase comparison units 28r, 28s, and 28t for each phase have the same configuration as that of the third embodiment, but the phase angle ⁇ r * of each phase AC voltage command Vr *, Vs *, Vt *, A phase angle threshold for ⁇ s * and ⁇ t * is generated and compared. That is, using the first reference phase ⁇ 1 and the second reference phase ⁇ 2, four phase angle threshold values (positive first threshold value, positive second threshold value, negative first threshold value, negative second threshold value). Is calculated. In each phase voltage phase comparison unit 28r, 28s, 28t, the phase angle ⁇ r *, ⁇ s *, ⁇ t * of each phase voltage and each phase angle threshold value are compared in the same manner as in the third embodiment.
  • the enable signal En is output.
  • switching switching is stopped or the number of times is reduced in the first period sandwiching the positive and negative peaks of each phase voltage and the second period sandwiching the zero cross point, and the same as the third embodiment. Switching loss can be reduced while suppressing harmonics effectively with simple control.

Abstract

L'invention concerne un dispositif de conversion de puissance (1) destiné à convertir un courant alternatif polyphasé en un courant continu, dans lequel une unité de commande (8) est pourvue : d'une unité de génération de signal de commande (83) pour générer une instruction de tension alternative de chaque phase servant à commander une tension continue afin de générer un signal de commande (Ga) ; et d'une unité de génération de signal de restriction (82) pour restreindre le nombre d'opérations de commutation par restriction du signal de commande (Ga) phase par phase. L'unité de génération de signal de restriction (82) génère un signal de validation (En) servant à restreindre le signal de commande (Ga) pendant une première période comprenant un pic positif ou négatif de chaque tension de phase de la tension alternative et une seconde période comprenant un point de passage par zéro.
PCT/JP2016/064493 2016-05-16 2016-05-16 Dispositif de conversion de puissance WO2017199293A1 (fr)

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PCT/JP2016/064493 WO2017199293A1 (fr) 2016-05-16 2016-05-16 Dispositif de conversion de puissance
JP2018517937A JP6452894B2 (ja) 2016-05-16 2016-05-16 電力変換装置
TW105120155A TW201742363A (zh) 2016-05-16 2016-06-27 電力變換裝置

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03265495A (ja) * 1990-03-14 1991-11-26 Hitachi Ltd 電力変換装置の制御装置
JP2000102290A (ja) * 1998-09-25 2000-04-07 Mitsubishi Electric Corp 電動機の駆動制御装置
JP2012005202A (ja) * 2010-06-15 2012-01-05 Fuji Electric Co Ltd 三相電力変換装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03265495A (ja) * 1990-03-14 1991-11-26 Hitachi Ltd 電力変換装置の制御装置
JP2000102290A (ja) * 1998-09-25 2000-04-07 Mitsubishi Electric Corp 電動機の駆動制御装置
JP2012005202A (ja) * 2010-06-15 2012-01-05 Fuji Electric Co Ltd 三相電力変換装置

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