WO2017197683A1 - 基于ltps半导体薄膜晶体管的goa电路 - Google Patents

基于ltps半导体薄膜晶体管的goa电路 Download PDF

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Publication number
WO2017197683A1
WO2017197683A1 PCT/CN2016/085597 CN2016085597W WO2017197683A1 WO 2017197683 A1 WO2017197683 A1 WO 2017197683A1 CN 2016085597 W CN2016085597 W CN 2016085597W WO 2017197683 A1 WO2017197683 A1 WO 2017197683A1
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electrically connected
thin film
film transistor
node
gate
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French (fr)
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李亚锋
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/308,843 priority Critical patent/US10170067B2/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to a GOA circuit based on an LTPS semiconductor thin film transistor which can improve the stability of a GOA circuit.
  • GOA Gate Driver on Array, line scan integrated on array substrate technology, utilizes existing TFT-LCD (Thin Film Transistor-Liquid Crystal) Display, thin film transistor liquid crystal display) Array process
  • TFT-LCD Thin Film Transistor-Liquid Crystal
  • Array process A technique in which the Gate line scan driving circuit is fabricated on an array substrate to realize the drive mode of Gate progressive scanning.
  • GOA technology can reduce external IC (Integrated Circuit, integrated circuit board (bonding) process, has the opportunity to increase production capacity and jump product cost, and can make LCD panel more suitable for making narrow border or borderless display products.
  • LTPS-TFT liquid crystal displays have the advantages of high resolution, fast response, high brightness and high aperture ratio.
  • the gate driver can be fabricated on the thin film transistor array substrate by using GOA technology to achieve the goal of system integration, space saving and cost of driving the IC.
  • the Q(n) point is the point for controlling the gate drive signal output; the P(n) point is used.
  • the relationship between the two nodes Q(n) and P(n) is mostly mutually restrained.
  • the GOA circuit includes a plurality of cascaded GOA units, wherein n is a positive integer, and the nth-level GOA unit includes: a first thin film transistor T1 whose gate is electrically connected to the first clock signal CK1, and the source is electrically Connected to the output terminal G(n-1) of the upper n-1th stage GOA unit, the drain is electrically connected to the third node K(n); the second thin film transistor T2 is electrically connected to the gate a node Q(n), the source is electrically connected to the second clock signal CK2, the drain is electrically connected to the output terminal G(n), and the third thin film transistor T3 is electrically connected to the third clock signal CK3.
  • the source is electrically connected to the output terminal G(n+1) of the n+1th GOA unit of the next stage
  • the drain is electrically connected to the third node K(n);
  • the fourth thin film transistor T4 has a gate electrically connected to the fourth clock signal CK4, and the source is electrically connected to the constant voltage low level VGL, and the drain is electrically Connected to the output terminal G(n);
  • the fifth thin film transistor T5 has a gate electrically connected to the constant voltage high level VGH, the source is electrically connected to the third node K(n), and the drain is electrically connected to the drain a first node Q(n);
  • a sixth thin film transistor T6 whose gate is electrically connected to the second node P(n)
  • the source is electrically connected to the constant voltage low level VGL, the drain is electrically connected to the third node K(n), and the seventh thin film transistor T7 is electrically connected to the second node P(n), the source
  • the pole is electrically connected to the constant voltage
  • the bootstrap capacitor C1 has one end electrically connected to the first node Q(n), the other end electrically connected to the output terminal G(n), and the second capacitor C2, one end of which is electrically The second node P(n) is connected to the second node P(n), and the other end is electrically connected to the constant voltage low level VGL.
  • FIG. 2 is a forward scan timing diagram of a conventional LTPS semiconductor thin film transistor-based GOA circuit shown in FIG. 1.
  • the working process is: Phase 1, pre-charge: G(n-1) and CK1 are at the same time high level, T1 is turned on, T5 gate is connected to constant voltage high level VGH, so T5 is always in the lead In the on state, the first node Q(n) is precharged to a high level.
  • the output terminal G(n) outputs a high level: G(n-1) and CK1 jump to a low level, CK2 provides a high level, and the first node Q(n) is stored by a bootstrap capacitor C1.
  • T2 is turned on, the high level of CK2 is output to the output terminal G(n), so that the output terminal G(n) outputs a high level, and the first node Q(n) is raised to a higher level.
  • stage 3 the output terminal G(n) outputs a low level: CK3 and G(n+1) both provide a high level, the first node Q(n) is still at a high level, and CK2 jumps to a low level, CK2 The low level is output to the output terminal G(n), so that the output terminal G(n) outputs a low level.
  • phase 4 the first node Q(n) is pulled low to a constant voltage low level VGL: CK1 provides a high level again, G(n-1) remains low, and T1 turns on the first node Q(n) To constant voltage low level VGL, T8 is cut off.
  • stage 5 the first node Q(n) and the output terminal G(n) are maintained at a low level: CK2 provides a high level, T9 is turned on, and the second node P(n) is charged to a high level, T6, T7 Passing, respectively, continuing to pull down the first node Q(n) and the output terminal G(n) to the constant voltage low level VGL, and the second node P(n) continues to maintain the high level under the storage of the second capacitor C2. , T6, T7 are always on for one frame time, keeping the low level of the first node Q(n) and the output terminal G(n).
  • the high level corresponding to the second node P(n) is close to the constant voltage high level VGH (the high level of the second node P(n) can be adjusted to some extent by the size of T9)
  • the low level is a constant voltage low level VGL (there is no way to make changes).
  • T6 and T7 work for a long time, which will cause the threshold voltages of T6 and T7 to shift. Shift), causing the stability of the circuit to drop, causing the GOA circuit output to be abnormal.
  • the present invention provides a GOA circuit based on an LTPS semiconductor thin film transistor, comprising: a plurality of cascaded GOA units, each of which includes a scan control module, an output module, a bootstrap capacitor, and a pull-down module; let n be a positive integer, in addition to the first-stage and last-stage GOA units, in the n-th stage GOA unit: the scan control module includes: a first thin film transistor, a third thin film transistor, and a fifth thin film transistor The gate of the first thin film transistor is electrically connected to the first clock signal, and the source is electrically connected to the output terminal G(n-1) of the upper n-1th stage GOA unit, and the drain is electrically connected.
  • the gate of the third thin film transistor is electrically connected to the third clock signal, and the source is electrically connected to the output terminal G(n+1) of the n+1th GOA unit of the next stage.
  • the drain is electrically connected to the third node;
  • the gate of the fifth thin film transistor is electrically connected to the constant voltage high level, the source is electrically connected to the third node, and the drain is electrically connected to the drain a first node;
  • the output module includes: a second thin film transistor, a gate of the second thin film transistor is electrically connected to the first node, a source is electrically connected to the second clock signal, and a drain is electrically connected The output terminal G(n); one end of the bootstrap capacitor is electrically connected to the first node, and the other end is electrically connected to the output terminal G(n);
  • the pull-down module includes: a fourth thin film transistor a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, a tenth thin film
  • the present invention provides a GOA circuit based on an LTPS semiconductor thin film transistor, comprising: a plurality of cascaded GOA units, each stage GOA unit including a scan control module, an output module, a bootstrap capacitor, and a pull-down module
  • n be a positive integer
  • the scan control module includes: a first thin film transistor, a third thin film transistor, and a fifth thin film transistor
  • the gate of the first thin film transistor is electrically connected to the first clock signal, and the source is electrically connected to the output terminal G(n-1) of the upper n-1th stage GOA unit, and the drain is electrically connected to the first a third node;
  • a gate of the third thin film transistor is electrically connected to the third clock signal, and a source is electrically connected to an output terminal G(n+1) of the n+1th GOA unit of the next stage
  • the drain is electrically connected to the third node; the gate
  • An advantage of the present invention is that the present invention provides LTPS based
  • the GOA circuit of the semiconductor thin film transistor introduces a high level and a frequency of a voltage corresponding to a second node P(n) by a resistor and a timing signal.
  • the GOA circuit provided by the invention can be applied to the field of gate driving of mobile phones, displays and televisions.
  • FIG. 1 is a schematic diagram of a conventional GOA circuit based on an LTPS semiconductor thin film transistor
  • FIG. 2 is a forward scan timing diagram of a conventional LTPS semiconductor thin film transistor-based GOA circuit shown in FIG. 1;
  • FIG. 3 is a schematic diagram of a GOA circuit based on an LTPS semiconductor thin film transistor according to the present invention.
  • FIG. 4 is a timing chart of forward scanning of the LTPS semiconductor thin film transistor-based GOA circuit of the present invention shown in FIG. 3;
  • FIG. 5 is a reverse scan timing diagram of the LTPS semiconductor thin film transistor-based GOA circuit of the present invention shown in FIG.
  • the GOA circuit includes: a plurality of cascaded GOA units, each of which includes a scan control module 32, an output module 34, a bootstrap capacitor C1, and a pull-down module 36.
  • the scan control module 32 includes: a first thin film transistor T1, a third thin film transistor T3, and a fifth thin film transistor
  • the output module 34 includes: a second thin film transistor T2;
  • the pull-down module 36 includes: a fourth thin film transistor T4, a sixth thin film transistor T6, a seventh thin film transistor T7, an eighth thin film transistor T8, and a ninth thin film transistor. T9, tenth thin film transistor T10 and resistor R1.
  • the gate of the first thin film transistor T1 is electrically connected to the first clock signal CK1, and the source is electrically connected to the output terminal G of the upper n-1th GOA unit (n- 1), the drain is electrically connected to the third node K(n); the gate of the third thin film transistor T3 is electrically connected to the third clock signal CK3, and the source is electrically connected to the next n+1th GOA
  • the output terminal G(n+1) of the cell is electrically connected to the third node K(n); the gate of the fifth thin film transistor T5 is electrically connected to the constant voltage high level VGH, and the source is electrically connected to
  • the third node K(n) has a drain electrically connected to the first node Q(n).
  • the gate of the second thin film transistor T2 is electrically connected to the first node Q(n), the source is electrically connected to the second clock signal CK2, and the drain is electrically connected to the output terminal G ( n).
  • One end of the bootstrap capacitor C1 is electrically connected to the first node Q(n), and the other end is electrically connected to the output end G(n).
  • the gate of the fourth thin film transistor T4 is electrically connected to the fourth clock signal CK4, the source is electrically connected to the constant voltage low level VGL, and the drain is electrically connected to the output terminal G (n).
  • the gate of the sixth thin film transistor T6 is electrically connected to the second node P(n), the source is electrically connected to the constant voltage low level VGL, and the drain is electrically connected to the third node K(n);
  • the gate of the seven thin film transistor T7 is electrically connected to the second node P(n), the source is electrically connected to the constant voltage low level VGL, the drain is electrically connected to the output terminal G(n), and the eighth thin film transistor T8 The gate is electrically connected to the third node K(n)
  • the source is electrically connected to the constant voltage low level VGL, and the drain is electrically connected to the second node P(n);
  • the gate of the ninth thin film transistor T9 is electrically connected to the fourth node M(n), the source Electrically connected to the timing signal Reset
  • each of the thin film transistors described in the present invention is a low temperature polysilicon semiconductor thin film transistor.
  • the four clock signals of the GOA circuit are: the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are sequentially rotated. Output, and do not overlap each other.
  • the source of the first thin film transistor T1 is electrically connected to the circuit start signal STV; at the final stage GOA In the cell, the source of the third thin film transistor T3 is electrically connected to the circuit start signal STV.
  • LTPS based on the present invention
  • the GOA circuit of the semiconductor thin film transistor can perform forward scanning step by step from the first stage to the last stage, or can perform reverse scanning from the last stage to the first stage step by step.
  • first to the first level GOA First thin film transistor T1 in the cell Providing a first clock signal (ie, CK1 is a high level) and a circuit start signal STV; that is, a first clock signal CK1 and a previous level electrically connected to the first thin film transistor T1 during forward scanning Output G(n-1) of n-1 level GOA unit Also provide a high level.
  • a first clock signal ie, CK1 is a high level
  • STV a circuit start signal
  • the GOA circuit of the semiconductor thin film transistor can pull down the level of the second node P(n) at a certain frequency whether in forward scanning or reverse scanning.
  • FIG. 4 it is a forward scan timing diagram of the LTPS semiconductor thin film transistor-based GOA circuit of the present invention shown in FIG. In the forward scan, the working process is:
  • Phase 1, pre-charge the clock signal CK1 and the output terminal G(n-1) both provide a high level, the clock signals CK2, CK3, and CK4 both provide a low level, and the output terminal G(n+1) also provides a low level.
  • phase 2 output G(n) outputs a high level: the clock signal CK1 and the output terminal G(n-1) both jump to a low level, the clock signal CK2 provides a high level, the clock signals CK3, CK4 and the output end G(n+1) still provides a low level; the first node Q(n) is due to the bootstrap capacitor C1 The storage function remains high; the second thin film transistor T2 Turned on, the high level of the clock signal CK2 is output to the output terminal G(n), so that the output terminal G(n) outputs a high level, and causes the first node Q(n) to be raised to a higher level, Eight, tenth thin film transistor T8, T10 Still conducting; the second and fourth nodes P(n), M(n) maintain a constant voltage low level VGL, and the sixth and seventh thin film transistors T6 and T7 controlled by the second node P(n) are still turned off. The ninth thin film transistor T9 controlled by the fourth node M(n) is still turned off.
  • Phase 3 the output terminal G(n) outputs a low level: the clock signal CK2 jumps to a low level, and the clock signal CK3 and the output terminal G(n+1) both provide a high level, the clock signals CK1, CK4 and the output end. G(n-1) still provides a low level; the third thin film transistor T3 controlled by the clock signal CK3 Turning on; the first node Q(n) is still at a high level, and the second, eighth, and tenth thin film transistors T2, T8, and T10 are controlled by the first node Q(n).
  • the second and fourth nodes P(n), M(n) still maintain a constant voltage low level VGL, and the sixth and seventh thin film transistors T6 and T7 controlled by the second node P(n) are still turned off.
  • the ninth thin film transistor T9 controlled by the fourth node M(n) is still turned off; since the second thin film transistor T2 is still turned on, the low level of the clock signal CK2 is output to the output terminal G(n), thereby outputting the terminal G ( n) Output low level.
  • phase 4 the first node Q(n) is pulled low to a constant voltage low level VGL: the clock signal CK1 is again supplied with a high level, and the clock signals CK2, CK3, CK4 and the output terminal G(n-1) are supplied with a low level; First thin film transistor T1 controlled by clock signal CK1 Turning on, pulling down the first node Q(n) to the constant voltage low level VGL; the second, eighth, and tenth thin film transistors T2, T8, and T10 controlled by the first node Q(n) are turned off.
  • Phase 5 first node Q(n) and output terminal G(n) low level maintenance phase: fourth node M(n) due to resistance R1
  • the divided voltage is always at a high level, the ninth thin film transistor T9 Always on, the timing signal Reset will be transmitted to the second node P(n); as the timing signal Reset alternately provides high and low levels, the level of the second node P(n) will be the same high and low.
  • the level jump that is, the high-low transition frequency of the second node P(n) is consistent with the timing signal Reset.
  • the timing signal Reset When the timing signal Reset is high, the second node P(n) is charged to the high level, and the sixth and seventh thin film transistors T6, T7 When the timing signal Reset is low, the second node P(n) is pulled low to the low level, and the sixth and seventh thin film transistors T6 and T7 are turned on. Cutoff; the first node Q(n) and the output terminal G(n) remain low. That is, at the stage where the output terminal G(n) is kept low, the level of the second node P(n) occurs with the same high and low level jumps as the timing signal Reset transitions between high and low levels. change.
  • the high level V2 of the timing signal Reset is lower than or equal to the constant voltage high level VGH and higher than the threshold voltage VTH of the sixth and seventh thin film transistors T6 and T7 (ie, VTH ⁇ V2 ⁇ VGH); the timing signal Reset
  • the low level V1 is lower than 0 and higher than or equal to the constant voltage low level VGL (ie, VGL ⁇ V1 ⁇ 0).
  • the duty ratio corresponding to the timing signal Reset can be 25%, 33%, 50%, etc., as long as the high level V2 causes a threshold voltage shift (Vth) under a certain duty cycle. Shift to the right) and the threshold voltage offset caused by the low voltage V1 (Vth shift to the left) can be offset to some extent.
  • the second node P(n) maintains a high level for a long time
  • the sixth and seventh thin film transistors T6 and T7 The LTPS is provided based on the LTPS provided by the present invention.
  • the GOA circuit of the thin film transistor is pulled down at a certain frequency in phase 5, effectively avoiding the second node P(n) being at a high level for a long time, preventing the sixth and seventh thin film transistors T6 , T7
  • the problem of threshold voltage shift caused by long-time work improves the stability of the GOA circuit.
  • FIG. 5 is a reverse scan timing diagram of the LTPS semiconductor thin film transistor-based GOA circuit of the present invention shown in FIG. 3; since the working processes of the forward and reverse scans are similar, the operation of the reverse scan will be briefly described below. In reverse scan, the working process is:
  • Phase 1 pre-charge: both the clock signal CK3 and the output terminal G(n+1) provide a high level, the third thin film transistor T3 is turned on by the control of the clock signal CK3, and the third node K(n) is precharged to a high level.
  • Phase 2 output G(n) outputs a high level: the clock signal CK2 provides a high level; the first node Q(n) is due to the bootstrap capacitor C1 The storage function remains high, the second thin film transistor T2 Turning on, the high level of the clock signal CK2 is output to the output terminal G(n), so that the output terminal G(n) outputs a high level, and causes the first node Q(n) to be raised to a higher level.
  • Phase 3 the output terminal G(n) outputs a low level: the clock signal CK2 jumps to a low level, and the clock signal CK1 and the output terminal G(n-1) both provide a high level, and the first node Q(n) remains When the level is high, the second thin film transistor T2 is still turned on, and the low level of the clock signal CK2 is output to the output terminal G(n), so that the output terminal G(n) outputs a low level.
  • phase 4 the first node Q(n) is pulled low to a constant voltage low level VGL: the clock signal CK3 provides a high level again, the output terminal G(n+1) provides a low level; the third thin film transistor T3 is turned on, Pull down the first node Q(n) to the constant voltage low level VGL.
  • Phase 5 the first node Q(n) and the output terminal G(n) are maintained at a low level: when the first node Q(n) is pulled down to a constant voltage low level VGL, the second, eighth, and Ten thin film transistors T2, T8, T10 are turned off, the first node Q(n) and the output terminal G(n) are kept low; the fourth node M(n) is due to the resistance R1
  • the divided voltage is always at a high level, the ninth thin film transistor T9 Always on, the timing signal Reset will be transmitted to the second node P(n); as the timing signal Reset alternately provides high and low levels, the level of the second node P(n) will be the same high and low.
  • the level jump that is, the high-low transition frequency of the second node P(n) is consistent with the timing signal Reset.
  • the timing signal Reset is high
  • the second node P(n) is charged to the high level
  • the sixth and seventh thin film transistors T6, T7 When the timing signal Reset is low, the second node P(n) is pulled low to the low level, and the sixth and seventh thin film transistors T6 and T7 are turned on.
  • Deadline That is, at the stage where the output terminal G(n) is kept low, the level of the second node P(n) occurs with the same high and low level jumps as the timing signal Reset transitions between high and low levels. change.
  • the high level V2 of the timing signal Reset is lower than or equal to the constant voltage high level VGH and higher than the threshold voltage VTH of the sixth and seventh thin film transistors T6 and T7 (ie, VTH ⁇ V2 ⁇ VGH); the timing signal Reset
  • the low level V1 is lower than 0 and higher than or equal to the constant voltage low level VGL (ie, VGL ⁇ V1 ⁇ 0).
  • the duty ratio corresponding to the timing signal Reset can be 25%, 33%, 50%, etc., as long as the high level V2 causes a threshold voltage shift (Vth) under a certain duty cycle. Shift to the right) and the threshold voltage offset caused by the low voltage V1 (Vth shift to the left) can be offset to some extent.
  • the second node P(n) maintains a high level for a long time
  • the sixth and seventh thin film transistors T6 and T7 The LTPS is provided based on the LTPS provided by the present invention.
  • the GOA circuit of the thin film transistor is pulled down at a certain frequency in phase 5, effectively avoiding the second node P(n) being at a high level for a long time, preventing the sixth and seventh thin film transistors T6 , T7
  • the problem of threshold voltage shift caused by long-time work improves the stability of the GOA circuit.
  • the present invention provides LTPS based
  • the GOA circuit of the semiconductor thin film transistor introduces a resistor and a timing signal.
  • the output terminal G(n) can be kept at a low level.
  • the level of the two nodes P(n) occurs with the same high and low transitions as the timing signal transitions between high and low levels, that is, the power of the second node P(n) is pulled down at a certain frequency.
  • the circuit provided by the invention can be applied to the field of gate driving of mobile phones, displays and televisions.

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Abstract

一种基于LTPS半导体薄膜晶体管的GOA电路，引入了电阻R1与一时序信号Reset调整第二节点P(n)对应的电压的高低电平和频率。采用电阻R1与第十薄膜晶体管T10取代现有技术中的第二电容C2，将电阻R1的一端接恒压高电位VGH，另一端接第九薄膜晶体管T9的栅极，第九薄膜晶体管T9的源极电性连接于时序信号Reset；能够在输出端G(n)保持低电平的阶段，使第二节点P(n)的电平随着时序信号Reset在高、低电平之间跳变而发生同样的高、低电平跳变，即按一定频率拉低第二节点P(n)的电平，有效避免了第二节点P(n)长时间处于高电平，防止因第六与第七薄膜晶体管T6、T7长时间工作引起的阈值电压偏移问题，提升GOA电路的稳定性。

Description

基于LTPS半导体薄膜晶体管的GOA电路 技术领域
本发明涉及液晶显示领域，尤其是涉及一种可以提升GOA电路稳定性的基于LTPS半导体薄膜晶体管的GOA电路。
 背景技术
GOA（Gate Driver on Array，集成在阵列基板上的行扫描）技术，是利用现有TFT-LCD（Thin Film Transistor-Liquid Crystal Display，薄膜晶体管液晶显示器）阵列制程将Gate行扫描驱动电路制作在阵列基板上，实现对Gate逐行扫描的驱动方式的一项技术。GOA技术能减少外接IC（Integrated Circuit，集成电路板）的焊接（bonding）工序，有机会提升产能并跳变产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
随着低温多晶硅（Low Temperature Poly-silicon，LTPS)半导体薄膜晶体管的发展，LTPS-TFT液晶显示器也越来越受关注，LTPS-TFT液晶显示器具有高分辨率、反应速度快、高亮度、高开口率等优点。而且由于LTPS半导体本身具有超高载流子迁移率的特性，可以采用GOA技术将栅极驱动器制作在薄膜晶体管阵列基板上，达到系统整合的目标、节省空间及驱动IC的成本。为了保证输出端G(n)点的稳定，都会引入Q(n)、P(n)两节点，Q(n)点为用于控制栅极驱动信号输出的点；P(n)点为用于维持Q(n)点及输出端G(n)点低电平的稳定点，而Q(n)、P(n)两节点之间多为相互牵制的关系。
参考图1，现有的基于LTPS半导体薄膜晶体管的GOA电路的示意图。所述的GOA电路包括级联的多个GOA单元，设n为正整数，第n级GOA单元包括：第一薄膜晶体管T1，其栅极电性连接于第一时钟信号CK1，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点K(n)；第二薄膜晶体管T2，其栅极电性连接于第一节点Q(n)，源极电性连接于第二时钟信号CK2，漏极电性连接于输出端G(n)；第三薄膜晶体管T3，其栅极电性连接于第三时钟信号CK3，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1) ，漏极电性连接于第三节点K(n)；第四薄膜晶体管T4，其栅极电性连接于第四时钟信号CK4，源极电性连接于恒压低电平VGL，漏极电性连接于输出端G(n)；第五薄膜晶体管T5，其栅极电性连接于恒压高电平VGH，源极电性连接于第三节点K(n)，漏极电性连接于第一节点Q(n)；第六薄膜晶体管T6，其栅极电性连接于第二节点P(n) ，源极电性连接于恒压低电平VGL，漏极电性连接于第三节点K(n)；第七薄膜晶体管T7，其栅极电性连接于第二节点P(n)，源极电性连接于恒压低电平VGL，漏极电性连接于输出端G(n)；第八薄膜晶体管T8，其栅极电性连接于第三节点K(n)，源极电性连接于恒压低电平VGL，漏极电性连接于第二节点P(n)；第九薄膜晶体管T9，其栅极与源极均电性连接于第二时钟信号CK2，漏极电性连接于第二节点P(n)；自举电容C1，其一端电性连接于第一节点Q(n)，另一端电性连接于输出端G(n)；第二电容C2，其一端电性连接于第二节点P(n)，另一端电性连接于恒压低电平VGL。
图1所示的GOA电路既可以正向扫描也可以反向扫描，正、反向扫描的工作过程类似。结合图1与图2，以正向扫描为例进行说明，其中，图2为图1所示现有的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图。在正向扫描时，其工作过程为：阶段1，预充电：G(n-1)与CK1同时为高电平，T1导通，T5栅极接恒压高电平VGH因此T5一直处于导通的状态，第一节点Q(n)被预充电至高电平。阶段2，输出端G(n)输出高电平：G(n-1)与CK1跳变为低电平，CK2提供高电平，第一节点Q(n)因自举电容C1的存储作用保持高电平，T2导通，CK2的高电平输出到输出端G(n)，从而输出端G(n)输出高电平，并使得第一节点Q(n)被抬升至更高的电平，同时T8导通，第二节点P(n)被拉低，T6、T7截止。阶段3，输出端G(n)输出低电平：CK3与G(n+1)均提供高电平，第一节点Q(n)仍为高电平，CK2跳变为低电平，CK2的低电平输出到输出端G(n)，从而输出端G(n)输出低电平。阶段4，第一节点Q(n)拉低到恒压低电平VGL：CK1再次提供高电平，G(n-1)保持低电平，T1导通拉低第一节点Q(n)至恒压低电平VGL，T8截止。阶段5，第一节点Q(n)及输出端G(n)低电平维持阶段：CK2提供高电平，T9导通，第二节点P(n)被充电至高电平，T6、T7导通，分别继续拉低第一节点Q(n)及输出端G(n)至恒压低电平VGL，在第二电容C2的存储作用下，第二节点P(n)持续保持高电平，T6、T7在一帧时间内一直导通，保持第一节点Q(n)及输出端G(n)的低电平。
从图2中不难看出，第二节点P(n)对应的高电平接近恒压高电平VGH（第二节点P(n)的高电平一定程度上可以通过T9的大小来调整），低电平为恒压低电平VGL（没有办法做改动）。在上述现有的GOA电路中，由于第二节点P(n)一直处于高电平的状态，也就是T6、T7一直处于导通的状态。T6、T7长时间工作，会造成T6、T7这两个关键薄膜晶体管阈值电压发生偏移（Vth Shift)，造成电路的稳定能力下降，从而引起GOA电路输出异常。
因此，亟需提供一种新的GOA电路，以提升GOA电路的稳定性。
 技术问题
本发明的目的在于，提供一种基于LTPS半导体薄膜晶体管的GOA电路，与现有的基于LTPS半导体薄膜晶体管的GOA电路相比，可以避免第二节点P(n)长时间处于高电平，防止因第六与第七薄膜晶体管长T6、T7时间工作引起的阈值电压偏移问题，提升GOA电路的稳定性，提高液晶面板显示品质。
 技术解决方案
为实现上述目的，本发明提供了一种基于LTPS半导体薄膜晶体管的GOA电路，其中，包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块、输出模块、自举电容以及下拉模块；设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：所述扫描控制模块包括：第一薄膜晶体管、第三薄膜晶体管以及第五薄膜晶体管；所述第一薄膜晶体管的栅极电性连接于第一时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点；所述第三薄膜晶体管的栅极电性连接于第三时钟信号，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1) ，漏极电性连接于所述第三节点；所述第五薄膜晶体管的栅极电性连接于恒压高电平，源极电性连接于所述第三节点，漏极电性连接于第一节点；所述输出模块包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于第二时钟信号，漏极电性连接于输出端G(n)；所述自举电容的一端电性连接于所述第一节点，另一端电性连接于所述输出端G(n)；所述下拉模块包括：第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管以及电阻；所述第四薄膜晶体管的栅极电性连接于第四时钟信号，源极电性连接于恒压低电平，漏极电性连接于所述输出端G(n)；所述第六薄膜晶体管的栅极电性连接于第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第三节点；所述第七薄膜晶体管的栅极电性连接于所述第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述输出端G(n)；所述第八薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第二节点；所述第九薄膜晶体管的栅极电性连接于第四节点，源极电性连接于时序信号，漏极电性连接于所述第二节点；所述第十薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第四节点；所述电阻的一端电性连接于所述恒压高电平，另一端电性连接于所述第四节点；以及所有薄膜晶体管均为低温多晶硅半导体薄膜晶体管，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的脉冲是依序轮流输出，且互不重叠，在所述输出端G(n)保持低电平的阶段，所述第二节点的电平随着所述时序信号在高、低电平之间跳变而发生同样的高、低电平跳变。
为实现上述目的，本发明提供了一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块、输出模块、自举电容以及下拉模块；设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：所述扫描控制模块包括：第一薄膜晶体管、第三薄膜晶体管以及第五薄膜晶体管；所述第一薄膜晶体管的栅极电性连接于第一时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点；所述第三薄膜晶体管的栅极电性连接于第三时钟信号，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1) ，漏极电性连接于所述第三节点；所述第五薄膜晶体管的栅极电性连接于恒压高电平，源极电性连接于所述第三节点，漏极电性连接于第一节点；所述输出模块包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于第二时钟信号，漏极电性连接于输出端G(n)；所述自举电容的一端电性连接于所述第一节点，另一端电性连接于所述输出端G(n)；以及所述下拉模块包括：第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管以及电阻；所述第四薄膜晶体管的栅极电性连接于第四时钟信号，源极电性连接于恒压低电平，漏极电性连接于所述输出端G(n)；所述第六薄膜晶体管的栅极电性连接于第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第三节点；所述第七薄膜晶体管的栅极电性连接于所述第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述输出端G(n)；所述第八薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第二节点；所述第九薄膜晶体管的栅极电性连接于第四节点，源极电性连接于时序信号，漏极电性连接于所述第二节点；所述第十薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第四节点；所述电阻的一端电性连接于所述恒压高电平，另一端电性连接于所述第四节点。
 有益效果
本发明的优点在于，本发明提供的基于LTPS 半导体薄膜晶体管的GOA电路，引入了电阻与一时序信号调整第二节点P(n)对应的电压的高低电平和频率。采用电阻与第十薄膜晶体管取代现有技术中的第二电容，并改变现有技术中第九薄膜晶体管的二极体接法；将电阻的一端接恒压高电位，另一端接第九薄膜晶体管的栅极，第九薄膜晶体管的源极电性连接于时序信号；能够在输出端G(n)保持低电平的阶段，使第二节点P(n)的电平随着时序信号在高、低电平之间跳变而发生同样的高、低电平跳变，即按一定频率拉低第二节点P(n)的电平，有效避免了第二节点P(n)长时间处于高电平，防止因第六与第七薄膜晶体管长T6、T7时间工作引起的阈值电压偏移问题，提升GOA电路的稳定性，以适用高解析度的液晶面板设计。本发明所提供的GOA电路可应用于手机，显示器，电视的栅极驱动领域。
 附图说明
图1为现有的基于LTPS半导体薄膜晶体管的GOA电路的示意图；
图2为图1所示现有的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图；
图3，本发明所述的基于LTPS半导体薄膜晶体管的GOA电路的示意图；
图4为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图；
图5为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的反向扫描时序图。
 本发明的最佳实施方式
下面结合附图对本发明提供的基于LTPS半导体薄膜晶体管的GOA电路做详细说明。
参考图3，本发明所述的基于LTPS半导体薄膜晶体管的GOA电路的示意图。所述的GOA电路包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块32、输出模块34、自举电容C1以及下拉模块36。
设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：所述扫描控制模块32包括：第一薄膜晶体管T1、第三薄膜晶体管T3以及第五薄膜晶体管T5；所述输出模块34包括：第二薄膜晶体管T2；所述下拉模块36包括：第四薄膜晶体管T4、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10以及电阻R1。
在所述扫描控制模块32中：第一薄膜晶体管T1的栅极电性连接于第一时钟信号CK1，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点K(n)；第三薄膜晶体管T3的栅极电性连接于第三时钟信号CK3，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)，漏极电性连接于第三节点K(n)；第五薄膜晶体管T5的栅极电性连接于恒压高电平VGH，源极电性连接于第三节点K(n)，漏极电性连接于第一节点Q(n)。
在所述输出模块34中：第二薄膜晶体管T2的栅极电性连接于第一节点Q(n)，源极电性连接于第二时钟信号CK2，漏极电性连接于输出端G(n)。
所述自举电容C1的一端电性连接于第一节点Q(n)，另一端电性连接于输出端G(n)。
在所述下拉模块36中：第四薄膜晶体管T4的栅极电性连接于第四时钟信号CK4，源极电性连接于恒压低电平VGL，漏极电性连接于输出端G(n)；第六薄膜晶体管T6的栅极电性连接于第二节点P(n)，源极电性连接于恒压低电平VGL，漏极电性连接于第三节点K(n)；第七薄膜晶体管T7的栅极电性连接于第二节点P(n)，源极电性连接于恒压低电平VGL，漏极电性连接于输出端G(n)；第八薄膜晶体管T8的栅极电性连接于第三节点K(n) ，源极电性连接于恒压低电平VGL，漏极电性连接于第二节点P(n)；第九薄膜晶体管T9的栅极电性连接于第四节点M(n)，源极电性连接于时序信号Reset，漏极电性连接于第二节点P(n)；第十薄膜晶体管T10的栅极电性连接于第三节点K(n)，源极电性连接于恒压低电平VGL，漏极电性连接于第四节点M(n)；电阻R1的一端电性连接于恒压高电平VGH，另一端电性连接于第四节点M(n)。
具体的，本发明所述的各个薄膜晶体管均为低温多晶硅半导体薄膜晶体管。
具体的，所述的GOA电路的四条时钟信号：所述第一时钟信号CK1、所述第二时钟信号CK2、所述第三时钟信号CK3和所述第四时钟信号CK4的脉冲是依序轮流输出，且互不重叠。
特别地，在第一级GOA 单元中，第一薄膜晶体管T1 的源极电性连接于电路起始信号STV；在最后一级GOA 单元中，第三薄膜晶体管T3 的源极电性连接于电路起始信号STV。本发明所述的基于LTPS 半导体薄膜晶体管的GOA电路既可以从第一级向最后一级逐级进行正向扫描，也可以从最后一级向第一级逐级进行反向扫描。其中，在正向扫描时，首先向第一级GOA 单元中的第一薄膜晶体管T1 提供第一条时钟信号（即CK1为高电平）和电路起始信号STV；也即正向扫描时，与所述第一薄膜晶体管T1电性连接的第一时钟信号CK1和上一级第n-1级GOA单元的输出端G(n-1) 同时提供高电平。反向扫描时，首先向最后一级GOA 单元中的第三薄膜晶体管T3 提供第一条时钟信号（即CK3为高电平）和电路起始信号STV；也即反向扫描时，与所述第三薄膜晶体管电性连接的第三时钟信号CK3和下一级第n+1级GOA单元的输出端G(n+1)同时提供高电平。
本发明所述的基于LTPS 半导体薄膜晶体管的GOA电路，无论是在正向扫描时还是反向扫描时，均能够按一定频率拉低所述第二节点P(n) 的电平。
参考图4，其为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图。在正向扫描时，其工作过程为：
阶段1、预充电：时钟信号CK1与输出端G(n-1)均提供高电平，时钟信号CK2、CK3、CK4均提供低电平，输出端G(n+1)也提供低电平；第一薄膜晶体管T1 受时钟信号CK1的控制导通，第三节点K(n)被预充电至高电平，受第三节点K(n)控制的第八、第十薄膜晶体管T8、T10 导通；第五薄膜晶体管T5 受恒压高电平VGH 的控制始终导通，故第三节点K(n)与第一节点Q(n)的电平始终相同，第一节点Q(n)被预充电至高电平；第二、第四节点P(n)、M(n)被拉低至恒压低电平VGL，受第二节点P(n)控制的第六、第七薄膜晶体管T6、T7 截止，受第四节点M(n)控制的第九薄膜晶体管T9 截止。
阶段2、输出端G(n)输出高电平：时钟信号CK1与输出端G(n-1)均跳变为低电平，时钟信号CK2提供高电平，时钟信号CK3、CK4和输出端G(n+1)仍提供低电平；第一节点Q(n)因自举电容C1 的存储作用保持高电平；第二薄膜晶体管T2 导通，时钟信号CK2的高电平输出到输出端G(n)，从而输出端G(n)输出高电平，并使得第一节点Q(n)被抬升至更高的电平，第八、第十薄膜晶体管T8、T10 仍导通；第二、第四节点P(n)、M(n)保持恒压低电平VGL，受第二节点P(n)控制的第六、第七薄膜晶体管T6、T7仍截止，受第四节点M(n)控制的第九薄膜晶体管T9仍截止。
阶段3、输出端G(n)输出低电平：时钟信号CK2跳变为低电平，时钟信号CK3与输出端G(n+1)均提供高电平，时钟信号CK1、CK4及输出端G(n-1)仍提供低电平；受时钟信号CK3控制的第三薄膜晶体管T3 导通；第一节点Q(n)仍为高电平，受第一节点Q(n)控制的第二、第八、第十薄膜晶体管T2、T8、T10 仍导通；第二、第四节点P(n)、M(n)仍保持恒压低电平VGL，受第二节点P(n)控制的第六、第七薄膜晶体管T6、T7仍截止，受第四节点M(n)控制的第九薄膜晶体管T9仍截止；由于第二薄膜晶体管T2仍导通，时钟信号CK2的低电平输出到输出端G(n)，从而输出端G(n)输出低电平。
阶段4，第一节点Q(n)拉低到恒压低电平VGL：时钟信号CK1再次提供高电平，时钟信号CK2、CK3、CK4和输出端G(n-1)提供低电平；受时钟信号CK1控制的第一薄膜晶体管T1 导通，拉低第一节点Q(n)至恒压低电平VGL；受第一节点Q(n)控制的第二、第八、第十薄膜晶体管T2、T8、T10截止。
阶段5、第一节点Q(n)及输出端G(n)低电平维持阶段：第四节点M(n)由于电阻R1 的分压始终处于高电平，第九薄膜晶体管T9 始终导通，时序信号Reset会被传输到第二节点P(n)；随着时序信号Reset交替提供高、低电平，第二节点P(n)的电平随着发生同样的高、低电平跳变，即第二节点P(n)的高低电平跳变频率与时序信号Reset一致。当时序信号Reset为高电平时，第二节点P(n)会被充电到高电平，第六、第七薄膜晶体管T6、T7 导通；当时序信号Reset为低电平时，第二节点P(n)会被拉低到低电平，第六、第七薄膜晶体管T6、T7 截止；第一节点Q(n)及输出端G(n)保持低电平。即在输出端G(n)保持低电平的阶段，第二节点P(n)的电平随着时序信号Reset在高、低电平之间跳变而发生同样的高、低电平跳变。
具体地：时序信号Reset的高电平V2低于或等于恒压高电平VGH且高于第六、第七薄膜晶体管T6、T7的阈值电压VTH（即VTH＜V2≤VGH）；时序信号Reset的低电平V1低于0且高于或等于恒压低电平VGL（即VGL≤V1＜0）。时序信号Reset对应的占空比可以为25%、33%、50%等等，只要在某一占空比下，高电平V2造成阈值电压偏移（Vth shift向右）和低压V1造成的阈值电压偏移（Vth shift向左）一定程度上可以抵消即可。
相比于现有技术中第二节点P(n)长时间保持高电平，第六、第七薄膜晶体管T6、T7 在一帧时间内一直导通，本发明提供的基于LTPS 薄膜晶体管的GOA电路在阶段5中第二节点P(n)按一定频率被拉低，有效避免了第二节点P(n)长时间处于高电平，防止因第六与第七薄膜晶体管T6、T7 长时间工作引起的阈值电压偏移问题，提升GOA电路的稳定性。
参考图5，其为图3所示本发明的基于LTPS半导体薄膜晶体管的GOA电路的反向扫描时序图；由于正、反向扫描的工作过程类似，以下简述反向扫描的工作过程。在反向扫描时，其工作过程为：
阶段1、预充电：时钟信号CK3与输出端G(n+1)均提供高电平，第三薄膜晶体管T3受时钟信号CK3的控制导通，第三节点K(n)被预充电至高电平，受第三节点K(n)控制的第八、第十薄膜晶体管T8、T10 导通；第五薄膜晶体管T5 受恒压高电平VGH 的控制始终导通，故第三节点K(n)与第一节点Q(n)的电平始终相同，第一节点Q(n)被预充电至高电平；第二、第四节点P(n)、M(n)被拉低至恒压低电平VGL，第六、第七、第九薄膜晶体管T6、T7、T9 截止。
阶段2、输出端G(n)输出高电平：时钟信号CK2提供高电平；第一节点Q(n)因自举电容C1 的存储作用保持高电平，第二薄膜晶体管T2 导通，时钟信号CK2的高电平输出到输出端G(n)，从而输出端G(n)输出高电平，并使得第一节点Q(n)被抬升至更高的电平。
阶段3、输出端G(n)输出低电平：时钟信号CK2跳变为低电平，时钟信号CK1与输出端G(n-1)均提供高电平，第一节点Q(n)仍为高电平，第二薄膜晶体管T2仍导通，时钟信号CK2的低电平输出到输出端G(n)，从而输出端G(n)输出低电平。
阶段4，第一节点Q(n)拉低到恒压低电平VGL：时钟信号CK3再次提供高电平，输出端G(n+1)提供低电平；第三薄膜晶体管T3导通，拉低第一节点Q(n)至恒压低电平VGL。
阶段5、第一节点Q(n)及输出端G(n)低电平维持阶段：当第一节点Q(n)被拉低至恒压低电平VGL后，第二、第八、第十薄膜晶体管T2、T8、T10截止，第一节点Q(n)及输出端G(n)保持低电平；第四节点M(n)由于电阻R1 的分压始终处于高电平，第九薄膜晶体管T9 始终导通，时序信号Reset会被传输到第二节点P(n)；随着时序信号Reset交替提供高、低电平，第二节点P(n)的电平随着发生同样的高、低电平跳变，即第二节点P(n)的高低电平跳变频率与时序信号Reset一致。当时序信号Reset为高电平时，第二节点P(n)会被充电到高电平，第六、第七薄膜晶体管T6、T7 导通；当时序信号Reset为低电平时，第二节点P(n)会被拉低到低电平，第六、第七薄膜晶体管T6、T7 截止。即在输出端G(n)保持低电平的阶段，第二节点P(n)的电平随着时序信号Reset在高、低电平之间跳变而发生同样的高、低电平跳变。
具体地：时序信号Reset的高电平V2低于或等于恒压高电平VGH且高于第六、第七薄膜晶体管T6、T7的阈值电压VTH（即VTH＜V2≤VGH）；时序信号Reset的低电平V1低于0且高于或等于恒压低电平VGL（即VGL≤V1＜0）。时序信号Reset对应的占空比可以为25%、33%、50%等等，只要在某一占空比下，高电平V2造成阈值电压偏移（Vth shift向右）和低压V1造成的阈值电压偏移（Vth shift向左）一定程度上可以抵消即可。
相比于现有技术中第二节点P(n)长时间保持高电平，第六、第七薄膜晶体管T6、T7 在一帧时间内一直导通，本发明提供的基于LTPS 薄膜晶体管的GOA电路在阶段5中第二节点P(n)按一定频率被拉低，有效避免了第二节点P(n)长时间处于高电平，防止因第六与第七薄膜晶体管T6、T7 长时间工作引起的阈值电压偏移问题，提升GOA电路的稳定性。
综上所述，本发明提供的基于LTPS 半导体薄膜晶体管的GOA电路，引入了电阻与一时序信号，通过调整第二节点P(n)对应的电压的高低电平和频率，能够在输出端G(n)保持低电平的阶段，使第二节点P(n)的电平随着时序信号在高、低电平之间跳变而发生同样的高、低电平跳变，即按一定频率拉低第二节点P(n)的电平，有效避免了第二节点P(n)长时间处于高电平，防止因第六与第七薄膜晶体管长T6、T7时间工作引起的阈值电压偏移问题，提升GOA电路的稳定性，以适用高解析度的液晶面板设计。本发明所提供的电路可应用于手机，显示器，电视的栅极驱动领域。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (11)

  1. 一种基于LTPS半导体薄膜晶体管的GOA电路，其中，包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块、输出模块、自举电容以及下拉模块；
    设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：
    所述扫描控制模块包括：第一薄膜晶体管、第三薄膜晶体管以及第五薄膜晶体管；所述第一薄膜晶体管的栅极电性连接于第一时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点；所述第三薄膜晶体管的栅极电性连接于第三时钟信号，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1) ，漏极电性连接于所述第三节点；所述第五薄膜晶体管的栅极电性连接于恒压高电平，源极电性连接于所述第三节点，漏极电性连接于第一节点；
    所述输出模块包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于第二时钟信号，漏极电性连接于输出端G(n)；
    所述自举电容的一端电性连接于所述第一节点，另一端电性连接于所述输出端G(n)；
    所述下拉模块包括：第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管以及电阻；所述第四薄膜晶体管的栅极电性连接于第四时钟信号，源极电性连接于恒压低电平，漏极电性连接于所述输出端G(n)；所述第六薄膜晶体管的栅极电性连接于第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第三节点；所述第七薄膜晶体管的栅极电性连接于所述第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述输出端G(n)；所述第八薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第二节点；所述第九薄膜晶体管的栅极电性连接于第四节点，源极电性连接于时序信号，漏极电性连接于所述第二节点；所述第十薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第四节点；所述电阻的一端电性连接于所述恒压高电平，另一端电性连接于所述第四节点；以及
    所有薄膜晶体管均为低温多晶硅半导体薄膜晶体管，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的脉冲是依序轮流输出，且互不重叠，在所述输出端G(n)保持低电平的阶段，所述第二节点的电平随着所述时序信号在高、低电平之间跳变而发生同样的高、低电平跳变。
  2. 如权利要求1所述的GOA电路，其中，所述时序信号的高电平低于或等于所述恒压高电平且高于所述第六薄膜晶体管与所述第七薄膜晶体管的阈值电压；所述时序信号的低电平低于0且高于或等于所述恒压低电平。
  3. 如权利要求1所述的GOA电路，其中，所述时序信号对应的占空比为25%、33%或50%的其中之一。
  4. 如权利要求1所述的GOA电路，其中，正向扫描时，与所述第一薄膜晶体管电性连接的所述第一时钟信号和所述输出端G(n-1) 同时提供高电平；反向扫描时，与所述第三薄膜晶体管电性连接的所述第三时钟信号和所述输出端G(n+1)同时提供高电平。
  5. 一种基于LTPS半导体薄膜晶体管的GOA电路，其中，包括：级联的多个GOA单元，每一级GOA单元均包括扫描控制模块、输出模块、自举电容以及下拉模块；
    设n为正整数，除第一级与最后一级GOA单元以外，在第n级GOA单元中：
    所述扫描控制模块包括：第一薄膜晶体管、第三薄膜晶体管以及第五薄膜晶体管；所述第一薄膜晶体管的栅极电性连接于第一时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点；所述第三薄膜晶体管的栅极电性连接于第三时钟信号，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1) ，漏极电性连接于所述第三节点；所述第五薄膜晶体管的栅极电性连接于恒压高电平，源极电性连接于所述第三节点，漏极电性连接于第一节点；
    所述输出模块包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于所述第一节点，源极电性连接于第二时钟信号，漏极电性连接于输出端G(n)；
    所述自举电容的一端电性连接于所述第一节点，另一端电性连接于所述输出端G(n)；以及
    所述下拉模块包括：第四薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管以及电阻；所述第四薄膜晶体管的栅极电性连接于第四时钟信号，源极电性连接于恒压低电平，漏极电性连接于所述输出端G(n)；所述第六薄膜晶体管的栅极电性连接于第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第三节点；所述第七薄膜晶体管的栅极电性连接于所述第二节点，源极电性连接于所述恒压低电平，漏极电性连接于所述输出端G(n)；所述第八薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第二节点；所述第九薄膜晶体管的栅极电性连接于第四节点，源极电性连接于时序信号，漏极电性连接于所述第二节点；所述第十薄膜晶体管的栅极电性连接于所述第三节点，源极电性连接于所述恒压低电平，漏极电性连接于所述第四节点；所述电阻的一端电性连接于所述恒压高电平，另一端电性连接于所述第四节点。
  6. 如权利要求5所述的GOA电路，其中，在所述输出端G(n)保持低电平的阶段，所述第二节点的电平随着所述时序信号在高、低电平之间跳变而发生同样的高、低电平跳变。
  7. 如权利要求6所述的GOA电路，其中，所述时序信号的高电平低于或等于所述恒压高电平且高于所述第六薄膜晶体管与所述第七薄膜晶体管的阈值电压；所述时序信号的低电平低于0且高于或等于所述恒压低电平。
  8. 如权利要求5所述的GOA电路，其中，所述时序信号对应的占空比为25%、33%或50%的其中之一。
  9. 如权利要求5所述的GOA电路，其中，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的脉冲是依序轮流输出，且互不重叠。
  10. 如权利要求5所述的GOA电路，其中，正向扫描时，与所述第一薄膜晶体管电性连接的所述第一时钟信号和所述输出端G(n-1) 同时提供高电平；反向扫描时，与所述第三薄膜晶体管电性连接的所述第三时钟信号和所述输出端G(n+1)同时提供高电平。
  11. 如权利要求5所述的GOA电路，其中，所有薄膜晶体管均为低温多晶硅半导体薄膜晶体管。
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