WO2017197561A1 - 一种卷积ldpc译码方法、装置、译码器及系统 - Google Patents

一种卷积ldpc译码方法、装置、译码器及系统 Download PDF

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Publication number
WO2017197561A1
WO2017197561A1 PCT/CN2016/082211 CN2016082211W WO2017197561A1 WO 2017197561 A1 WO2017197561 A1 WO 2017197561A1 CN 2016082211 W CN2016082211 W CN 2016082211W WO 2017197561 A1 WO2017197561 A1 WO 2017197561A1
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bit
decoding
node information
check node
llr
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PCT/CN2016/082211
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English (en)
French (fr)
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李沫
肖治宇
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华为技术有限公司
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Priority to EP16901947.8A priority Critical patent/EP3447926B1/en
Priority to PCT/CN2016/082211 priority patent/WO2017197561A1/zh
Priority to CN201680084091.9A priority patent/CN108886370B/zh
Publication of WO2017197561A1 publication Critical patent/WO2017197561A1/zh
Priority to US16/191,664 priority patent/US10903855B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/1154—Low-density parity-check convolutional codes [LDPC-CC]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
    • H03M13/1125—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6325—Error control coding in combination with demodulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0059—Convolutional codes

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a convolutional LDPC decoding method, apparatus, decoder, and system.
  • the conventional LDPC decoding is performed for a single packet information, and can be specifically implemented by a parity check matrix (H matrix).
  • a general LDPC packet decoder divides M check equations into m layers, each layer containing M/m check equations. The decoding process is that the LDPC packet decoder checks a codeword with the first layer to the mth layer check equation, and the output decoding result is fed back to the input end of the LDPC packet decoder for multiple iterations. Until the decoding process is completed.
  • a convolutional LDPC decoding mode is also included.
  • a serial pipeline decoding architecture for convolutional LDPC is proposed.
  • the demapping unit processes the symbols, passes through the decoding units 1 to n in turn, and finally passes through the decision output unit.
  • the result of the decoding is a positive integer greater than 1, and the decoding control unit can be used to control the opening of other units.
  • the above method can reduce the code length of the single processing information, reduce the implementation difficulty of the circuit, and improve the performance of the compiled code, but there is still a problem of inaccurate decoding.
  • Embodiments of the present invention provide a convolutional LDPC decoding method, apparatus, decoder, and system, which can improve the accuracy of the decoding process.
  • the embodiment of the present invention adopts the following technical solutions:
  • an embodiment of the present invention provides a convolutional LDPC decoding method, where the method includes: receiving first check node information, where the first check node information includes an output bit of a previous level decoding unit. All check node information; reading a symbol value corresponding to the target bit from a symbol buffer unit; determining a log likelihood ratio LLR and a first posterior probability pair according to the first check node information and the symbol value a number ratio APP, the first APP is used to indicate a decoding result of the target bit at a first moment; the first parity node information and the first APP are sent to a next-level decoding unit, so as to facilitate
  • the first level decoding unit obtains the second APP and the second check node information according to the first check node information and the first APP, where the second APP is used to indicate the target bit at the second moment.
  • the second check node information includes all check node information that the next-stage decoding unit outputs the target bit.
  • the accuracy of the convolutional LDPC decoding process is further improved by adjusting the LLR. Therefore, the accuracy of the decoding process performed in the coherent optical transmission system can be improved, that is, the receiver can decode according to the received symbol value from the transmitter, and obtain an accurate decoding result, thereby improving Transmission performance of a coherent optical transmission system.
  • the determining the LLR and the first APP according to the first check node information and the symbol value including: determining that the symbol value corresponds to The outer information of each bit, the symbol value corresponding to at least two bits, the outer information being the sum of all check node information output by the upper level decoding unit; according to the outer information of each bit, Determining the LLR; determining a sum of the outer information of the target bit and the LLR as the first APP.
  • the symbol value corresponds to the outer information of each bit, that is, the single bit is determined by summing all the check node information of the single bit.
  • the external information and then the LLR is determined according to the obtained external information of each bit, to ensure that the determined LLR can achieve the convergence effect, thereby further improving the accuracy of the decoding process, that is, further improving the transmission performance of the coherent optical transmission system.
  • the symbol value includes an I value and a Q value, where the symbol value is used to represent a symbol point, where Determining the LLR, including: determining, according to the I value and the Q value, coordinates of the symbol point; using a formula Performing a calculation to obtain an LLR corresponding to the i-th bit, that is, the LLR, where a represents a target constellation point, a set of constellation points indicating that the i-th bit has a value of 1, a set of constellation points indicating that the i-th bit has a value of 0, Denoting the Euclidean distance of the symbol point to the target constellation point, Representing the value of the jth bit in the target constellation point, and G(x) represents a function of x.
  • L(C j ) represents the outer information of the j-th bit
  • ⁇ represents the standard deviation
  • m is a positive integer greater than 1
  • i and j are
  • an embodiment of the present invention provides a convolutional LDPC decoding method, where the method is used in a coherent optical transmission system, where the method includes: acquiring, by a decoder, a symbol value output by a receiver in the coherent optical transmission system The decoder calculates each bit corresponding to the symbol value according to an iterative algorithm to obtain a decoding result of each bit, and the iterative algorithm includes updating at least one check node information with at least one logarithm However, the update of the LLR; the decoder determines the decoding result of each bit according to the check node information and the LLR that are last updated by the iterative algorithm.
  • the accuracy of the convolutional LDPC decoding process is further improved. Therefore, the accuracy of the decoding process performed in the coherent optical transmission system can be improved, that is, the receiver can decode according to the received symbol value from the transmitter, and obtain an accurate decoding result, thereby improving Transmission performance of a coherent optical transmission system.
  • the method includes: decoding, by the decoder, each bit As a result, the decoding result corresponding to the symbol value is determined.
  • each bit corresponding to the symbol value is first decoded in the decoding process and the corresponding decoding result is obtained, and then The decoding results are integrated to obtain a decoding result corresponding to the complete symbol value, so that the accuracy of the decoding process can be further improved, and since the data is decoded in units of bits, it is also possible to To some extent, the error rate generated during the decoding process is reduced.
  • the decoding result corresponding to the symbol value is a binary bit stream
  • the symbol value is determined by the decoder
  • the decoder includes: the decoder sends the binary bit stream to a network device of the switching node, so that the network device sends the binary bit stream to the target device to complete transmission of the communication data. process.
  • the decoding result is transmitted by transmitting the decoding result to the network device and transmitting it to the target device by the network device.
  • an embodiment of the present invention provides a convolutional LDPC decoding apparatus, where the apparatus includes: a receiving module, configured to receive first check node information, where the first check node information includes upper level decoding The unit outputs all check node information of the target bit; the reading module is configured to read the symbol value corresponding to the target bit from the symbol buffer unit; and the determining module is configured to use the first check node information and the symbol a value, a log likelihood ratio LLR and a first a posteriori probability log ratio APP, wherein the first APP is used to represent a decoding result of the target bit at a first time; and a sending module is used to translate to a next level Code list Transmitting the first check node information and the first APP, so that the next-level decoding unit obtains the second APP and the second school according to the first check node information and the first APP Checking the node information, the second APP is used to indicate the decoding result of the target bit at the second moment, and the second check
  • the determining module is specifically configured to determine that the symbol value corresponds to outer information of each bit, where the symbol value corresponds to at least two bits,
  • the outer information is a sum of all check node information output by the upper level decoding unit; the LLR is determined according to the outer information of each bit; the outer information of the target bit and the LLR are And determined as the first APP.
  • the symbol value includes an I value and a Q value, where the symbol value is used to represent a symbol point
  • the determining module is Specifically, determining, according to the I value and the Q value, a coordinate of the symbol point; using a formula Performing a calculation to obtain an LLR corresponding to the i-th bit, that is, the LLR, where a represents a target constellation point, a set of constellation points indicating that the i-th bit has a value of 1, a set of constellation points indicating that the i-th bit has a value of 0, Denoting the Euclidean distance of the symbol point to the target constellation point, Representing the value of the jth bit in the target constellation point, and G(x) represents a function of x.
  • L(C j ) represents the outer information of the j-th bit
  • ⁇ represents the standard deviation
  • m is a positive integer greater than 1
  • i and j are
  • an embodiment of the present invention provides a convolutional LDPC decoding apparatus, where the apparatus is used in a coherent optical transmission system, and the apparatus includes: an acquiring module, configured to acquire a receiver in the coherent optical transmission system And a calculation module, configured to calculate, according to an iterative algorithm, each bit corresponding to the symbol value, to obtain a decoding result of each bit, where the iterative algorithm includes updating the check node information at least once And an update of the LLR with at least one log likelihood ratio; a determining module, configured to determine the decoding of each bit according to the check node information and the LLR that are last updated by the iterative algorithm result.
  • the determining module is further configured to determine, according to the decoding result of each bit, a decoding result corresponding to the symbol value.
  • the decoding result corresponding to the symbol value is a binary bit stream
  • the device further includes: a sending module, configured to: And transmitting the binary bit stream to a network device of the switching node, so that the network device sends the binary bit stream to the target device to complete a transmission process of the communication data.
  • an embodiment of the present invention provides a decoder, where the decoder is used in a coherent optical transmission system, and the decoder includes: an interface circuit, configured to acquire a receiver in the coherent optical transmission system. An output symbol value; a processor, configured to calculate, according to an iterative algorithm, each bit corresponding to the symbol value to obtain a decoding result of the each bit, where the iterative algorithm includes updating at least one check node information And an update of the LLR with at least one log likelihood ratio; the processor is further configured to determine a decoding result of each bit according to the check node information and the LLR that are last updated by the iterative algorithm.
  • the processor is further configured to perform decoding according to each bit As a result, the decoding result corresponding to the symbol value is determined and transmitted.
  • an embodiment of the present invention provides a coherent optical transmission system, where the coherent optical transmission system includes a transmitter, a receiver, and a decoder, and the decoder is the decoder according to the fifth aspect.
  • a convolutional LDPC decoding method, apparatus, decoder and system provided by an embodiment of the present invention, according to the received upper-level decoding unit, outputting all check node information of a target bit, and reading from a symbol buffer unit
  • the symbol value corresponding to the target bit is used to determine the LLR and the first APP, and then all the check node information and the first APP of the target bit output by the upper-level decoding unit are sent to the next set of decoding units, so as to facilitate
  • the primary decoding unit obtains the second APP and the second check node information.
  • the symbols are processed, and then the decoding units 1 to n are sequentially passed, and finally the decision is made.
  • the output unit obtains the decoding result, which means that in the prior art convolutional LDPC decoding process, the accuracy of the decoding is improved only by adjusting the check node information, and the present invention can be combined with the output of the upper level decoding unit. All check node information of the target bit, and the symbol value corresponding to the target bit, to adjust the LLR in the convolutional LDPC decoding process, that is, adjusting the LLR to make the volume based on adjusting the information of the first check node The accuracy of the LDPC decoding process is further improved. Therefore, the accuracy of the decoding process performed in the coherent optical transmission system can be improved, that is, the receiver can decode according to the received symbol value from the transmitter, and obtain an accurate decoding result, thereby improving Transmission performance of a coherent optical transmission system.
  • FIG. 1 is a schematic diagram of a specific application scenario according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of another specific application scenario according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of another specific application scenario according to an embodiment of the present disclosure.
  • FIG. 4 is a flowchart of a method for decoding a convolutional LDPC according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a decoding process according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a re-mapping process according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of another method for decoding a convolutional LDPC according to an embodiment of the present invention.
  • FIG. 8 is a flowchart of another method for decoding a convolutional LDPC according to an embodiment of the present invention.
  • FIG. 9 is a flowchart of another method for decoding a convolutional LDPC according to an embodiment of the present invention.
  • FIG. 10 is a flowchart of another method for decoding a convolutional LDPC according to an embodiment of the present invention.
  • FIG. 11 is a flowchart of another method for decoding a convolutional LDPC according to an embodiment of the present invention.
  • FIG. 12 is a schematic structural diagram of a convolutional LDPC decoding apparatus according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of another convolutional LDPC decoding apparatus according to an embodiment of the present invention. schematic diagram;
  • FIG. 14 is a schematic structural diagram of a decoder according to an embodiment of the present invention.
  • the embodiment of the present invention may add a symbol buffer unit and at least one re-mapping unit on the basis of the architecture shown in FIG. 1 , and then adjust the LLR based on the information of the first check node in the existing decoding process.
  • the architecture tried by the present invention may be located in a coherent transmission system, wherein the coherent optical transmission system includes a transmitter and a receiver, and the architecture tested by the present invention may be regarded as part of the receiver, or The architecture used to perform the decoding process after the receiver receives the data transmitted via the link.
  • the transmitter transmits data, and obtains a symbol value including an I/Q component via FEC encoding and modulation mapping process, and transmits it to the receiver via a link, via multiple equalization/compensation Then, the symbol value including the I/Q component is obtained, and the subsequent decoding operation is completed in the decoder by using the method flow provided by the present invention to obtain a decoding result.
  • an architecture of m re-mapping units is added on the basis of the original architecture, where m is a positive integer greater than 1 and less than n.
  • the decoding control unit may also be used to control the opening of each re-mapping unit and the symbol buffer unit; the symbol buffer unit may be used to store the symbol values of the respective bits, so that when each re-mapping unit needs When the corresponding symbol value is obtained, it can be obtained from the symbol buffer unit.
  • the re-mapping unit may be disposed between two adjacent decoding units in the serial architecture.
  • each row of decoding needs to perform multiple row layer decoding, if you want to further improve the accuracy of the decoding process, you can also increase the decoding process between two adjacent row layers inside the decoding unit. Remap the mapping unit.
  • one or more re-mapping units are set, and the position and number of the re-mapping unit are not specifically limited herein.
  • An embodiment of the present invention provides a convolutional LDPC decoding method.
  • the re-mapping mapping unit is disposed between two adjacent decoding units. As shown in FIG. 4, the method may be performed by a re-mapping unit. Execution, the method flow includes:
  • the first check node information includes all check node information of the output target bit of the upper level decoding unit.
  • each check equation corresponds to one check node information
  • the target bit corresponds to four check equations in the upper stage decoding unit
  • four checksums are output after the previous level decoding unit.
  • the node information, the set of the four check node information can be regarded as the first check node information, and the first check node information can be specifically represented as CN (English: Check node information, Chinese: check node information) ) 1, CN2, CN3 and CN4.
  • each decoding unit can not only output the first check node information, but also output the APP obtained by the decoding unit (English: A Priori Probability, Chinese: posterior probability log ratio).
  • the APP finally obtained through the entire serial structure is output, and the APP is the output information of the LDCP decoder.
  • the decision output unit may determine that the bit decision result is 0 when the APP is greater than or equal to 0, or the decision result of the bit is 1 when the APP is less than 0, and the decision result is outputted by the decision output unit.
  • the symbol When the symbol is input into the demapping unit, or before the symbol is about to be input into the demapping unit, the symbol can be stored in the symbol buffer unit, so that when the re-mapping unit needs to acquire the symbol value corresponding to the target bit, Read directly from the symbol cache unit.
  • the first APP is used to indicate the decoding result of the target bit at the first moment. Also Means that if there is no next-level decoding unit or other re-mapping unit after the re-mapping unit, the first APP can be used to represent the final decoding result of the target bit, if after the re-mapping unit There is a next-level decoding unit or other re-mapping unit, then the first APP can only be used to represent the decoding result of the target bit at the first moment, and can also be regarded as a temporary decoding result in the entire decoding process. .
  • the first time is a time when the target bit passes through the re-mapping unit, and the first APP is obtained.
  • the LLR is the input soft information of the bit, which can be obtained from the channel or the front-end equalization module, and the value of the LLR is constant, which means that the prior art adjusts the ⁇ CN through each decoding unit.
  • the main function of the added re-mapping unit is to update the LLR.
  • the operation of de-mapping the symbol is also required, that is, the re-mapping unit performs weighting according to the first check node information and the acquired symbol value.
  • the demapping operation obtains a new LLR, thereby implementing the LLR update.
  • the re-mapping unit outputs a sum of all CNs output according to the new LLR and the previous-stage decoding unit when the new LLR is output, that is, the ⁇ CN performs calculation.
  • the new APP obtained, the first APP.
  • the input of the re-mapping unit is the symbol value corresponding to the current ⁇ CN and the target bit, and the output is the first APP.
  • the upper-level decoding unit can output the CN corresponding to each check equation.
  • the ⁇ CN can be directly calculated by the upper-level decoding unit and then sent to the re-mapping unit, but Since the re-mapping unit further needs to send the CN corresponding to each of the check-up equations in the previous-stage decoding unit to the next-stage decoding unit, in the embodiment of the present invention, the ⁇ CN can also directly be in the re-mapping map.
  • next-stage decoding unit After the series and re-mapping unit, since the input parameter of the next-stage decoding unit is the first APP output by the re-mapping unit, and all the outputs of the previous-level decoding unit CN, therefore, the next-stage decoding unit can derive the LLR updated by the re-mapping unit according to the above-mentioned decoding formula, and update according to the updated LLR. CN.
  • the next-level decoding unit may obtain the LLR updated by the re-mapping unit according to the sum of all the check node information in the first APP and the first check node information, that is, ⁇ CN, and combine the above-mentioned decoding formula.
  • the second APP is calculated.
  • the ⁇ CN updated by the decoding unit of the next stage may be obtained by summing the CN values corresponding to each check equation in the decoding unit of the next level.
  • the set of all CN values may be It is regarded as the second check node information.
  • the second APP is used to indicate the decoding result of the target bit at the second time, and the second check node information includes all the check node information of the output target bit of the next-stage decoding unit. That is to say, if there is no other decoding unit or re-mapping unit after the next-stage decoding unit, the second APP can be used to represent the final decoding result of the target bit, if after the next-level decoding unit There are still other decoding units or re-mapping units, and the second APP can only be used to represent the decoding result of the target bit at the second moment, and can also be regarded as a temporary decoding result in the entire decoding process.
  • the second time is a time when the target bit passes through the next-level decoding unit to obtain the second APP.
  • the input of the i-th row layer decoding is the old ⁇ CN and the first APP
  • the output is the new ⁇ CN and the second APP.
  • the re-mapping unit may be disposed between two adjacent decoding units, or may be disposed between adjacent two row layer decoding units.
  • the updated ⁇ CN and the updated second APP can also be obtained.
  • the old ⁇ CN may be the sum of all CNs calculated by the row layer decoding unit or the re-mapping unit before the ith row layer decoding unit, or the previous row layer decoding unit or All CNs output by the demapping unit perform a summation operation in the ith row layer decoding unit.
  • the new CN can also perform the summation operation in the i-th row layer decoding unit and output, or the row layer decoding unit or the re-mapping unit after the input, and the subsequent layer translation. code The unit or the re-mapping unit performs the calculation.
  • the second APP of the target bit can be obtained. If the second APP is the last APP value output during the decoding process, the value of the target bit may be determined to be 0 or 1 according to the relationship between the value of the APP and 0. For example, when the value of the APP is greater than or equal to 0, the target bit corresponding to the APP value is 0; when the value of the APP is less than 0, the target bit corresponding to the APP value is determined to be 1. Since each symbol corresponds to a plurality of bits, the above steps 101 to 104 are repeatedly performed, and the decision result of all the bits corresponding to one symbol can be obtained, thereby obtaining the decoding result of the symbol. Similarly, if there are multiple symbols, the decoding result of the multiple symbols can be obtained in the above manner.
  • a convolutional LDPC decoding method according to an embodiment of the present invention, according to the received first-level decoding unit, outputting all check node information of a target bit, and a symbol value corresponding to a target bit read from a symbol buffer unit, Determining the LLR and the first APP, and then transmitting, to the next set of decoding units, all check node information and the first APP of the target bit output by the upper-level decoding unit, so that the next-stage decoding unit obtains the second APP and second check node information.
  • the demapping unit processes the symbols, sequentially passes through the decoding units 1 to n, and finally obtains the decoding result through the decision output unit, which means that the convolutional LDPC decoding process in the prior art is performed.
  • the accuracy of the decoding is improved only by adjusting the check node information, and the present invention can adjust the convolution in combination with all the check node information of the target bit output by the upper-level decoding unit and the symbol value corresponding to the target bit.
  • the LLR in the LDPC decoding process that is, on the basis of adjusting the information of the first check node, adjusts the LLR to further improve the accuracy of the convolutional LDPC decoding process. Therefore, the accuracy of the decoding process performed in the coherent optical transmission system can be improved, that is, the receiver can decode according to the received symbol value from the transmitter, and obtain an accurate decoding result, thereby improving Transmission performance of a coherent optical transmission system.
  • step 103 is based on the first school
  • the node information and the symbol value are determined, and the LLR and the first APP are determined, which may be specifically implemented as steps 1031 to 1033:
  • the symbol value corresponds to at least two bits, and the outer information is the sum of all check node information output by the decoding unit of the previous stage.
  • a convolutional LDPC decoding method provided by an embodiment of the present invention may determine an LLR by determining that the obtained symbol value corresponds to the outer information of each bit, and determine the sum of the outer information of the target bit and the LLR as the first APP. .
  • the demapping unit processes the symbols, sequentially passes through the decoding units 1 to n, and finally obtains the decoding result through the decision output unit, which means that the convolutional LDPC decoding process in the prior art is performed.
  • the accuracy of the decoding is improved only by adjusting the check node information.
  • the present invention can further improve the accuracy of the convolutional LDPC decoding process by adjusting the LLR on the basis of adjusting the information of the first check node.
  • the accuracy of the decoding process performed in the coherent optical transmission system can be improved, that is, the receiver can decode according to the received symbol value from the transmitter, and obtain an accurate decoding result, thereby improving the coherent light.
  • Transmission performance of the transmission system the outer information of each bit corresponding to the symbol value may be determined first, that is, the outer information of the single bit is determined by summing all the check node information of the single bit, and then according to each obtained The outer information of the bits determines the LLR, ensuring that the determined LLR can achieve the convergence effect, thereby further improving the accuracy of the decoding process, that is, further improving the transmission performance of the coherent optical transmission system.
  • the symbol The value includes the I value and the Q value.
  • the symbol value is used to represent the symbol point.
  • the external information of each bit of the same symbol can be combined and calculated by the formula in step 10322 to obtain the desired LLR. Therefore, on the basis of the implementation shown in FIG. 5, it can also be implemented as the implementation shown in FIG.
  • the step 1032 determines the LLR according to the external information of each bit, which may be specifically implemented as steps 10321 to 10322:
  • the calculation is performed to obtain the LLR corresponding to the i-th bit, that is, the LLR.
  • a represents the target constellation point, a set of constellation points indicating that the i-th bit has a value of 1, a set of constellation points indicating that the i-th bit has a value of 0,
  • the Euclidean distance from the symbol point to the target constellation point Indicates the value of the jth bit in the target constellation point
  • G(x) represents the function of x.
  • L(C j ) represents the outer information of the j-th bit
  • ⁇ represents the standard deviation
  • m is a positive integer greater than 1
  • i and j are positive integers greater than or equal to 1.
  • step 10322 is for determining the LLR of the 1st bit, then i is 1, and j may be 2 or 3.
  • the first bit may be 1 or 0, and for 8 values, the point at which the first bit takes a value of 0 is 4, and the 4 points constitute a set.
  • the point with a value of 1 is also 4, which constitutes a set.
  • the serial demodulation and decoding schemes in the prior art are back-to-back (English: Back To Back, BTB, multi-wave hybrid transmission, and 12span).
  • the off-line experimental results of G.652 fiber transmission have a certain OSNR (English: Optical Signal Noise Ratio) performance improvement in all three scenarios.
  • a convolutional LDPC decoding method provided by an embodiment of the present invention may determine a coordinate of a symbol point according to an I value and a Q value in the obtained symbol value, and then calculate an LLR by using a formula. .
  • the demapping unit processes the symbols, sequentially passes through the decoding units 1 to n, and finally obtains the decoding result through the decision output unit, which means that the convolutional LDPC decoding process in the prior art is performed. Only by adjusting the check section Point information to improve the accuracy of decoding, the present invention can adjust the LLR to adjust the accuracy of the convolutional LDPC decoding process based on the adjustment of the first check node information, thereby improving the coherent optical transmission system.
  • the accuracy of the decoding process performed in the receiver that is, the receiver can decode according to the received symbol value from the transmitter, and obtain an accurate decoding result, thereby improving the transmission performance of the coherent optical transmission system.
  • the accuracy of the decoding process is ensured by alternately adjusting the LLR and the ⁇ CN, and the transmission performance of the coherent optical transmission system is further improved.
  • An embodiment of the present invention provides a convolutional LDPC decoding method, which is used in a coherent optical transmission system, and the method can be performed by a decoder. As shown in FIG. 9, the method includes:
  • the decoder obtains a symbol value output by the receiver in the coherent optical transmission system.
  • the decoder calculates each bit corresponding to the symbol value according to an iterative algorithm to obtain a decoding result of each bit.
  • the iterative algorithm includes updating the update of the node information at least once and updating the LLR at least once.
  • the decoder determines a decoding result of each bit according to the check node information and the LLR that are last updated by the iterative algorithm.
  • a convolutional LDPC decoding method is provided by the embodiment of the present invention.
  • the decoder obtains the symbol value output by the receiver in the coherent optical transmission system, and then calculates each bit corresponding to the symbol value according to an iterative algorithm to obtain each The decoding result of the bit, and the decoding node information and the LLR which are updated last time according to the iterative algorithm, thereby determining the decoding result of each bit.
  • the demapping unit processes the symbols, sequentially passes through the decoding units 1 to n, and finally obtains the decoding result through the decision output unit, which means that the convolutional LDPC decoding process in the prior art is performed. Only by adjusting the check node The information is used to improve the accuracy of the decoding.
  • the present invention can perform the iterative algorithm operation on each bit corresponding to the symbol value, thereby adjusting the LLR in the convolutional LDPC decoding process, that is, adjusting the information of the first check node. Based on the adjustment of the LLR, the accuracy of the convolutional LDPC decoding process is further improved. Therefore, the accuracy of the decoding process performed in the coherent optical transmission system can be improved, that is, the receiver can decode according to the received symbol value from the transmitter, and obtain an accurate decoding result, thereby improving Transmission performance of a coherent optical transmission system.
  • step 204 after the decoder determines the decoding result of each bit according to the check node information and the LLR that is last updated by the iterative algorithm, step 204 may be performed:
  • the decoder determines, according to the decoding result of each bit, a decoding result corresponding to the symbol value.
  • the decoder can obtain the decoding result of each bit, it means that the decoder can obtain the decoding result of each bit of all the bits corresponding to the symbol value.
  • the decoding result obtained here can determine the decoding result of each bit according to the correspondence between the decoding result of each bit and each bit. The location in the binary bit stream. That is, by orderly arranging the decoding results of each bit, an ordered binary bit stream, that is, a decoding result corresponding to the symbol value can be obtained.
  • a convolutional LDPC decoding method provided by an embodiment of the present invention needs to determine a decoding result of each bit corresponding to a symbol value in the process of determining a decoding result, and then determine a decoding result corresponding to the symbol value.
  • the demapping unit processes the symbols, sequentially passes through the decoding units 1 to n, and finally obtains the decoding result through the decision output unit, which means that the convolutional LDPC decoding process in the prior art is performed.
  • the present invention can improve the accuracy of the decoding process performed in the coherent optical transmission system by decoding
  • each bit corresponding to the symbol value is first decoded and the corresponding decoding result is obtained, and then the decoding results are integrated to obtain a decoding result corresponding to the complete symbol value, so that not only can further
  • the accuracy of the decoding process is improved, and since the data is decoded in units of bits, it is also possible to reduce the error rate generated in the decoding process to some extent.
  • the decoding result corresponding to the symbol value may be a binary bit stream, which means that the decoder can directly transmit the decoding result as communication data to the network device of the switching node, and The network device transmits to the target device that needs the communication data, thereby completing the forwarding process of the communication data. Therefore, on the basis of the implementation shown in FIG. 10, an implementation as shown in FIG. 11 can also be implemented.
  • step 204 after the decoder determines the decoding result corresponding to the symbol value according to the decoding result of each bit, step 205 may be further performed:
  • the decoder sends the binary bit stream to the network device of the switching node.
  • the binary bit stream can be directly transmitted as the communication data. Therefore, the decoder can directly send the decoded result corresponding to the obtained symbol value to the network device of the switching node, and then can be forwarded by the network device to the network device. The target device, thereby completing the transmission process of the communication data.
  • the decoder can directly send the voice signal to the target device, that is, the corresponding terminal that needs to receive the voice signal, or forward to the target device through the network device, that is, by having the forwarding function.
  • the routing device forwards to the terminal that needs to receive the voice signal.
  • the type of data represented by the binary bit stream is not specifically limited, and may be determined according to different communication data transmission scenarios, and for different communication data, the target device is also It may be various types of devices having a receiving function corresponding to the communication data, and the type of the target device is not specifically limited herein.
  • a convolutional LDPC decoding method provided by an embodiment of the present invention may send the obtained binary bit stream as communication data to a network device after the decoding process is completed, so that the network device can send the communication data to the target. device.
  • the symbols are processed, and then the decoding units 1 to n are sequentially passed.
  • the decoded output result is obtained by the decision output unit, which means that in the prior art convolutional LDPC decoding process, the accuracy of the decoding is improved only by adjusting the check node information, and the present invention can improve the coherent optical transmission.
  • the decoding result is transmitted by transmitting the decoding result to the network device and transmitting it to the target device by the network device.
  • the embodiment of the present invention provides a convolutional LDPC decoding apparatus 30, which is used in a coherent optical transmission system, and the apparatus 30 can be used to execute the method flow shown in FIG. 4, FIG. 7, or FIG. As shown in Figure 12, the apparatus 30 includes:
  • the receiving module 31 is configured to receive first check node information, where the first check node information includes all check node information of the output target bit of the upper level decoding unit.
  • the reading module 32 is configured to read the symbol value corresponding to the target bit from the symbol buffer unit.
  • the determining module 33 is configured to determine a log likelihood ratio LLR and a first a posteriori probability log ratio APP according to the first check node information received by the receiving module 31 and the symbol value read by the reading module 32.
  • An APP is used to indicate the decoding result of the target bit at the first moment.
  • the sending module 34 is configured to send the first check node information and the first APP determined by the determining module 33 to the next level decoding unit, so that the next level decoding unit is configured according to the first check node information and the first APP.
  • the determining module 33 is specifically configured to determine that the symbol value corresponds to the outer information of each bit, the symbol value corresponds to at least two bits, and the outer information is all the schools output by the upper level decoding unit. Check the sum of the node information;
  • the sum of the outer information of the target bit and the LLR is determined as the first APP.
  • the symbol value includes an I value and a Q value
  • the symbol value is used to represent the symbol point
  • the determining module 33 is specifically configured to determine the coordinates of the symbol point according to the I value and the Q value
  • Adopt formula Performing a calculation to obtain an LLR corresponding to the i-th bit, that is, an LLR, where a represents a target constellation point, a set of constellation points indicating that the i-th bit has a value of 1, a set of constellation points indicating that the i-th bit has a value of 0,
  • the Euclidean distance from the symbol point to the target constellation point Indicates the value of the jth bit in the target constellation point, and G(x) represents the function of x.
  • L(C j ) represents the outer information of the j-th bit, ⁇ represents the standard deviation, m is a positive integer greater than 1, and i and j are positive integers greater than or equal to 1.
  • a convolutional LDPC decoding apparatus according to an embodiment of the present invention, according to the received upper-level decoding unit, outputs all check node information of a target bit, and a symbol value corresponding to a target bit read from a symbol buffer unit, Determining the LLR and the first APP, and then transmitting, to the next set of decoding units, all check node information and the first APP of the target bit output by the upper-level decoding unit, so that the next-stage decoding unit obtains the second APP and second check node information.
  • the demapping unit processes the symbols, sequentially passes through the decoding units 1 to n, and finally obtains the decoding result through the decision output unit, which means that the convolutional LDPC decoding process in the prior art is performed.
  • the accuracy of the decoding is improved only by adjusting the check node information, and the present invention can adjust the convolution in combination with all the check node information of the target bit output by the upper-level decoding unit and the symbol value corresponding to the target bit.
  • the LLR in the LDPC decoding process that is, on the basis of adjusting the information of the first check node, adjusts the LLR to further improve the accuracy of the convolutional LDPC decoding process. Therefore, the accuracy of the decoding process performed in the coherent optical transmission system can be improved, that is, the receiver can decode according to the received symbol value from the transmitter, and obtain an accurate decoding result, thereby improving Transmission performance of a coherent optical transmission system.
  • the embodiment of the present invention provides a convolutional LDPC decoding apparatus 40, which is used in a coherent optical transmission system, and the apparatus 40 can be used to perform any of the foregoing method flows as shown in FIG. 9 to FIG. As shown in FIG. 13, the device 40 includes:
  • the obtaining module 41 is configured to obtain a symbol value output by the receiver in the coherent optical transmission system.
  • the calculation module 42 is configured to calculate, according to an iterative algorithm, each bit corresponding to the symbol value acquired by the obtaining module 41, to obtain a decoding result of each bit, and the iterative algorithm includes at least one update of the check node information and at least one pair.
  • the number likelihood is better than the LLR update.
  • the determining module 43 is configured to determine a decoding result of each bit according to the check node information and the LLR that is last updated by the calculation module 42 performing the iterative algorithm.
  • the determining module 43 is further configured to determine, according to the decoding result of each bit, a decoding result corresponding to the symbol value.
  • the decoding result corresponding to the symbol value is a binary bit stream
  • the apparatus 40 further includes:
  • the sending module 44 is configured to send the binary bit stream to the network device of the switching node, so that the network device sends the binary bit stream to the target device to complete the transmission process of the communication data.
  • a convolutional LDPC decoding apparatus is provided by the embodiment of the present invention.
  • the decoder obtains the symbol value output by the receiver in the coherent optical transmission system, and then calculates each bit corresponding to the symbol value according to an iterative algorithm to obtain each The decoding result of the bit, and the decoding node information and the LLR which are updated last time according to the iterative algorithm, thereby determining the decoding result of each bit.
  • the demapping unit processes the symbols, sequentially passes through the decoding units 1 to n, and finally obtains the decoding result through the decision output unit, which means that the convolutional LDPC decoding process in the prior art is performed.
  • the accuracy of the decoding is improved only by adjusting the check node information.
  • the present invention can perform the iterative algorithm operation on each bit corresponding to the symbol value, thereby adjusting the LLR in the convolutional LDPC decoding process, that is, Based on the adjustment of the first check node information, the accuracy of the convolutional LDPC decoding process is further improved by adjusting the LLR. Therefore, the accuracy of the decoding process performed in the coherent optical transmission system can be improved, that is, the receiver can decode according to the received symbol value from the transmitter, and obtain an accurate decoding result, thereby improving Transmission performance of a coherent optical transmission system.
  • the embodiment of the present invention provides a decoder 50 for a coherent optical transmission system, and the decoder 50 can be used to perform the foregoing as shown in FIG. 4, FIG. 7, or FIG.
  • the method flow shown, as shown in FIG. 14, the decoder 50 includes a processor 51 and an interface circuit 52.
  • the memory 53 and the bus 54 are also shown.
  • the processor 51, the interface circuit 52 and the memory 53 pass through the bus. 54 connect and complete communication with each other.
  • the processor 51 herein may be a processing component or a collective name of multiple processing components.
  • the processing component may be a central processing unit (English: Central Processing Unit, CPU for short), or may be an application specific integrated circuit (ASIC), or configured to implement the implementation of the present invention.
  • One or more integrated circuits such as one or more microprocessors (English: digital singnal processor, DSP for short), or one or more field programmable gate arrays (English: Field Programmable Gate Array, referred to as :FPGA).
  • the memory 53 may be a storage device or a collective name of a plurality of storage elements, and is used to store executable program code or parameters, data, and the like required for the operation of the access network management device.
  • the memory 53 may include a random access memory (abbreviation: RAM), and may also include a non-volatile memory (English: non-volatile memory), such as a magnetic disk memory, a flash memory (abbreviation: Flash), or the like.
  • the bus 54 can be an Industry Standard Architecture (ISA) bus, an external device interconnection (English: Peripheral Component, PCI for short) or an extended industry standard architecture (English: Extended Industry Standard Architecture, referred to as: EISA) bus and so on.
  • ISA Industry Standard Architecture
  • PCI Peripheral Component
  • EISA Extended Industry Standard Architecture
  • the bus 54 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 14, but it does not mean that there is only one bus or one type of bus.
  • the decoder 50 may also include input and output means coupled to the bus 54 for connection to other portions, such as the processor 51, via the bus 54.
  • the processor 51 calls the program code in the memory 53 for performing the operations performed by the decoder 50 in the above method embodiment.
  • the processor 51 calls the program code in the memory 53 for performing the operations performed by the decoder 50 in the above method embodiment.
  • the program code in the memory 53 for performing the operations performed by the decoder 50 in the above method embodiment.
  • the symbol value output by the receiver in the coherent optical transmission system is obtained through the interface circuit 52.
  • Each bit corresponding to the symbol value is counted by the processor 51 according to an iterative algorithm. Calculated, the decoding result of each bit is obtained.
  • the iterative algorithm includes updating the update node information at least once and updating the LLR with at least one log likelihood ratio.
  • the decoding result of each bit is determined by the processor 51 based on the check node information and the LLR that were last updated by the iterative algorithm.
  • the decoding result corresponding to the symbol value is determined by the processor 51 and transmitted.
  • a decoder obtains a symbol value output by a receiver in a coherent optical transmission system, and then calculates each bit corresponding to the symbol value according to an iterative algorithm to obtain a translation of each bit.
  • the demapping unit processes the symbols, sequentially passes through the decoding units 1 to n, and finally obtains the decoding result through the decision output unit, which means that the convolutional LDPC decoding process in the prior art is performed.
  • the accuracy of the decoding is improved only by adjusting the check node information.
  • the present invention can perform the iterative algorithm operation on each bit corresponding to the symbol value, thereby adjusting the LLR in the convolutional LDPC decoding process, that is, Based on the adjustment of the first check node information, the accuracy of the convolutional LDPC decoding process is further improved by adjusting the LLR. Therefore, the accuracy of the decoding process performed in the coherent optical transmission system can be improved, that is, the receiver can decode according to the received symbol value from the transmitter, and obtain an accurate decoding result, thereby improving Transmission performance of a coherent optical transmission system.
  • Embodiments of the present invention provide a coherent optical transmission system including a transmitter, a receiver, and a decoder, wherein the decoder is the decoder 50 shown in FIG.
  • a coherent optical transmission system is provided by the embodiment of the present invention.
  • the decoder obtains the symbol value output by the receiver in the coherent optical transmission system, and then calculates each bit corresponding to the symbol value according to an iterative algorithm to obtain each bit.
  • the result of the decoding is decoded, and the decoding result of each bit is determined according to the check node information and the LLR that are last updated by the iterative algorithm.
  • the symbols are processed, and then Through the decoding units 1 to n, the decoded output result is finally obtained through the decision output unit, which means that in the prior art convolutional LDPC decoding process, the accuracy of the decoding is improved only by adjusting the check node information.
  • the present invention can adjust the LLR in the convolutional LDPC decoding process by performing an iterative algorithm operation on each bit corresponding to the symbol value, that is, adjusting the LLR to make the volume based on adjusting the information of the first check node.
  • the accuracy of the LDPC decoding process is further improved. Therefore, the accuracy of the decoding process performed in the coherent optical transmission system can be improved, that is, the receiver can decode according to the received symbol value from the transmitter, and obtain an accurate decoding result, thereby improving Transmission performance of a coherent optical transmission system.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (English: Read-Only Memory, ROM for short) or a random access memory (English: Random Access Memory, RAM for short).

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Abstract

本发明实施例公开了一种卷积LDPC译码方法、装置、译码器及系统，涉及通信技术领域，能够提高译码过程的准确性。本发明实施例的方法包括：接收第一校验节点信息，第一校验节点信息包括上一级译码单元输出目标比特的所有校验节点信息；从符号缓存单元读取目标比特对应的符号值；根据第一校验节点信息和符号值，确定LLR和第一APP，第一APP用于表示第一时刻目标比特的译码结果；向下一级译码单元发送第一校验节点信息和第一APP，以便于下一级译码单元根据第一校验节点信息和第一APP得到第二APP和第二校验节点信息，第二APP用于表示第二时刻目标比特的译码结果，第二校验节点信息包括下一级译码单元输出目标比特的所有校验节点信息。

Description

一种卷积LDPC译码方法、装置、译码器及系统 技术领域
本发明涉及通信技术领域，尤其涉及一种卷积LDPC译码方法、装置、译码器及系统。
背景技术
随着高速信息传输系统的发展，尤其是FEC(英文：Forward Error Correction，中文：前向纠错)技术的普及，为了在通信网络系统中实现高性能、高流量、低实现难度的FEC过程，可以使用具有较高传输性能的LDPC(英文：Low Density Parity Code，中文：低密度奇偶校验码)来完成信息传输。
传统LDPC译码是针对单个分组信息进行的，具体可以通过校验矩阵(H矩阵)来实现。H矩阵为一个M×N矩阵，其中，N为分组码长度，K为信息的长度，M＝N-K，表示有M个校验方程，H矩阵的每行均表示一个校验方程。一般LDPC分组译码器将M个校验方程分为m层，每层含有M/m个校验方程。译码过程就是LDPC分组译码器将一个码字，分别用第1层至第m层校验方程进行校验，输出的译码结果会反馈回LDPC分组译码器输入端进行多次迭代，直到完成译码过程。
在LDPC译码方式中，除了上述传统的分组LDPC译码方式，还包括卷积LDPC译码方式。目前，提出了一种用于卷积LDPC的串行流水译码架构，如图1所示，解映射单元将符号进行处理后，依次通过译码单元1至n，最终经过判决输出单元得到最终译码结果。其中，n为大于1的正整数，译码控制单元可以用于控制其他各个单元的开启。相比较于传统LDPC译码过程，采用上述方法，虽然能够降低单次处理信息的码长，降低电路的实现难度，提高编译码的性能，但仍然会存在译码不准确的问题。
发明内容
本发明实施例提供一种卷积LDPC译码方法、装置、译码器及系统，能够提高译码过程的准确性。
为达到上述目的，本发明实施例采用如下技术方案：
第一方面，本发明实施例提供一种卷积LDPC译码方法，所述方法包括：接收第一校验节点信息，所述第一校验节点信息包括上一级译码单元输出目标比特的所有校验节点信息；从符号缓存单元读取所述目标比特对应的符号值；根据所述第一校验节点信息和所述符号值，确定对数似然比LLR和第一后验概率对数比APP，所述第一APP用于表示第一时刻所述目标比特的译码结果；向下一级译码单元发送所述第一校验节点信息和所述第一APP，以便于所述下一级译码单元根据所述第一校验节点信息和所述第一APP得到第二APP和第二校验节点信息，所述第二APP用于表示第二时刻所述目标比特的译码结果，所述第二校验节点信息包括所述下一级译码单元输出所述目标比特的所有校验节点信息。
结合上一级译码单元输出的目标比特的所有校验节点信息，以及目标比特对应的符号值，来调整卷积LDPC译码过程中的LLR，也就是在调整第一校验节点信息的基础上，通过调整LLR来使卷积LDPC译码过程的准确率进一步提升。因此，能够提高相干光传输系统中所执行的译码过程的准确性，也就是接收机可以根据所接收的来自于发射机的符号值，进行译码，并得到准确的译码结果，从而提高相干光传输系统的传输性能。
结合第一方面，在第一方面第一种可能的实现方式中，所述根据所述第一校验节点信息和所述符号值，确定LLR和第一APP，包括：确定所述符号值对应每个比特的外信息，所述符号值对应至少两个比特，所述外信息为所述上一级译码单元输出的所有校验节点信息之和；根据所述每个比特的外信息，确定所述LLR；将所述目标比特的外信息与所述LLR之和确定为所述第一APP。
在确定LLR过程中，可以先确定符号值对应每个比特的外信息，也就是通过对单个比特的所有校验节点信息求和来确定该单个比特 的外信息，之后根据所得到的每个比特的外信息来确定LLR，确保所确定的LLR能够达到收敛的效果，从而进一步提升译码过程的准确率，即进一步提高相干光传输系统的传输性能。
结合第一方面第一种可能的实现方式，在第一方面第二种可能的实现方式中，所述符号值包括I值和Q值，所述符号值用于表示符号点，所述根据所述每个比特的外信息，确定所述LLR，包括：根据所述I值和所述Q值，确定所述符号点的坐标；采用公式
Figure PCTCN2016082211-appb-000001
进行计算，得到第i个比特对应的LLR，即所述LLR，其中，a表示目标星座点，
Figure PCTCN2016082211-appb-000002
表示第i个比特取值为1的星座点的集合，表示第i个比特取值为0的星座点的集合，
Figure PCTCN2016082211-appb-000004
表示所述符号点到所述目标星座点的欧式距离，
Figure PCTCN2016082211-appb-000005
表示所述目标星座点中第j个比特的取值，G(x)表示x的函数，
Figure PCTCN2016082211-appb-000006
L(Cj)表示第j个比特的外信息，σ表示标准差，m为大于1的正整数，i和j为大于或等于1的正整数。
在确定LLR过程中，不仅考虑到了符号点所处的位置，同时考虑到了符号值所能够对应的每个比特的外信息，并结合公式，经过计算得到更加适用的LLR。也就意味着，通过交替调节LLR和∑CN来确保译码过程的准确性，进一步提高了相干光传输系统的传输性能。
第二方面，本发明实施例提供一种卷积LDPC译码方法，所述方法用于相干光传输系统，所述方法包括：译码器获取所述相干光传输系统中接收机输出的符号值；译码器将所述符号值对应的每个比特按照迭代算法进行计算，得到所述每个比特的译码结果，所述迭代算法包括至少一次校验节点信息的更新与至少一次对数似然比LLR的更新；译码器根据所述迭代算法最后一次更新的校验节点信息和LLR，确定所述每个比特的译码结果。
通过将符号值对应的每个比特进行迭代算法的运算，从而调整卷积LDPC译码过程中的LLR，也就是在调整第一校验节点信息的基 础上，通过调整LLR来使卷积LDPC译码过程的准确率进一步提升。因此，能够提高相干光传输系统中所执行的译码过程的准确性，也就是接收机可以根据所接收的来自于发射机的符号值，进行译码，并得到准确的译码结果，从而提高相干光传输系统的传输性能。
结合第二方面，在第二方面第一种可能的实现方式中，在所述译码器确定所述每个比特的译码结果之后，包括：译码器根据所述每个比特的译码结果，确定所述符号值对应的译码结果。
在提高相干光传输系统中所执行的译码过程的准确性的基础上，通过在译码过程中先将符号值对应的每个比特进行译码并得到各自对应的译码结果，之后再将这些译码结果进行整合，从而得到完整符号值对应的译码结果，这样一来不仅能够进一步提升译码过程的准确性，且由于数据是以比特为单位进行译码的，因此，还能够在一定程度上减少译码过程中产生错误率。
结合第二方面第一种可能的实现方式，在第二方面第二种可能的实现方式中，所述符号值对应的译码结果为二进制比特流，在所述译码器确定所述符号值对应的译码结果之后，包括：所述译码器将所述二进制比特流发送至交换节点的网络设备，以便于所述网络设备将所述二进制比特流发送至目标设备，完成通信数据的传输过程。
在提高相干光传输系统中所执行的译码过程的准确性的基础上，通过将译码结果发送至网络设备，并由网络设备发送至目标设备，以完成通信数据的转发过程。
第三方面，本发明实施例提供一种卷积LDPC译码装置，所述装置包括：接收模块，用于接收第一校验节点信息，所述第一校验节点信息包括上一级译码单元输出目标比特的所有校验节点信息；读取模块，用于从符号缓存单元读取所述目标比特对应的符号值；确定模块，用于根据所述第一校验节点信息和所述符号值，确定对数似然比LLR和第一后验概率对数比APP，所述第一APP用于表示第一时刻所述目标比特的译码结果；发送模块，用于向下一级译码单 元发送所述第一校验节点信息和所述第一APP，以便于所述下一级译码单元根据所述第一校验节点信息和所述第一APP得到第二APP和第二校验节点信息，所述第二APP用于表示第二时刻所述目标比特的译码结果，所述第二校验节点信息包括所述下一级译码单元输出所述目标比特的所有校验节点信息。
结合第三方面，在第三方面第一种可能的实现方式中，所述确定模块，具体用于确定所述符号值对应每个比特的外信息，所述符号值对应至少两个比特，所述外信息为所述上一级译码单元输出的所有校验节点信息之和；根据所述每个比特的外信息，确定所述LLR；将所述目标比特的外信息与所述LLR之和确定为所述第一APP。
结合第三方面第一种可能的实现方式，在第三方面第二种可能的实现方式中，所述符号值包括I值和Q值，所述符号值用于表示符号点，所述确定模块，具体用于根据所述I值和所述Q值，确定所述符号点的坐标；采用公式
Figure PCTCN2016082211-appb-000007
进行计算，得到第i个比特对应的LLR，即所述LLR，其中，a表示目标星座点，
Figure PCTCN2016082211-appb-000008
表示第i个比特取值为1的星座点的集合，
Figure PCTCN2016082211-appb-000009
表示第i个比特取值为0的星座点的集合，
Figure PCTCN2016082211-appb-000010
表示所述符号点到所述目标星座点的欧式距离，
Figure PCTCN2016082211-appb-000011
表示所述目标星座点中第j个比特的取值，G(x)表示x的函数，
Figure PCTCN2016082211-appb-000012
L(Cj)表示第j个比特的外信息，σ表示标准差，m为大于1的正整数，i和j为大于或等于1的正整数。
第四方面，本发明实施例提供一种卷积LDPC译码装置，所述装置用于一种相干光传输系统，所述装置包括：获取模块，用于获取所述相干光传输系统中接收机输出的符号值；计算模块，用于将所述符号值对应的每个比特按照迭代算法进行计算，得到所述每个比特的译码结果，所述迭代算法包括至少一次校验节点信息的更新与至少一次对数似然比LLR的更新；确定模块，用于根据所述迭代算法最后一次更新的校验节点信息和LLR，确定所述每个比特的译码 结果。
结合第四方面，在第四方面第一种可能的实现方式中，所述确定模块，还用于根据所述每个比特的译码结果，确定所述符号值对应的译码结果。
结合第四方面第一种可能的实现方式，在第四方面第二种可能的实现方式中，所述符号值对应的译码结果为二进制比特流，所述装置还包括：发送模块，用于将所述二进制比特流发送至交换节点的网络设备，以便于所述网络设备将所述二进制比特流发送至目标设备，完成通信数据的传输过程。
第五方面，本发明实施例提供一种译码器，所述译码器用于一种相干光传输系统，所述译码器包括：接口电路，用于获取所述相干光传输系统中接收机输出的符号值；处理器，用于将所述符号值对应的每个比特按照迭代算法进行计算，得到所述每个比特的译码结果，所述迭代算法包括至少一次校验节点信息的更新与至少一次对数似然比LLR的更新；所述处理器，还用于根据所述迭代算法最后一次更新的校验节点信息和LLR，确定所述每个比特的译码结果。
结合第五方面，在第五方面第一种可能的实现方式中，在所述确定所述每个比特的译码结果之后，所述处理器，还用于根据所述每个比特的译码结果，确定所述符号值对应的译码结果并发送。
第六方面，本发明实施例提供一种相干光传输系统，所述相干光传输系统包括发射机、接收机和译码器，所述译码器为上述第五方面所述的译码器。
本发明实施例提供的一种卷积LDPC译码方法、装置、译码器及系统，根据接收到的上一级译码单元输出目标比特的所有校验节点信息，以及从符号缓存单元读取的目标比特对应的符号值，来确定LLR和第一APP，之后向下一集译码单元发送上一级译码单元所输出的目标比特的所有校验节点信息和第一APP，以便于下一级译码单元得到第二APP和第二校验节点信息。相比较于现有技术中解映射单元将符号进行处理后，依次通过译码单元1至n，最终经过判决 输出单元得到译码结果，也就意味着在现有技术的卷积LDPC译码过程中，仅通过调整校验节点信息来提高译码的准确率，本发明可以结合上一级译码单元输出的目标比特的所有校验节点信息，以及目标比特对应的符号值，来调整卷积LDPC译码过程中的LLR，也就是在调整第一校验节点信息的基础上，通过调整LLR来使卷积LDPC译码过程的准确率进一步提升。因此，能够提高相干光传输系统中所执行的译码过程的准确性，也就是接收机可以根据所接收的来自于发射机的符号值，进行译码，并得到准确的译码结果，从而提高相干光传输系统的传输性能。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本发明实施例提供的一种具体应用场景示意图；
图2为本发明实施例提供的另一种具体应用场景示意图；
图3为本发明实施例提供的另一种具体应用场景示意图；
图4为本发明实施例提供的一种卷积LDPC译码方法流程图；
图5为本发明实施例提供的一种译码过程的示意图；
图6为本发明实施例提供的一种重解映射过程的示意图；
图7为本发明实施例提供的另一种卷积LDPC译码方法流程图；
图8为本发明实施例提供的另一种卷积LDPC译码方法流程图；
图9为本发明实施例提供的另一种卷积LDPC译码方法流程图；
图10为本发明实施例提供的另一种卷积LDPC译码方法流程图；
图11为本发明实施例提供的另一种卷积LDPC译码方法流程图；
图12为本发明实施例提供的一种卷积LDPC译码装置的结构示意图；
图13为本发明实施例提供的另一种卷积LDPC译码装置的结构 示意图；
图14为本发明实施例提供的一种译码器的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
本发明实施例可以在如图1所示架构的基础上，增加符号缓存单元以及至少一个重解映射单元，之后在现有译码过程中调整第一校验节点信息的基础上，通过调整LLR来使卷积LDPC译码过程得到的译码结果更加准确。需要说明的是，本发明所试用的架构可以位于相干传输系统中，其中，相干光传输系统包括发射机和接收机，而本发明所试用的架构可以被视为接收机的一部分，或是在接收机接收到经由链路传输的数据之后，用于执行译码过程的架构。如图2所示的相干传输系统中，发射机发送数据，并经由FEC编码、调制映射过程之后得到包括I/Q分量的符号值，并经由链路传输至接收机，经由多种均衡/补偿之后，得到包括I/Q分量的符号值，并采用本发明所提供的方法流程在译码器中完成后续译码操作，得到译码结果。例如：如图3所示，为在原有架构的基础上增加了m个重解映射单元的架构，其中，m为大于1且小于n的正整数。在本发明实施例中，译码控制单元也可以用于控制各个重解映射单元和符号缓存单元的开启；符号缓存单元可以用于存储各个比特的符号值，以便于当各个重解映射单元需要获取相应符号值时，能够从符号缓存单元来获取。需要说明的是，重解映射单元可以设置在串行架构中两个相邻的译码单元之间。另外，由于每个译码单元内部都需要进行多个行层译码，如果想进一步提高译码过程的准确率，还可以在译码单元内部的两个相邻行层译码过程之间增加重解映射单元。在本发明实施例中，可以根据对译码准确率的需求和/或能够用于重 解映射的资源情况，设置一个或多个重解映射单元，在此对于设置重解映射单元的位置以及数量不作具体限定。
本发明实施例提供一种卷积LDPC译码方法，以重解映射单元设置在两个相邻的译码单元之间为例，如图4所示，该方法均可以由重解映射单元来执行，该方法流程包括：
101、接收第一校验节点信息。
其中，第一校验节点信息包括上一级译码单元输出目标比特的所有校验节点信息。
由于每一个校验方程都会对应一个校验节点信息，因此，在上一级译码单元中，若目标比特对应了4个校验方程，则经过上一级译码单元会输出4个校验节点信息，这4个校验节点信息所构成的集合可以被视为第一校验节点信息，第一校验节点信息具体可以被表示为CN(英文：Check node information，中文：校验节点信息)1、CN2、CN3和CN4。
需要说明的是，每个译码单元不仅能输出第一校验节点信息，还可以输出经过该译码单元得到的APP(英文：A Priori Probability，中文：后验概率对数比)。在如图3所示的架构中，经过译码单元n，会输出经过整个串行结构最终得到的APP，该APP为LDCP译码器的输出信息。之后可以由判决输出单元来确定当APP大于或者等于0时，该比特判决结果为0，或是当APP小于0时，该比特的判决结果为1，并将判决结果经过判决输出单元输出。
102、从符号缓存单元读取目标比特对应的符号值。
当符号输入解映射单元时，或是在符号即将输入解映射单元之前，可以将该符号存储至符号缓存单元，这样一来，当重解映射单元需要获取目标比特对应的符号值时，就可以直接从符号缓存单元中读取。
103、根据第一校验节点信息和符号值，确定LLR(英文：Log Likelihood Ratio，中文：对数似然比)和第一APP。
其中，第一APP用于表示第一时刻目标比特的译码结果。也就 意味着，若在重解映射单元之后不存在下一级译码单元或是其他重解映射单元，那么第一APP可以用于表示目标比特最终的译码结果，若在重解映射单元之后仍然存在下一级译码单元或是其他重解映射单元，那么第一APP仅能用于表示第一时刻目标比特的译码结果，也可以被视为整个译码过程中一个临时的译码结果。其中，第一时刻为将目标比特经过重解映射单元之后，得到第一APP时的时刻。
LDCP译码算法的核心译码公式为APP＝LLR+∑CN。在现有技术中，LLR为比特的输入软信息，可以从信道或是前段均衡模块获得，LLR的数值是不变的，也就意味着，现有技术是通过各个译码单元来调整∑CN从而实现APP的更新，最终得到更加准确的译码结果。而在本发明实施例中，所添加的重解映射单元的主要作用在于对LLR的更新。由于初始的LLR为解映射的结果，因此，为了得到新的LLR，也同样需要对符号进行解映射的操作，即重解映射单元根据第一校验节点信息和所获取的符号值来进行重解映射操作，得到新的LLR，从而实现LLR的更新。结合上述译码公式，由于LLR被更新，因此，重解映射单元在输出新的LLR时，还会输出根据新的LLR以及上一级译码单元输出的所有CN之和，即∑CN进行计算得到的新的APP，即第一APP。
如图5所示，重解映射单元的输入为当前∑CN和目标比特对应的符号值，输出为第一APP。需要说明的是，上一级译码单元能够输出每个校验方程对应的CN，在本发明实施例中，∑CN可以直接由上一级译码单元计算后发送给重解映射单元，但由于重解映射单元还需要向下一集译码单元发送上一级译码单元中每个校验方程分别对应的CN，因此，在本发明实施例中，∑CN也可以直接在重解映射单元中进行计算，或是由其他单元经过计算后发送至重解映射单元。对于串联与重解映射单元之后的下一级译码单元而言，由于下一级译码单元的输入参数为重解映射单元输出的第一APP，以及上一级译码单元所输出的所有CN，因此，下一级译码单元可以根据上述译码公式推算出重解映射单元更新的LLR，并根据更新的LLR来更新 CN。
104、向下一级译码单元发送第一校验节点信息和第一APP。
由于重解映射单元仅对LLR进行了更新，因此，在输出时会输出经计算得到的第一APP，以及上一级译码单元输出的第一校验节点信息。之后下一级译码单元可以根据第一APP与第一校验节点信息中所有校验节点信息之和，即∑CN，经过计算得到重解映射单元所更新的LLR，并结合上述译码公式，根据更新的LLR以及下一级译码单元本身更新的∑CN，经过计算得到第二APP。需要说明的是，下一级译码单元本身更新的∑CN可以根据下一级译码单元中每个校验方程对应的CN值进行求和得到，在这里，所有CN值所构成的集合可以被视为第二校验节点信息。其中，第二APP用于表示第二时刻目标比特的译码结果，第二校验节点信息包括下一级译码单元输出目标比特的所有校验节点信息。也就意味着，若在下一级译码单元之后不存在其他译码单元或是重解映射单元，那么第二APP可以用于表示目标比特最终的译码结果，若在下一级译码单元之后仍然存在其他译码单元或是重解映射单元，那么第二APP仅能用于表示第二时刻目标比特的译码结果，也可以被视为整个译码过程中一个临时的译码结果。其中，第二时刻为将目标比特经过下一级译码单元之后，得到第二APP时的时刻。
如图6所示，第i行层译码的输入为旧∑CN和第一APP，输出为新∑CN和第二APP。需要说明的是，重解映射单元可以设置在相邻两个译码单元之间，也可以设置在相邻两个行层译码单元之间。在这里，以第i行层译码过程为例，经过第i行层译码之后，同样可以得到更新后的∑CN和更新后的第二APP。其中，旧∑CN可以是串联在第i行层译码单元之前的行层译码单元或是重解映射单元经过计算得到的所有CN之和，或是将之前的行层译码单元或重解映射单元输出的所有CN在第i行层译码单元中进行求和运算。同理，新∑CN也可以是在第i行层译码单元中进行求和运算并输出，或是在输入之后的行层译码单元或是重解映射单元时，由之后的行层译码 单元或是重解映射单元进行计算。
需要说明的是，采用上述步骤101至步骤104，可以得到目标比特的第二APP。若第二APP为译码过程中最后一次输出的APP值，那么可以根据该APP的取值与0之间的大小关系来确定目标比特的取值为0或1。比如：当APP的取值大于或等于0时，该APP值对应的目标比特判决为0；当APP的取值小于0时，该APP值对应的目标比特判决为1。由于每个符号会对应多个比特，因此，重复执行上述步骤101至步骤104，可以得到一个符号对应的所有比特的判决结果，从而得到该符号的译码结果。同理，若存在多个符号，则可以采用上述方式得到这多个符号的译码结果。
本发明实施例提供的一种卷积LDPC译码方法，根据接收到的上一级译码单元输出目标比特的所有校验节点信息，以及从符号缓存单元读取的目标比特对应的符号值，来确定LLR和第一APP，之后向下一集译码单元发送上一级译码单元所输出的目标比特的所有校验节点信息和第一APP，以便于下一级译码单元得到第二APP和第二校验节点信息。相比较于现有技术中解映射单元将符号进行处理后，依次通过译码单元1至n，最终经过判决输出单元得到译码结果，也就意味着在现有技术的卷积LDPC译码过程中，仅通过调整校验节点信息来提高译码的准确率，本发明可以结合上一级译码单元输出的目标比特的所有校验节点信息，以及目标比特对应的符号值，来调整卷积LDPC译码过程中的LLR，也就是在调整第一校验节点信息的基础上，通过调整LLR来使卷积LDPC译码过程的准确率进一步提升。因此，能够提高相干光传输系统中所执行的译码过程的准确性，也就是接收机可以根据所接收的来自于发射机的符号值，进行译码，并得到准确的译码结果，从而提高相干光传输系统的传输性能。
在本发明实施例的一个实现方式中，提供了一种具体用于确定LLR及第一APP的方法，因此，在如图4所示的实现方式的基础上，还可以实现为如图7所示的实现方式。其中，步骤103根据第一校 验节点信息和符号值，确定LLR和第一APP，可以具体实现为步骤1031至步骤1033：
1031、确定符号值对应每个比特的外信息。
其中，符号值对应至少两个比特，外信息为上一级译码单元输出的所有校验节点信息之和。
由于每个符号值能够对应IQ坐标系中多个点，也就意味着每个符号值能够对应多个比特。比如：1个符号可以对应8个取值，而这8个取值在IQ坐标系中分别表示8个不同的点，由于8＝23，因此，该符号值对应3个比特，则步骤1031需要分别确定这3个比特的外信息。
1032、根据每个比特的外信息，确定LLR。
1033、将目标比特的外信息与LLR之和确定为第一APP。
本发明实施例提供的一种卷积LDPC译码方法，可以通过确定所获取的符号值对应每个比特的外信息来确定LLR，并将目标比特的外信息与LLR之和确定为第一APP。相比较于现有技术中解映射单元将符号进行处理后，依次通过译码单元1至n，最终经过判决输出单元得到译码结果，也就意味着在现有技术的卷积LDPC译码过程中，仅通过调整校验节点信息来提高译码的准确率，本发明可以在调整第一校验节点信息的基础上，通过调整LLR来使卷积LDPC译码过程的准确率进一步提升，从而能够提高相干光传输系统中所执行的译码过程的准确性，也就是接收机可以根据所接收的来自于发射机的符号值，进行译码，并得到准确的译码结果，从而提高相干光传输系统的传输性能。并且，在确定LLR过程中，可以先确定符号值对应每个比特的外信息，也就是通过对单个比特的所有校验节点信息求和来确定该单个比特的外信息，之后根据所得到的每个比特的外信息来确定LLR，确保所确定的LLR能够达到收敛的效果，从而进一步提升译码过程的准确率，即进一步提高相干光传输系统的传输性能。
为了准确确定LLR，在本发明实施例的一个实现方式中，符号 值包括I值和Q值，符号值用于表示符号点，可以结合同一符号各个比特的外信息，采用步骤10322中的公式进行计算，得到所需LLR。因此，在如图5所示的实现方式的基础上，还可以实现为如图8所示的实现方式。其中，步骤1032根据每个比特的外信息，确定LLR，可以具体实现为步骤10321至步骤10322：
10321、根据I值和Q值，确定符号点的坐标。
10322、采用公式
Figure PCTCN2016082211-appb-000013
进行计算，得到第i个比特对应的LLR，即LLR。
其中，a表示目标星座点，
Figure PCTCN2016082211-appb-000014
表示第i个比特取值为1的星座点的集合，
Figure PCTCN2016082211-appb-000015
表示第i个比特取值为0的星座点的集合，
Figure PCTCN2016082211-appb-000016
表示符号点到目标星座点的欧式距离，
Figure PCTCN2016082211-appb-000017
表示目标星座点中第j个比特的取值，G(x)表示x的函数，
Figure PCTCN2016082211-appb-000018
L(Cj)表示第j个比特的外信息，σ表示标准差，m为大于1的正整数，i和j为大于或等于1的正整数。
例如：当符号值对应3个比特，也就是符号值对应8个值时，若步骤10322是用于确定第1比特的LLR，那么i为1，j可以为2或3。其中，第1比特可能为1或0，且对于8个值而言，第1比特取值为0的点为4个，这4个点构成集合
Figure PCTCN2016082211-appb-000019
取值为1的点也为4个，这4个点构成集合
Figure PCTCN2016082211-appb-000020
需要说明的是，采用本发明实施例所提出的技术方案，相比较于现有技术中串联解调译码方案分别在背靠背(英文：Back To Back，简称：BTB)、多波混传和12span G.652光纤传输的离线实验结果，在这三种场景下均有一定OSNR(英文：Optical Signal Noise Ratio，中文：光信噪比)性能提升。
本发明实施例提供的一种卷积LDPC译码方法，可以根据所获取的符号值中的I值和Q值来确定符号点的坐标，之后结合公式经计算得到LLR。。相比较于现有技术中解映射单元将符号进行处理后，依次通过译码单元1至n，最终经过判决输出单元得到译码结果，也就意味着在现有技术的卷积LDPC译码过程中，仅通过调整校验节 点信息来提高译码的准确率，本发明可以在调整第一校验节点信息的基础上，通过调整LLR来使卷积LDPC译码过程的准确率进一步提升，从而能够提高在相干光传输系统中所执行的译码过程的准确性，也就是接收机可以根据所接收的来自于发射机的符号值，进行译码，并得到准确的译码结果，从而提高相干光传输系统的传输性能。并且，在确定LLR过程中，不仅考虑到了符号点所处的位置，同时考虑到了符号值所能够对应的每个比特的外信息，并结合公式，经过计算得到更加适用的LLR。也就意味着，通过交替调节LLR和∑CN来确保译码过程的准确性，进一步提高了相干光传输系统的传输性能。
本发明实施例提供一种卷积LDPC译码方法，该方法用于相干光传输系统，该方法均可以由译码器来执行，如图9所示，该方法流程包括：
201、译码器获取相干光传输系统中接收机输出的符号值。
202、译码器将符号值对应的每个比特按照迭代算法进行计算，得到每个比特的译码结果。
其中，迭代算法包括至少一次校验节点信息的更新与至少一次LLR的更新。
203、译码器根据迭代算法最后一次更新的校验节点信息和LLR，确定每个比特的译码结果。
需要说明的是，在译码器中对于每个比特进行迭代算法进行计算的过程，可以参考上述的各种实现方式，在此不做赘述。
本发明实施例提供的一种卷积LDPC译码方法，译码器通过获取相干光传输系统中接收机输出的符号值，之后将符号值对应的每个比特按照迭代算法进行计算，得到每个比特的译码结果，并根据迭代算法最后一次更新的校验节点信息和LLR，从而确定每个比特的译码结果。相比较于现有技术中解映射单元将符号进行处理后，依次通过译码单元1至n，最终经过判决输出单元得到译码结果，也就意味着在现有技术的卷积LDPC译码过程中，仅通过调整校验节点 信息来提高译码的准确率，本发明可以通过将符号值对应的每个比特进行迭代算法的运算，从而调整卷积LDPC译码过程中的LLR，也就是在调整第一校验节点信息的基础上，通过调整LLR来使卷积LDPC译码过程的准确率进一步提升。因此，能够提高相干光传输系统中所执行的译码过程的准确性，也就是接收机可以根据所接收的来自于发射机的符号值，进行译码，并得到准确的译码结果，从而提高相干光传输系统的传输性能。
为了得到整个符号值的译码结果，在本发明实施例的一个实现方式中，需要先确定符号值对应的每个比特的译码结果，之后再确定符号值对应的译码结果。因此，在如图9所示的实现方式的基础上，还可以实现为如图10所示的实现方式。其中，在执行步骤203译码器根据迭代算法最后一次更新的校验节点信息和LLR，确定每个比特的译码结果之后，还可以执行步骤204：
204、译码器根据每个比特的译码结果，确定符号值对应的译码结果。
由于译码器可以得到每个比特的译码结果，也就意味着译码器能够得到符号值对应的所有比特中每个比特的译码结果。考虑到符号值所对应的比特为连续排列的二进制比特流，因此，这里得到的译码结果按照每个比特的译码结果与每个比特的对应关系，可以确定每个比特的译码结果在二进制比特流中所处的位置。也就是通过将每个比特的译码结果进行有序的排列，能够得到有序的二进制比特流，即符号值对应的译码结果。
本发明实施例提供的一种卷积LDPC译码方法，在确定译码结果的过程中，需要先确定符号值对应的每个比特的译码结果，之后再确定符号值对应的译码结果。相比较于现有技术中解映射单元将符号进行处理后，依次通过译码单元1至n，最终经过判决输出单元得到译码结果，也就意味着在现有技术的卷积LDPC译码过程中，仅通过调整校验节点信息来提高译码的准确率，本发明可以在提高相干光传输系统中所执行的译码过程的准确性的基础上，通过在译码 过程中先将符号值对应的每个比特进行译码并得到各自对应的译码结果，之后再将这些译码结果进行整合，从而得到完整符号值对应的译码结果，这样一来不仅能够进一步提升译码过程的准确性，且由于数据是以比特为单位进行译码的，因此，还能够在一定程度上减少译码过程中产生错误率。
在本发明实施例的一个实现方式中，符号值对应的译码结果可以为二进制比特流，也就意味着译码器可以直接将译码结果作为通信数据传输至交换节点的网络设备，并由网络设备发送至需要该通信数据的目标设备，从而完成通信数据的转发过程。因此，在如图10所示的实现方式的基础上，还可以实现为如图11所示的实现方式。其中，在执行步骤204、译码器根据每个比特的译码结果，确定符号值对应的译码结果之后，还可以执行步骤205：
205、译码器将二进制比特流发送至交换节点的网络设备。
在本发明实施例中，二进制比特流可以作为通信数据直接进行传输，因此，译码器可以将得到的符号值对应的译码结果直接发送至交换节点的网络设备，之后可以由网络设备转发至目标设备，从而完成通信数据的传输过程。比如：当二进制比特流用于表示语音信号时，译码器可以直接将语音信号发送至目标设备，即对应的需要接收语音信号的终端，或是通过网络设备转发至目标设备，即通过具有转发功能的路由设备转发至需要接收语音信号的终端。
需要说明的是，在本发明实施例中，对于二进制比特流所表示的数据的类型不作具体限定，可以根据不同的通信数据传输场景来确定，并且，对于不同的通信数据而言，目标设备也可以是与通信数据所对应的各类具有接收功能的设备，在此对于目标设备的类型也不进行具体限定。
本发明实施例提供的一种卷积LDPC译码方法，在完成译码过程之后，可以将得到的二进制比特流作为通信数据，发送至网络设备，以便于该网络设备能够将通信数据发送至目标设备。相比较于现有技术中解映射单元将符号进行处理后，依次通过译码单元1至n， 最终经过判决输出单元得到译码结果，也就意味着在现有技术的卷积LDPC译码过程中，仅通过调整校验节点信息来提高译码的准确率，本发明可以在提高相干光传输系统中所执行的译码过程的准确性的基础上，通过将译码结果发送至网络设备，并由网络设备发送至目标设备，以完成通信数据的转发过程。
本发明实施例提供一种卷积LDPC译码装置30，该装置30用于一种相干光传输系统，该装置30可以用于执行上述如图4、图7或图8所示的方法流程，如图12所示，该装置30包括：
接收模块31，用于接收第一校验节点信息，第一校验节点信息包括上一级译码单元输出目标比特的所有校验节点信息。
读取模块32，用于从符号缓存单元读取目标比特对应的符号值。
确定模块33，用于根据接收模块31所接收的第一校验节点信息和读取模块32所读取的符号值，确定对数似然比LLR和第一后验概率对数比APP，第一APP用于表示第一时刻目标比特的译码结果。
发送模块34，用于向下一级译码单元发送第一校验节点信息和通过确定模块33确定的第一APP，以便于下一级译码单元根据第一校验节点信息和第一APP得到第二APP和第二校验节点信息，第二APP用于表示第二时刻目标比特的译码结果，第二校验节点信息包括下一级译码单元输出目标比特的所有校验节点信息。
在本发明实施例的一个实现方式中，确定模块33，具体用于确定符号值对应每个比特的外信息，符号值对应至少两个比特，外信息为上一级译码单元输出的所有校验节点信息之和；
根据每个比特的外信息，确定LLR；
将目标比特的外信息与LLR之和确定为第一APP。
在本发明实施例的一个实现方式中，符号值包括I值和Q值，符号值用于表示符号点，确定模块33，具体用于根据I值和Q值，确定符号点的坐标；
采用公式
Figure PCTCN2016082211-appb-000021
进行计算，得到第i个比特对应的LLR，即LLR，其中，a表示目标星座点，
Figure PCTCN2016082211-appb-000022
表示第i个比特取值为1的星座点的集合，
Figure PCTCN2016082211-appb-000023
表示第i个比特取值为0的星座点的集合，
Figure PCTCN2016082211-appb-000024
表示符号点到目标星座点的欧式距离，
Figure PCTCN2016082211-appb-000025
表示目标星座点中第j个比特的取值，G(x)表示x的函数，
Figure PCTCN2016082211-appb-000026
L(Cj)表示第j个比特的外信息，σ表示标准差，m为大于1的正整数，i和j为大于或等于1的正整数。
本发明实施例提供的一种卷积LDPC译码装置，根据接收到的上一级译码单元输出目标比特的所有校验节点信息，以及从符号缓存单元读取的目标比特对应的符号值，来确定LLR和第一APP，之后向下一集译码单元发送上一级译码单元所输出的目标比特的所有校验节点信息和第一APP，以便于下一级译码单元得到第二APP和第二校验节点信息。相比较于现有技术中解映射单元将符号进行处理后，依次通过译码单元1至n，最终经过判决输出单元得到译码结果，也就意味着在现有技术的卷积LDPC译码过程中，仅通过调整校验节点信息来提高译码的准确率，本发明可以结合上一级译码单元输出的目标比特的所有校验节点信息，以及目标比特对应的符号值，来调整卷积LDPC译码过程中的LLR，也就是在调整第一校验节点信息的基础上，通过调整LLR来使卷积LDPC译码过程的准确率进一步提升。因此，能够提高相干光传输系统中所执行的译码过程的准确性，也就是接收机可以根据所接收的来自于发射机的符号值，进行译码，并得到准确的译码结果，从而提高相干光传输系统的传输性能。
本发明实施例提供一种卷积LDPC译码装置40，该装置40用于一种相干光传输系统，该装置40可以用于执行上述如图9至11中所示的任意一种方法流程，如图13所示，该装置40包括：
获取模块41，用于获取相干光传输系统中接收机输出的符号值。
计算模块42，用于将获取模块41所获取的符号值对应的每个比特按照迭代算法进行计算，得到每个比特的译码结果，迭代算法包括至少一次校验节点信息的更新与至少一次对数似然比LLR的更新。
确定模块43，用于根据通过计算模块42执行迭代算法最后一次更新的校验节点信息和LLR，确定每个比特的译码结果。
在本发明实施例的一个实现方式中，确定模块43，还用于根据每个比特的译码结果，确定符号值对应的译码结果。
在本发明实施例的一个实现方式中，符号值对应的译码结果为二进制比特流，该装置40还包括：
发送模块44，用于将二进制比特流发送至交换节点的网络设备，以便于网络设备将二进制比特流发送至目标设备，完成通信数据的传输过程。
本发明实施例提供的一种卷积LDPC译码装置，译码器通过获取相干光传输系统中接收机输出的符号值，之后将符号值对应的每个比特按照迭代算法进行计算，得到每个比特的译码结果，并根据迭代算法最后一次更新的校验节点信息和LLR，从而确定每个比特的译码结果。相比较于现有技术中解映射单元将符号进行处理后，依次通过译码单元1至n，最终经过判决输出单元得到译码结果，也就意味着在现有技术的卷积LDPC译码过程中，仅通过调整校验节点信息来提高译码的准确率，本发明可以通过将符号值对应的每个比特进行迭代算法的运算，从而调整卷积LDPC译码过程中的LLR，也就是在调整第一校验节点信息的基础上，通过调整LLR来使卷积LDPC译码过程的准确率进一步提升。因此，能够提高相干光传输系统中所执行的译码过程的准确性，也就是接收机可以根据所接收的来自于发射机的符号值，进行译码，并得到准确的译码结果，从而提高相干光传输系统的传输性能。
本发明实施例提供一种译码器50，该译码器50用于一种相干光传输系统，该译码器50可以用于执行上述如图4、图7或图8所 示的方法流程，如图14所示，该译码器50包括处理器51和接口电路52，图中还示出了存储器53和总线54，该处理器51、接口电路52和存储器53通过总线54连接并完成相互间的通信。
需要说明的是，这里的处理器51可以是一个处理元件，也可以是多个处理元件的统称。例如，该处理元件可以是中央处理器(英文：Central Processing Unit，简称：CPU)，也可以是特定集成电路(英文：Application Specific Integrated Circuit，简称：ASIC)，或者是被配置成实施本发明实施例的一个或多个集成电路，例如：一个或多个微处理器(英文：digital singnal processor，简称：DSP)，或，一个或者多个现场可编程门阵列(英文：Field Programmable Gate Array，简称：FPGA)。
存储器53可以是一个存储装置，也可以是多个存储元件的统称，且用于存储可执行程序代码或接入网管理设备运行所需要参数、数据等。且存储器53可以包括随机存储器(简称：RAM)，也可以包括非易失性存储器(英文：non-volatile memory)，例如磁盘存储器，闪存(简称：Flash)等。
总线54可以是工业标准体系结构(英文：Industry Standard Architecture，ISA)总线、外部设备互连(英文：Peripheral Component，简称：PCI)总线或扩展工业标准体系结构(英文：Extended Industry Standard Architecture，简称：EISA)总线等。该总线54可以分为地址总线、数据总线、控制总线等。为便于表示，图14中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
该译码器50还可以包括输入输出装置，连接于总线54，以通过总线54与处理器51等其它部分连接。
其中，处理器51调用存储器53中的程序代码，用于执行以上方法实施例中译码器50执行的操作。例如，包括：
通过接口电路52获取相干光传输系统中接收机输出的符号值。
通过处理器51将符号值对应的每个比特按照迭代算法进行计 算，得到每个比特的译码结果，迭代算法包括至少一次校验节点信息的更新与至少一次对数似然比LLR的更新。
根据迭代算法最后一次更新的校验节点信息和LLR，通过处理器51确定每个比特的译码结果。
在本发明实施例的一个实现方式中，在确定每个比特的译码结果之后，根据每个比特的译码结果，通过处理器51确定符号值对应的译码结果并发送。
本发明实施例提供的一种译码器，译码器通过获取相干光传输系统中接收机输出的符号值，之后将符号值对应的每个比特按照迭代算法进行计算，得到每个比特的译码结果，并根据迭代算法最后一次更新的校验节点信息和LLR，从而确定每个比特的译码结果。相比较于现有技术中解映射单元将符号进行处理后，依次通过译码单元1至n，最终经过判决输出单元得到译码结果，也就意味着在现有技术的卷积LDPC译码过程中，仅通过调整校验节点信息来提高译码的准确率，本发明可以通过将符号值对应的每个比特进行迭代算法的运算，从而调整卷积LDPC译码过程中的LLR，也就是在调整第一校验节点信息的基础上，通过调整LLR来使卷积LDPC译码过程的准确率进一步提升。因此，能够提高相干光传输系统中所执行的译码过程的准确性，也就是接收机可以根据所接收的来自于发射机的符号值，进行译码，并得到准确的译码结果，从而提高相干光传输系统的传输性能。
本发明实施例提供一种相干光传输系统，相干光传输系统包括发射机、接收机和译码器，其中，译码器为上述如图14所示的译码器50。
本发明实施例提供的一种相干光传输系统，译码器通过获取相干光传输系统中接收机输出的符号值，之后将符号值对应的每个比特按照迭代算法进行计算，得到每个比特的译码结果，并根据迭代算法最后一次更新的校验节点信息和LLR，从而确定每个比特的译码结果。相比较于现有技术中解映射单元将符号进行处理后，依次 通过译码单元1至n，最终经过判决输出单元得到译码结果，也就意味着在现有技术的卷积LDPC译码过程中，仅通过调整校验节点信息来提高译码的准确率，本发明可以通过将符号值对应的每个比特进行迭代算法的运算，从而调整卷积LDPC译码过程中的LLR，也就是在调整第一校验节点信息的基础上，通过调整LLR来使卷积LDPC译码过程的准确率进一步提升。因此，能够提高相干光传输系统中所执行的译码过程的准确性，也就是接收机可以根据所接收的来自于发射机的符号值，进行译码，并得到准确的译码结果，从而提高相干光传输系统的传输性能。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于设备实施例而言，由于其基本相似于方法实施例，所以描述得比较简单，相关之处参见方法实施例的部分说明即可。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(英文：Read-Only Memory，简称：ROM)或随机存储记忆体(英文：Random Access Memory，简称：RAM)等。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (15)

  1. 一种卷积LDPC译码方法，其特征在于，所述方法包括：
    接收第一校验节点信息，所述第一校验节点信息包括上一级译码单元输出目标比特的所有校验节点信息；
    从符号缓存单元读取所述目标比特对应的符号值；
    根据所述第一校验节点信息和所述符号值，确定对数似然比LLR和第一后验概率对数比APP，所述第一APP用于表示第一时刻所述目标比特的译码结果；
    向下一级译码单元发送所述第一校验节点信息和所述第一APP，以便于所述下一级译码单元根据所述第一校验节点信息和所述第一APP得到第二APP和第二校验节点信息，所述第二APP用于表示第二时刻所述目标比特的译码结果，所述第二校验节点信息包括所述下一级译码单元输出所述目标比特的所有校验节点信息。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述第一校验节点信息和所述符号值，确定LLR和第一APP，包括：
    确定所述符号值对应每个比特的外信息，所述符号值对应至少两个比特，所述外信息为所述上一级译码单元输出的所有校验节点信息之和；
    根据所述每个比特的外信息，确定所述LLR；
    将所述目标比特的外信息与所述LLR之和确定为所述第一APP。
  3. 根据权利要求2所述的方法，其特征在于，所述符号值包括I值和Q值，所述符号值用于表示符号点，所述根据所述每个比特的外信息，确定所述LLR，包括：
    根据所述I值和所述Q值，确定所述符号点的坐标；
    采用公式
    Figure PCTCN2016082211-appb-100001
    进行计算，得到第i个比特对应的LLR，即所述LLR，其中，a表示目标星座点，
    Figure PCTCN2016082211-appb-100002
    表示第i个比特取值为1的星座点的集合，
    Figure PCTCN2016082211-appb-100003
    表示第i个比特取值为0的星座点的集合，
    Figure PCTCN2016082211-appb-100004
    表示所述符号点到所述目标星座点的欧式距离，
    Figure PCTCN2016082211-appb-100005
    表示所述目标星座点中第j个比特的取值，G(x)表示x的函数，
    Figure PCTCN2016082211-appb-100006
    L(Cj)表示第j个比特的外信息，σ表示标准差，m为大于1的正整数，i和j为大于或等于1的正整数。
  4. 一种卷积LDPC译码方法，其特征在于，所述方法用于相干光传输系统，所述方法包括：
    译码器获取所述相干光传输系统中接收机输出的符号值；
    译码器将所述符号值对应的每个比特按照迭代算法进行计算，得到所述每个比特的译码结果，所述迭代算法包括至少一次校验节点信息的更新与至少一次对数似然比LLR的更新；
    译码器根据所述迭代算法最后一次更新的校验节点信息和LLR，确定所述每个比特的译码结果。
  5. 根据权利要求4所述的方法，其特征在于，在所述译码器确定所述每个比特的译码结果之后，包括：
    译码器根据所述每个比特的译码结果，确定所述符号值对应的译码结果。
  6. 根据权利要求5所述的方法，其特征在于，所述符号值对应的译码结果为二进制比特流，在所述译码器确定所述符号值对应的译码结果之后，包括：
    所述译码器将所述二进制比特流发送至交换节点的网络设备，以便于所述网络设备将所述二进制比特流发送至目标设备。
  7. 一种卷积LDPC译码装置，其特征在于，所述装置包括：
    接收模块，用于接收第一校验节点信息，所述第一校验节点信息包括上一级译码单元输出目标比特的所有校验节点信息；
    读取模块，用于从符号缓存单元读取所述目标比特对应的符号值；
    确定模块，用于根据所述第一校验节点信息和所述符号值，确定对数似然比LLR和第一后验概率对数比APP，所述第一APP用于表示第一时刻所述目标比特的译码结果；
    发送模块，用于向下一级译码单元发送所述第一校验节点信息和 所述第一APP，以便于所述下一级译码单元根据所述第一校验节点信息和所述第一APP得到第二APP和第二校验节点信息，所述第二APP用于表示第二时刻所述目标比特的译码结果，所述第二校验节点信息包括所述下一级译码单元输出所述目标比特的所有校验节点信息。
  8. 根据权利要求7所述的装置，其特征在于，所述确定模块，具体用于确定所述符号值对应每个比特的外信息，所述符号值对应至少两个比特，所述外信息为所述上一级译码单元输出的所有校验节点信息之和；
    根据所述每个比特的外信息，确定所述LLR；
    将所述目标比特的外信息与所述LLR之和确定为所述第一APP。
  9. 根据权利要求8所述的装置，其特征在于，所述符号值包括I值和Q值，所述符号值用于表示符号点，所述确定模块，具体用于根据所述I值和所述Q值，确定所述符号点的坐标；
    采用公式
    Figure PCTCN2016082211-appb-100007
    进行计算，得到第i个比特对应的LLR，即所述LLR，其中，a表示目标星座点，
    Figure PCTCN2016082211-appb-100008
    表示第i个比特取值为1的星座点的集合，
    Figure PCTCN2016082211-appb-100009
    表示第i个比特取值为0的星座点的集合，
    Figure PCTCN2016082211-appb-100010
    表示所述符号点到所述目标星座点的欧式距离，
    Figure PCTCN2016082211-appb-100011
    表示所述目标星座点中第j个比特的取值，G(x)表示x的函数，
    Figure PCTCN2016082211-appb-100012
    L(Cj)表示第j个比特的外信息，σ表示标准差，m为大于1的正整数，i和j为大于或等于1的正整数。
  10. 一种卷积LDPC译码装置，其特征在于，所述装置用于一种相干光传输系统，所述装置包括：
    获取模块，用于获取所述相干光传输系统中接收机输出的符号值；
    计算模块，用于将所述符号值对应的每个比特按照迭代算法进行计算，得到所述每个比特的译码结果，所述迭代算法包括至少一次校验节点信息的更新与至少一次对数似然比LLR的更新；
    确定模块，用于根据所述迭代算法最后一次更新的校验节点信息和LLR，确定所述每个比特的译码结果。
  11. 根据权利要求10所述的装置，其特征在于，所述确定模块，还用于根据所述每个比特的译码结果，确定所述符号值对应的译码结果。
  12. 根据权利要求11所述的装置，其特征在于，所述符号值对应的译码结果为二进制比特流，所述装置还包括：
    发送模块，用于将所述二进制比特流发送至交换节点的网络设备，以便于所述网络设备将所述二进制比特流发送至目标设备。
  13. 一种译码器，其特征在于，所述译码器用于一种相干光传输系统，所述译码器包括：
    接口电路，用于获取所述相干光传输系统中接收机输出的符号值；
    处理器，用于将所述符号值对应的每个比特按照迭代算法进行计算，得到所述每个比特的译码结果，所述迭代算法包括至少一次校验节点信息的更新与至少一次对数似然比LLR的更新；
    所述处理器，还用于根据所述迭代算法最后一次更新的校验节点信息和LLR，确定所述每个比特的译码结果。
  14. 根据权利要求13所述的译码器，其特征在于，在所述确定所述每个比特的译码结果之后，所述处理器，还用于根据所述每个比特的译码结果，确定所述符号值对应的译码结果并发送。
  15. 一种相干光传输系统，其特征在于，所述相干光传输系统包括发射机、接收机和译码器，所述译码器为上述权利要求13或14所述的译码器。
PCT/CN2016/082211 2016-05-16 2016-05-16 一种卷积ldpc译码方法、装置、译码器及系统 WO2017197561A1 (zh)

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