WO2017190533A1 - 阵列基板、液晶显示面板及显示装置 - Google Patents

阵列基板、液晶显示面板及显示装置 Download PDF

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Publication number
WO2017190533A1
WO2017190533A1 PCT/CN2017/071417 CN2017071417W WO2017190533A1 WO 2017190533 A1 WO2017190533 A1 WO 2017190533A1 CN 2017071417 W CN2017071417 W CN 2017071417W WO 2017190533 A1 WO2017190533 A1 WO 2017190533A1
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Prior art keywords
insulating layer
conductive pattern
substrate
array substrate
via hole
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PCT/CN2017/071417
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English (en)
French (fr)
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程鸿飞
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京东方科技集团股份有限公司
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Priority to US15/535,643 priority Critical patent/US10678106B2/en
Publication of WO2017190533A1 publication Critical patent/WO2017190533A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • Embodiments of the present invention relate to the field of display technologies, and in particular, to an array substrate, a liquid crystal display panel, and a display device.
  • the liquid crystal display technology is widely used in television, mobile phone and public information display.
  • the existing liquid crystal display panel comprises a color film substrate and an array substrate.
  • the array substrate is provided with a plurality of pixel regions, and each pixel region is provided with a pixel electrode and a film.
  • the transistor and the pixel electrode are connected to the drain of the thin film transistor through the pixel electrode via, the drain of the thin film transistor is generally made of metal, the pixel electrode is generally made of a transparent conductive material, and the adhesion between the pixel electrode and the metal is poor, so
  • the existing array substrate there is a problem that the drain of the pixel electrode and the thin film transistor is easily peeled off at the joint, which affects the yield of the array substrate.
  • the technical problem to be solved by the present invention is to provide an array substrate, a liquid crystal display panel, and a display device, which can solve the problem that the pixel electrode and the drain of the existing array substrate are easily peeled off at the joint, and improve the yield of the array substrate.
  • an array substrate comprising: a first insulating layer formed on a substrate, a first conductive pattern on the first insulating layer, and a second insulating layer on the first conductive pattern a second conductive pattern on the second insulating layer, the second conductive pattern being connected to the first conductive pattern through a second via extending through the second insulating layer, the array substrate further comprising Having a first via extending through the first conductive pattern of the first insulating layer, an orthographic projection of the first via on the base substrate and the second via being in the lining The orthographic projections on the base substrate at least partially overlap, and the second conductive pattern contacts the first insulating layer through the first vias.
  • liquid crystal display panel comprising the array as described above Column substrate.
  • a display device comprising the liquid crystal display panel as described above.
  • FIG. 1 is a schematic plan view of an array substrate according to an embodiment of the present invention.
  • Figure 2 is a cross-sectional view along line A1A2 of Figure 1;
  • FIG. 3 is a schematic plan view of another array substrate according to an embodiment of the present invention.
  • Figure 4 is a cross-sectional view along line A1A2 of Figure 3;
  • Figure 5 is a cross-sectional view along B1B2 of Figures 1 and 3.
  • the embodiment of the present invention provides an array substrate, a liquid crystal display panel and a display device for the problem that the pixel electrode and the drain are easily peeled off at the joint, which can solve the problem that the pixel electrode and the drain of the existing array substrate are easily peeled off at the joint. Problem, improve the yield of the array substrate.
  • An embodiment of the present invention provides an array substrate including a first insulating layer formed on a substrate, a first conductive pattern on the first insulating layer, and a second insulating layer on the first conductive pattern. a second conductive pattern on the insulating layer, the second conductive pattern being connected to the first conductive pattern through the second via hole penetrating the second insulating layer, the array substrate further comprising a first conductive pattern extending through the first insulating layer A via, the orthographic projection of the first via on the substrate substrate at least partially overlaps the orthographic projection of the second via on the substrate, and the second conductive pattern contacts the first insulating layer through the first via.
  • the second conductive pattern is connected to the first conductive pattern through the second via hole, and is in contact with the first insulating layer through the first via hole at the connection with the first conductive pattern, on the one hand, the second conductive pattern is Electrical connection is achieved between the first conductive patterns, and on the other hand, because of good adhesion between the conductive material and the insulating layer, the second conductive pattern can be prevented from being peeled off from the first insulating layer, thereby making The two conductive patterns and the first conductive pattern are not easily peeled off at the joint.
  • the first via hole also penetrates the first insulating layer to expose the substrate, and the second conductive pattern is further in contact with the substrate through the first via, since the substrate also belongs to the insulating material, The second conductive pattern is also not easily peeled off from the base substrate, so that the second conductive pattern and the first conductive pattern are not easily peeled off at the joint.
  • the first via penetrates through the first insulating layer, the first via can still expose a portion of the first insulating layer in a direction perpendicular to the substrate, and the second conductive pattern not only contacts the substrate through the first via It is also possible to contact the first insulating layer of this portion through the first via.
  • the cross section of the first via parallel to the surface of the substrate substrate may be circular, elliptical, square, rectangular, hexagonal or octagonal; second parallel to the surface of the substrate
  • the cross section of the via is circular, elliptical, square, rectangular, hexagonal or octagonal.
  • the first via hole parallel to the surface of the base substrate has a circular cross section
  • the second via hole parallel to the surface of the base substrate has a circular cross section
  • the first via hole is on the base substrate.
  • the upper orthographic projection completely falls into the orthographic projection of the second via on the substrate.
  • the first via has a smaller dimension in the first direction than the second via in the first a dimension in the direction; a dimension of the first via in the second direction is greater than a dimension of the second via in the second direction, the first direction being perpendicular to the second direction.
  • a dimension of the first via in the second direction is smaller than a dimension of the second via in the second direction; a dimension of the first via in the first direction is greater than a dimension of the second via in the first The upward dimension, the first direction being perpendicular to the second direction.
  • a first via hole parallel to a surface of the base substrate has an elliptical cross section
  • a second via hole parallel to a surface of the base substrate has an elliptical cross section
  • the long axis of the first via hole The direction is parallel to the second direction
  • the direction of the major axis of the second via is parallel to the first direction.
  • the angle between the long axis of the first via hole and the long axis of the second via hole may also be It is 30 degrees or 60 degrees.
  • a first via hole parallel to a surface of the base substrate has an elliptical cross section
  • a second via hole parallel to a surface of the base substrate has an elliptical cross section
  • the long axis of the first via hole The direction is parallel to the first direction
  • the direction of the long axis of the second via is parallel to the second direction.
  • the first direction is an extension direction of the gate line and the second direction is an extension direction of the data line.
  • the first conductive pattern is the drain of the thin film transistor and the second conductive pattern is the pixel electrode.
  • the first insulating layer may be a gate insulating layer and the second insulating layer is a passivation layer.
  • the first conductive pattern is a drain of the thin film transistor
  • the second conductive pattern is a pixel electrode
  • the first insulating layer is a gate insulating layer
  • the second insulating layer is a passivation layer
  • the first conductive pattern and the first An active layer is further disposed between the insulating layers, and the first via penetrates the active layer in addition to the first conductive pattern.
  • first insulating layer as a gate insulating layer and a second insulating layer as a passivation layer as an example.
  • the array substrate of the present embodiment includes a gate electrode 10a, a gate line 10, a common electrode line 100, a common electrode line first branch 100a, and a common electrode formed on the base substrate 1.
  • the second branch 100b of the line covers the gate 10a, the gate line 10, the common electrode line 100, and the common electrode
  • the array substrate further includes a passivation layer via 35h (ie, the second via) penetrating the passivation layer, and a drain via 33h (ie, the first via) described above.
  • the passivation layer via 35h exposes the drain 33, the drain via 33h can expose the gate insulating layer 15, the orthogonal projection of the drain via 33h on the base substrate 1 and the passivation layer via 35h on the substrate
  • the orthographic projections on the substrate 1 at least partially overlap such that a portion of the pixel electrodes 50 (eg, portions of the pixel electrodes 50 located on the sidewalls of the drain vias 33h) are always connected to the drain 33, and another portion of the pixel electrodes 50 (eg, the pixel electrodes 50)
  • the portion located at the bottom of the drain via 33h is in contact with the gate insulating layer 15 through the passivation layer via 35h and the drain via 33h.
  • the pixel electrode 50 On the one hand, electrical connection is achieved between the pixel electrode 50 and the drain 33, and on the other hand, since the conductive material and the insulating layer have good adhesion, the pixel electrode 50 can be prevented from being easily removed from the gate insulating layer 15. The peeling is performed so that the pixel electrode 50 and the drain electrode 33 are not easily peeled off at the joint.
  • the drain via 33h may also penetrate the gate insulating layer 15 to expose the substrate 1 such that the pixel electrode 50 is not only in contact with the gate insulating layer 15 but also in contact with the substrate 1 due to
  • the base substrate 1 also belongs to an insulating material, and therefore, the pixel electrode 50 is also not easily peeled off from the base substrate 1, so that the connection of the pixel electrode 50 and the drain electrode 33 is made closer.
  • the drain via 33h and the passivation via 35h are both circular, that is, the first via parallel to the surface of the base substrate 1 (drain The hole 33h) has a circular cross section, and the second via hole (passivation layer via 35h) parallel to the surface of the base substrate 1 has a circular cross section, and the passivation layer via 35h has a larger diameter than the drain.
  • the diameter of the via hole 33h, the orthographic projection of the drain via 33h on the base substrate 1 completely falls within the orthographic projection of the passivation layer via 35h on the base substrate 1. That is, the first via hole and the second via hole each constitute a concentric circle in a cross section parallel to the surface of the base substrate 1.
  • the drain via 33h when the active layer 20 is further disposed between the gate insulating layer 15 and the drain 33, the drain via 33h also penetrates the active layer 20 to expose the gate insulating layer 15; or the drain The via hole 33h also penetrates the active layer 20 and the gate insulating layer 15 to expose the base substrate 1.
  • the method for preparing an array substrate according to an embodiment of the present invention includes the following steps:
  • Step 1 Sputter deposit a gate metal layer on the base substrate 1, and form a gate electrode 10a, a gate line 10, a common electrode line 100, a common electrode line first branch 100a, and a common electrode line second branch 100b by a patterning process.
  • the gate metal layer is prepared by using a metal material such as Cu, Al, Mo, Ti, Cr, W, or the like, and may be prepared by using an alloy of these materials.
  • the gate metal layer may be a single layer structure or a multilayer structure such as Mo ⁇ Al. ⁇ Mo, Ti ⁇ Cu ⁇ Ti, MoTi ⁇ Cu.
  • Step 2 Depositing a gate insulating layer 15.
  • the gate insulating layer 15 is, for example, at least one of silicon nitride and silicon oxide.
  • the gate insulating layer 15 may have a single layer structure or a multilayer structure such as a silicon oxide/silicon nitride structure.
  • Step 3 Depositing a semiconductor material, and forming a pattern of the active layer 20 by a patterning process.
  • the semiconductor material is, for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon or an oxide semiconductor, such as a conventional film forming method such as PECVD (Plasma Enhanced Chemical Vapor Deposition), which continuously deposits a-Si and n. +a-Si, or sputter deposition of IGZO, and then forming a pattern of the active layer 20 by a patterning process;
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • Step 4 depositing a source/drain metal layer by sputtering, and forming a pattern of the data line 30, the source 31, and the drain 33 by a patterning process, wherein the drain 33 includes a drain via 33h.
  • the source/drain metal layer is prepared by using a metal material such as Cu, Al, Mo, Ti, Cr, W, or the like, and may be prepared by using an alloy of these materials.
  • the source/drain metal layer may be a single layer structure or a multilayer structure such as Mo. ⁇ Al ⁇ Mo, Ti ⁇ Cu ⁇ Ti, MoTi ⁇ Cu.
  • a passivation layer 35 is deposited, and a passivation layer via 35h exposing the drain electrode 33 is formed by a patterning process.
  • the passivation layer 35 is made of, for example, an inorganic material such as silicon nitride, or an organic insulating layer such as an organic resin material.
  • the passivation layer 35 may be a single layer structure or a multilayer structure, and may be, for example, a multilayer inorganic material layer or a multilayer structure composed of an inorganic material layer and an organic material layer.
  • silicon nitride is deposited by PECVD, and then a passivation layer via 35h exposing the drain electrode 33 is formed by a patterning process.
  • Step 6 Sputter deposit a layer of a transparent conductive material, such as ITO, and form a pattern of the pixel electrode 50 by a patterning process.
  • the pixel electrode 50 is in contact with the gate insulating layer 15 through the passivation layer via 35h and the drain via 33h.
  • the pixel electrode 50 may also employ other transparent conductive materials such as IZO.
  • the array substrate of the present invention is formed on the base substrate 1.
  • the gate 10a, the gate line 10, the common electrode line 100, the common electrode line first branch 100a, and the common electrode line second branch 100b cover the gate 10a, the gate line 10, the common electrode line 100, and the first branch of the common electrode line a conductive insulating layer 15 on the gate insulating layer 15, a data line 30, a source 31
  • the first conductive pattern covers the passivation layer 35 of the active layer 20, the data line 30, the source 31, and the drain 33 (ie, the second insulating layer), and the pixel electrode 50 on the passivation layer 35 (ie, The second conductive pattern described above).
  • the array substrate further includes a passivation layer via 35h (ie, the second via) passing through the passivation layer, a drain via 33h (ie, the first via), and a passivation layer via 35h exposed.
  • the drain 33, the drain via 33h can expose the gate insulating layer 15, the orthographic projection of the drain via 33h on the substrate substrate 1 and the orthographic projection of the passivation layer via 35h on the substrate 1 are at least partially The overlapping, such that a part of the pixel electrode 50 is always connected to the drain 33, and the other part of the pixel electrode 50 is in contact with the gate insulating layer 15 through the passivation layer via 35h and the drain via 33h, on the one hand, the pixel electrode 50 and the drain 33 The electrical connection is realized, and on the other hand, since the conductive material and the insulating layer have good adhesion, the pixel electrode 50 can be prevented from being peeled off from the gate insulating layer 15, so that the pixel electrode 50 and the drain are made. 33 is not
  • the drain via 33h may also penetrate the gate insulating layer 15 to expose the substrate 1 such that the pixel electrode 50 is not only in contact with the gate insulating layer 15 but also in contact with the substrate 1 due to
  • the base substrate 1 also belongs to an insulating material, and therefore, the pixel electrode 50 is also not easily peeled off from the base substrate 1, so that the connection of the pixel electrode 50 and the drain electrode 33 is made closer.
  • the size of the first via (drain via 33h) in the first direction is smaller than the dimension of the second via (passivation layer via 35h) in the first direction; the first via (drain via) 33h)
  • the dimension in the second direction is larger than the dimension of the second via (passivation layer via 35h) in the second direction, the first direction being perpendicular to the second direction.
  • the size of the first via (drain via 33h) in the second direction is smaller than the dimension of the second via (passivation layer via 35h) in the second direction; the first via ( The size of the drain via 33h) in the first direction is larger than the size of the second via (passivation layer via 35h) in the first direction, and the first direction is perpendicular to the second direction.
  • the first direction may be at an angle of 0 degrees, an angle of 30 degrees, or an angle of 60 degrees, etc., with respect to the direction in which the gate lines extend.
  • the first direction is the extending direction of the gate line
  • the second direction is the extension of the data line. to.
  • the drain via 33h and the passivation via via 35h are both elliptical, that is, the first via parallel to the surface of the base substrate 1 (drain The hole 33h) has an elliptical cross section, and the second via hole (passivation layer via 35h) parallel to the surface of the base substrate 1 has an elliptical cross section.
  • the long axis of the passivation layer via 35h and the long axis of the drain via 33h are perpendicular to each other.
  • the angle between the long axis of the passivation layer via 35h and the long axis of the drain via 33h is not limited to 90 degrees, and may be any angle, for example, 30 degrees, 60 degrees, 120 degrees, 150 degrees, or the like.
  • the long axis of the drain via 33h is parallel to the second direction
  • the long axis of the passivation layer via 35h is parallel to the first direction
  • the drain via 33h is The size in one direction is smaller than the size of the passivation layer via 35h in the first direction
  • the size of the drain via 33h in the second direction is larger than the size of the passivation layer via 35h in the second direction.
  • the long axis of the drain via 33h may be parallel to the first direction
  • the long axis of the passivation layer via 35h may be parallel to the second direction
  • the drain via 33h may be in the first direction.
  • the size is larger than the size of the passivation layer via 35h in the first direction
  • the size of the drain via 33h in the second direction is smaller than the size of the passivation layer via 35h in the second direction.
  • the drain via 33h when the active layer 20 is further disposed between the gate insulating layer 15 and the drain 33, the drain via 33h also penetrates the active layer 20 to expose the gate insulating layer 15; or the drain The via hole 33h also penetrates the active layer 20 and the gate insulating layer 15 to expose the base substrate 1.
  • the method for preparing an array substrate according to an embodiment of the present invention includes the following steps:
  • Step 1 Sputter deposit a gate metal layer on the base substrate 1, and form a gate electrode 10a, a gate line 10, a common electrode line 100, a common electrode line first branch 100a, and a common electrode line second branch 100b by a patterning process.
  • the gate metal layer is prepared by using a metal material such as Cu, Al, Mo, Ti, Cr, W, or the like, and may be prepared by using an alloy of these materials.
  • the gate metal layer may be a single layer structure or a multilayer structure such as Mo ⁇ Al. ⁇ Mo, Ti ⁇ Cu ⁇ Ti, MoTi ⁇ Cu.
  • Step 2 Depositing a gate insulating layer 15.
  • the gate insulating layer 15 is made of, for example, silicon nitride or silicon oxide, and the gate insulating layer 15 may have a single layer structure or a multilayer structure such as a silicon oxide/silicon nitride structure.
  • Step 3 Depositing a semiconductor material, and forming a pattern of the active layer 20 by a patterning process.
  • the semiconductor material is, for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon or an oxide semiconductor, such as A film formation method of PECVD (Plasma Enhanced Chemical Vapor Deposition) continuously deposits a-Si and n+a-Si, or sputter-deposits IGZO, and then forms a pattern of the active layer 20 by a patterning process.
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • Step 4 depositing a source/drain metal layer by sputtering, and forming a pattern of the data line 30, the source 31, and the drain 33 by a patterning process, wherein the drain 33 includes a drain via 33h.
  • the source/drain metal layer is prepared by using a metal material such as Cu, Al, Mo, Ti, Cr, W, or the like, and may be prepared by using an alloy of these materials.
  • the source/drain metal layer may be a single layer structure or a multilayer structure such as Mo. ⁇ Al ⁇ Mo, Ti ⁇ Cu ⁇ Ti, MoTi ⁇ Cu;
  • a passivation layer 35 is deposited, and a passivation layer via 35h exposing the drain electrode 33 is formed by a patterning process.
  • the passivation layer 35 is made of, for example, an inorganic material such as silicon nitride, or an organic insulating layer.
  • an organic resin material may be used.
  • the passivation layer 35 may be a single layer structure or a multilayer structure, and may be, for example, a plurality of inorganic materials. It may also be a multilayer structure composed of an inorganic material layer and an organic material layer. If silicon nitride is deposited by PECVD, a passivation layer via 35h exposing the drain 33 is formed by a patterning process.
  • Step 6 Sputter deposit a transparent conductive material layer such as ITO, and form a pattern of the pixel electrode 50 by a patterning process, and the pixel electrode 50 is in contact with the gate insulating layer 15 through the passivation layer via 35h and the drain via 33h.
  • the pixel electrode 50 may also employ other transparent conductive materials such as IZO.
  • the embodiment of the invention further provides a liquid crystal display panel comprising the array substrate according to any of the above embodiments.
  • Embodiments of the present invention also provide a display device including the liquid crystal display panel as described above.
  • the display device may be any product or component having a display function such as a liquid crystal panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, a navigator, an electronic paper, or the like.

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Abstract

一种阵列基板、液晶显示面板及显示装置。阵列基板包括形成在衬底基板(1)上的第一绝缘层(15)，位于第一绝缘层(15)上的第一导电图形(20、30、31、33)，位于所述第一导电图形(20、30、31、33)上的第二绝缘层(35)，位于所述第二绝缘层(35)上的第二导电图形(50)，所述第二导电图形(50)通过贯穿所述第二绝缘层(35)的第二过孔(35h)与所述第一导电图形(20、30、31、33)连接，所述阵列基板还包括有暴露出所述第一绝缘层(15)的贯穿所述第一导电图形(20、30、31、33)的第一过孔(33h)，所述第一过孔(33h)在所述衬底基板(1)上的正投影与所述第二过孔(35h)在所述衬底基板(1)上的正投影至少部分重叠，所述第二导电图形(50)通过所述第一过孔(33h)与所述第一绝缘层(15)接触。上述阵列基板能够解决像素电极和漏极在连接处易剥离的问题，提高阵列基板的良品率。

Description

阵列基板、液晶显示面板及显示装置 技术领域
本发明实施例涉及显示技术领域，特别是指一种阵列基板、液晶显示面板及显示装置。
背景技术
液晶显示技术广泛应用于电视、手机以及公共信息显示中，现有的液晶显示面板包括彩膜基板和阵列基板，阵列基板上设置有多个像素区域，每一像素区域内设置有像素电极和薄膜晶体管，像素电极通过像素电极过孔与薄膜晶体管的漏极连接，薄膜晶体管的漏极一般采用金属制作，像素电极一般采用透明导电材料制作，像素电极与金属之间的粘附性较差，因此，现有阵列基板中存在像素电极和薄膜晶体管的漏极在连接处易剥离的问题，影响了阵列基板的良品率。
发明内容
本发明要解决的技术问题是提供一种阵列基板、液晶显示面板及显示装置，能够解决现有阵列基板中像素电极和漏极在连接处易剥离的问题，提高阵列基板的良品率。
根据本发明第一方面，提供一种阵列基板，包括形成在衬底基板上的第一绝缘层，位于第一绝缘层上的第一导电图形，位于所述第一导电图形上的第二绝缘层，位于所述第二绝缘层上的第二导电图形，所述第二导电图形通过贯穿所述第二绝缘层的第二过孔与所述第一导电图形连接，所述阵列基板还包括有暴露出所述第一绝缘层的贯穿所述第一导电图形的第一过孔，所述第一过孔在所述衬底基板上的正投影与所述第二过孔在所述衬底基板上的正投影至少部分重叠，所述第二导电图形通过所述第一过孔与所述第一绝缘层接触。
根据本发明第二方面，还提供了一种液晶显示面板，包括如上所述的阵 列基板。
根据本发明第三方面，还提供了一种显示装置，包括如上所述的液晶显示面板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明实施例的阵列基板的平面示意图；
图2为图1中沿A1A2的剖面示意图；
图3本发明实施例的另一阵列基板的平面示意图；
图4为图3中沿A1A2的剖面示意图；
图5为图1和图3中沿B1B2的剖面示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置 关系也可能相应地改变。
本发明的实施例针对像素电极和漏极在连接处易剥离的问题，提供一种阵列基板、液晶显示面板及显示装置，能够解决现有阵列基板中像素电极和漏极在连接处易剥离的问题，提高阵列基板的良品率。
本发明实施例提供一种阵列基板，包括形成在衬底基板上的第一绝缘层，位于第一绝缘层上的第一导电图形，位于第一导电图形上的第二绝缘层，位于第二绝缘层上的第二导电图形，第二导电图形通过贯穿第二绝缘层的第二过孔与第一导电图形连接，阵列基板还包括有暴露出第一绝缘层的贯穿第一导电图形的第一过孔，第一过孔在衬底基板上的正投影与第二过孔在衬底基板上的正投影至少部分重叠，第二导电图形通过第一过孔与第一绝缘层接触。
本实施例中，第二导电图形通过第二过孔与第一导电图形连接，同时在与第一导电图形的连接处通过第一过孔与第一绝缘层接触，一方面第二导电图形与第一导电图形之间实现了电连接，另一方面由于导电材料与绝缘层之间具有良好的粘附性，因此，能够使第二导电图形不容易从第一绝缘层上剥离，从而使得第二导电图形与第一导电图形在连接处不易剥离。
至少一些实施例中，第一过孔还贯穿第一绝缘层、暴露出衬底基板，第二导电图形还通过第一过孔与衬底基板接触，由于衬底基板也属于绝缘材料，因此，第二导电图形也不容易从衬底基板上剥离，从而使得第二导电图形与第一导电图形在连接处不易剥离。在第一过孔贯穿第一绝缘层时，第一过孔仍能暴露出第一绝缘层在垂直于衬底基板方向上的一部分，第二导电图形不但通过第一过孔与衬底基板接触，还能通过第一过孔与这部分的第一绝缘层接触。
至少一些实施例中，平行于衬底基板的表面的第一过孔的截面可以为圆形，椭圆形，正方形，长方形，六边形或八边形；平行于衬底基板的表面的第二过孔的截面为圆形，椭圆形，正方形，长方形，六边形或八边形。
至少一些实施例中，平行于衬底基板的表面的第一过孔的截面为圆形，平行于衬底基板的表面的第二过孔的截面为圆形，第一过孔在衬底基板上的正投影完全落入第二过孔在衬底基板上的正投影中。
至少一些实施例中，第一过孔在第一方向上的尺寸小于第二过孔在第一 方向上的尺寸；第一过孔在第二方向上的尺寸大于第二过孔在第二方向上的尺寸，第一方向垂直于第二方向。
至少一些实施例中，第一过孔在第二方向上的尺寸小于第二过孔在第二方向上的尺寸；第一过孔在第一方向上的尺寸大于第二过孔在第一方向上的尺寸，第一方向垂直于第二方向。
至少一些实施例中，平行于衬底基板的表面的第一过孔的截面为椭圆形，平行于衬底基板的表面的第二过孔的截面为椭圆形，第一过孔的长轴的方向平行于第二方向，第二过孔的长轴的方向平行于第一方向。当然，在第一过孔和第二过孔在平行于衬底基板方向上的截面均为椭圆形时，第一过孔的长轴与第二过孔的长轴之间的夹角还可以为30度或60度。
至少一些实施例中，平行于衬底基板的表面的第一过孔的截面为椭圆形，平行于衬底基板的表面的第二过孔的截面为椭圆形，第一过孔的长轴的方向平行于第一方向，第二过孔的长轴的方向平行于第二方向。
至少一些实施例中，第一方向为栅线的延伸方向，第二方向为数据线的延伸方向。
至少一些实施例中，第一导电图形为薄膜晶体管的漏极，第二导电图形为像素电极。
至少一些实施例中，第一绝缘层可以为栅极绝缘层，第二绝缘层为钝化层。
至少一些实施例中，第一导电图形为薄膜晶体管的漏极，第二导电图形为像素电极；第一绝缘层为栅极绝缘层，第二绝缘层为钝化层；第一导电图形和第一绝缘层之间还设置有有源层，第一过孔除贯穿第一导电图形之外，还贯穿有源层。
下面结合附图，以第一绝缘层为栅极绝缘层、第二绝缘层为钝化层为例对本发明实施例进行进一步说明。
实施例一
如图1、图2和图5所示，本实施例的阵列基板包括形成在衬底基板1上的栅极10a、栅线10、公共电极线100、公共电极线第一分支100a、公共电极线第二分支100b，覆盖栅极10a、栅线10、公共电极线100、公共电极 线第一分支100a、公共电极线第二分支100b的栅极绝缘层15(即上述第一绝缘层)，位于栅极绝缘层15上的有源层20、数据线30、源极31、漏极33(即上述第一导电图形)，覆盖有源层20、数据线30、源极31、漏极33的钝化层35(即上述第二绝缘层)，位于钝化层35上的像素电极50(即上述第二导电图形)。阵列基板还包括贯穿钝化层的钝化层过孔35h(即上述第二过孔)、贯穿漏极的漏极过孔33h(即上述第一过孔)。钝化层过孔35h暴露出漏极33，漏极过孔33h能够暴露出栅极绝缘层15，漏极过孔33h在衬底基板1上的正投影与钝化层过孔35h在衬底基板1上的正投影至少部分重叠，这样一部分像素电极50(例如，像素电极50位于漏极过孔33h侧壁的部分)始终与漏极33连接，另一部分像素电极50(例如，像素电极50位于漏极过孔33h底部的部分)通过钝化层过孔35h和漏极过孔33h与栅极绝缘层15接触。一方面像素电极50与漏极33之间实现了电连接，另一方面由于导电材料与绝缘层之间具有良好的粘附性，因此，能够使像素电极50不容易从栅极绝缘层15上剥离，从而使得像素电极50与漏极33在连接处不易剥离。
至少一些实施例中，漏极过孔33h还可以贯穿栅极绝缘层15，暴露出衬底基板1，这样像素电极50不仅与栅极绝缘层15接触，还将与衬底基板1接触，由于衬底基板1也属于绝缘材料，因此，像素电极50也不容易从衬底基板1上剥离，从而使得像素电极50与漏极33的连接更加紧密。
本实施例中，如图1所示，漏极过孔33h和钝化层过孔35h均为圆形，即平行于所述衬底基板1的表面的所述第一过孔(漏极过孔33h)的截面为圆形，平行于所述衬底基板1的表面的所述第二过孔(钝化层过孔35h)的截面为圆形，钝化层过孔35h的直径大于漏极过孔33h的直径，漏极过孔33h在衬底基板1上的正投影完全落入钝化层过孔35h在衬底基板1上的正投影内。也就是说，第一过孔和第二过孔各自在平行于所述衬底基板1的表面的截面构成同心圆。
至少一些实施例中，在栅极绝缘层15和漏极33之间还设置有有源层20时，漏极过孔33h还贯穿有源层20，暴露出栅极绝缘层15；或者漏极过孔33h还贯穿有源层20和栅极绝缘层15，暴露出衬底基板1。
例如，本发明实施例的阵列基板的制备方法包括以下步骤：
步骤1、在衬底基板1上溅射沉积栅金属层，并且通过构图工艺形成栅极10a、栅线10、公共电极线100、公共电极线第一分支100a、公共电极线第二分支100b的图形。栅金属层例如采用Cu，Al，Mo，Ti，Cr，W等金属材料制备，也可以采用这些材料的合金制备，栅金属层可以是单层结构，也可以采用多层结构，如Mo\Al\Mo,Ti\Cu\Ti,MoTi\Cu。
步骤2、沉积栅极绝缘层15。栅极绝缘层15例如采用氮化硅和氧化硅中至少一种，栅极绝缘层15可以是单层结构，也可以是多层结构，例如氧化硅\氮化硅结构。
步骤3、沉积半导体材料，并且通过构图工艺形成有源层20的图形。例如，半导体材料例如采用非晶硅，多晶硅，微晶硅或氧化物半导体，如采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)等常规成膜方法连续沉积a-Si和n+a-Si,或溅射沉积IGZO，然后通过构图工艺形成有源层20的图形；
步骤4、溅射沉积源漏金属层,并且通过构图工艺形成数据线30、源极31、漏极33的图形，其中漏极33包括有漏极过孔33h。源漏金属层例如采用Cu，Al，Mo，Ti，Cr，W等金属材料制备，也可以采用这些材料的合金制备，源漏金属层可以是单层结构，也可以采用多层结构，如Mo\Al\Mo,Ti\Cu\Ti,MoTi\Cu。
步骤5、沉积钝化层35，并且通过构图工艺形成暴露出漏极33的钝化层过孔35h。钝化层35例如采用无机物如氮化硅，或者采用有机绝缘层，如采用有机树脂材料。钝化层35可以是单层结构，也可以是多层结构，例如可以是多层无机材料层，也可以是无机材料层和有机材料层构成的多层结构。例如，采用PECVD沉积氮化硅，然后通过构图工艺形成暴露出漏极33的钝化层过孔35h。
步骤6、溅射沉积透明导电材料层，如ITO，并且通过构图工艺形成像素电极50的图形。像素电极50通过钝化层过孔35h和漏极过孔33h与栅极绝缘层15接触。像素电极50还可以采用诸如IZO等其他透明导电材料。
实施例二
如图3、图4和图5所示，本发明的阵列基板包括形成在衬底基板1上 的栅极10a、栅线10、公共电极线100、公共电极线第一分支100a、公共电极线第二分支100b，覆盖栅极10a、栅线10、公共电极线100、公共电极线第一分支100a、公共电极线第二分支100b的栅极绝缘层15(即上述第一绝缘层)，位于栅极绝缘层15上的有源层20、数据线30、源极31、漏极33(即上述第一导电图形)，覆盖有源层20、数据线30、源极31、漏极33的钝化层35(即上述第二绝缘层)，位于钝化层35上的像素电极50(即上述第二导电图形)。阵列基板还包括贯穿钝化层的钝化层过孔35h(即上述第二过孔)、贯穿漏极的漏极过孔33h(即上述第一过孔)，钝化层过孔35h暴露出漏极33，漏极过孔33h能够暴露出栅极绝缘层15，漏极过孔33h在衬底基板1上的正投影与钝化层过孔35h在衬底基板1上的正投影至少部分重叠，这样一部分像素电极50始终与漏极33连接，另一部分像素电极50通过钝化层过孔35h和漏极过孔33h与栅极绝缘层15接触，一方面像素电极50与漏极33之间实现了电连接，另一方面由于导电材料与绝缘层之间具有良好的粘附性，因此，能够使像素电极50不容易从栅极绝缘层15上剥离，从而使得像素电极50与漏极33在连接处不易剥离。
至少一些实施例中，漏极过孔33h还可以贯穿栅极绝缘层15，暴露出衬底基板1，这样像素电极50不仅与栅极绝缘层15接触，还将与衬底基板1接触，由于衬底基板1也属于绝缘材料，因此，像素电极50也不容易从衬底基板1上剥离，从而使得像素电极50与漏极33的连接更加紧密。
例如，第一过孔(漏极过孔33h)在第一方向上的尺寸小于第二过孔(钝化层过孔35h)在第一方向上的尺寸；第一过孔(漏极过孔33h)在第二方向上的尺寸大于第二过孔(钝化层过孔35h)在第二方向上的尺寸，第一方向垂直于第二方向。
作为另一种替代，第一过孔(漏极过孔33h)在第二方向上的尺寸小于第二过孔(钝化层过孔35h)在第二方向上的尺寸；第一过孔(漏极过孔33h)在第一方向上的尺寸大于第二过孔(钝化层过孔35h)在第一方向上的尺寸，第一方向垂直于第二方向。
例如，第一方向可以与栅线的延伸方向成0度角，30度角，或60度角等。本实施例中，第一方向为栅线的延伸方向，第二方向为数据线的延伸方 向。
本实施例中，如图3所示，漏极过孔33h和钝化层过孔35h均为椭圆形，即平行于所述衬底基板1的表面的所述第一过孔(漏极过孔33h)的截面为椭圆形，平行于所述衬底基板1的表面的所述第二过孔(钝化层过孔35h)的截面为椭圆形。钝化层过孔35h的长轴和漏极过孔33h的长轴相互垂直。当然，钝化层过孔35h的长轴和漏极过孔33h的长轴之间的夹角不限于90度，可以为任意角度，例如，30度，60度，120度，150度等。
例如，如图3、图4和图5所示，漏极过孔33h的长轴与第二方向平行，钝化层过孔35h的长轴与第一方向平行，漏极过孔33h在第一方向上的尺寸小于钝化层过孔35h在第一方向上的尺寸，漏极过孔33h在第二方向上的尺寸大于钝化层过孔35h在第二方向上的尺寸。
作为另一种替代，漏极过孔33h的长轴还可以与第一方向平行，钝化层过孔35h的长轴还可以与第二方向平行，漏极过孔33h在第一方向上的尺寸大于钝化层过孔35h在第一方向上的尺寸，漏极过孔33h在第二方向上的尺寸小于钝化层过孔35h在第二方向上的尺寸。
至少一些实施例中，在栅极绝缘层15和漏极33之间还设置有有源层20时，漏极过孔33h还贯穿有源层20，暴露出栅极绝缘层15；或者漏极过孔33h还贯穿有源层20和栅极绝缘层15，暴露出衬底基板1。
例如，本发明实施例的阵列基板的制备方法包括以下步骤：
步骤1、在衬底基板1上溅射沉积栅金属层，并且通过构图工艺形成栅极10a、栅线10、公共电极线100、公共电极线第一分支100a、公共电极线第二分支100b的图形。栅金属层例如采用Cu，Al，Mo，Ti，Cr，W等金属材料制备，也可以采用这些材料的合金制备，栅金属层可以是单层结构，也可以采用多层结构，如Mo\Al\Mo,Ti\Cu\Ti,MoTi\Cu。
步骤2、沉积栅极绝缘层15。栅极绝缘层15例如采用氮化硅或氧化硅，栅极绝缘层15可以是单层结构，也可以是多层结构，例如氧化硅\氮化硅结构。
步骤3、沉积半导体材料，并且通过构图工艺形成有源层20的图形。半导体材料例如采用非晶硅，多晶硅，微晶硅或氧化物半导体，如采用诸如 PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)的成膜方法连续沉积a-Si和n+a-Si,或溅射沉积IGZO，然后通过构图工艺形成有源层20的图形。
步骤4、溅射沉积源漏金属层,并且通过构图工艺形成数据线30、源极31、漏极33的图形，其中漏极33包括有漏极过孔33h。源漏金属层例如采用Cu，Al，Mo，Ti，Cr，W等金属材料制备，也可以采用这些材料的合金制备，源漏金属层可以是单层结构，也可以采用多层结构，如Mo\Al\Mo,Ti\Cu\Ti,MoTi\Cu；
步骤5、沉积钝化层35，并且通过构图工艺形成暴露出漏极33的钝化层过孔35h。钝化层35例如采用无机材料如氮化硅，或者采用有机绝缘层，如采用有机树脂材料，钝化层35可以是单层结构，也可以是多层结构，例如可以是多层无机物，也可以是无机材料层和有机材料层构成的多层结构。如采用PECVD沉积氮化硅，然后通过构图工艺形成暴露出漏极33的钝化层过孔35h。
步骤6、溅射沉积透明导电材料层，如ITO，并且通过构图工艺形成像素电极50的图形，像素电极50通过钝化层过孔35h和漏极过孔33h与栅极绝缘层15接触。例如，像素电极50还可以采用诸如IZO的其他透明导电材料。
本发明实施例还提供了一种液晶显示面板，包括如上任一实施例所述的阵列基板。
本发明实施例还提供了一种显示装置，包括如上所述的液晶显示面板。所述显示装置可以为：液晶面板、液晶电视、液晶显示器、数码相框、手机、平板电脑、导航仪、电子纸等任何具有显示功能的产品或部件。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请基于并且要求于2016年5月5日递交的中国专利申请第201620401036.5号的优先权，在此全文引用上述中国专利申请公开的内容。

Claims (14)

  1. 一种阵列基板，包括形成在衬底基板上的第一绝缘层，位于第一绝缘层上的第一导电图形，位于所述第一导电图形上的第二绝缘层，位于所述第二绝缘层上的第二导电图形，所述第二导电图形通过贯穿所述第二绝缘层的第二过孔与所述第一导电图形连接，所述阵列基板还包括：
    暴露出所述第一绝缘层的贯穿所述第一导电图形的第一过孔，所述第一过孔在所述衬底基板上的正投影与所述第二过孔在所述衬底基板上的正投影至少部分重叠，所述第二导电图形通过所述第一过孔与所述第一绝缘层接触。
  2. 根据权利要求1所述的阵列基板，其中，所述第一过孔还贯穿所述第一绝缘层、暴露出所述衬底基板，所述第二导电图形通过所述第一过孔与所述衬底基板接触。
  3. 根据权利要求1所述的阵列基板，其中，平行于所述衬底基板的表面的所述第一过孔的截面为圆形，椭圆形，正方形，长方形，六边形或八边形；
    平行于所述衬底基板的表面的所述第二过孔的截面为圆形，椭圆形，正方形，长方形，六边形或八边形。
  4. 根据权利要求1所述的阵列基板，其中，平行于所述衬底基板的表面的所述第一过孔的截面为圆形，平行于所述衬底基板的表面的所述第二过孔的截面为圆形，所述第一过孔在所述衬底基板上的正投影完全落入所述第二过孔在所述衬底基板上的正投影中。
  5. 根据权利要求1所述的阵列基板，其中，所述第一过孔在第一方向上的尺寸小于所述第二过孔在所述第一方向上的尺寸；所述第一过孔在第二方向上的尺寸大于所述第二过孔在所述第二方向上的尺寸，所述第一方向垂直于所述第二方向。
  6. 根据权利要求1所述的阵列基板，其中，所述第一过孔在第二方向上的尺寸小于所述第二过孔在所述第二方向上的尺寸；所述第一过孔在第一方向上的尺寸大于所述第二过孔在所述第一方向上的尺寸，所述第一方向垂直于所述第二方向。
  7. 根据权利要求5所述的阵列基板，其中，平行于所述衬底基板的表面 的所述第一过孔的截面为椭圆形，平行于所述衬底基板的表面的所述第二过孔的截面为椭圆形，所述第一过孔的长轴的方向平行于所述第二方向，所述第二过孔的长轴的方向平行于所述第一方向。
  8. 根据权利要求6所述的阵列基板，其中，平行于所述衬底基板的表面的所述第一过孔的截面为椭圆形，平行于所述衬底基板的表面的所述第二过孔的截面为椭圆形，所述第一过孔的长轴的方向平行于所述第一方向，所述第二过孔的长轴的方向平行于所述第二方向。
  9. 根据权利要求5至8中任一项所述的阵列基板，其中，所述第一方向为栅线的延伸方向，所述第二方向为数据线的延伸方向。
  10. 根据权利要求1所述的阵列基板，其中，所述第一导电图形为薄膜晶体管的漏极，所述第二导电图形为像素电极。
  11. 根据权利要求10所述的阵列基板，其中，所述第一绝缘层为栅极绝缘层，所述第二绝缘层为钝化层。
  12. 根据权利要求1或2所述的阵列基板，其中，所述第一导电图形为薄膜晶体管的漏极，所述第二导电图形为像素电极；所述第一绝缘层为栅极绝缘层，所述第二绝缘层为钝化层；所述第一导电图形和所述第一绝缘层之间还设置有有源层，所述第一过孔还贯穿所述有源层。
  13. 一种液晶显示面板，包括如权利要求1至12中任一项所述的阵列基板。
  14. 一种显示装置，包括如权利要求13所述的液晶显示面板。
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CN105552024A (zh) * 2016-03-14 2016-05-04 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

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