WO2017177376A1 - 大电流读出铁电单晶薄膜存储器及其制备方法和操作方法 - Google Patents

大电流读出铁电单晶薄膜存储器及其制备方法和操作方法 Download PDF

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WO2017177376A1
WO2017177376A1 PCT/CN2016/079068 CN2016079068W WO2017177376A1 WO 2017177376 A1 WO2017177376 A1 WO 2017177376A1 CN 2016079068 W CN2016079068 W CN 2016079068W WO 2017177376 A1 WO2017177376 A1 WO 2017177376A1
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electrode
ferroelectric
single crystal
thin film
film layer
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江安全
耿文平
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Fudan University
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Fudan University
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Priority to JP2017562045A priority Critical patent/JP6674478B2/ja
Priority to CN201680061638.3A priority patent/CN108475523B/zh
Priority to US15/556,889 priority patent/US10403348B2/en
Priority to US16/901,132 priority patent/USRE49620E1/en
Priority to PCT/CN2016/079068 priority patent/WO2017177376A1/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2275—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H10D1/684—Capacitors having no potential barriers having dielectrics comprising perovskite structures the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers

Definitions

  • the invention belongs to the technical field of ferroelectric storage, and particularly relates to a non-destructive readout ferroelectric memory, in particular to a non-destructive readout ferroelectric single crystal thin film memory with large read current and a preparation method and operation of the ferroelectric memory. method.
  • Ferroelectric Random Access Memory is a method of storing data by using two different polarization orientations ("0" or “1") in a electric field using ferroelectric domains (or “domains”).
  • Non-volatile memory which may also be referred to as “ferroelectric memory.”
  • the storage medium layer of the ferroelectric memory is a ferroelectric thin film layer having a ferroelectric domain that can be reversed (or referred to as "flip").
  • the fastest phase of the domain inversion that can be measured in the laboratory can be achieved. 0.2ns, in fact it can be faster.
  • the inversion speed of the domain determines the read and write time of the memory.
  • the coercive voltage of the domain inversion determines the read/write voltage of the device, which decreases almost proportionally as the thickness of the film decreases. Therefore, the ferroelectric memory has the advantages of fast data reading speed, low driving voltage and high storage density, and has received extensive attention and rapid development in recent years.
  • ferroelectric memories can be mainly divided into two categories: destructive readout (DRO) FRAM and non-destructive readout (NDRO) ferroelectric memory.
  • DRO destructive readout
  • NDRO non-destructive readout
  • a conventional non-destructive readout (NDRO) ferroelectric memory is constructed with a transistor T and a ferroelectric capacitor C (ie, 1T1C) and is based on charge reading.
  • Non-destructive Readout Ferroelectric Memory is disclosed in a non-destructive readout by current reading (ie, a ferroelectric memory and its method of preparation and method of operation).
  • current reading ie, a ferroelectric memory and its method of preparation and method of operation.
  • the read current of such a non-destructive current read ferroelectric memory is relatively small, for example, on the order of pA
  • the stable read current disclosed in the above Chinese patent is also 100 to Within the range of 1000pA. Smaller read currents can cause problems such as poor readability of data and slow read speeds (on the order of milliseconds to seconds), which severely limits the practical application of the ferroelectric memory.
  • the present invention proposes a non-destructive large current readout ferroelectric single crystal thin film memory, a preparation method thereof and an operation method thereof.
  • a non-destructive readout ferroelectric memory comprising a ferroelectric thin film layer and a first electrode layer disposed over the ferroelectric thin film layer, wherein the first electrode layer comprises Separatingly disposed first electrode and second electrode, wherein polarization directions of the domains in the ferroelectric thin film layer are substantially not parallel to a normal direction of the ferroelectric thin film layer; at the first electrode and the second electrode The local domain inversion in the ferroelectric thin film layer is enabled when an electrical signal is applied, so that the first domain wall conductive path connecting the first electrode and the second electrode can be established;
  • the ferroelectric thin film layer is a ferroelectric single crystal thin film layer.
  • a method for fabricating the above non-destructive readout ferroelectric memory comprising the steps of:
  • a first electrode layer including the first electrode and the second electrode disposed separately is formed on the ferroelectric single crystal thin film layer.
  • the ferroelectric single crystal thin film layer includes a program bump disposed convexly with respect to the first electrode thereof And a second electrode disposed on both sides of the programming bump and separated by at least the programming bump; enabling at least a portion when a write signal in a first direction is applied between the first electrode and the second electrode
  • the domains in the programming bumps are inverted to establish the first domain wall conductive vias.
  • a write signal in a first direction is applied between the first electrode and the second electrode to enable at least a portion of the domain inversion in the programming bump, thereby establishing the First domain wall conductive channel;
  • a write signal in a second direction opposite to the first direction is applied between the first electrode and the second electrode to enable inverted domains in the programming bump Inverting back to the initial polarization direction, thereby causing the first domain wall conductive path to disappear.
  • Figure 1 is a cross-sectional view showing the structure of a non-destructive readout ferroelectric memory in accordance with a first embodiment of the present invention.
  • Figure 2 is a top plan view of the top electrode of the non-destructive readout ferroelectric memory of the embodiment of Figure 1.
  • FIG. 3 is a schematic diagram showing the operation process and operation principle of the write "1" and read “1" of the ferroelectric memory of the embodiment shown in FIG. 1.
  • FIG. 4 is a schematic diagram showing the operation process and operation principle of the write "0" and the read “0" of the ferroelectric memory of the embodiment shown in FIG. 1.
  • Figure 5 is a cross-sectional view showing the structure of a non-destructive readout ferroelectric memory in accordance with still another embodiment of the present invention.
  • Fig. 6 is a plan view showing a plan view of a read/write electrode of the nonvolatile ferroelectric memory shown in Fig. 1.
  • FIG. 7 is a schematic diagram showing the operation process and operation principle of the write "1" and read “1" of the ferroelectric memory of the embodiment shown in FIG. 1.
  • FIG. 8 is a schematic diagram showing the operation process and operation principle of the write "0" and the read “0" of the ferroelectric memory of the embodiment shown in FIG. 5.
  • Fig. 9 is a graph showing the I-V characteristic of the ferroelectric memory of the embodiment shown in Fig. 5 when performing a voltage scanning type read/write operation.
  • Fig. 10 is a schematic view showing the piezoelectric imaging of the establishment and disappearance of the domain wall conduction path of the ferroelectric memory of the embodiment shown in Fig. 5.
  • Fig. 11 is a view showing the data retention characteristic curve of the ferroelectric memory of the embodiment shown in Fig. 5.
  • Figure 12 is a graph showing the fatigue characteristic curve of the ferroelectric memory of the embodiment shown in Figure 5.
  • Figure 13 is a flow chart showing the method of preparing the ferroelectric memory of the embodiment shown in Figure 5.
  • Figure 14 is a cross-sectional view showing the structure of a non-destructive readout ferroelectric memory in accordance with still another embodiment of the present invention.
  • Fig. 15 is a view showing the operation procedure and operation principle of the write "1" and read “1" of the ferroelectric memory of the embodiment shown in Fig. 14.
  • Fig. 16 is a view showing the operation procedure and operation principle of the write "0" and the read “0" of the ferroelectric memory of the embodiment shown in Fig. 14.
  • the domain direction or the polarization direction is exemplarily given for clarity of description, but it should be understood that the domain direction or polarization direction of the ferroelectric memory is not limited to the embodiment as shown in the figure. The direction of the out.
  • the ferroelectric single crystal thin film layer may be a single crystal thin film formed by epitaxial single crystal growth, or a thin film layer formed by separating or dicing from a single crystal, which means a "grain boundary" in which no polycrystalline structure exists inside.
  • the single crystal structure or the single crystal-like structure, that is, each memory cell of the finally formed non-destructive readout ferroelectric memory is a single crystal structure, and the cell size is not limited.
  • FIG. 1 is a cross-sectional structural view showing a non-destructive readout ferroelectric memory according to a first embodiment of the present invention
  • FIG. 2 is a view showing an upper electrode of the nondestructive readout ferroelectric memory of the embodiment shown in FIG. 1. Look down on the plane structure.
  • a partial cross-sectional structure of a ferroelectric memory 10 which mainly includes a substrate 101, a ferroelectric thin film layer 105, and an electrode layer 107, wherein the electrode layer 107 is disposed on the ferroelectric thin film layer 105.
  • the upper electrode layer 107 is provided with a gap 109 which is divided into a plurality of portions, and therefore, the upper electrode layer 107 includes at least two or more electrodes which are provided separately.
  • the gap 109 divides the upper electrode layer 107 into two portions, a first electrode 1071 and a second electrode 1073, and the first electrode 1071 and the second electrode 1073 constitute a pair of read/write electrodes, in this embodiment,
  • This pair of read/write electrodes constitutes the upper electrode layer 107 of this embodiment, which can be used for both the write operation of the ferroelectric memory 10 of this embodiment and the read operation of the ferroelectric memory 10 of this embodiment.
  • the substrate 101 may be various substrate materials commonly used in ferroelectric memories, for example, it may be Si, SrTiO 3 or LiNbO 3 .
  • the material selection of the substrate 100 is primarily determined by the lower electrode layer 103 and the ferroelectric thin film layer 105.
  • the substrate 101 may be a single crystal Si substrate that is easily compatible with semiconductor CMOS processes and contributes to mass production.
  • a base material such as SrTiO 3 or LiNbO 3 is selected in accordance with the lattice constant requirements of the lower electrode 101 and the ferroelectric thin film layer 105 to obtain an epitaxial thin film layer excellent in performance.
  • a ferroelectric thin film layer 105 is formed over the substrate 101, which is a ferroelectric material having a suitable domain structure, especially a ferroelectric single crystal material, and therefore, the ferroelectric thin film layer 105 is selected as a ferroelectric single crystal thin film layer.
  • the ferroelectric single crystal layer may be formed on the substrate 101, or may be formed by cutting or peeling the surface of the ferroelectric single crystal grown and formed, and then bonding or pasting on the substrate 101 to form a ferroelectric single crystal thin film layer.
  • the specific preparation method is not limited, and the following detailed examples are explained.
  • a lithium niobate LiNbO 3 ferroelectric single crystal thin film layer is bonded on the substrate 101 of single crystal silicon.
  • a high-purity (for example, 99.99%) Li 2 CO 3 powder and Nb 2 O 5 powder are melted at about 1250 degrees Celsius, and then grown.
  • CZ method Czochralski method
  • a high-purity (for example, 99.99%) Li 2 CO 3 powder and Nb 2 O 5 powder are melted at about 1250 degrees Celsius, and then grown.
  • Forming a homogenous LiNbO 3 having Li 2 Omol. 48.5%; forming a LiNbO 3 single crystal having 49.6 mol.% Li 2 O by a double hearth CZ method and using an automatic powder feeding system thus, Li in a LiNbO 3 single crystal
  • the stoichiometric ratio of Nb is close to or equal to 1:1.
  • LiNbO 3 single crystal is doped with 2 mol.% of MgO. Subsequently, a surface layer of the LiNbO 3 single crystal was peel-bonded using ion implantation and bonding to a silicon wafer to form a LiNbO 3 ferroelectric single crystal thin film layer.
  • the ferroelectric thin film layer 105 (i.e., the ferroelectric single crystal thin film layer) is prepared, and the ferroelectric thin film layer 105 is specifically MgO doped single crystal lithium niobate LiNbO 3 .
  • ferroelectric single crystal thin film layer 105 of different material types can be obtained by different processes, materials, and the like, and the specific material type is not limited to the above embodiments, for example, it can also be other single crystal tannic acid.
  • Lithium type ferroelectrics for example, single crystal lithium niobate LiTaO 3
  • single crystal lead zirconate titanate (Pb, Zr) TiO 3 La-doped barium ferrite may be used.
  • MgO doping in the above LiNbO 3 ferroelectric single crystal thin film layer can increase the current when conducting electricity based on the domain wall conductive channel.
  • the basic principle is that Mg ion substitution can cause lattice distortion and generate donor level.
  • the LiNbO 3 ferroelectric single crystal thin film layer or other ferroelectric single crystal thin film layer may also be doped with FeO or TaO.
  • FeO FeO
  • TaO any combination of MgO, FeO and TaO may be used for the ferroelectric
  • the single crystal thin film layer 105 is doped.
  • the molar doping percentage of the doping material is 0.1% to 10%.
  • the process of peeling and cutting the LiNbO 3 single crystal in the above embodiment is to form a LiNbO 3 ferroelectric single crystal thin film layer by X-cutting. Therefore, the ferroelectric single crystal thin film layer 105 is finally prepared to be 2 mol.%. MgO doped-X-cut-LiNbO 3 ferroelectric single crystal thin film layer. In other embodiments, the LiNbO 3 ferroelectric single crystal thin film layer may also be formed based on XYZ or XZ (YZ) dicing.
  • the thickness of the ferroelectric thin film layer 105 may range from greater than or equal to 5 nanometers and less than or equal to 22 micrometers, for example, it may be 40 nm, 80 nm, or 200 nm.
  • the first electrode 1071 and the second electrode 1073 may be formed in this embodiment by patterning the etch gap 109 through a continuous metal film layer, although in other embodiments they are It is also possible to form a composition separately.
  • the first electrode 1071 and the second electrode 1073 constitute a pair of read and write electrodes, where "read” reflects that they have at least a function of a read operation, and "write” reflects that they have at least a write operation.
  • the first electrode 1071 and/or the second electrode 1073 may be a low resistivity conductive material, for example, it may be selected from the group consisting of Pt, SrRuO 3 , LaNiO 3 , Al, Cu, Ru, Ir, IrO 2 A combination of one or more.
  • the thickness of the first electrode 1071 and/or the second electrode 1073 may be 5 to 100 nm, for example, 20 nm.
  • the first electrode 1071 and/or the second electrode 1073 may be formed, but not limited to, by a thin film deposition method such as sputtering, CVD, PLD, or the like.
  • the gap 109 is used to achieve relative electrical isolation between the first electrode 1071 and the second electrode 1073 (the electrical isolation does not include the following case of the domain wall conductive path established during operation), that is, without the ferroelectric thin film layer 105 or the like.
  • the first electrode 1071 and the second electrode 1073 are electrically isolated.
  • the gap 109 can be obtained by metal flat layer electron beam processing, nanoimprinting, or other photolithography methods, but the method of forming the gap 109 is not limited to the embodiment of the present invention.
  • the pitch d of the gap 109 may range from greater than or equal to 2 nanometers and less than Or equal to 10 micrometers, more preferably greater than or equal to 5 nanometers and less than or equal to 2 micrometers, for example, may be 10 nanometers, 100 nanometers, 1 micrometer, etc., the smaller the spacing d, the more advantageous to increase the storage density of the ferroelectric memory, and The more favorable it is to reduce the write voltage and the read voltage, increase the read current, and the read power consumption and write power consumption are smaller, therefore, the ferroelectric memory 10 of the embodiment of the present invention can be scaled down (Scaling-down), the gap 109 Optionally, it can be set to various nano-sized gaps.
  • the shape of the gap 109 is not limited to the shape shown in FIG. 2, and in other embodiments, the gap 109 may even be zigzag or the like.
  • the width w dimension (ie, the width dimension of the gap) of the first electrode 1071 and the second electrode 1073 in the vertical gap direction may be greater than or equal to 2 nanometers and less than or equal to 10 micrometers, for example, 100 nanometers.
  • the ferroelectric thin film layer 105 is required to satisfy the condition that its ferroelectric domain has a component in-plane, that is, has an in-plane component (spontaneous polarization of ferroelectric domains).
  • the ferroelectric thin film layer 105 can form the domains 1051 or 1053 in two directions as shown in FIG. 1, and the polarization direction of the domain 1051 is completely opposite to the polarization direction of the domain 1053. After being set to be larger than the coercive voltage, the domains are oriented in the direction of the electric field.
  • the domains 1051 or 1053 are inverted.
  • the polarization direction of the domains of the ferroelectric thin film layer 105 is substantially not perpendicular to the normal to the ferroelectric thin film layer 105 (as indicated by the dashed line perpendicular to the ferroelectric thin film layer 105), or substantially not vertical.
  • FIG. 3 is a schematic diagram showing the operation process and operation principle of the write "1" and read “1" of the ferroelectric memory of the embodiment shown in FIG. 1.
  • the first electrode 1071 and the second electrode 1073 apply a write signal Vwrite1 such that the first electrode 1071 is biased positive.
  • the voltage and the second electrode 1073 are biased by a negative voltage (defined as "+" write voltage at this time), and based on the write signal Vwrite1 in the direction, an electric field E1 substantially in the direction shown in Fig. 3(a) is formed.
  • the electric field E1 can locally affect the electrical domain of the portion of the ferroelectric thin film layer 1053 corresponding to the gap 109.
  • the corresponding partial ferroelectric thin film layer 105 that is, the portion exposed to the surface portion of the gap 109, in which the domains are reversed, that is, the domain 1053 corresponding to the gap 109 is partially inverted as shown in FIG. 3 (a).
  • the illustrated domain 1053b, the other domains of the ferroelectric thin film layer 105 are substantially unaffected by the electric field E1 (or the electric field E1 is insufficiently affected to cause the domain to reverse), and the domains are not inverted.
  • the polarization of the domain 1053b is substantially opposite to the polarization of the domain 1053a.
  • the domain 1053b is inverted by the electric field component in the direction opposite to the polarization direction of the domain 1053a by the electric field E1. Therefore, when the coercive voltage of the ferroelectric thin film layer is known, it can be calculated.
  • the minimum voltage that forms the domain 1053b the minimum write voltage.
  • the boundary between the ferroelectric thin film layer portion having the electric domain 1053a and the ferroelectric thin film layer portion having the electric domain 1053b that is, the boundary wall or interface between the electric domain 1053a and the electric domain 1053b, generates a charged domain.
  • the wall or domain boundary and thus, based on the domain wall conduction mechanism, generates a conductive path between the second electrode 1073 and the first electrode 1071, that is, the domain wall conductive path 1054.
  • the establishment of the domain wall conductive path 1054 indicates that the write "1" operation is successful, that is, the data "1" is stored.
  • the first positive bias voltage electrode 1071, second electrode 1073 a negative bias voltage (this case is defined as "+ The "read voltage”, the direction of the read signal Vread is also not limiting, and it may also be biased to a "-" read voltage on the first electrode 1071 and the second electrode 1073.
  • Voltage V write1 write signal is compared to the read signal voltage V read small, which can prevent erroneous write operation coercive voltage during a read operation, for example, a read voltage V read signal is less than the electrical domain inverted 1051 or 1053 Therefore, the electric field in FIG.
  • the first electrode 1071 and the second electrode 1073 respectively generate a read current I read1 , and the read current I read1 is relatively large, indicating an on state (On state). Thus, the logical information "1" is read.
  • FIG. 4 is a schematic diagram showing the operation process and operation principle of the write "0" and the read “0" of the ferroelectric memory of the embodiment shown in FIG. 1.
  • the first electrode 1071 and the second electrode 1073 apply a write signal Vwrite0 to bias the second electrode 1073 to a positive voltage, and the first electrode 1071 is biased to a negative voltage (defined as "-" at this time.
  • the write voltage based on the write signal Vwrite0 in this direction, forms an electric field E3 substantially in the direction shown in Fig. 4(a), which is opposite to the electric field direction E1 of Fig. 3(a).
  • the electric field E1 works in the same manner as the ferroelectric single crystal thin film layer 105 during the operation of "1" in the above FIG. 3(a), and the electric field E3 can reverse the domain 1053b (as shown in FIG.
  • the original polarization direction is such that the domains 1053 are uniformly formed in the ferroelectric single crystal thin film layer 105.
  • the domain wall or the domain boundary disappears, and the domain wall conductive path 1054 originally generated between the second electrode 1073 and the first electrode 1071 also disappears.
  • the operation of writing "0" is successful, that is, the data is stored as 0. ".
  • the first electrode 1071 and the second electrode 1073 apply a read signal Vread which is the same as the read signal in FIG. 3(b), that is, the first electrode 1071 is biased with a positive voltage, The two electrodes 1073 are biased with a negative voltage (defined as a "+" read voltage at this time). Since the domain wall conductive path 1054 disappears, a corresponding read current between the first electrode 1071 and the second electrode 1073 is substantially zero or very small. Read0 indicates the off state (Off state), thereby reading out the logical information "0".
  • the domain of the ferroelectric single crystal thin film layer 105 during the operation of reading "1” or reading “0” is also substantially unchanged, and therefore, after the read signal Vread is removed, the state of the domain wall conductive path 1054 ("present” or “” Does not change, so that there is no influence on the stored data "1” or “0", achieving non-destructive readout. Moreover, the above reading "1” or reading “0” operation distinguishes the data state by the magnitude of the read current, which is completely different from the charge reading mode in the conventional ferroelectric memory.
  • the read current I read1 of the read "1" operation can reach the order of magnitude of 100 nA to 1000 nA, and the current I read1 of the "1" operation is compared with the current I of the "1" operation. There can be an order of magnitude difference of 4-7 or more between read0 . Therefore, the readout window is large and the data is legible.
  • the inventors of the present application found that this is mainly due to the use of a single crystal ferroelectric thin film layer 105 as a memory layer to form a memory cell, which effectively reduces lattice defects such as grain boundaries, domain boundaries, defect rich regions, and second equals. .
  • the inventors of the present application found that the data retention (Retention) characteristics and the data persistence (Endurance) characteristics of the ferroelectric memory 10 of the embodiment shown in Fig. 1 above are compared with the background.
  • the non-destructive ferroelectric memory cited in the technology is greatly improved, mainly because in the single crystal structure, the positive and negative polarization directions of the single crystal domain are stable and the defects are small. .
  • FIG. 5 is a cross-sectional structural view showing a non-destructive readout ferroelectric memory according to still another embodiment of the present invention
  • FIG. 6 is a plan view showing a read/write electrode of the nonvolatile ferroelectric memory shown in FIG. structure.
  • a partial cross-sectional structure of the ferroelectric memory 30 is shown, which mainly includes a substrate 301, a ferroelectric thin film layer 303, a programming bump 305 disposed in the ferroelectric thin film layer 303, and a read/write electrode layer. 307.
  • the "read" of the read and write electrode layers 307 reflects that they have at least the function of a read operation
  • the "write" of the read and write electrode layers 307 reflects that they have at least a write operation.
  • the substrate 301 can be various substrate materials commonly used in ferroelectric memories, for example, it can be Si, SrTiO 3 or LiNbO 3 .
  • the material selection of the substrate 301 is primarily determined by the substrate 301 and the ferroelectric thin film layer 303.
  • the substrate 301 can be a Si substrate that is easily compatible with semiconductor CMOS processes and contributes to mass production.
  • a base material such as SrTiO 3 or LiNbO 3 is selected in accordance with the lattice constant requirement of the ferroelectric thin film layer 303 to obtain an epitaxial thin film layer excellent in performance.
  • the substrate 301 and the ferroelectric thin film layer 303 may be the same material, that is, a ferroelectric material, including a ferroelectric bulk ceramic, a single crystal, or the like.
  • the ferroelectric thin film layer 303 shown in FIG. 5 is also a ferroelectric single crystal thin film layer, and the material type, preparation process, etc.
  • the material types, preparation processes, and the like of the ferroelectric thin film layer 103 of the embodiment of the present invention are the same, and are not described herein again.
  • the programming bumps 305 are disposed on the ferroelectric single crystal thin film layer 303, which are integrally formed, that is, the programming bumps 305 are integrated with the ferroelectric single crystal thin film layer 303 and have the same material type. And they belong to a single crystal.
  • the patterning bump 305 which is convex relative to the ferroelectric thin single crystal film layer 303 can be formed by pattern etching the ferroelectric thin single crystal film layer 303, for example, by semiconductor process lithography, using electron beam direct writing Or a technique such as nanoimprinting or photolithography realizes pattern transfer of the programming bumps 305, and then forms a programming bump 305 on the surface of the ferroelectric thin single crystal film layer 303 by etching techniques, including dry etching and wet etching.
  • the programming bump 305 may be, for example, a rectangular block structure or a boss of a cylindrical structure, and the specific shape thereof is not limitative.
  • a separate first electrode 3071 and a second electrode 3073 are disposed in the read/write electrode layer 307, and the first electrode 3071 and the second electrode 3073 are disposed in the ferroelectric
  • the thin single crystal film layer 303 is disposed on both sides of the programming bump 305, that is, the first electrode 3071 and the second electrode 3073 are disposed on both sides of the programming bump 305 of the ferroelectric thin single crystal film layer 303 and are at least programmed.
  • the bumps 305 are spaced apart.
  • the first electrode 3071 and the second electrode 3073 are in contact with the side edges of the programming bump 305, respectively.
  • the width d of the programming bump 305 corresponds to the gap spacing between the first electrode 3071 and the second electrode 3073, and d may be greater than or equal to 2 nanometers and less than or equal to 10 micrometers, for example, may be 10 nanometers. , 100 nm, 1 micron, etc.
  • the smaller the spacing d the more advantageous it is to increase the storage density of the ferroelectric memory, and the more favorable it is to reduce the write voltage, the read voltage, and the lower the read/write power consumption, therefore, the programming bumps 305 can be various micron nanometer sizes. structure.
  • the height of the programming bump 305 relative to the ferroelectric thin single crystal film layer 303, that is, the thickness of the programming bump 305 may be greater than or equal to 2 nanometers and less than or equal to 1 micrometer, such as 50 nm.
  • the read/write electrode layer 307 may be a sidewall structure disposed on both sides of the programming bump 305, and the first electrode 3071 and the second electrode 3073 are disposed as separate sidewalls on the programming bump 305. The two opposite side edges.
  • the first electrode 3071 and the second electrode 3073 are made of a low resistivity conductive material, for example, it may be selected from Pt, SrRuO 3 , LaNiO 3 , Al, Cu, Ru, Ir, IrO 2 a combination of one or more of them.
  • the thickness of the first electrode 3071 and/or the second electrode 3073 may be 2 to 100 nm, for example, 30 nm.
  • the thickness of the read and write electrode layer 307 can be greater than or equal to the thickness of the programming bump 305.
  • the first electrode 3071 and/or the second electrode 3073 may be formed, but not limited to, by a thin film deposition method such as sputtering, evaporation, CVD, PLD, or the like.
  • the ferroelectric thin film layer 303 and the programming bump 305 are required to satisfy the condition that the ferroelectric domain has a component in the plane, that is, have an in-plane component (spontaneous pole of the ferroelectric domain).
  • the projection of the direction on the film surface), the ferroelectric thin film layer 303 can form the domains 3031 or 3033 in two directions as shown in FIG. 1, and the programming bumps 305 can form electricity in two directions as shown in FIG.
  • Domain 3051 or 3053 the polarization directions of the domains 3031 and 3051 are completely opposite to the polarization directions of the domains 3033 and 3053, respectively, and after the bias is greater than the coercive voltage, the domains are oriented in the direction of the electric field, and therefore, biased When the direction of the electric field is opposite to the direction of the original domain and the voltage is greater than the coercive voltage, the domains 3031 and 3051 or 3033 and 3053 are inverted.
  • the polarization directions of the domains of the ferroelectric thin film layer 303 and the programming bumps 305 are substantially not parallel to the normal to the read/write electrode layer 307 (as indicated by the dashed line perpendicular to the read/write electrode layer 307).
  • the ferroelectric thin film layer 303 can be realized by controlling the crystal orientation of the ferroelectric thin film layer 303.
  • a 100 nm thick BiFeO 3 ferroelectric thin film layer 303 can be epitaxially grown on the (001) SrTiO 3 substrate 301, wherein The polarization direction of the domains of the BiFeO 3 ferroelectric thin film layer 303 is along the ⁇ 111> direction.
  • the domains of the ferroelectric thin film layer 303 and the programming bump 305 are separately shown in FIG. 5, but in practice, it is possible that they are not separated, and instead, they may be The continuous, ferroelectric thin film layer 303 and the domains in the programming bumps 305 constitute a single domain.
  • the polarization directions of the ferroelectric thin film layer 303 and the programming bump 305 are identical, for example, the domain 3031 and the domain 3051 have a uniform polarization direction (or the domains 3033 and 3053 have a uniform polarization direction). They can be expressed continuously.
  • FIG. 7 is a schematic diagram showing the operation process and operation principle of the write "1" and read “1" of the ferroelectric memory of the embodiment shown in FIG. 1.
  • the write signal Vwrite1 is biased between the first electrode 3071 and the second electrode 3073 of the read/write electrode layer 307, that is, the read and write of the second electrode 3073 and the first electrode 3071.
  • the electrode pair is biased with the write signal V write1 , the direction of the write signal V write1 is the second electrode 3073 biased negative, and the first electrode 3071 is biased forward, so that they form an electric field substantially in the direction shown in FIG. 3( a ) E4.
  • the electric field intensity in the programming bump 305 is relatively greater in the ferroelectric single crystal thin film layer 303 according to the distribution characteristic of the electric field E4.
  • the influence on the domain in the programming bump 305 is relatively large, and the domain 3051 of the programming bump 305 is more easily reversed with respect to the domain 3031 in the ferroelectric single crystal thin film layer 303, and therefore, at the electric field E4 Under the action, the domains 3051 are reversed to form the domains 3053, that is, the electric field component of the electric field E4 in the opposite direction to the polarization direction of the domain 3051 of the programming bump 305 is larger than the coercion that causes the domain to be inverted.
  • the domain having the in-plane ferroelectric polarization component in the programming bump 305 is inverted, that is, the domain 3051 is inverted to form the domain 3053.
  • the domain 3051 of the programming bump 305 can be inverted by setting the size of the write signal Vwrite1 and the domain 3031 of the ferroelectric thin film layer 303 is substantially not inverted (or only a small portion of the programming bump 305 is inverted). That is, at this time, the domain 3031 of the ferroelectric thin film layer 303 is substantially unaffected by the electric field E4 (or the electric field E4 is insufficiently affected to cause the domain 3031 to reverse).
  • the polarization direction of the domain 3053 in the programming bump 305 will be substantially opposite to the polarization direction of the domain 3031 in the ferroelectric thin film layer 303, the domain 3031 and the domain 3053 (program bump 305) Charged domain walls or domain boundaries are formed between the surrounding non-inverting domains to form domain wall conductive vias 3054.
  • the first electrode 3071 and the second electrode 3073 may be electrically connected through the domain wall conductive channel 3054, and the establishment of the domain wall conductive channel 3054 indicates that the write "1" operation is successful, that is, the data "1" is stored.
  • the write operation principle of the ferroelectric memory 10 as shown in FIG. 4 may be similar, and more and more close to the programming convexity in the ferroelectric single crystal thin film layer 303.
  • the domain 3031 in the portion of block 305 is inverted by the influence of the electric field E4. Therefore, the domain wall conductive path 3054 is continuously convex downward until it approaches the substrate 301. Thus, it is possible to cause the domain wall conductive path 3054 to break near the substrate 301, so that the conductive path of the second electrode 3073 and the first electrode 3071 is turned off. .
  • the voltage magnitude of the write signal Vwrite1 can be set to invert only the domains 3051 or 3053 in the programming bump 305 without inverting the domains of the domains 3031 or 3033 of the ferroelectric thin film layer 303;
  • the thickness of the ferroelectric single crystal thin film layer 303 may be set to be larger than the height of the programming bump 305, so that the domain wall conductive via 3054 formed after the "1" operation cannot be substantially longitudinally penetrated through the upper surface and the lower surface of the ferroelectric thin film layer 303. surface.
  • the width (d) of the programming bump and the coercive voltage V are programmed.
  • the minimum write voltage Vwrite1 that reverses the domain 3051 to form the domain 3053 can be calculated.
  • the read operation principle is completely different from the conventional read operation principle of the ferroelectric memory, in which the substrate 301 does not need a bias signal during the read operation, which can be left floating and read.
  • the signal Vread is biased between the pair of read/write electrodes, and the following description will be made by taking the first electrode 3071 and the second electrode 3073 as an example.
  • an electric field E5 (E5 is smaller than the coercive field E c ) in the direction shown in the figure is formed between the second electrode 3073 and the first electrode 3071, and the electric field component which inverts the domain 3053 does not exist due to the electric field E5.
  • the domain 3053 is completely unchanged, so that the formed domain wall conductive channel 3054 is not turned off.
  • the second electrode 3073 and the first electrode 3071 generate a read current I read1 , and the read current I read1 is relatively large. Indicated as the On state (ie, on state), indicating that the logic information "1" is read.
  • the read voltage of the read signal V read may be smaller than the write voltage of the write signal V write1 , thus facilitating the avoidance of an “over” write operation during a read operation.
  • the domain of the programming bump 305 does not change after the read signal V read is removed.
  • the domain wall conductive path 3054 will be stably present, and the data "1" can always be maintained, and therefore, the read operation is non-destructive readout.
  • FIG. 8 is a schematic diagram showing the operation process and operation principle of the write “0" and the read “0” of the ferroelectric memory of the embodiment shown in FIG. 5.
  • the second electrode 3073 and the electrode 3071 composed of a first electrode of the read-write offset V write0 write signal, a write signal and a write signal V write0 V write1
  • the direction is reversed, in which the second electrode 3073 is biased in the forward direction and the first electrode 3071 is biased in the negative direction so that they form an electric field E6 substantially in the direction shown in Fig. 8(a).
  • V write0 program write signal for the write operation principle and the bump V write1 305 of the write signal to write programming principle of projection 305 is substantially the same.
  • the electric field E6 can affect the domain corresponding to the programming bump 305, that is, it can affect the domain 3053 shown in FIG. 7(a), and the electric field E6 is in the polarization direction of the domain 3053 with the programming bump 305.
  • the electric field component in the opposite direction is larger than the coercive voltage for inverting the domain, the domain 3053 is inverted, returns to the original or initial polarization direction, and the domain 3051 is uniformly formed.
  • the domain 3051 of the programming bump 305 and the domain 3031 of the ferroelectric single crystal thin film layer 303 have the same polarization direction, and there is no domain wall or domain boundary between the two, which is originally at the second electrode 3073 and the first
  • the domain wall conductive path 3054 generated between the electrodes 3071 also disappears. At this time, it indicates that the write "0" operation is successful, that is, the data "0" is stored.
  • the specific signal form of the write signals V write0 and V write1 is not limited, for example, it may be a voltage pulse signal of a certain frequency or the like.
  • Electric field E5 in FIG. 8 (b), the read "0" operation, a first electrode 3071, the read signal V read bias between the second electrode 3073 is formed as shown in FIG direction of the electric field less than the program E5
  • the polarization direction of the domain 3033 of the crystalline thin film layer 303 stores logic information "0"
  • the domain 3051 of the programming bump 305 and the polarization direction of the domain 3033 of the ferroelectric single crystal thin film layer 303 store logic information "1"
  • the direction of the voltage signal in the corresponding write and read operations can also be adaptively varied to achieve a read and write operation similar to that shown in Figures 7 and 8.
  • the ferroelectric single crystal thin film layer 303 (including the programming bumps 305) of the ferroelectric memory 50 is specifically a 2 mol.% MgO doped-X-cut-LiNbO 3 ferroelectric single crystal thin film layer.
  • Fig. 9 is a graph showing the I-V characteristic of the ferroelectric memory of the embodiment shown in Fig. 5 when performing a voltage scanning read/write operation.
  • the solid line indicates the I-V characteristic curve of the sample in which the width d of the programming bump 305 is 150 nm
  • the broken line indicates the I-V characteristic curve of the sample in which the width d of the programming bump 305 is 50 nm.
  • a voltage can be applied between the first electrode 3071 and the second electrode 3073 for scanning, for example, first from 0V to +12V, back to 0V, and then from 0V to -12V.
  • Fig. 10 is a schematic view showing the piezoelectric imaging of the establishment and disappearance of the domain wall conduction path of the ferroelectric memory of the embodiment shown in Fig. 5.
  • the width of the programming bump 305 is 150 nm
  • the "left electrode” and the “right electrode” constitute a pair of read/write electrodes, and when bias voltages in different directions are biased (for example, +7V, -7V), the voltage is pressed at ⁇ 7V.
  • Electrical imaging from which the switching state of the domain wall can be clearly seen, that is, when the data "1" is written, the domain wall conductive channel is obviously established, and the domain wall conductive channel is obviously disappeared when the data "0" is written.
  • Fig. 11 is a view showing the data retention characteristic curve of the ferroelectric memory of the embodiment shown in Fig. 5.
  • the width of the programming bump 305 is 150 nm
  • the first electrode 3071 and the second electrode 3073 are metal Pt electrodes having a width of 100 nm.
  • the on-state read current can reach 10 -7 A to 10 -6 A, and the read current is large; on the other hand, the ratio of the On state to the Off state (ie, the switching ratio) It can be larger than 10 6 and the data window is large; on the other hand, the read current is stable with time, and the data can be well maintained after 10 6 seconds, that is, the data retention is very good.
  • Fig. 12 is a view showing the fatigue characteristic curve of the ferroelectric memory of the embodiment shown in Fig. 5.
  • the width of the programming bump 305 is 150 nm
  • the first electrode 3071 and the second electrode 3073 are metal Pt electrodes having a width of 100 nm
  • a write period of +8 V/-10 V including writing "0" and Write "1"
  • write the corresponding switch current at 4V every time after writing "0" and writing "1”.
  • Figure 12 shows the write cycle for each write cycle. The switching current varies with the number of write cycles. As can be seen at least from FIG.
  • the on-state read current can reach 10 -7 A, the read current is large, and as the write operation continues, the on-state read current does not decrease; on the other hand, On The ratio of the state current to the off state current (ie, the switching ratio) can be greater than 10 6 and the data window is large; on the other hand, the read and write cycle is greater than 10 10 .
  • the ferroelectric memory 30 of the embodiment shown in FIG. 5 at least since the ferroelectric thin film layer 303 and the programming bump 305 both use a ferroelectric single crystal material, the programming operation occurs in the same single crystal or class. In the single crystal structure, therefore, the read current is large (up to the order of ⁇ A), the data is readable, and the reliability of data retention characteristics, fatigue characteristics, and the like are excellent, and the switching ratio is large. Since the ferroelectric memory 30 also employs the programming bumps 305, the electric fields of the first electrode 3071 and the second electrode 3072 applied to both sides thereof can better and more effectively act on the domains in the programming bumps 305.
  • FIG. 13 is a flow chart showing the method of preparing the ferroelectric memory of the embodiment shown in Figure 5. intention.
  • a substrate 310 as shown in FIG. 1 is provided.
  • the material selection of the substrate 310 is mainly determined by the ferroelectric thin film layer 303, and may be the same as the ferroelectric material, that is, iron. Electrical ceramic block or single crystal.
  • the substrate 301 can be a Si substrate that is easily compatible with semiconductor CMOS processes.
  • a ferroelectric thin film layer 303 is formed.
  • the ferroelectric thin film layer 303 may be, but not limited to, selected from the group consisting of single crystal lithium niobate type ferroelectrics (for example, single crystal lithium niobate LiTaO 3 ), single crystal lead zirconate titanate (Pb, Zr)TiO 3 , La-doped barium ferrite salt (Bi, La)FeO 3 , or barium ferrite BiFeO 3 , or single crystal Bi 4 Ti 3 O 12 , (La,Bi) 4 Ti 3 O 12 , or SrBi 2 Ta 2 O 9 .
  • the ferroelectric thin film layer 303 can be formed by a thin film deposition method such as ion bonding technique, sputtering, CVD, PLD, or the like.
  • a lithium niobate LiNbO 3 ferroelectric single crystal thin film layer is bonded to a single crystal silicon substrate 301.
  • a high-purity (for example, 99.99%) Li 2 CO 3 powder and Nb 2 O 5 powder are melted at about 1250 degrees Celsius, and then grown.
  • CZ method Czochralski method
  • a high-purity (for example, 99.99%) Li 2 CO 3 powder and Nb 2 O 5 powder are melted at about 1250 degrees Celsius, and then grown.
  • Forming a homogenous LiNbO 3 having Li 2 Omol. 48.5%; forming a LiNbO 3 single crystal having 49.6 mol.% Li 2 O by a double hearth CZ method and using an automatic powder feeding system thus, Li in a LiNbO 3 single crystal
  • the stoichiometric ratio of Nb is close to or equal to 1:1.
  • the LiNbO 3 single crystal is doped with 2 mol.% of MgO. Subsequently, a surface layer of the LiNbO 3 single crystal was peeled off by ion implantation and a silicon wafer bonding technique to form a LiNbO 3 ferroelectric single crystal thin film layer.
  • a layer of SiO 2 may be deposited on the substrate 301 of the single crystal silicon to improve its adhesion to the LiNbO 3 single crystal; a layer of LiNbO 3 iron and electricity adhered to the substrate 301
  • the crystalline film layer is separated from the LiNbO 3 single crystal.
  • a ferroelectric thin film layer 303 (i.e., a ferroelectric single crystal thin film layer) is prepared, and the ferroelectric thin film layer 303 is specifically MgO doped single crystal lithium niobate LiNbO 3 .
  • the use of MgO doping in the above LiNbO 3 ferroelectric single crystal thin film layer can improve the current when conducting electricity based on the domain wall conductive path.
  • the LiNbO 3 ferroelectric single crystal thin film layer or other ferroelectric single crystal thin film layer may be doped with FeO or Ta 2 O 5 .
  • MgO, FeO and Ta 2 O 5 may also be used.
  • the ferroelectric single crystal thin film layer 105 is doped in any combination. The molar doping percentage of the doping material is 0.1% to 10%.
  • the process of peeling and cutting the LiNbO 3 single crystal in the above embodiment is to form a LiNbO 3 ferroelectric single crystal thin film layer by X-cutting. Therefore, the ferroelectric single crystal thin film layer 303 is finally prepared to be 2 mol.%. MgO doped-X-cut-LiNbO 3 ferroelectric single crystal thin film layer. In other embodiments, the LiNbO 3 ferroelectric single crystal thin film layer may also be formed by XYZ or XZ (YZ) dicing.
  • the programming bumps 305 are etched in the plane of the ferroelectric thin film layer 303.
  • the programming bump 305 can transfer the pattern to the ferroelectric thin film layer 303 by semiconductor lithography, electron beam direct writing or nanoimprinting, and then dry etching (reactive ion etching (RIE)
  • the programming bumps 303 are formed by inductively coupled plasma etching (ICP) or wet etching.
  • ICP inductively coupled plasma etching
  • the height of the programming bump 305 is preferably smaller than the thickness of the etched ferroelectric thin film layer 303.
  • the height of the programming bump 305 may be 2-500 nm.
  • an in-plane read/write electrode pair is formed on the ferroelectric thin film layer 303 and the programming bump 305.
  • the pair of read/write electrodes is mainly composed of the first electrode 3071 and the second electrode 3073, and the first electrode 3071 and the second electrode 3073 are separated by the programming bump 305;
  • the pair of read/write electrodes may be selected from Pt a combination of one or more of SrRuO 3 , LaNiO 3 , Al, Cu, Ru, Ir, IrO 2 ; the thickness of the first electrode 3071 and the second electrode 3073 is greater than or equal to the height of the programming bump 305, such as It can be 2-100 nm (for example, 30 nm).
  • the read/write electrode layer 307 where the first electrode 3071 and the second electrode 3073 are located may be, but not limited to, formed by a thin film deposition method such as sputtering, CVD or PLD, and the first electrode 3071 and the second electrode 3073 may further, but not limited to, pass Obtained by electron beam processing, nanoimprinting or other lithography methods.
  • ferroelectric memory 30 of the embodiment shown in Fig. 5 is basically formed.
  • FIG. 14 is a cross-sectional view showing the structure of a non-destructive readout ferroelectric memory in accordance with still another embodiment of the present invention.
  • the ferroelectric memory 40 further includes a third electrode 4075 disposed on the programming bump 305 as compared to the ferroelectric memory 30 of the embodiment shown in FIG. 5, such that the first electrode 3071, the second The electrode 3073 and the third electrode 4075 together constitute the read/write electrode layer 407 of the ferroelectric memory 40.
  • the third electrode 4075 has a function of a read electrode for applying an electrical signal during a read operation.
  • the third electrode 4075 is made of the same metal material and synchronized with the first electrode 3071 and the second electrode 3073.
  • the ground pattern is etched to form.
  • the other components in the ferroelectric memory 40 are substantially the same as the other components of the ferroelectric memory 30 of the embodiment shown in FIG. 5 and will not be further described herein.
  • Fig. 15 is a view showing the operation process and operation principle of the write "1" and read “1" of the ferroelectric memory of the embodiment shown in Fig. 14.
  • the writing operation of "1" is substantially the same as the writing operation shown in FIG. 7(a).
  • the third electrode 4075 can be applied.
  • a suitable bias voltage such as ground, is effective to reduce the write voltage and also to increase the read domain wall current; of course, the third electrode 4075 can also be left floating.
  • the write signal V write1 is biased between the first electrode 3071 and the second electrode 3073. Therefore, the write "1" operation principle of the ferroelectric memory 40 is substantially the same as the write “1” operation principle of the ferroelectric memory 30, and is no longer Narration. After the "1" operation is written, as shown in FIG.
  • the domains 3051 and 3053 in the programming bump 305 are unified into the domain 3053 under the influence of the electric field E4, that is, all the domains 3051 are inverted to form the domain.
  • the polarization directions of the domains in the programming bumps 305 are the same, and are completely opposite to the polarization directions of the unified domains 3031 in the ferroelectric thin film layer 303. Therefore, the domain wall conductive vias 3054 are established, which can be electrically The first electrode 3071 and the second electrode 3073 are connected.
  • FIG. 15 (b) the read "1" operation, any of a read signal V read offset 4075 between the first electrode and the third electrode and the second electrode 3073 in 3071.
  • the offset read signal V read between the first electrode 3071 and the third electrode 4075 will be described as an example.
  • the domain in the programming bump 305 does not substantially change during the above read operation, the domain in the programming bump 305 does not change after the read signal V read is removed, and the stored data is not changed. "1" does not change, so there is no destructive reading.
  • 15 (b) is a schematic broken line read signal V read between the second electrode 3073 and third electrode 4075 in FIG bias when, in the same manner can be read logic information "1."
  • the read voltage different from the read signal V read shown in FIG. 7(b) must be smaller than the write voltage of the write signal V write1 , and the read voltage shown in FIG. 15(b) is completely independent of the write voltage limit. Moreover, the domain wall conductive path 3054 is not substantially affected, and therefore, a miswrite operation is not generated during the read operation.
  • Fig. 16 is a view showing the operation process and operation principle of the write "0" and the read “0" of the ferroelectric memory of the embodiment shown in Fig. 14.
  • the write "0" operation process is substantially the same as the write operation process shown in FIG. 8(a).
  • the third electrode 4075 can be left floating.
  • a suitable bias voltage such as ground, may be applied to effectively reduce the write voltage; the write signal V write0 is biased between the first electrode 3071 and the second electrode 3073, and thus the write operation of the ferroelectric memory 40 is "0".
  • the principle is basically the same as the write "0" operation principle of the ferroelectric memory 30, and details are not described herein again.
  • the domains 3051 and 3053 in the programming bump 305 are unified into the domain 3051 under the influence of the electric field E4, that is, all the domains 3053 are inverted to form a domain.
  • the polarization directions of the domains in the programming bumps 305 are the same, and are substantially the same as the polarization directions of the unified domains 3031 in the ferroelectric thin film layer 303, and thus, the previously established domain wall conductive vias 3054 disappear.
  • FIG. 16 (b) the read "0" operation, any of a read signal V read offset 4075 between the first electrode and the third electrode and the second electrode 3073 in 3071.
  • the offset read signal V read between the first electrode 3071 and the third electrode 4075 will be described as an example.
  • FIG. 16 (b) the read "0" operation, the read signal V read offset 4075 between the first electrode and the third electrode 3071, a third electrode 4075 to a negative bias, a first bias electrode 3071 forward, thereby forming the direction shown in FIG between the first electrode and the third electrode 4075 field 3071 E7 (E7 greater than the coercive field E c), due to the presence of the electric field E7 domain inversion electric field component 3053, the electric field When the electric field component of E7 in a direction opposite to the polarization direction of the domain 3051 is greater than the coercive voltage for inverting the domain, the corresponding partial programming convex below the gap between the first electrode 3071 and the third electrode 4075
  • block 305 ie, programming bump 305 portion
  • the domain 3051 is partially inverted to form the domain 3053b, and the unreversed correspondence in the domain 3051 is 3051a, such that the domain 3053b and the domain 3051b are polarized in opposite directions.
  • a domain wall or a domain boundary is formed between the two, so that a domain wall conductive path formed when a write "1" operation is generated in the programming bump 305, that is, a domain is established between the first electrode 3071 and the third electrode 4075.
  • Wall conductive channel 3057 At this time, the first electrode 3071 and the third electrode 4075 can be electrically connected through the domain wall conductive channel 3057, thereby generating a large read current I read , which corresponds to between the programming bump 305 and the ferroelectric thin film layer 303.
  • the domain wall conductive channel 3054 is in the Off state (ie, the OFF state), and the logic information "0" is read.
  • the bias read signal V read is removed between the electrode 3071 and the third electrode 4075, and the electric field E7 disappears.
  • the domain 3053b is inverted by the domain 3051a and reversed to the original polarization direction, that is, the domain 3053b disappears instantaneously, and the domain 3051 is substantially restored to the state before the read operation, and the domain wall conductive channel 3057 is also substantially disappeared, but not It will affect the domain wall conductive channel 3054. Therefore, the logical information "0" stored by the ferroelectric memory 40 before the read operation does not change after the read operation, realizing non-destructive reading.
  • the domain wall conductive channel 3057 always exists after the read signal is removed. Since the read signal V read direction is relatively fixed, 3053b] domain will not affect the logical information stored in the ferroelectric memory 40, and the presence of domain wall conductive pathway 3057 will not affect the logic information read out thereafter. Moreover, it can be understood that when the write operation is performed after the read operation, the domain 3053b is surely repolarized, and the domain wall conductive path 3057 is also erased.
  • the read operation performance of the ferroelectric memory 40 can be optimized by designing the height of the bump 305, the area parameter, the read voltage, and/or the pitch d of the gap between the first electrode 3071 and the third electrode 3075.
  • the pitch d of the gap between the first electrode 3071 and the third electrode 3075 is smaller than the height of the programming bump 305.
  • the direction of the read signal Vread used in the above Figs. 15 and 16 can be changed, and the data states "1" and "0" stored therein can also be read out differently.
  • the specific signal forms of the write signals V write1 , V write0 , and V read are not limited, and for example, they may be voltage pulse signals of a certain frequency or the like.

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Abstract

一种非破坏大电流读出铁电单晶薄膜存储器及其制备方法和操作方法，属于铁电存储技术领域。该非破坏大电流读出铁电单晶薄膜存储器采用的铁电薄膜层（105）为铁电单晶薄膜层，在开态下的读电流大大增加，并且，数据保持特性和数据持久特性得到提升。

Description

大电流读出铁电单晶薄膜存储器及其制备方法和操作方法 技术领域
本发明属于铁电存储技术领域，具体涉及非破坏性读出铁电存储器，尤其涉及一种读出电流大的非破坏性读出铁电单晶薄膜存储器以及该铁电存储器的制备方法和操作方法。
背景技术
铁电随机存储器FRAM(Ferroelectric Random Access Memory)是利用铁电畴(或称为“电畴”)在电场中两种不同极化取向作为逻辑信息(“0”或“1”)来存储数据的非易失性存储器(Non-volatile Memory)，其也可以称为“铁电存储器”。
铁电存储器的存储介质层即为具有可反转(或称为“翻转”)的铁电畴的铁电薄膜层，目前，实验室内可测出的电畴反转的最快速度可达到0.2ns，实际上它还可以更快。通常地，电畴的反转速度决定了存储器的读写时间，电畴反转的矫顽电压决定了器件的读写电压，它会随着薄膜厚度的降低而几乎呈等比例地减小。因此，铁电存储器具有数据读速度快、驱动电压低和存储密度高等优点，近年来得到了广泛的关注和较快的发展。
目前，铁电存储器按基本工作或操作模式主要可分为：破坏性读出(DRO)的FRAM和非破坏性读出(NDRO)的铁电存储器两大类。
传统的非破坏性读出(NDRO)的铁电存储器是以1个晶体管T和一个铁电电容C(即1T1C)构建存储单元，并且是基于电荷读取的。
中国专利申请号为201510036256.X、名称为“非破坏性读出铁电存储器及其制备方法和读/写操作方法”的专利中，以及中国专利申请号为201510036586.1、名称为“非破坏性读出铁电存储器及其制备方法和操作方法”的专利中，揭示了另一种非破坏性读出(NDRO)的铁电存储器，其是以电流读取方式实现非破坏性读出的(即非破坏性电流读取)，制备简单、成本低、存储密度高的优势。因此，备受业界关注。
但是，这种非破坏性电流读取的铁电存储器的读电流相对较小，例如，在pA数量级，以上中国专利中公开的稳定读电流也在100至 1000pA的范围内。较小的读电流会导致数据可读性差、读取速度慢(毫秒至秒的量级)等问题，其严重制约了该铁电存储器的实际应用。
发明内容
为解决以上问题或其他问题，本发明提出一种非破坏性大电流读出的铁电单晶薄膜存储器及其制备方法和操作方法。
按照本发明的一方面，提供一种非破坏性读出铁电存储器，包括铁电薄膜层和设置在所述铁电薄膜层之上的第一电极层，其中，所述第一电极层包括分离设置的第一电极和第二电极，所述铁电薄膜层中的电畴的极化方向基本不平行所述铁电薄膜层的法线方向；在所述第一电极和第二电极之间施加电信号时使能所述铁电薄膜层中的局部电畴反转，从而能够建立连接所述第一电极和第二电极的第一畴壁导电通道；
其中，所述铁电薄膜层为铁电单晶薄膜层。
按照本发明的又一方面，提供一种上述非破坏性读出铁电存储器的制备方法，其特征在于，包括步骤：
提供基底；
形成铁电单晶薄膜层；以及
在所述铁电单晶薄膜层上形成包括分离设置的第一电极和第二电极的第一电极层。
按照本发明的还一方面，提供一种上述非破坏性读出铁电存储器的操作方法，其中，所述铁电单晶薄膜层包括相对其外凸设置的编程凸块，所述第一电极和第二电极设置在所述编程凸块的两侧并至少被所述编程凸块分隔开；在所述第一电极和第二电极之间施加第一方向的写信号时使能至少部分所述编程凸块中的电畴反转，从而建立所述第一畴壁导电通道。
其中，在写数据“1”时，在所述第一电极和第二电极之间施加第一方向的写信号，使能至少部分所述编程凸块中的电畴反转，从而建立所述第一畴壁导电通道；
在写数据“0”时，在所述第一电极和第二电极之间施加与所述第一方向相反的第二方向的写信号，使能所述编程凸块中已反转的电畴反转回到初始极化方向，从而使所述第一畴壁导电通道消失。
根据以下描述和附图本发明的以上特征和操作将变得更加显而易见。
附图说明
从结合附图的以下详细说明中，将会使本发明的上述和其他目的及优点更加完整清楚，其中，相同或相似的要素采用相同的标号表示。
图1是按照本发明第一实施例的非破坏性读出铁电存储器的截面结构示意图。
图2是图1所示实施例的非破坏性读出铁电存储器的上电极的俯视平面结构。
图3是图1所示实施例的铁电存储器的写“1”和读“1”操作过程以及操作原理示意图。
图4是图1所示实施例的铁电存储器的写“0”和读“0”操作过程以及操作原理示意图。
图5是按照本发明又一实施例的非破坏性读出铁电存储器的截面结构示意图。
图6是图1所示的非易失性铁电存储器的读写电极的俯视平面结构。
图7是图1所示实施例的铁电存储器的写“1”和读“1”操作过程以及操作原理示意图。
图8是图5所示实施例的铁电存储器的写“0”和读“0”操作过程以及操作原理示意图。
图9是图5所示实施例的铁电存储器的进行电压扫描式读写操作时的I-V特性曲线图。
图10是图5所示实施例的铁电存储器的畴壁导电通道的建立和消失的压电成像示意图。
图11是图5所示实施例的铁电存储器的数据保持特性曲线示意图。
图12是图5所示实施例的铁电存储器的疲劳特性曲线示意图。
图13是制备如图5所示实施例的铁电存储器的方法流程示意图。
图14是按照本发明还一实施例的非破坏性读出铁电存储器的截面结构示意图。
图15是图14所示实施例的铁电存储器的写“1”和读“1”操作过程以及操作原理示意图。
图16是图14所示实施例的铁电存储器的写“0”和读“0”操作过程以及操作原理示意图。
具体实施方式
下面介绍的是本发明的多个可能实施例中的一些，旨在提供对本发明的基本了解，并不旨在确认本发明的关键或决定性的要素或限定所要保护的范围。
在附图中，为了清楚起见，夸大了层和区域的厚度，图示中的各部分之间的尺寸比例关系并不反映实际的尺寸比例关系。
在以下实施例中，为了描述的清楚，示例性地给出了电畴方向或者极化方向，但是应当理解到，铁电存储器的电畴方向或极化方向并不限于如图所示实施例示出的方向。
在本文中，铁电单晶薄膜层可以是外延单晶生长所形成的单晶薄膜、或者从单晶体中分离或切割所形成的薄膜层，其是指内部不存在多晶结构的“晶界”的单晶结构或类单晶结构，即最终形成的非破坏性读出铁电存储器的每个存储单元是一个单晶体结构，单元尺寸不限。
图1所示为按照本发明第一实施例的非破坏性读出铁电存储器的截面结构示意图；图2所示为图1所示实施例的非破坏性读出铁电存储器的上电极的俯视平面结构。
如图1所示，其中示出了铁电存储器10的部分截面结构，其主要地包括基底101、铁电薄膜层105以及电极层107，其中，电极层107设置在铁电薄膜层105上并与其接触，上电极层107中设置有将其分割为若干部分的间隙109，因此，上电极层107至少包括分离设置的两个或两个以上的电极。在该示例中，间隙109将上电极层107分割为两个部分，即第一电极1071和第二电极1073，第一电极1071和第二电极1073组成读写电极对，在该实施例中，该读写电极对构成了该实施例的上电极层107，其既能用于该实施例的铁电存储器10的写操作，也能用于该实施例的铁电存储器10的读操作。
基底101可以是铁电存储器中常用的各种基底材料，例如其可以为Si、SrTiO3或LiNbO3。通常地，基底100的材料选择主要由下电 极层103和铁电薄膜层105共同决定。在该实施例中，基底101可以是单晶Si衬底，其易于与半导体CMOS工艺兼容，有助于大规模生产。另外，根据下电极101和铁电薄膜层105的晶格常数要求来选择SrTiO3或LiNbO3等基底材料，以便得到性能优异的外延薄膜层。
铁电薄膜层105形成在基底101之上，其是具有合适畴结构的铁电材料，尤其是铁电单晶材料，因此，铁电薄膜层105选择为铁电单晶薄膜层。该铁电单晶层可以在基底101上生长形成，也可以通过将生长形成好的铁电单晶体表面进行切割或剥离等，再键合或粘贴于基体101上形成，铁电单晶薄膜层的具体制备形成办法不是限制性的，以下详细示例进行说明。
在一具体实施例中，在单晶硅的基底101上键合形成铌酸锂LiNbO3铁电单晶薄膜层。
具体地，首先，采用柴式拉晶法(Czochralski method，简称CZ法)，使用高纯度的(例如达到99.99％)的Li2CO3粉末和Nb2O5粉末在约1250摄氏度熔化，然后生长形成同形的LiNbO3，其中具有Li2Omol.48.5％；通过双炉缸CZ法并使用自动粉末送料系统，具有49.6mol.％Li2O的LiNbO3单晶体生成，这样，LiNbO3单晶体中Li与Nb的化学计量比接近或等于1∶1。在该过程中，为增加最后制备形成的铁电单晶薄膜层中的畴壁导电通道的电流大小，LiNbO3单晶体中掺杂2mol.％的MgO。随后，使用离子注入和与硅片键合技术，将LiNbO3单晶体的一表层剥离键合以形成LiNbO3铁电单晶薄膜层。例如，首先，在表面使用H+或He+离子注入，通过控制离子注入能量控制离子进入LiNbO3单晶体的深度；第二，清洗离子注入后的LiNbO3单晶体并将离子注入面化学键合到作为基底101的单晶硅衬底上，该单晶硅的基底101上可以沉积一层SiO2层以提高其与LiNbO3单晶体粘附性；将粘附在基底101上的一层LiNbO3铁电单晶薄膜层从LiNbO3单晶体分离。这样，铁电薄膜层105(即铁电单晶薄膜层)制备形成，铁电薄膜层105具体为MgO掺杂的单晶铌酸锂LiNbO3。
需要说明的是，制备的工艺、材料等差异，可以得到不同材料类型的铁电单晶薄膜层105，其具体材料类型并不限于以上实施例，例如其还可以为其他的单晶的铌酸锂型铁电体(例如单晶的钽酸锂LiTaO3)，甚至在其他替换实施例中，还可以采用单晶的锆钛酸铅盐 (Pb，Zr)TiO3、掺La的铁酸铋盐(Bi，La)FeO3、或铁酸铋BiFeO3，或者单晶的Bi4Ti3O12、(La，Bi)4Ti3O12、或SrBi2Ta2O9。
以上LiNbO3铁电单晶薄膜层中使用MgO掺杂能提高基于畴壁导电通道进行导电时的电流大小，其基本原理是：Mg离子替代能够引起晶格畸变，并产生施主能级。
在其他实施例中，也可以采用FeO或TaO对LiNbO3铁电单晶薄膜层或其他铁电单晶薄膜层进行掺杂，当然，也可以采用MgO、FeO与TaO的任意组合来对铁电单晶薄膜层105进行掺杂。其中掺杂材料的摩尔掺杂百分比为0.1％至10％。
需要说明的是，以上实施例对LiNbO3单晶体进行剥离切割的过程，是基于X向切割形成LiNbO3铁电单晶薄膜层，因此，最终具体制备得到铁电单晶薄膜层105为2mol.％MgO掺杂-X向切割-LiNbO3铁电单晶薄膜层。在其他实施例中，也可以基于XYZ向或XZ(YZ)向切割形成LiNbO3铁电单晶薄膜层。
在一实施例中，铁电薄膜层105的厚度范围可以大于或等于5纳米且小于或等于22微米，例如，其可以为40nm、80nm或200nm。
继续如图1和图2所示，第一电极1071和第二电极1073在该实施例中可以是通过连续的金属薄膜层通过构图刻蚀间隙109来形成，当然，在其他实施例中，它们也可以分别地构图形成。在本文中，第一电极1071和第二电极1073组成读写电极对，在此处“读”反映它们至少具有读出操作的功能、“写”反映它们至少具有写操作的功能。
第一电极1071和/或第二电极1073其可以是一种低电阻率的导电材料，例如，其可以选自于Pt、SrRuO3、LaNiO3、Al、Cu、Ru、Ir、IrO2中的一种或多种的组合。第一电极1071和/或第二电极1073的厚度可以为5～100nm，例如，20nm。第一电极1071和/或第二电极1073可以但不限于通过溅射、CVD、PLD等薄膜淀积方法制备形成。
间隙109用于将第一电极1071和第二电极1073实现相对电隔离(该电隔离不包括以下通过操作过程中建立的畴壁导电通道的情形)，也即不借助铁电薄膜层105等的情况下第一电极1071和第二电极1073是电隔离的。间隙109可以通过对金属平层电子束加工、纳米压印或其他光刻方法获得，但是间隙109的形成方法并不限于本发明实施例。间隙109的间距d的范围可以大于或等于2纳米且小于 或等于10微米，更优地大于或等于5纳米且小于或等于2微米，例如可以为10纳米、100纳米、1微米等，间距d越小，越有利于提高铁电存储器的存储密度，并且越有利于减小写电压和读电压、增大读电流，并且读功耗和写功耗越小，因此，本发明实施例的铁电存储器10可以按比例(Scaling-down)缩小，间隙109可选地可以设置为各种纳米尺寸的间隙。间隙109的形状并不限于如图2所示形状，在其他实施例中，间隙109甚至还可以为锯齿形等。第一电极1071和第二电极1073在垂直间隙方向上的宽度w尺寸(也即间隙的宽度尺寸)可以大于或等于2纳米且小于或等于10微米，例如100纳米。
继续如图1所示，在本发明中，铁电薄膜层105要求满足其铁电畴在面内(in-plane)有分量的条件，也即具有面内分量(铁电畴的自发极化在膜面上的投影)，铁电薄膜层105可以形成如图1所示两个方向的电畴1051或1053，电畴1051的极化方向与电畴1053的极化方向完全相反，在偏置大于矫顽电压后，电畴会沿电场方向取向，因此，在偏置电场方向与原电畴方向相反的电压且大于矫顽电压时，电畴1051或1053会发生反转。在该实施例中，铁电薄膜层105的电畴的极化方向基本不垂直铁电薄膜层105的法线(如图所示垂直于铁电薄膜层105的虚线)方向，或者基本不垂直于上电极层107。具体如图1所示，铁电薄膜层105的法线与电畴的极化方向的夹角α为不等于0和180°，例如α＝45°，这样电畴1051或1053具有面内分量，易于实现写操作。具体地，可以通过控制铁电单晶薄膜层105生长的晶向或者切割方向(例如X切向或XYZ切向)来实现。
以下进一步说明图1所示实施例的铁电存储器10的存储和操作原理。
图3所示为图1所示实施例的铁电存储器的写“1”和读“1”操作过程以及操作原理示意图。
如图3所示，在该实施例中，在写操作过程中，假设铁电单晶薄膜层105中的电畴的极化方向统一为图1中电畴1053的方向(在其他实施例中，也可以统一为图1中电畴1051的方向)，首先，如图3(a)所示，第一电极1071和第二电极1073施加写信号Vwrite1，使，第一电极1071偏置正电压、第二电极1073偏置负电压(此时定义为“+”写电压)，基于该方向的写信号Vwrite1时，将形成大致如图3(a) 所示方向的电场E1。
由于间隙109的存在，电场E1可以局部地对间隙109所对应的部分铁电薄膜层1053的电畴产生影响，随着电场E1的增大，如图3(a)所示，间隙109的下方的对应的部分铁电薄膜层105中，也即暴露于间隙109的表层部分的局部，其中的电畴发生反转，也即对应间隙109的电畴1053局部被反转形成如图3(a)所示的电畴1053b，铁电薄膜层105的其他部分的电畴1053由于基本不受电场E1影响(或者电场E1对其影响不足使其电畴生反转)，电畴未反转，对应形成如图所示的电畴1053a，电畴1053b的极化方向基本与电畴1053a的极化方向基本相反。其中，电畴1053b是利用电场E1在与电畴1053a的极化方向相反的方向上的电场分量来实现翻转的，因此，在铁电薄膜层的矫顽电压已知的情况下，可以计算出形成电畴1053b的最小电压，即最小写电压。
此时，具有电畴1053a的铁电薄膜层部分与具有电畴1053b的铁电薄膜层部分的邻接处，也即电畴1053a和电畴1053b之间的界壁或界面，会产生带电的畴壁或畴界，从而，主要基于畴壁导电机理，在第二电极1073与第一电极1071之间产生导电通道，即畴壁导电通道1054。畴壁导电通道1054的建立表示写“1”操作成功，也即存储了数据“1”。
如图3(b)所示，在第一电极1071和第二电极1073施加读信号Vread，使第一电极1071偏置正电压、第二电极1073偏置负电压(此时定义为“+”读电压)，读信号Vread的方向也不是限制性的，其也可以在第一电极1071和第二电极1073上偏置为“-”读电压。在读信号Vread的电压相比写信号Vwrite1的电压小，其可以防止读操作过程中的误写入操作，例如，读信号Vread的电压小于使电畴1051或1053反转的矫顽电压，因此，如图3(b)中由读信号Vread产生的电场E2小于矫顽场Ec，从而不存在足够使电畴1053b反转的电场分量，铁电单晶薄膜层105中的电畴1053b和1053a基本保持不变，畴壁导电通道1054也保持，第一电极1071和第二电极1073相应产生读电流Iread1，此时读电流Iread1相对较大，表示开态(On态)，从而读出逻辑信息“1”。
图4所示为图1所示实施例的铁电存储器的写“0”和读“0”操作过程以及操作原理示意图。
如图4(a)所示，第一电极1071和第二电极1073施加写信号Vwrite0，使第二电极1073偏置正电压、第一电极1071偏置负电压(此时定义为“-”写电压)，基于该方向的写信号Vwrite0时，将形成大致如图4(a)所示方向的电场E3，其与图3(a)的电场方向E1相反。与以上图3(a)写“1”操作过程中电场E1对铁电单晶薄膜层105的作用原理相同，电场E3可以使电畴1053b(如图3(a)所示)反转恢复至原来的极化方向，从而在铁电单晶薄膜层105统一形成电畴1053。此时，畴壁或畴界消失，原来在第二电极1073与第一电极1071之间产生的畴壁导电通道1054也消失，此时，表示写“0”操作成功，也即存储数据“0”。
如图4(b)所示，第一电极1071和第二电极1073施加读信号Vread，该读信号与图3(b)中的读信号相同，即第一电极1071偏置正电压、第二电极1073偏置负电压(此时定义为“+”读电压)，由于畴壁导电通道1054消失，第一电极1071和第二电极1073之间相应产生读电流基本为0或非常小的Iread0，表示关态(Off态)，从而读出逻辑信息“0”。
以上读“1”或读“0”操作过程中铁电单晶薄膜层105的电畴也基本不发生变化，因此，在读信号Vread撤去后，畴壁导电通道1054的状态(“存在”或“消失”)不会发生变化，从而对存储的数据“1”或“0”不会产生影响，实现非破坏性读出。并且，以上读“1”或读“0”操作是以读出的电流大小来区分数据状态的，完全区别于传统的铁电存储器中的电荷读取方式。
在以上图1所示实施例的铁电存储器中，读“1”操作的读电流Iread1可以达到100nA至1000nA的数量级范围，读“1”操作的电流Iread1相对“1”操作的电流Iread0之间可以存在4-7以上的数量级的差别。因此，读出窗口大，并且，数据易读性强。本申请的发明人发现，这是主要是由于采用单晶的铁电薄膜层105作为存储层形成存储单元，有效减少了晶格缺陷，例如晶界、畴界、缺陷富集区、第二相等。
并且，图1所示实施例的铁电存储器10的读电流大大增加的情况下，其读取速度也将明显增加。
本申请的发明人发现，以上图1所示实施例的铁电存储器10的数据保持(Retention)特性和数据持久(Endurance)特性相比于背景 技术中引用的非破坏性铁电存储器大大提升，这主要是因为在单晶结构中，单晶畴正、负极化方向稳定，缺陷少。。
图5所示为按照本发明又一实施例的非破坏性读出铁电存储器的截面结构示意图；图6所示为图1所示的非易失性铁电存储器的读写电极的俯视平面结构。如图5所示，其中示出了铁电存储器30的部分截面结构，其主要地包括基底301、铁电薄膜层303、铁电薄膜层303中设置的编程凸块305、以及读写电极层307。读写电极层307的“读”反映它们至少具有读出操作的功能，读写电极层307的“写”反映它们至少具有写操作的功能。
继续如图5所示，基底301可以是铁电存储器中常用的各种基底材料，例如其可以为Si、SrTiO3或LiNbO3。通常地，基底301的材料选择主要由基底301和铁电薄膜层303共同决定。在该实施例中，基底301可以是Si衬底，其易于与半导体CMOS工艺兼容，有助于大规模生产。另外，根据铁电薄膜层303的晶格常数要求来选择SrTiO3或LiNbO3等基底材料，以便得到性能优异的外延薄膜层。此外，基底301和铁电薄膜层303可以是同一种材料，即铁电材料，包括铁电块体陶瓷和单晶等。
对比与图1所示实施例的铁电存储器10的铁电薄膜层103，图5所示的铁电薄膜层303同样为铁电单晶薄膜层，其采用的材料类型、制备工艺等可以与以上图1实施例的铁电薄膜层103的材料类型、制备工艺等分别相同，在此不再赘述。
编程凸块305是设置在铁电单晶薄膜层303上，它们是一体地制备形成的，也就是说，编程凸块305与铁电单晶薄膜层303是一体的并且具有相同的材料类型，并且它们同属于一个单晶体。具体地，可以通过对铁电薄单晶膜层303构图刻蚀后，形成相对铁电薄单晶膜层303外凸的编程凸块305，例如，通过半导体工艺光刻，采用电子束直写或纳米压印或光刻等技术实现编程凸块305的图形转移，而后通过刻蚀技术，包括干法刻蚀和湿法刻蚀在对铁电薄单晶膜层303表面形成编程凸块305。编程凸块305例如可以为矩形方块结构或圆柱结构的凸台，其具体形状并不是限制性的。
继续如图5和图6所示，读写电极层307中设置分离的第一电极3071和第二电极3073，第一电极3071和第二电极3073设置在铁电 薄单晶膜层303上并分别位于编程凸块305两侧，也即第一电极3071和第二电极3073设置在铁电薄单晶膜层303的编程凸块305的两侧并至少被编程凸块305分隔开。第一电极3071和第二电极3073分别与编程凸块305的侧沿接触。
在该实施例中，编程凸块305的宽度d即对应第一电极3071和第二电极3073之间的间隙间距，d具体可以大于或等于2纳米且小于或等于10微米，例如可以为10纳米、100纳米、1微米等。间距d越小，越有利于提高铁电存储器的存储密度，并且越有利于减小写电压、读电压，并且读/写功耗越小，因此，编程凸块305可以为各种微米纳米尺寸结构。编程凸块305相对铁电薄单晶膜层303的高度，也即编程凸块305的厚度，可以大于或等于2纳米且小于或等于1微米，例如50nm。
在又一实施例中，读写电极层307可以是在编程凸块305的两侧设置的边墙结构，第一电极3071和第二电极3073作为分离的两个边墙设置在编程凸块305的两相对的侧沿。
具体地，第一电极3071和第二电极3073其通过一种低电阻率的导电材料制成，例如，其可以选自于Pt、SrRuO3、LaNiO3、Al、Cu、Ru、Ir、IrO2中的一种或多种的组合。第一电极3071和/或第二电极3073的厚度可以为2-100nm，例如，30nm。读写电极层307的厚度可以大于或等于编程凸块305的厚度。第一电极3071和/或第二电极3073可以但不限于通过溅射、蒸发、CVD、PLD等薄膜淀积方法制备形成。
继续如图1所示，在本发明中，铁电薄膜层303和编程凸块305要求满足其铁电畴在面内有分量的条件，也即具有面内分量(铁电电畴的自发极化在膜面上的方向的投影)，铁电薄膜层303可以形成如图1所示两个方向的电畴3031或3033，编程凸块305中可以形成如图1所示两个方向的电畴3051或3053，电畴3031和3051的极化方向分别与电畴3033和3053的极化方向完全相反，在偏置大于矫顽电压后，电畴会沿电场方向取向，因此，在偏置电场方向与原电畴方向相反且电压大于矫顽电压时，电畴3031和3051或3033和3053会发生反转。在该实施例中，铁电薄膜层303和编程凸块305的电畴的极化方向基本不平行读写电极层307的法线(如图所示垂直于读写电极 层307的虚线)方向，具体地，可以通过控制铁电薄膜层303生长的晶向来实现，示例地，可以在晶面为(001)的SrTiO3基底301上外延生长100纳米厚的BiFeO3铁电薄膜层303，其中BiFeO3铁电薄膜层303的电畴的极化方向是沿<111>方向。
需要说明的是，为示意方便，图5中将铁电薄膜层303和编程凸块305的电畴分离地表示，但是，在实际中，有可能它们并不是分离地，相反地，它们可能是连续的，铁电薄膜层303和编程凸块305中的电畴构成单畴。例如，铁电薄膜层303和编程凸块305的极化方向一致时，例如，电畴3031和电畴3051具有一致的极化方向(或者电畴3033和电畴3053具有一致的极化方向)，它们可以连续地表示。
以下进一步说明图5所示实施例的铁电存储器30的存储原理和读写操作原理。
图7所示为图1所示实施例的铁电存储器的写“1”和读“1”操作过程以及操作原理示意图。
如图7(a)所示，在该实施例中，在写“1”操作过程中，假设铁电单晶薄膜层305中的电畴的极化方向统一为图5中所示的电畴3031的方向。在写“1”操作过程中，在读写电极层307的第一电极3071和第二电极3073之间偏置写信号Vwrite1，也即在第二电极3073和第一电极3071构成的读写电极对上偏置写信号Vwrite1，写信号Vwrite1的方向为第二电极3073偏置负向、第一电极3071偏置正向，从而它们形成大致如图3(a)所示方向的电场E4。由于第一电极3071和第二电极3073是分布在编程凸块305的两侧，根据电场E4的分布特点，在编程凸块305中电场强度相对在铁电单晶薄膜层303中电场强度更大，对编程凸块305中的电畴产生影响相对更大，表现在编程凸块305的电畴3051相对铁电单晶薄膜层303中的电畴3031更容易反转，因此，在电场E4的作用下，电畴3051均反转形成电畴3053，也即，电场E4在与编程凸块305的电畴3051的极化方向相反的方向上的电场分量大于使该电畴发生翻转的矫顽电压时，该编程凸块305中的具有面内铁电极化分量的电畴发生反转，即电畴3051发生反转形成电畴3053。可以通过设置写信号Vwrite1的大小，使编程凸块305的电畴3051反转而铁电薄膜层303的电畴3031基本不反转(或者仅接近编程凸块305的很小一部分反转)，也即此时，铁电薄膜层303的电畴3031 基本不受电场E4影响(或者电场E4对其影响不足使其电畴3031生反转)。
因此，此时，编程凸块305中的电畴3053的极化方向将基本与铁电薄膜层303中的电畴3031的极化方向完全相反，电畴3031和电畴3053(编程凸块305周边的不反转电畴)之间形成带电的畴壁或畴界，从而形成畴壁导电通道3054。此时，第一电极3071和第二电极3073可以通过畴壁导电通道3054导电连接，畴壁导电通道3054的建立表示写“1”操作成功，也即存储了数据“1”。
需要说明的是，随着写信号Vwrite1的电压增大，可能会如4所示的铁电存储器10的写操作原理类似，铁电单晶薄膜层303中的越来越多的接近编程凸块305部分中的电畴3031受电场E4影响被反转。从而畴壁导电通道3054不断往下凸，直至接近基底301，这样，是有可能在接近基底301的地方导致畴壁导电通道3054断裂，从而第二电极3073和第一电极3071的导电通道关断。因此，一方面，可以设置写信号Vwrite1的电压大小以仅使编程凸块305中电畴3051或3053反转而不使铁电薄膜层303的电畴3031或3033的电畴反转；另一方面，可以设置铁电单晶薄膜层303的厚度大于编程凸块305的高度，使写“1”操作后形成的畴壁导电通道3054不能大致纵向贯通铁电薄膜层303的上表面和下表面。
需要说明的是，由于电畴3053是利用电场E4在与电畴3031的极化方向相反的方向上的电场分量来实现翻转的，因此，在编程凸块的宽度(d)、矫顽电压Vc已知的情况下，可以计算出使电畴3051反转形成电畴3053的最小写电压Vwrite1。
如图7(b)所示，在该实施例中，读操作原理完全不同于传统的铁电存储器的读操作原理，其中，在读操作时，基底301不需要偏置信号，其可以悬空，读信号Vread是偏置在读写电极对之间，以下以偏置在第一电极3071、第二电极3073为示例进行说明。
继续如图7(b)所示，在读“1”操作过程中，第一电极3071、第二电极3073之间偏置读信号Vread，第二电极3073偏置负向、第一电极3071偏置正向，从而在第二电极3073与第一电极3071之间形成如图所示方向的电场E5(E5小于矫顽场Ec)，由于电场E5不存在使电畴3053反转的电场分量，电畴3053完全保持不变，从而所形成 的畴壁导电通道3054未被关断，此时，第二电极3073与第一电极3071产生读电流Iread1，读电流Iread1相对较大，其表示为On态(即开态)，表示读出逻辑信息“1”。
需要说明的是，读信号Vread的读电压可以小于写信号Vwrite1的写电压，这样，有利于避免在读操作时产生“过”写操作。
需要理解的是，当读信号Vread撤去以后，由于以上读操作过程中编程凸块305的电畴3053不发生变化，因此，读信号Vread撤去以后编程凸块305的电畴也不发生变化，畴壁导电通道3054将稳定存在，数据“1”一直能够得到保持，因此，该读操作过程为非破坏性读出。
图8所示为图5所示实施例的铁电存储器的写“0”和读“0”操作过程以及操作原理示意图。如图8(a)所示，在写“0”操作过程中，在第二电极3073和第一电极3071构成读写电极对上偏置写信号Vwrite0，写信号Vwrite0与写信号Vwrite1的方向相反，其中，第二电极3073偏置正向、第一电极3071偏置负向，从而它们形成大致如图8(a)所示方向的电场E6。写信号Vwrite0对编程凸块305的写操作原理与写信号Vwrite1对编程凸块305的写操作原理基本相同。电场E6可以对编程凸块305所对应的电畴产生影响，也即可以对如图7(a)所示电畴3053产生影响，电场E6在与编程凸块305的电畴3053的极化方向相反的方向上的电场分量大于使该电畴发生翻转的矫顽电压时，该电畴3053发生反转，回复到原来的或初始的极化方向，统一形成电畴3051。此时，编程凸块305的电畴3051与铁电单晶薄膜层303的电畴3031的极化方向相同，二者之间不存在畴壁或畴界，原来在第二电极3073与第一电极3071之间产生的畴壁导电通道3054也消失，此时，表示写“0”操作成功，也即存储数据“0”。
需要说明的是，写信号Vwrite0和Vwrite1的具体信号形式不是限制性的，例如其可以为一定频率的电压脉冲信号等。
如图8(b)所示，在读“0”操作过程中，第一电极3071、第二电极3073之间偏置读信号Vread，形成如图所示方向的电场E5，由于电场E5小于编程凸块305的矫顽场Ec，编程凸块305的电畴3051在读操作过程中不会发生反转，从而不能形成如图7中所示的畴壁导电通道。由于畴壁导电通道3054消失，此时，第二电极3073与第一电极3071未产生读电流(Iread＝0)或者读电流非常小，读电流Iread为Off 态(即关态)，表示读出逻辑信息“0”。
需要理解的是，当读信号Vread撤去以后，由于以上读操作过程中编程凸块305的电畴3051不发生变化，因此，读信号Vread撤去以后编程凸块305的电畴也不发生变化，数据“0”一直能够得到保持，因此，该读操作过程为非破坏性读出。
需要说明的是，尽管以上是以编程凸块305的电畴3051和铁电单晶薄膜层303的电畴3031所在极化方向存储逻辑信息“0”、编程凸块305的电畴3053和铁电单晶薄膜层303的电畴3031所在极化方向存储逻辑信息“1”为示例进行说明的，本领域技术人员将理解到，也可以是以编程凸块305的电畴3053和铁电单晶薄膜层303的电畴3033所在极化方向存储逻辑信息“0”、编程凸块305的电畴3051和铁电单晶薄膜层303的电畴3033所在极化方向存储逻辑信息“1”，相应的写操作和读操作中的电压信号方向也可以进行适用性地变化，以实现类似如图7和图8中所示的读写操作过程。
以下基于图5所示实施例的铁电存储器50，进行了相关测试。其中，铁电存储器50的铁电单晶薄膜层303(包括编程凸块305)具体是2mol.％MgO掺杂-X向切割-LiNbO3铁电单晶薄膜层。
图9所示为图5所示实施例的铁电存储器的进行电压扫描式读写操作时的I-V特性曲线图。其中，实线表示编程凸块305的宽度d为150nm的样品的I-V特性曲线，虚线表示编程凸块305的宽度d为50nm的样品的I-V特性曲线。如图9所示，可以在第一电极3071和第二电极3073之间偏置电压进行扫描，例如，首先从0V逐渐增加至+12V、再返回至0V、再从0V扫描增加至-12V。可以看到，在0V逐渐增加至+12V的过程中，电流会突然增大，表示写“1”操作成功，畴壁导电通道建立，随后能够读出的最大电流可以达到微安数量级，因此，读电流大大增加。
图10所示为图5所示实施例的铁电存储器的畴壁导电通道的建立和消失的压电成像示意图。其中，编程凸块305的宽度为150nm，“左电极”和“右电极”即组成读写电极对，偏置不同方向的写电压时(例如，+7V、-7V)，在±7V下压电成像，从中，可明显看出畴壁的开关状态，即写入数据“1”时，畴壁导电通道明显建立，写入数据“0”时畴壁导电通道明显消失。
图11所示为图5所示实施例的铁电存储器的数据保持特性曲线示意图。在该测试样品中，编程凸块305的宽度为150nm、第一电极3071和第二电极3073为宽100nm的金属Pt电极，在读信号Vread＝4V作用下，读出的开关电流随时间变化并形成如图11所示的曲线。从图11至少可以看到，一方面，开态的读电流可以达到10-7A至10-6A，读电流大；另一方面，On态电流和Off态电流之比(即开关比)能够大于106，数据窗口大；还一方面，读出电流随时间稳定，在106秒以后数据还能得到很好保持，即数据保持性非常好。
图12所示为图5所示实施例的铁电存储器的疲劳特性曲线示意图。在该测试样品中，编程凸块305的宽度为150nm、第一电极3071和第二电极3073为宽100nm的金属Pt电极，在+8V/-10V为一个写周期(其中包括写“0”和写“1”)、周期频率为1MHz的写电压作用下，每次写“0”和写“1”后在4V电压下读出相应的开关电流，图12中示出了每个写周期的开关电流随写周期数的变化。从图12至少可以看到，一方面，开态的读电流可以达到10-7A，读电流大并且随着写操作的不断进行，开态的读电流不会减小；另一方面，On态电流和Off态电流之比(即开关比)能够大于106，数据窗口大；还一方面，读写周期大于1010。
因此，可以看到，图5所示实施例的铁电存储器30中，至少由于铁电薄膜层303和编程凸块305都是使用铁电单晶材料，编程操作是发生在同一单晶或类单晶结构中，因此，读电流大(可以达到μA数量级)、数据可读性好，并且，数据保持特性、疲劳特性等可靠性方面非常好，而且，开关比大。铁电存储器30由于还采用编程凸块305，能使施加在其两侧的第一电极3071和第二电极3072的电场能够更好且更有效地对编程凸块305中的电畴产生作用，编程操作时，很容易通过控制写电压(或读电压)的大小来使编程作用(即电畴的反转)基本发生在编程凸块305中。编程凸块305的存在能够使电畴反转有效电场增大，写电压降低，退极化效应减小。从而，在同样电压大小作用下可以实现更有效地编程操作，建立后的畴壁导电通道也更加稳定，这样，进一步减小写“0”或写“1”的写电压、提高数据存储的可靠性。
图13所示为制备如图5所示实施例的铁电存储器的方法流程示 意图。结合图5和图13所示，首先，步骤S810，提供如图1所示的基底310，基底310的材料选择主要由铁电薄膜层303共同决定，也可与铁电材料相同，即为铁电陶瓷块体或单晶。在该实施例中，基底301可以是Si衬底，其易于与半导体CMOS工艺兼容。
进一步，步骤S820，形成铁电薄膜层303。在该实施例中，铁电薄膜层303可以但不限于选自于以下材料：单晶的铌酸锂型铁电体(例如，单晶钽酸锂LiTaO3)、单晶锆钛酸铅盐(Pb，Zr)TiO3、掺La的铁酸铋盐(Bi，La)FeO3、或铁酸铋BiFeO3，或者单晶的Bi4Ti3O12、(La，Bi)4Ti3O12、或SrBi2Ta2O9。铁电薄膜层303可以通过离子键合技术、溅射、CVD、PLD等薄膜淀积方法制备形成。
在一实施例中，在单晶硅的基底301上键合形成铌酸锂LiNbO3铁电单晶薄膜层。
具体地，首先，采用柴式拉晶法(Czochralski method，简称CZ法)，使用高纯度的(例如达到99.99％)的Li2CO3粉末和Nb2O5粉末在约1250摄氏度熔化，然后生长形成同形的LiNbO3，其中具有Li2Omol.48.5％；通过双炉缸CZ法并使用自动粉末送料系统，具有49.6mol.％Li2O的LiNbO3单晶体生成，这样，LiNbO3单晶体中Li与Nb的化学计量比接近或等于1∶1。在该过程中，为增加最后制备形成的铁电单晶薄膜层的畴壁导电通道的电流大小，LiNbO3单晶体中掺杂2mol.％的MgO。随后，使用离子注入和硅片键合技术，将LiNbO3单晶体的一表层剥离切割以形成LiNbO3铁电单晶薄膜层。例如，首先，在表面使用H+或He+离子注入，通过控制离子注入能量控制离子进入LiNbO3单晶体的深度；第二，清洗离子注入后的LiNbO3单晶体并将离子注入面化学键合到作为基底301的单晶硅衬底上，该单晶硅的基底301上可以沉积一层SiO2层以提高其与LiNbO3单晶体粘附性；将粘附在基底301上的一层LiNbO3铁电单晶薄膜层从LiNbO3单晶体分离。这样，铁电薄膜层303(即铁电单晶薄膜层)制备形成，铁电薄膜层303具体为MgO掺杂的单晶铌酸锂LiNbO3。
以上LiNbO3铁电单晶薄膜层中使用MgO掺杂能提高基于畴壁导电通道进行导电时的电流。在其他实施例中，也可以采用FeO或Ta2O5对LiNbO3铁电单晶薄膜层或其他铁电单晶薄膜层进行掺杂，当然，也可以采用MgO、FeO与Ta2O5的任意组合来对铁电单晶薄膜层105 进行掺杂。其中掺杂材料的摩尔掺杂百分比为0.1％至10％。
需要说明的是，以上实施例对LiNbO3单晶体进行剥离切割的过程，是基于X向切割形成LiNbO3铁电单晶薄膜层，因此，最终具体制备得到铁电单晶薄膜层303为2mol.％MgO掺杂-X向切割-LiNbO3铁电单晶薄膜层。在其他实施例中，也可以基于XYZ或XZ(YZ)向切割形成LiNbO3铁电单晶薄膜层。
进一步，步骤S830，在铁电薄膜层303的面内刻蚀出编程凸块305。在该实施例中，编程凸块305可以通过半导体光刻、电子束直写或纳米压印等技术将图形转移到铁电薄膜层303上，然后通过干法刻蚀(反应离子刻蚀(RIE)或电感耦合等离子体刻蚀(ICP))或湿法刻蚀形成编程凸块303。需要说明的是，该编程凸块303是从单晶的铁电薄膜层303上制备形成，因此，铁电薄膜层303与编程凸块303均是在同一单晶结构中。编程凸块305的高度优选地小于刻蚀后的铁电薄膜层303的厚度，例如，编程凸块305的高度可以为2-500nm。
进一步，步骤S840，在铁电薄膜层303和编程凸块305上形成面内读写电极对。在该实施例中，读写电极对主要由第一电极3071和第二电极3073构成，第一电极3071和第二电极3073之间被编程凸块305分开；读写电极对可以选自于Pt、SrRuO3、LaNiO3、Al、Cu、Ru、Ir、IrO2中的一种或多种的组合；第一电极3071和第二电极3073的厚度大于或等于编程凸块305的高度，其例如可以为2-100nm(例如，30nm)。第一电极3071和第二电极3073所在的读写电极层307可以但不限于通过溅射、CVD或PLD等薄膜淀积方法制备形成，第一电极3071和第二电极3073进一步可以但不限于通过电子束加工、纳米压印或其他光刻方法获得。
这样，基本形成如图5所示实施例的铁电存储器30。
图14所示为按照本发明还一实施例的非破坏性读出铁电存储器的截面结构示意图。在该实施例中，铁电存储器40相比于图5所示实施例的铁电存储30，其还包括在编程凸块305上设置的第三电极4075，从而，第一电极3071、第二电极3073和第三电极4075共同构成了铁电存储器40的读写电极层407。第三电极4075具有读电极的功能，其用于在读操作的过程中施加电信号。在一实施例中，第三电极4075与第一电极3071、第二电极3073采用同样的金属材料并同步 地构图刻蚀形成。
铁电存储器40中的其他部件与图5所示实施例的铁电存储30的其他部件基本相同，在此不再一一赘述。
图15所示为图14所示实施例的铁电存储器的写“1”和读“1”操作过程以及操作原理示意图。
如图15(a)所示，在该实施例中，其写“1”操作过程与图7(a)所示的写操作过程基本相同，具体在该实施例中，第三电极4075可以施加一个合适的偏压，例如接地，从而有效地降低写电压，也有利于增大读出畴壁电流；当然第三电极4075也可以悬空。第一电极3071和第二电极3073之间偏置写信号Vwrite1，因此，铁电存储器40的写“1”操作原理与铁电存储器30的写“1”操作原理基本相同，在此不再赘述。在写“1”操作后，如图15(a)所示，编程凸块305中电畴3051和3053在电场E4的影响下统一为电畴3053，也即所有电畴3051反转形成电畴3053，编程凸块305中的电畴的极化方向是相同的，并且与铁电薄膜层303中统一的电畴3031的极化方向完全相反，因此，建立畴壁导电通道3054，其能够电连接第一电极3071和第二电极3073。
如图15(b)所示，在读“1”操作过程中，在第一电极3071和第二电极3073中任意一个与第三电极4075之间偏置读信号Vread。以下以第一电极3071和第三电极4075之间偏置读信号Vread为示例进行说明。
如图15(b)所示，在读“1”操作过程中，第一电极3071和第三电极4075之间偏置读信号Vread，第三电极4075偏置负向、第一电极3071偏置正向，从而在第一电极3071与第三电极4075之间形成如图所示方向的电场E7(E7大于矫顽场Ec)，由于电场E7不存在使电畴3053反转的电场分量，第一电极3071与第三电极4075之间的间隙下方的对应的部分编程凸块305中，电畴3053不会发生反转，这样，在编程凸块305内不会产生类似写“1”操作时形成的畴壁导电通道，即第一电极3071与第三电极4075之间未形建立畴壁导电通道，此时，第一电极3071与第三电极4075之间基本未产生读出电流，读电流Iread＝0，其对应表示编程凸块305与铁电薄膜层303之间的畴壁导电通道3054为On态(即开态)，读出逻辑信息“1”。
在读信号Vread撤去以后，由于以上读操作过程中编程凸块305中 的电畴基本没有发生变化，因此，读信号Vread撤去以后编程凸块305中的电畴也不发生变化，存储的数据“1”并不会变化，因此，不会产生破坏性读取。
需要理解的是，在第二电极3073和第三电极4075之间偏置如图15(b)的虚线示意的读信号Vread时，同样地可以读出逻辑信息“1”。
需要说明的是，不同于图7(b)所示的读信号Vread的读电压必须小于写信号Vwrite1的写电压，图15(b)所示的读出电压完全不受写电压大小限制并且基本不会对畴壁导电通道3054产生影响，因此，读操作过程中不会产生误写操作。
图16所示为图14所示实施例的铁电存储器的写“0”和读“0”操作过程以及操作原理示意图。
如图16(a)所示，在该实施例中，其写“0”操作过程与图8(a)所示的写操作过程基本相同，在该实施例中，第三电极4075可以悬空，或者也可以施加一个合适的偏压，例如接地，从而有效地降低写电压；第一电极3071和第二电极3073之间偏置写信号Vwrite0，因此，铁电存储器40的写“0”操作原理与铁电存储器30的写“0”操作原理基本相同，在此不再赘述。
在写“0”操作后，如图16(a)所示，编程凸块305中电畴3051和3053在电场E4的影响下统一为电畴3051，也即所有电畴3053反转形成电畴3051，编程凸块305中的电畴的极化方向是相同的，并且与铁电薄膜层303中统一的电畴3031的极化方向基本相同，因此，之前建立畴壁导电通道3054消失。
需要说明的是，基于编程凸块305在写信号Vwrite0作用下的电场强度分布可知，Vwrite0的写电压越大，使电畴3053回复反转的深度越深。因此，可以通过控制写信号Vwrite0的电压大小，使电畴3053全部恢复反转为电畴3031；示例地，如图16(a)所示，在具有一定电压大小的写信号Vwrite0作用下，对应编程凸块的电畴3053(如图15(a)所示)被完全被回转形成电畴3051，畴壁导电通道3054完全消失。
如图16(b)所示，在读“0”操作过程中，在第一电极3071和第二电极3073中任意一个与第三电极4075之间偏置读信号Vread。以下以第一电极3071和第三电极4075之间偏置读信号Vread为示例进行说明。
如图16(b)所示，在读“0”操作过程中，第一电极3071和第三电极4075之间偏置读信号Vread，第三电极4075偏置负向、第一电极3071偏置正向，从而在第一电极3071与第三电极4075之间形成如图所示方向的电场E7(E7大于矫顽场Ec)，由于电场E7存在使电畴3053反转的电场分量，电场E7在与电畴3051的极化方向相反的方向上的电场分量大于使该电畴发生翻转的矫顽电压时，第一电极3071与第三电极4075之间的间隙下方的对应的部分编程凸块305(即编程凸块305局部)中，电畴3051局部会发生反转形成电畴3053b，电畴3051中未反转的对应为3051a，这样，电畴3053b与电畴3051b极化方向相反，二者之间形成畴壁或畴界，从而，在编程凸块305内会产生类似写“1”操作时形成的畴壁导电通道，即第一电极3071与第三电极4075之间建立畴壁导电通道3057。此时，第一电极3071与第三电极4075之间可以通过畴壁导电通道3057导通连接，从而产生较大的读电流Iread，其对应表示编程凸块305与铁电薄膜层303之间的畴壁导电通道3054为Off态(即关态)，读出逻辑信息“0”。
需要理解的是，在第二电极3073和第三电极4075之间偏置如图16(b)的虚线示意的读信号Vread时，同样地可以读出逻辑信息“0”。
进一步需要说明的是，在读出电流信号Iread后，电极3071和第三电极4075之间偏置读信号Vread撤去，电场E7消失，此时，在去极化场的作用下，电畴3053b会受电畴3051a影响而反转为大致原来的极化方向，也即电畴3053b瞬间消失，基本恢复到读操作之前的状态的电畴3051，畴壁导电通道3057也基本消失，但是不会对畴壁导电通道3054产生影响。因此，铁电存储器40在读操作之前所存储的逻辑信息“0”在读操作后并没有发生变化，实现了非破坏性读取。
同时，还需要理解的是，在其他实施例中，即使可能存在电场E7消失而电畴3053b并没有反转回读操作前的极化方向，也即畴壁导电通道3057在读信号撤去后始终存在，由于读信号Vread的方向是相对固定的，电畴3053b不会影响铁电存储器40存储的逻辑信息，并且畴壁导电通道3057的存在也不会影响其后读出的逻辑信息。并且，可以理解到，其该读操作过程后进行写操作时，电畴3053b肯定会被重新极化，畴壁导电通道3057也会被擦除。
继续如图16(b)所示，在该实施例中，具有电畴3053b的编程 凸块部分相对具有电畴3051a的编程凸块部分的体积越小越好，也即在读过程中发生局部反转的电畴(例如电畴3053b)的编程凸块部分的体积占比越小越好，通过设计编程凸块305的高度、面积参数、读电压和/或第一电极3071与第三电极3075之间的间隙的间距d，可以优化该铁电存储器40的读操作性能。可选地，第一电极3071与第三电极3075之间的间隙的间距d小于编程凸块305的高度。
以上图15和图16中使用的读信号Vread的方向可以发生变化，同样也可以区别地读出其中存储的数据状态“1”和“0”。并且，写信号Vwrite1、Vwrite0和Vread具体信号形式不是限制性的，例如，其可以为一定频率的电压脉冲信号等。
在以上描述中，使用方向性术语(例如“上”、“下”等)以及类似术语描述的各种实施方式的部件表示附图中示出的方向或者能被本领域技术人员理解的方向。这些方向性术语用于相对的描述和澄清，而不是要将任何实施例的定向限定到具体的方向或定向。
以上例子主要说明了本发明的铁电存储器及其操作方法和制备方法，尤其说明了读操作方法及原理。尽管只对其中一些本发明的实施方式进行了描述，但是本领域普通技术人员应当了解，本发明可以在不偏离其主旨与范围内以许多其他的形式实施，例如，第一电极3071和第二电极3073的形状变化、编程凸块305的3D形状变化等。因此，所展示的例子与实施方式被视为示意性的而非限制性的，在不脱离如所附各权利要求所定义的本发明精神及范围的情况下，本发明可能涵盖各种的修改与替换。

Claims (37)

  1. 一种非破坏性读出铁电存储器，包括铁电薄膜层和设置在所述铁电薄膜层之上的第一电极层，其中，所述第一电极层包括分离设置的第一电极和第二电极，所述铁电薄膜层中的电畴的极化方向基本不平行所述铁电薄膜层的法线方向；在所述第一电极和第二电极之间施加电信号时使能所述铁电薄膜层中的局部电畴反转，从而能够建立连接所述第一电极和第二电极的第一畴壁导电通道；
    其中，所述铁电薄膜层为铁电单晶薄膜层。
  2. 如权利要求1所述的非破坏性读出铁电存储器，其中，所述铁电单晶薄膜层为单晶的铌酸锂型铁电体，或者为单晶的锆钛酸铅盐(Pb，Zr)TiO3、掺La的铁酸铋盐(Bi，La)FeO3、铁酸铋BiFeO3、Bi4Ti3O12、(La，Bi)4Ti3O12、或SrBi2Ta2O9。
  3. 如权利要求2所述的非破坏性读出铁电存储器，其中，所述铌酸锂型铁电体为铌酸锂LiNbO3、或钽酸锂LiTaO3。
  4. 如权利要求1或2所述的非破坏性读出铁电存储器，其中，所述铁电单晶薄膜层为掺杂的铁电单晶薄膜层，其中掺杂材料为MgO、FeO或Ta2O5，或者MgO、FeO与Ta2O5的任意组合。
  5. 如权利要求4所述的非破坏性读出铁电存储器，其中，所述掺杂材料的摩尔掺杂百分比为0.1％至10％。
  6. 如权利要求4所述的非破坏性读出铁电存储器，其中，所述铁电单晶薄膜层为0.1％至10％摩尔掺杂MgO的单晶铌酸锂LiNbO3。
  7. 如权利要求6所述的非破坏性读出铁电存储器，其中，所述单晶铌酸锂LiNbO3中Li与Nb的化学计量比接近或等于1∶1。
  8. 如权利要求1所述的非破坏性读出铁电存储器，其中，铁电单晶薄膜层通过对铁电单晶体进行X向切割或XYZ向切割或XZ(YZ)向切割形成。
  9. 如权利要求8所述的非破坏性读出铁电存储器，其中，所述铁电单晶薄膜层键合于硅基底之上。
  10. 如权利要求1所述的非破坏性读出铁电存储器，其中，所述铁电单晶薄膜层中设置相对外凸的编程凸块，所述第一电极和第二电 极设置在所述编程凸块的两侧并至少被所述编程凸块分隔开；
    其中，在所述第一电极和第二电极之间施加第一方向的写信号时使能至少部分所述编程凸块中的电畴反转，从而建立所述第一畴壁导电通道。
  11. 如权利要求10所述的非破坏性读出铁电存储器，其中，在所述第一电极和第二电极之间施加与所述第一方向相反的第二方向的写信号时使能所述编程凸块中的反转的电畴反转回到初始极化方向，从而使所述第一畴壁导电通道消失。
  12. 如权利要求11所述的非破坏性读出铁电存储器，其中，在所述第一电极和第二电极之间施加读信号以判断所述第一畴壁导电通道是否建立，在所述第一畴壁导电通道建立时表示存储第一逻辑状态，在所述第一畴壁导电通道消失时表示存储第二逻辑状态。
  13. 如权利要求12所述的非破坏性读出铁电存储器，其中，所述读信号的电压小于所述铁电单晶薄膜层的矫顽电压。
  14. 如权利要求1所述的非破坏性读出铁电存储器，其中，设置所述铁电单晶薄膜层的厚度大于所述编程凸块的高度。
  15. 如权利要求1所述的非破坏性读出铁电存储器，其中，所述编程凸块的宽度对应为所述第一电极和第二电极之间的间隙的间距，其大于或等于2纳米且小于或等于10微米。
  16. 如权利要求14所述的非破坏性读出铁电存储器，其中，所述编程凸块的高度大于或等于2纳米且小于或等于1微米。
  17. 如权利要求14所述的非破坏性读出铁电存储器，其中，所述第一电极层的厚度大于或等于所述编程凸块的高度。
  18. 如权利要求10所述的非破坏性读出铁电存储器，其中，所述第一电极层还包括设置在所述编程凸块之上的第三电极，所述第三电极相对所述第一电极和第二电极分离地设置，从而在所述第一电极与所述第三电极之间形成第一间隙，所述第二电极与所述第三电极之间形成第二间隙。
  19. 如权利要求18所述的非破坏性读出铁电存储器，其中，在所述第一电极/第二电极与第三电极之间施加读信号时使能对应所述第一间隙/第二间隙的部分所述编程凸块的电畴局部被反转，从而能够建立连接所述第一电极/第二电极与第三电极的第二畴壁导电通道。
  20. 如权利要求19所述的非破坏性读出铁电存储器，其中，在所述第二畴壁导电通道建立时对应读出的电流状态表示读出第一逻辑状态，在所述第二畴壁导电通道未建立时对应读出的电流状态表示读出第二逻辑状态。
  21. 如权利要求19所述的非破坏性读出铁电存储器，其中，在所述读信号取消时，所述编程凸块的局部被反转的电畴被反转回到原来的极化方向，从而所述第二畴壁导电通道消失。
  22. 如权利要求19所述的非破坏性读出铁电存储器，其中，所述第一间隙/第二间隙小于所述编程凸块的高度。
  23. 一种如权利要求1所述的非破坏性读出铁电存储器的制备方法，其中，包括步骤：
    提供基底；
    形成铁电单晶薄膜层；以及
    在所述铁电单晶薄膜层上形成包括分离设置的第一电极和第二电极的第一电极层。
  24. 如权利要求23所述的制备方法，其中，所述铁电单晶薄膜层为单晶的铌酸锂型铁电体，或者为单晶的锆钛酸铅盐(Pb，Zr)TiO3、掺La的铁酸铋盐(Bi，La)FeO3、铁酸铋BiFeO3、Bi4Ti3O12、(La，Bi)4Ti3O12、或SrBi2Ta2O9。
  25. 如权利要求24所述的制备方法，其中，所述铌酸锂型铁电体为铌酸锂LiNbO3、或钽酸锂LiTaO3。
  26. 如权利要求23或24所述的制备方法，其中，所述铁电单晶薄膜层为掺杂的铁电单晶薄膜层，其中掺杂材料为MgO、FeO或Ta2O5，或者MgO、FeO与Ta2O5的任意组合。
  27. 如权利要求26所述的制备方法，其中，所述掺杂材料的摩尔掺杂百分比为0.1％至10％。
  28. 如权利要求26所述的制备方法，其中，所述铁电单晶薄膜层为0.1％至10％摩尔掺杂MgO的单晶铌酸锂LiNbO3。
  29. 如权利要求28所述的制备方法，其中，所述单晶铌酸锂LiNbO3中Li与Nb的化学计量比接近或等于1∶1。
  30. 如权利要求23所述的制备方法，其中，形成铁电单晶薄膜层的步骤包括：
    形成铁电单晶体；
    对所述铁电单晶体进行X向切割或XYZ向切割或XZ(YZ)向切割形成铁电单晶薄膜；以及
    将所述铁电单晶薄膜置于所述基底上形成所述铁电单晶薄膜层。
  31. 如权利要求23所述的制备方法，其特征在于，形成所述铁电单晶薄膜层包括：
    对铁电单晶薄膜层构图刻蚀形成编程凸块，其中所述第一电极和第二电极设置在所述编程凸块的两侧并至少被所述编程凸块分隔开。
  32. 如权利要求31所述的制备方法，其中，在形成第一电极层的步骤中，对用于形成第一电极层的金属层构图刻蚀形成所述第一电极和第二电极。
  33. 如权利要求31所述的制备方法，其中，如权利要求30所述的制备方法，其特征在于，在形成第一电极层的步骤中，对用于形成第一电极层的金属层构图刻蚀形成第一电极、第二电极和第三电极，其中所述第三电极设置在所述编程凸块之上。
  34. 一种如权利要求10所述的非破坏性读出铁电存储器的操作方法，其中，
    在写数据“1”时，在所述第一电极和第二电极之间施加第一方向的写信号，使能至少部分所述编程凸块中的电畴反转，从而建立所述第一畴壁导电通道；
    在写数据“0”时，在所述第一电极和第二电极之间施加与所述第一方向相反的第二方向的写信号，使能所述编程凸块中已反转的电畴反转回到初始极化方向，从而使所述第一畴壁导电通道消失。
  35. 如权利要求34所述的操作方法，其中，
    在读数据“1”或“0”时，在所述第一电极和第二电极之间施加读信号以判断所述第一畴壁导电通道是否建立，在所述第一畴壁导电通道建立时读出的电流大小表示读出数据“1”，在所述第一畴壁导电通道消失时读出的电流大小表示读出数据“0”。
  36. 如权利要求34所述的操作方法，其中，所述第一电极层还包括设置在所述编程凸块之上的第三电极，所述第三电极相对所述第一电极和第二电极分离地设置，从而在所述第一电极与所述第三电极之间形成第一间隙，所述第二电极与所述第三电极之间形成第二间隙；
    在读数据“1”或“0”时，在所述第一电极/第二电极与第三电极之间施加读信号以判断所述第二畴壁导电通道是否建立，在所述第二畴壁导电通道建立时读出的电流大小表示读出数据“0”，在所述第一畴壁导电通道消失时读出的电流大小表示读出数据“1”。
  37. 如权利要求36所述的操作方法，其中，在写数据“1”或“0”时，所述第三电极接地或者偏置电压以降低所述写信号的电压大小。
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