WO2017176309A1 - Codes polaires pour transmissions harq - Google Patents

Codes polaires pour transmissions harq Download PDF

Info

Publication number
WO2017176309A1
WO2017176309A1 PCT/US2016/053026 US2016053026W WO2017176309A1 WO 2017176309 A1 WO2017176309 A1 WO 2017176309A1 US 2016053026 W US2016053026 W US 2016053026W WO 2017176309 A1 WO2017176309 A1 WO 2017176309A1
Authority
WO
WIPO (PCT)
Prior art keywords
bits
codeword
llrs
polar
internal
Prior art date
Application number
PCT/US2016/053026
Other languages
English (en)
Inventor
Wook Bong Lee
Eren SASOGLU
Shilpa Talwar
Ajit Nimbalker
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to CN202210307415.8A priority Critical patent/CN114679242B/zh
Priority to CN201680083369.0A priority patent/CN108886438B/zh
Priority to TW106106964A priority patent/TWI717473B/zh
Publication of WO2017176309A1 publication Critical patent/WO2017176309A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/618—Shortening and extension of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]
    • H04L1/1819—Hybrid protocols; Hybrid automatic repeat request [HARQ] with retransmission of additional or different redundancy
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1829—Arrangements specially adapted for the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1867—Arrangements specially adapted for the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]
    • H04L1/1816—Hybrid protocols; Hybrid automatic repeat request [HARQ] with retransmission of the same, encoded, message
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1829—Arrangements specially adapted for the receiver end
    • H04L1/1835—Buffer management
    • H04L1/1845—Combining techniques, e.g. code combining

Definitions

  • the present disclosure relates to polar code design including support for hybrid automatic repeat request (HARQ) transmissions.
  • HARQ hybrid automatic repeat request
  • the present disclosure relates to polar encoding and decoding for HARQ transmissions.
  • FIG. 1 is a system diagram illustrating a polar coding chain according to one embodiment.
  • FIG. 2 is a block diagram illustrating rate matching and interleaving according to one embodiment.
  • FIG. 3 is a diagram illustrating performance of different parameter setups depending on HARQ scheme according to one embodiment.
  • FIG. 4 is a diagram illustrating polar encoding circuitry according to one embodiment.
  • FIG. 5 is a block diagram illustrating a receive processing chain according to one embodiment.
  • FIG. 6 is a diagram illustrating polar decoding circuitry according to one embodiment.
  • FIG. 7 is a diagram illustrating nodes in a polar decoding circuitry according to one embodiment.
  • FIG. 8 is a block diagram illustrating electronic device circuitry that may be eNodeB circuitry, user equipment (UE) circuitry, network node circuitry, or some other type of circuitry according to one embodiment.
  • UE user equipment
  • FIG. 9 is a block diagram illustrating a method for performing polar encoding according to one embodiment.
  • FIG. 10 is a block diagram illustrating a method for performing polar encoding according to one embodiment.
  • FIG. 1 1 is a block diagram illustrating a method for a polar decoder according to one embodiment.
  • FIG. 12 is a block diagram illustrating components of a device according to one embodiment.
  • FIG. 13 is a block diagram illustrating components according to some embodiments.
  • Wireless mobile communication technology uses various standards and protocols to generate and/or transmit data between a base station and a wireless communication device.
  • Wireless communication system standards and protocols can include, for example, 3rd Generation Partnership Project (3GPP) long term evolution (LTE); the Institute of Electrical and Electronics Engineers (IEEE) 802.16 standard, which is commonly known to industry groups as worldwide interoperability for microwave access (WiMAX); and the IEEE 802.1 1 standard, which is commonly known to industry groups as Wireless Local Area Network (WLAN) or Wi-Fi.
  • 3GPP 3rd Generation Partnership Project
  • LTE long term evolution
  • IEEE 802.16 which is commonly known to industry groups as worldwide interoperability for microwave access
  • WiMAX Wireless Local Area Network
  • Wi-Fi Wireless Local Area Network
  • a base station may include Evolved Universal Terrestrial Radio Access Network (E-UTRAN) Node B (also commonly denoted as evolved Node B, enhanced Node B, eNodeB, or eNB) and/or Radio Network Controllers (RNCs) in the E-UTRAN, which communicate with a wireless communication device, known as user equipment (UE).
  • E-UTRAN Evolved Universal Terrestrial Radio Access Network
  • Node B also commonly denoted as evolved Node B, enhanced Node B, eNodeB, or eNB
  • RNCs Radio Network Controllers
  • the E-UTRAN may include a plurality of eNodeBs and may communicate with the plurality of UEs.
  • LTE networks include a radio access technology (RAT) and core radio network architecture that can provide high data rate, low latency, packet optimization, and improved system capacity and coverage.
  • RAT radio access technology
  • Polar codes are a class of error-correction codes that achieve the capacity of memoryless communication channels. Some examples described herein reference binary polar codes, although non-binary polar codes can also be employed using the examples descried herein.
  • the codeword can comprise a vector of binary bits. N denotes the length of a vector.
  • the vector of binary bits and the codeword can each comprise N binary bits.
  • the codeword can be transm itted through a communication channel such as a physical uplink shared channel (PUSCH) and/or a physical downlink shared channel (PDSCH), among other examples of a communication channel, t/ can be provided to an encoder to encode.
  • PUSCH physical uplink shared channel
  • PDSCH physical downlink shared channel
  • Various coding rates can be achieved by setting the desired number of encoder inputs U t to data bits (e.g. , information bits) and freezing the remaining bit values to predeterm ined values (e.g. , zeros) and encoding the result to form an output codeword.
  • a coding rate can be defined as the ratio of the number of data bits that are input to the encoder to the number of codeword bits output by the encoder. For example, to obtain a rate of a half code, half of the Ui bits can be set to data bits (e.g. , information bits) and the remaining half of the Ui bits can be frozen to their predeterm ined values (e. g. zeros).
  • the choice of which bit indices to freeze, what values to freeze to, and which bits to use for data can be fixed before transmission and can be known at both the transm itter and the receiver.
  • the receiver e.g. , user equipment (UE)
  • the UE can request additional transm issions of the data packet.
  • the transm itter e.g. , evolved node B (eNodeB)
  • eNodeB evolved node B
  • This may be in the form of a repetition of the same codeword (or a part of it) via a Chase combining transm ission of a HARQ transm ission and/or fresh information about the original data often in the form of additional parity bits via an incremental redundancy I R transm ission of a HARQ transm ission (HARQ-IR), or a combination thereof.
  • HARQ-IR incremental redundancy I R transm ission of a HARQ transm ission
  • retransm issions may take place (e.g. , until the receiver UE can correctly decode the data packet).
  • the transmitter can repeat the same packet or transport block in a second transmission. Based on the encoding (e.g. , redundancy version, allocated modulation, and coding schemes, etc.), the parity bits selected for the second transmission may or may not be identical to that transmitted in the first transmission.
  • each code bit X t can be sent through independent realizations of a channel W.
  • each code bit X t can pass through a different type of channel. The qualities of these different types of channels can vary widely.
  • a polar coding chain can be implemented for HARQ transm ission that address coding for high order modulation, robust performance under varying channel conditions, support Chase combining HARQ transm issions and HARQ-IR transm issions, and/or rate matching that provides flexible polar codeword length.
  • FIG. 1 is a system diagram illustrating a polar coding chain according to one embodiment.
  • FIG. 1 includes a polar coding chain 100 comprising a shortened polar encoder module 1 10, a rate matching and channel interleaver (RM&CI) module 1 12, a modulation module 1 14, a channel 1 16, a demodulation module 1 18, a derate matching and channel interleaver (D-MR&CI) module 120, and a shortened polar decoder module 122.
  • the shortened polar encoder module 1 10, the RM&CI 1 12 module 1 12, and the modulation module 1 14 can including a coding scheme that can be performed by a UE and/or an eNodeB.
  • the demodulation module 1 18, the D- MR&CI module 120, and the shortened polar decoder module 122 can include a decomding scheme that can also be performed by the UE and/or the eNodeB.
  • N is a base code output length of 2".
  • 102 is a number of information bits.
  • S is a number of shortened bits.
  • P is a number of punctured bits.
  • E is a number of extension and/or repeated bits.
  • Ns is a number of spatial streams.
  • M is a number of bits per modulation.
  • N B c 104 (e.g., also referred to as N-S 104) is a base codeword length after shortened polar encoder equal to N-S.
  • N C B 106 (e.g., also referred to as N-S-P+E 106) is a codeword length after rate matching and channel interleaving (e.g., RM&CI module 1 12) equal to N-S-P+E.
  • a number of log-likelihood ratios (LLRs) associated with the K 102 are represented by k 103.
  • a number of LLRs associated with S are represented by s.
  • a number of LLRs associated with P are represented by p.
  • a number of LLRs associated with E are represented by e.
  • An LLR associated with M is represented by m.
  • a number of LLRs associated with N-S 104 is represented by n-s 105.
  • a number of LLRs associated with N-S-P+E 106 is represented by n-s-p+e 107.
  • a number of LLRs associated with a (N-S-P+E)/( N S * M) 108 is represented by (n-s- p+e)/( n s * m) 109.
  • K 102, N, S, P, E, N S , and M can refer to a plurality of bits and/or a quantity of bits
  • k 103, n, s, p, e, n s , and m can refer to a plurality of received bits, LLRs, and/or a quantity of LLRs.
  • the 102 can be a bit- vector comprising 512 bits.
  • the 102 can refer to both the bits in the bit-vector and/or the quantity of bits (e.g., bit-vector length) such as 512 bits.
  • the N-S 104 can refer to both the bit-vector resulting from removing the bit-vector S from the bit-vector N and the quantity of bits (e.g., bit-vector length) in a result bit-vector from removing the bit-vector S from the bit-vector N.
  • the K 102 can be provided to the shortened polar encoder 1 10 to produce the N-S 104.
  • the N-S 104 is provided to the RM&CI module 1 12 to produce the N-S-P+E 106.
  • the N-S-P+E 106 is provided to the modulation module 1 14 to produce a (N-S-P+E)/( N S * M) 108.
  • the (N-S-P+E)/( N S * M) 108 is provided to the channel 1 16 for transmission.
  • the channel 1 16 can provide the (n-s-p+e)/(n s * m) 109 to a demodulation module 1 18 go generate the n-s-p+e 107.
  • the n-d-p+r 107 can be provided to the D-RM&CI module 120 to generate the n-d 104.
  • the n-d 104 is provided to the shortened polar decoder module 122 to generate the k 102.
  • the shortened polar encoder module 1 10, the RM&CI module 1 12, the modulation module 1 14, and/or the channel 1 16 can be provided as part of a transmitting (e.g., eNodeB).
  • the channel 1 16, the demodulation module 1 18, the D-RM&CI module 120, and/or the shortened polar decoder module 122 can be provided as part of a receiver (e.g., UE).
  • SNR signal-to-noise ratio
  • Constructions for base codeword length N BC (e.g. , N-S 104), other than powers of 2, are obtained by the shortening procedure with a minimal loss in performance.
  • the shortening length S can be chosen in conjunction with the puncturing and extension parameters.
  • the polar coding chain can be used in conjunction with any modulation scheme such as QAM, multiple antenna mapping, resource mapping, OFDM, and/or single carrier modulation, for example.
  • the receiver performs the reverse operations of the transmitter.
  • the LLR values are calculated at the demodulator module 1 18.
  • the LLR values for extended bits are added together. Punctured bit LLRs are set to zero, and the whole LLR block is then de- interleaved via the D-RM&CI module 120.
  • the LLR block N-S 104 is then decoded via the shortened polar decoder module 122. Any polar decoding schemes can be utilized in the shortened polar decoder module 122.
  • FIG. 2 is a block diagram illustrating rate matching and interleaving according to one embodiment.
  • FIG. 2 includes an RM&CI module 212 comprising an interleaving module 230 and a rate-matching module 232.
  • An N-S 204-1 can be provided to the interleaving module 230 to generate an N-S 204-2.
  • the N-S 204-2 can be provided to the rate-matching module 232 to generate an N-S-P+E 206.
  • Code shortening is followed by the interleaving module 230 in the RM&CI module 212.
  • the RM&CI module 212 can configure the codeword such that each bit in the codeword statistically suffers the same amount of noise. That is, the RM&CI module 212 can configure the codeword such that each bit in the codeword is equally protected.
  • the RM&CI module 212 can be analogous to a bit-interleaver in a bit interleaved coded modulation (BICM) or a sub-block interleaver in LTE rate matching.
  • BICM bit interleaved coded modulation
  • the proposed embodiments avoid constructing different polar codes for every possible channel variation pattern. For example, channel gains at different subcarriers can be different in a frequency selective fading channel in orthogonal frequency division multiplexing (OFDM)/orthogonal frequency division multiple access (OFDMA) systems. Different bits have different bit channel qualities for most high order modulation methods, such as 16
  • Code puncturing can also cause a time varying channel, where punctured code bits have zero reliability at the receiver.
  • the interleaving module 230 can be optimized for shortening, puncturing, extension, and/or fading patterns. Since shortening, puncturing, and/or extension patterns may be optimized based on the channel's fading or time-variation patterns, the number of optimizations can be very large and/or the optimization may be intractable. As such, a single interleaving module 230 as part of the RM&CI module 212 is used in the embodiments described herein.
  • the interleaving module 230 can be a random interleaver.
  • Existing interleaving rules e.g. , the sub-block interleaver and/or the turbo code internal interleaver
  • LTE/LTE-A systems can be utilized in LTE/LTE-A systems.
  • Rate matching starts with a choice of shortening length for the base code output length (mother polar code).
  • the rate-matching module 232 completes the rate matching procedure by puncturing and/or extending the shortened and interleaved codeword N-S 204-2.
  • the shortening, puncturing, and/or extension lengths are chosen jointly to match the dictated code rate and HARQ requirements.
  • Puncturing a bit refers to removing a bit from a bit-vector. Extending the code refers to resending certain code bits.
  • N, S, P, and/or E are positive integers. If P > 0, then the last P bits of the shortened and interleaved base codeword can be punctured.
  • the last bit can refer to the bit associated with the greatest index of a bit-vector such as the codeword.
  • the last P bits refers to the P bits associated with the greatest indexes of the codeword. If E > 0, then the first E bits can be extended (e.g. , repeated).
  • the first bit of the codeword is a bit associated with a first index of the codeword bit-vector.
  • the first E bits refers to first E bits from the codeword bit-vector. If the (c 0 , c-i , C/v-s-i ) bit-vector represents the shortened and interleaved base codeword (e.g.
  • the output of the rate-matching module 232 can be the (c 0 , c-i , . . . , C/V-S-P-I , c 0 , c-i , c E-1 ) bit-vector (e.g. , N-S-P+E 206).
  • the N-S-P+E 206 can then be provided via a circular buffer for HARQ-IR transmission.
  • N, S, P, and/or E can be selected.
  • N 2 i log2 WcB l
  • the first example with shortening alone may be used for aiming an initial transmission.
  • no bits are punctured or extended.
  • Subsequent transmissions of the first example include a simple repetition of the first transmission.
  • a HARQ transmission can be performed using chase combining.
  • the first example can be selected for Chase combining HARQ
  • the second example can be selected for HARQ-IR transmissions.
  • the second example may perform worse than the first example for initial
  • the second example may perform better than the first example for subsequent HARQ transmissions as shown in FIG. 3.
  • the selecting S, P, and/or E may depend on the HARQ scheme used to transmit the codeword. Some of these values may be predetermined for a given transport block size and HARQ version, or may be explicitly signaled in a control channel such as a physical downlink control channel (PDCCH).
  • PDCH physical downlink control channel
  • FIG. 3 is a diagram illustrating the performance of different parameter setups depending of HARQ scheme according to one embodiment.
  • FIG. 3 includes the graph 336 comprising a block error rate (BLER) axis 338 and an SNR 340.
  • BLER block error rate
  • the graph 336 shows that an initial transmission 342 of the first example, described with relation to FIG. 2, performs better than an initial transmission 344 of the second example. Performance can be judged based on the BLER. As such, the initial transmission 342 can have a lower BLER than the initial transmission 344.
  • the graph 336 also shows that the second transmission 346 of the second example performs better than the second transmission 348 of the first example.
  • FIG. 4 is a diagram illustrating polar encoding circuitry 410 according to one embodiment.
  • the polar encoding circuitry 410 can correspond to the shortened polar encoder 1 10 in FIG. 1 .
  • the polar encoding circuitry 410 shows an A bit-vector 450 which corresponds to the 102 in FIG. 1 .
  • the polar encoding circuitry 410 also shows a D bit-vector 456 which corresponds to the N-S 104 in FIG. 1 .
  • the polar encoding circuitry 410 further shows a B bit-vector 452 and a C bit-vector 454.
  • the A bit-vector 450 can be an input bit-vector and the D bit-vector 456 can be a result bit-vector.
  • the B bit-vector 452 and the C bit-vector 454 are internal bit-vectors.
  • the A bit-vector 450 comprises the bits (a 0 , . . . , 7 ).
  • the B bit-vector 452 comprises the bits (b 0 , . . . , b 7 ).
  • the C bit-vector 454 comprises the bits
  • the D bit-vector 456 comprises the bits (d 0 , . . . , d 7 ).
  • the A bit-vector 450 can include the original data bits (e.g. , the K 1 02 in FIG. 1 ) and frozen bits that are input to the polar encoding circuitry 41 0.
  • the D bit-vector 456 comprises codeword bits (d 0 , . . . , d 7 ) that are output by the polar encoding circuitry 410.
  • the B bit-vector 452 e.g. , (b Q , . . . , b 7 )
  • the C bit-vector 454 e.g. , (c 0 , . . . , c 7 )
  • the transmitter e.g. , eNodeB
  • the transmitter can generate and/or transmit a subset of the 32 bits in each retransmission.
  • the transmitter can select different subsets based on different system requirements and/or capabilities.
  • the stage corresponding to generating the B bit-vector 452 and/or the C bit-vector 454 is referred to as an intermediate stage or a stage associated with internal bits.
  • the stage corresponding to the D bit-vector 456 is referred to as a stage associated with a conventional codeword of a polar coding.
  • the transmitter can generate, provide, and/or transmit a subset of the D bit-vector 456 in each transmission and retransmission to generate, provide, and/or transmit a chase combining HARQ transmission.
  • Retransmissions can include internal bits (e.g. , subsets of the B bit-vector 452 and/or the C bit-vector 454) that do not necessarily appear in the typical polar codeword.
  • generating and/or transmitting internal bits can include generating and/or transmitting a fresh set of parity bits.
  • a number of examples can support HARQ transmissions by utilizing bits that are typically internal to the polar encoding circuitry 410 and that do not typically appear in the original codeword.
  • the selected subset of bits can include a mixture of the typical codeword bits and internal bits. For example, this corresponds to a mixture of chase/IR scheme.
  • An example of this is to send (b 0 , . . . , b 7 ) in retransmission.
  • the unique bits may be placed in a circular buffer.
  • the buffer can be unrolled as
  • bits can be placed in the circular buffer in any other order.
  • the transmitter can send the next bits in the buffer.
  • the next bits can comprise as many bits in the buffer as required.
  • the buffer can wrap around to the beginning upon arriving at the last bit in the buffer.
  • the encoding can be systematic or partially systematic. That is, the information block bits or some of the information block bits can appear in the buffer.
  • the polar encoding circuitry 410 can comprise a plurality of nodes wherein a plurality of operations are performed.
  • the polar encoding circuitry 410 can comprise check nodes 460 and variable nodes 462.
  • the check nodes 460 are shown in FIG. 4 as circles with a plus sign inside the circles.
  • the check nodes 460 can perform an operation such as an exclusive OR (XOR) operation.
  • Each of the check nodes 460 can receive two bits as input and can generate an output by applying the operation on both the bits. For example, a check node in line with bit a 0 can receive as input the a 0 bit and the ai bit. The check node can generate the b 0 node.
  • a check node in line with the a 2 bit can receive the a 2 bit and the a 3 bit to generate the b 2 bit.
  • a check node in line with the a 0 bit and the bo bit can receive the b 0 bit and the b 2 bit to generate the c 0 bit, among other examples of check nodes 460.
  • the bits that are generated by the check nodes 460 are unique bits.
  • variable nodes 462 are shown as dots in the polar encoding circuitry 410.
  • the variable nodes 462 can perform a copy operation.
  • the variable node in line with the ai bit can copy the ai bit to generate the bi bit.
  • the ai bit is equal to the bi bit. That is, neither the ai bit nor the bi bit is unique.
  • the bits generated by the variable nodes 462 are non- unique bits.
  • FIG. 5 is a block diagram illustrating a receive processing chain 500 according to one embodiment.
  • the receive processing chain 500 includes decoder module 522, HARQ memory module 560, soft-combining module 562, and LLR initializer for internal bits module 564.
  • the receive processing chain 500 also includes channel LLRs.
  • the decoder module 522, the HARQ memory module 560, the soft-combining module 562, and/or the LLR initializer for internal bits module 564 can be analogous to the shortened polar decoder 122 in FIG. 1 .
  • the receive processing chain 500 can be implemented as part of a receiver (e.g., UE).
  • the channel LLRs module 568 can provide LLRs corresponding to bits provided by a channel.
  • the channel LLRs module 568 can generate the LLRs and/or can provide LLRs generated by the channel.
  • the LLRs correspond to the current transmission of the packet.
  • the soft-combining module 562 combines the LLRs of the current packet provided by the channel LLRs module 568 and LLRs of previous transmissions of the packet stored in the HARQ memory module 560.
  • the soft combining module 562 outputs both types of LLRs. That is, the soft combining module 562 generates and/or initializes the LLRs for internal bits via the LLR initializer for internal bits module 564.
  • the LLRs for internal bits are input to the decoder module 522 separately (e.g., logically) from the LLRs corresponding to the codeword LLRs such that the decoder module 522 can use the internal bit LLRs for initializing step in the decoding (e.g., list decoding, successive cancellation decoding, etc.).
  • FIG. 6 is a diagram illustrating polar decoding circuitry 622 according to one embodiment.
  • the polar decoding circuitry 622 can be part of a decoder 522 in FIG. 5.
  • the polar decoding circuitry 622 can include a D vector 656, a C vector 654, a B vector 652, and an A vector 650.
  • the polar decoding circuitry 622 can also include the check nodes 650 and the variable nodes 662.
  • the polar decoding circuitry 622 can also include dangling edges 670.
  • Polar decoders can be augment by incorporating information from (re)transmissions as shown by the dangling edges 670.
  • the polar decoder can be any message passing algorithm; for example, a successive cancellation decoder, a list decoder, and/or a belief propagation.
  • the augmentation including the dangling edges 670 can be incorporated into any polar decoder.
  • each edge can hold a message (e.g. , a list of messages, for example in the case of list decoding) in the form of LLRs.
  • Edges are shown in the polar decoder circuitry 622 both as edges that are connected at both ends to nodes, and as dangling edges that are connected to a node only at one end..
  • the vectors 650, 652, 654, and 656 represent bits and/or messages.
  • the messages can include the LLRs and/or the bits provided by the channel.
  • the messages associated with vectors 650, 652, 654, and 656 correspond to the A bit-vector 450, the B bit-vector 452, the C bit-vector 456, and the D bit-vector 458 in FIG. 4, respectively.
  • the augmented retransmission comprises sending parity bits that are typically internal to the original encoder in addition to the polar codeword. To use the parity bits (e.g.
  • variable nodes 662 with additional dangling edges 670 corresponding to strictly internal bit positions are incorporated into the decoder circuitry 622.
  • the unique bits can include, for example, a bit c 0 in FIG. 4 which can correspond to the c 0 message in FIG. 6 and a corresponding dangling edge coupled to the decoder circuitry 622 via a variable node 662.
  • Utilizing the dangling edges 670 associated with the unique bits can include initializing the LLRs and/or the messages associated with the dangling edges 670. That is, a decoder comprising decoder circuitry 622 can be initialized with the LLRs of the received bits. For example, if a 0 was frozen to zero in FIG. 4, then the a 0 message comprising an associated LLR can be initialized to infinity, or a very large number in schemes associating positive LLR to binary 0-bits and negative LLR to binary 1 -bits. In some examples, frozen bits on the edges of the decoder circuitry and/or the encoder circuitry can result in frozen internal bits.
  • bits from the encoder can be selected for transmission can exclude frozen bits given that the values for frozen bits are already known and can be recreated at the decoder with certainty.
  • its dangling edge LLR can be initialized to the sum of received LLRs for that bit and to zero if it was never transmitted.
  • the LLR for a dangling edge 670 corresponding to an internal bit on a third transmission can be initialized to the sum of a corresponding received LLR for that bit during a first transmission, a second transmission, and a third transmission,.
  • the LLRs can be utilized to determine whether the bit-vector received from a channel is the bit-vector provided to the channel.
  • FIG. 7 is a diagram illustrating nodes in a polar decoding circuitry according to one embodiment.
  • FIG. 7 includes nodes 772-1 and 772-2 shown in four different examples.
  • FIG. 7 also includes messages 780-1 and 780-2 and messages 784.
  • the message 780-1 can be provided from the node 772-2 to the node 772-1 .
  • the message 780-2 can also be provided from the node 772-1 to the node 772-2.
  • the message 780-1 can be provided from the node 772-2 to the node 772-1 through the node 772-3.
  • the message 780-2 can be provided from the node 772-1 to the node 772-2 through the node 772-3.
  • variable nodes e.g. , nodes 773
  • dangling edges corresponding to internal bits can allow to augment any existing message passing schedule in a decoder.
  • the edges in FIG. 7 represent horizontal edges in FIG. 6.
  • the nodes 772-1 and 772-2 e.g. , nodes X and Y
  • the augmented decoder can include added variable node 772-3 between the nodes 772-1 and 772-2 and the corresponding dangling edge with an associated message 784 (e.g. , message l XY ).
  • each visit to the node 772-1 that generates the message 780-2 e.g.
  • message m XY is followed by a visit to the newly introduced node 772-3, which computes l XY + m YX and writes the result to the node 772-2.
  • message 780-1 e.g. , message m YX
  • a visit to the newly introduced node 772-3 which computes l XY + m YX and writes the result to the node 772-1 .
  • a redundancy version indicator may be used to indicate which bits of the buffer are transmitted in a given transmission for a data packet.
  • the redundancy version may be explicitly indicated in the control information associated with the information block (or a transport block) or may be implicitly tied to a known parameter such as a subframe number or a transmission number.
  • the redundancy version indicator can be equal to one for the first transmission and/or two for the second transmission, etc. ).
  • the transmission number can be used in self-decodable transmissions.
  • FIG. 8 is a block diagram illustrating electronic device circuitry that may be eNodeB circuitry, user equipment (UE) circuitry, network node circuitry, or some other type of circuitry according to one embodiment.
  • FIG. 8 illustrates an electronic device 800 that may be, or may be incorporated into or otherwise part of, an eNodeB, a UE, or some other type of electronic device in accordance with various embodiments.
  • the electronic device 800 may be logic and/or circuitry that may be at least partially implemented in one or more of hardware, software, and/or firmware.
  • the electronic device logic may include radio transmit/transmitter logic (e.g., a first transmitter logic 877) and receive/receiver logic (e.g., a first receiver logic 883) coupled to a control logic 873 and/or a processor 871 .
  • the transmit/transmitter and/or receive/receiver logic may be elements or modules of transceiver logic.
  • the first transmitter logic 877 and the first receiver logic 883 may be housed in separate devices.
  • the first transmitter logic 877 can be incorporated into a first device while the first receiver logic 883 is incorporated into a second device, or the first transmitter logic 877 and the first receiver logic 883 can be incorporated into a device separate from a device including any combination of the control logic 873, a memory 879, and/or the processor 871 .
  • the electronic device 800 may be coupled with or include one or more antenna elements 885 of one or more antennas.
  • the electronic device 800 and/or the components of the electronic device 800 may be configured to perform operations similar to those described elsewhere in this disclosure.
  • the electronic device 800 can generate and/or transmit polar codes.
  • the processor 871 may be coupled to the first receiver and first transmitter.
  • the memory 879 may be coupled to the processor 871 having control logic instructions thereon that, when executed, generate and/or transmit polar codes.
  • the processor 871 may be coupled to a receiver and a transmitter.
  • the memory 879 may be coupled to the processor 871 having the control logic
  • logic may refer to, be part of, or include an application specific integrated circuit (ASIC), an electronic circuit, the processor 871 (shared, dedicated, or group), and/or the memory 879 (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide ASIC.
  • ASIC application specific integrated circuit
  • the processor 871 shared, dedicated, or group
  • the memory 879 shared, dedicated, or group
  • the logic may be at least partially
  • FIG. 9 is a block diagram illustrating a method 985 for performing polar encoding according to one embodiment.
  • the method 985 includes selecting 903 a length S of a number of shortened bits and a length P of a number of punctured bits based on a HARQ scheme, encoding 905 the plurality of information bits via a polar encoder module to generate a base code, with a length of N, minus the number of shortened bits, interleaving 907, via an interleaver module, a result of the polar encoder module to generate a codeword which includes the base code minus the shortened bits minus the number of punctured bits plus a number of extension bits with a length of E, providing 909 the codeword to a modulation module to generate a division of the codeword by a result of a multiplication of a number of spatial streams by a number of bits per modulation, and providing 91 1 a result of the division to a channel to transmit a polar code to a receiving device.
  • the HARQ scheme can include a chase combining transmission and/or a HARQ-IR transmission.
  • the method 985 further comprises setting N to
  • the method 985 also comprises setting S to N-N C B and P to zero.
  • the method 985 can further comprise setting S to zero and P to N-N C B-
  • the method 985 can further comprise setting N to 2 A (floor(log2(N C B)), wherein N C B is a length of the codeword and E to N C B-N.
  • the method 985 can also comprise setting S to zero and P to zero.
  • FIG. 10 is a block diagram illustrating a method 1087 for performing polar encoding according to one embodiment.
  • the method 1087 comprises generating 1021 at least a plurality of B internal bits by performing a plurality of operations on the A data bits, generating 1023 a plurality of D codeword bits by performing a plurality of operations on the B internal bits, wherein the D codeword bits correspond to a first stage of a polar encoder, and the B internal bits correspond to a second stage of the polar encoder and wherein the first stage and second stage are distinct stages of the polar encoder, and providing 1025 a subset of the A data bits, the D codeword bits, and the B internal bits to a channel for a transmission.
  • the HARQ transmission can be at least one of a chase combining HARQ transmission and a HARQ-IR transmission.
  • the A data bits can comprise data bits and frozen bits.
  • the length of the A data bits, the length of the B internal bits, and the length of the D codeword bits can be the same length.
  • the method 1087 further comprises generating a subsequent HARQ transmission comprising a subset of the A data bits, the B internal bits, and the D codeword bits.
  • the HARQ transmission can include a circular buffer of the subset of the A data bits, the B internal bits, and the D codeword bits.
  • the subset of the A data bits, the B internal bits, and the D codeword bits can include at least one of the D codeword bits and the B internal bits, the D codeword bits and a portion of the B internal bits, the B internal bits and a portion of the D codeword bits, or the B internal bits.
  • FIG. 1 1 is a block diagram illustrating a method 1 189 for a polar decoder according to one embodiment.
  • the method 1 189 comprises initializing 1 131 a first plurality of LLRs for a plurality of bits received from a channel associated with a HARQ transmission, initializing 1 133 a second plurality of LLRs for a plurality of dangling edges associated with the plurality of bits, performing 1 135 a plurality of operations on a first plurality of messages and a second plurality of messages to generate a third plurality of LLRs, where the first plurality of messages comprise the first plurality of LLRs and the second plurality of messages comprise the second plurality of LLRs, and determining 1 137 an estimate of an information block comprising the first plurality of bits and the second plurality of bits based on the third LLRs.
  • the plurality of operations comprise addition
  • Each of the plurality of operations can also comprise a minimum operation to determine a minimum LLR of an absolute value of a first LLR and an absolute value of a second LLR, a multiplication operation to determine a sign by multiplying a sign of the first LLR and a sign of the second LLR, and providing the minimum LLR with the sign.
  • the method 1 189 also comprises initializing LLRs from the first plurality of LLRs and the second plurality of LLRs associated with frozen bits from the first plurality of bits and the second plurality of bits to a predefined value, initializing LLRs from the first plurality of LLRs and the second plurality of LLRs associated with non- frozen bits from the first plurality of bits and the second plurality of bits to a sum of received LLRs that are associated with a bit, and initializing LLRs from the first plurality of LLRs and the second plurality of LLRs to zeros for bits that were not received.
  • the estimate of information block can comprise which codeword was transmitted through the channel.
  • the second plurality of bits can be associated with internal bits of a polar code.
  • FIG. 12 is a block diagram illustrating components of a device according to one embodiment.
  • the device may include application circuitry 1203, baseband circuitry 1205, Radio Frequency (RF) circuitry 1207, front- end module (FEM) circuitry 1209, and one or more antennas 1214, coupled together at least as shown in FIG. 12. Any combination or subset of these components can be included, for example, in a UE device or an eNodeB device.
  • RF Radio Frequency
  • FEM front- end module
  • the application circuitry 1203 may include one or more application processors.
  • the application circuitry 1203 may include one or more single-core or multi-core processors.
  • the processor(s) may include any combination of general-purpose processors and dedicated processors (e.g., graphics processors, application processors, etc.).
  • the processor(s) may be operably coupled and/or include memory/storage, and may be configured to execute instructions stored in the memory/storage to enable various applications
  • the baseband circuitry 1205 may include one or more single-core or multi-core processors.
  • the baseband circuitry 1205 may include one or more baseband processors and/or control logic.
  • the baseband circuitry 1205 may be configured to process baseband signals received from a receive signal path of the RF circuitry 1207.
  • the baseband circuitry 1205 may also be configured to generate baseband signals for a transmit signal path of the RF circuitry 1207.
  • the baseband circuitry 1205 may interface with the application circuitry 1203 for generation and processing of the baseband signals, and for controlling operations of the RF circuitry 1207.
  • the baseband circuitry 1205 may include at least one of a second generation (2G) baseband processor 121 1 A, a third generation (3G) baseband processor 121 1 B, a fourth generation (4G) baseband processor 121 1 C, and other baseband processor(s) 121 1 D for other existing generations and generations in development or to be developed in the future (e.g., fifth generation (5G), sixth generation (6G), etc.).
  • the baseband circuitry 1205 (e.g., at least one of the baseband processors 121 1 A-121 1 D) may handle various radio control functions that enable communication with one or more radio networks via the
  • the radio control functions may include signal modulation/demodulation, encoding/decoding, radio
  • modulation/demodulation circuitry of the baseband circuitry 1205 may be programmed to perform Fast-Fourier Transform (FFT), precoding, and
  • encoding/decoding circuitry of the baseband circuitry 1205 may be programmed to perform convolutions, tail-biting convolutions, turbo, Viterbi, Low Density Parity Check (LDPC) encoder/decoder functions, other functions, and combinations thereof.
  • LDPC Low Density Parity Check
  • modulation/demodulation and encoder/decoder functions are not limited to these examples, and may include other suitable functions.
  • the baseband circuitry 1205 may include elements of a protocol stack.
  • elements of an evolved universal terrestrial radio access network (E-UTRAN) protocol include, for example, physical (PHY), media access control (MAC), radio link control (RLC), packet data convergence protocol (PDCP), and/or radio resource control (RRC) elements.
  • a central processing unit (CPU) 121 1 E of the baseband circuitry 1205 may be programmed to run elements of the protocol stack for signaling of the PHY, MAC, RLC, PDCP and/or RRC layers.
  • the baseband circuitry 1205 may include one or more audio digital signal processor(s) (DSP) 121 1 F.
  • the audio DSP(s) 121 1 F may include elements for compression/decompression and echo cancellation.
  • the audio DSP(s) 121 1 F may also include other suitable processing elements.
  • the baseband circuitry 1205 may further include a memory/storage
  • the memory/storage 121 1 G may include data and/or instructions for operations performed by the processors of the baseband circuitry 1205 stored thereon.
  • the memory/storage 121 1 G may include any combination of suitable volatile memory and/or non-volatile memory.
  • memory/storage 121 1 G may also include any combination of various levels of memory/storage including, but not limited to, read-only memory (ROM) having embedded software instructions (e.g., firmware), random access memory (e.g., dynamic random access memory (DRAM)), caches, buffers, etc.
  • ROM read-only memory
  • DRAM dynamic random access memory
  • the memory/storage 121 1 G may be shared among the various processors or dedicated to particular processors.
  • Components of the baseband circuitry 1205 may be suitably combined in a single chip or a single chipset, or disposed on a same circuit board in some embodiments. In some embodiments, some or all of the constituent components of the baseband circuitry 1205 and the application circuitry 1203 may be
  • SOC system on a chip
  • the baseband circuitry 1205 may provide for communication compatible with one or more radio technologies.
  • the baseband circuitry 1205 may support communication with an evolved universal terrestrial radio access network (E-UTRAN) and/or other wireless metropolitan area networks (WMAN), a wireless local area network (WLAN), or a wireless personal area network (WPAN).
  • E-UTRAN evolved universal terrestrial radio access network
  • WMAN wireless metropolitan area networks
  • WLAN wireless local area network
  • WPAN wireless personal area network
  • multi-mode baseband circuitry Embodiments in which the baseband circuitry 1205 is configured to support radio communications of more than one wireless protocol.
  • the RF circuitry 1207 may enable communication with wireless networks using modulated electromagnetic radiation through a non-solid medium.
  • the RF circuitry 1207 may include switches, filters, amplifiers, etc., to facilitate the communication with the wireless network.
  • the RF circuitry 1207 may include a receive signal path, which may include circuitry to down-convert RF signals received from the FEM circuitry 1209, and provide baseband signals to the
  • the RF circuitry 1207 may also include a transmit signal path, which may include circuitry to up-convert baseband signals provided by the baseband circuitry 1205, and provide RF output signals to the FEM circuitry 1209 for transmission.
  • the RF circuitry 1207 may include a receive signal path and a transmit signal path.
  • the receive signal path of the RF circuitry 1207 may include a mixer circuitry 1213A, an amplifier circuitry 1213B, and a filter circuitry
  • the transmit signal path of the RF circuitry 1207 may include the filter circuitry 1213C and the mixer circuitry 1213A.
  • the RF circuitry 1207 may further include a synthesizer circuitry 1213D configured to synthesize a frequency for use by the mixer circuitry 1213A of the receive signal path and the transmit signal path.
  • the mixer circuitry 1213A of the receive signal path may be configured to down-convert RF signals received from the FEM circuitry 1209 based on the synthesized frequency provided by the synthesizer circuitry 1213D.
  • the amplifier circuitry 1213B may be configured to amplify the down-converted signals.
  • the filter circuitry 1213C may include a low-pass filter (LPF) or band-pass filter (BPF) configured to remove unwanted signals from the down-converted signals to generate output baseband signals.
  • LPF low-pass filter
  • BPF band-pass filter
  • Output baseband signals may be provided to the baseband circuitry 1205 for further processing.
  • the output baseband signals may include zero-frequency baseband signals, although this is not a requirement.
  • the mixer circuitry 1213A of the receive signal path may comprise passive mixers, although the scope of the embodiments is not limited in this respect.
  • the mixer circuitry 1213A of the transmit signal path may be configured to up-convert input baseband signals based on the synthesized frequency provided by the synthesizer circuitry 1213D to generate RF output signals for the FEM circuitry 1209.
  • the baseband signals may be provided by the baseband circuitry 1205 and may be filtered by the filter circuitry 1213C.
  • the filter circuitry 1213C may include a low-pass filter (LPF), although the scope of the embodiments is not limited in this respect.
  • the mixer circuitry 1213A of the receive signal path and the mixer circuitry 1213A of the transmit signal path may include two or more mixers, and may be arranged for quadrature downconversion and/or upconversion, respectively.
  • the mixer circuitry 1213A of the receive signal path and the mixer circuitry 1213A of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection).
  • the mixer circuitry 1213A of the receive signal path and the mixer circuitry 1213A of the transmit signal path may be arranged for direct downconversion and/or direct upconversion, respectively.
  • the mixer circuitry 1213A of the receive signal path and the mixer circuitry 1213A of the transmit signal path may be configured for super-heterodyne operation.
  • the output baseband signals and the input baseband signals may be analog baseband signals, although the scope of the embodiments is not limited in this respect.
  • the output baseband signals and the input baseband signals may be digital baseband signals.
  • the RF circuitry 1207 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry
  • the baseband circuitry 1205 may include a digital baseband interface to communicate with the RF circuitry 1207.
  • ADC analog-to-digital converter
  • DAC digital-to-analog converter
  • separate radio interference cancellation (IC) circuitry may be provided for processing signals for each spectrum, although the scope of the embodiments is not limited in this respect.
  • the synthesizer circuitry 1213D may include one or more of a fractional-N synthesizer and a fractional N/N+1 synthesizer, although the scope of the embodiments is not limited in this respect, as other types of frequency synthesizers may be suitable.
  • the synthesizer circuitry 1213D may include a delta-sigma synthesizer, a frequency multiplier, a synthesizer comprising a phase-locked loop with a frequency divider, other synthesizers, and combinations thereof.
  • the synthesizer circuitry 1213D may be configured to synthesize an output frequency for use by the mixer circuitry 1213A of the RF circuitry 1207 based on a frequency input and a divider control input.
  • the synthesizer circuitry 1213D may be a fractional N/N+1 synthesizer.
  • frequency input may be provided by a voltage controlled oscillator (VCO), although that is not a requirement.
  • VCO voltage controlled oscillator
  • Divider control input may be provided by either the baseband circuitry 1205 or the application circuitry 1203 depending on the desired output frequency.
  • a divider control input (e.g., N) may be determined from a look-up table based on a channel indicated by the application circuitry 1203.
  • the synthesizer circuitry 1213D of the RF circuitry 1207 may include a divider, a delay-locked loop (DLL), a multiplexer, and a phase accumulator.
  • the divider may include a dual modulus divider (DMD)
  • the phase accumulator may include a digital phase accumulator (DPA).
  • the DMD may be configured to divide the input signal by either N or N+1 (e.g., based on a carry-out) to provide a fractional division ratio.
  • the DLL may include a set of cascaded, tunable, delay elements; a phase detector; a charge pump; and a D-type flip-flop.
  • the delay elements may be configured to break a VCO period up into Nd equal packets of phase, where Nd is the number of delay elements in the delay line.
  • the DLL may provide negative feedback to help ensure that the total delay through the delay line is one VCO cycle.
  • the synthesizer circuitry 1213D may be configured to generate a carrier frequency as the output frequency.
  • the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency, etc.) and used in conjunction with a quadrature generator and divider circuitry to generate multiple signals at the carrier frequency with multiple different phases with respect to each other.
  • the output frequency may be an LO frequency (fLO).
  • the RF circuitry 1207 may include an IQ/polar converter.
  • the FEM circuitry 1209 may include a receive signal path, which may include circuitry configured to operate on RF signals received from the one or more antennas 1214, amplify the received signals, and provide the amplified versions of the received signals to the RF circuitry 1207 for further processing.
  • the FEM circuitry 1209 may also include a transmit signal path, which may include circuitry configured to amplify signals for transmission provided by the RF circuitry 1207 for transmission by at least one of the one or more antennas 1214.
  • the FEM circuitry 1209 may include a TX/RX switch configured to switch between a transmit mode and a receive mode operation.
  • the FEM circuitry 1209 may include a receive signal path and a transmit signal path.
  • the receive signal path of the FEM circuitry 1209 may include a low-noise amplifier (LNA) to amplify received RF signals and provide the amplified received RF signals as an output (e.g., to the RF circuitry 1207).
  • LNA low-noise amplifier
  • the transmit signal path of the FEM circuitry 1209 may include a power amplifier (PA) configured to amplify input RF signals (e.g., provided by the RF circuitry 1207), and one or more filters configured to generate RF signals for subsequent transmission (e.g., by the one or more antennas 1214).
  • PA power amplifier
  • the device may include additional elements such as, for example, memory/storage, a display, a camera, one of more sensors, an input/output (I/O) interface, other elements, and combinations thereof.
  • additional elements such as, for example, memory/storage, a display, a camera, one of more sensors, an input/output (I/O) interface, other elements, and combinations thereof.
  • the device may be configured to perform one or more processes, techniques, and/or methods as described herein, or portions thereof.
  • FIG. 13 is a block diagram illustrating components according to some embodiments. Specifically, FIG. 13 shows a diagrammatic representation of hardware resources 1300 including one or more processors (or processor cores)
  • the processors 1310 may include, for example, a processor 1312 and a processor 1314.
  • the memory/storage devices 1320 may include main memory, disk storage, or any suitable combination thereof.
  • the communication resources 1330 may include interconnection and/or network interface components or other suitable devices to communicate with one or more peripheral devices 1304 and/or one or more databases 131 1 via a network 1308.
  • the communication resources 1330 may include wired
  • USB Universal Serial Bus
  • cellular communication components e.g., for coupling via a Universal Serial Bus (USB)
  • NFC Near Field Communication
  • Bluetooth® components e.g., Bluetooth® Low Energy
  • Wi-Fi® components and other communication components.
  • Instructions 1350 may comprise software, a program, an application, an applet, an app, or other executable code for causing at least one of the processors 1310 to perform any one or more of the methodologies discussed herein.
  • the instructions 1350 may reside, completely or partially, within at least one of the processors 1310 (e.g., within the processor's cache memory), the memory/storage devices 1320, or any suitable combination thereof.
  • any portion of the instructions 1350 may be transferred to the hardware resources 1300 from any combination of the peripheral devices 1304 and/or the databases 131 1 .
  • the memory of the processors 1310, the memory/storage devices 1320, the peripheral devices 1304, and the databases 131 1 are examples of computer- readable and machine-readable media.
  • Example 1 is an apparatus for performing polar encoding.
  • the apparatus includes electronic memory to store a variety of data bits for use in a first stage of a polar encoder distinct from a second stage of the polar encoder.
  • the apparatus includes one or more baseband processing units designed to generate at least a variety of internal bits in the first stage of the polar encoder by performing a variety of operations on the data bits, where the internal bits are internal to the polar encoder.
  • the apparatus includes one or more baseband processing units designed to generate a variety of codeword bits in the second stage of the polar encoder by performing a variety of operations on the internal bits, where the codeword bits correspond to the second stage of a polar encoder, and the internal bits correspond to the first stage of the polar encoder.
  • the apparatus includes one or more baseband processing units designed for a hybrid automatic repeat request (HARQ) transmission, provide a subset of the data bits, the codeword bits, and the internal bits to a channel of a physical layer.
  • HARQ hybrid automatic repeat
  • Example 2 is the apparatus of Example 1 , where the apparatus is a user equipment (UE) and where the channel is at least one of an uplink channel and a sidelink channel.
  • UE user equipment
  • Example 3 is the apparatus of Example 1 , where the apparatus is an evolved user node (eNodeB) and where the channel is at least one of a downlink channel.
  • eNodeB evolved user node
  • Example 4 is the apparatus of Example 1 , where the transmission is at least one of a Chase combining HARQ transmission and a HARQ incremental redundancy (HARQ-IR) transmission.
  • HARQ-IR HARQ incremental redundancy
  • Example 5 is the apparatus of Example 1 , where the data bits for use in the first stage of the polar encoder include bits set to a predetermined value.
  • Example 6 is the apparatus of Example 1 , where a length of the data bits, a length of the internal bits, and a length of the codeword bits are a same length.
  • Example 7 is the apparatus of Example 1 , where the one or more processing units are further designed to generate a subsequent HARQ transmission including a subsequent subset of the data bits, the internal bits, and the codeword bits that are different than the subset of the data bits, the internal bits, and the codeword bits.
  • Example 8 is the apparatus of Example 1 , where the HARQ transmission includes a circular buffer of the subset of the data bits, the internal bits, and the codeword bits.
  • Example 9 is the apparatus of Example 1 , where the subset of the data bits, the internal bits, and the codeword bits includes one of the codeword bits and the internal bits, the codeword bits and a portion of the internal bits, the internal bits and a portion of the codeword bits; and the internal bits.
  • Example 10 is a computer-readable storage medium. The computer- readable storage medium having stored thereon instructions that, when implemented by a computing device, cause the computing device to initialize a first variety of log- likelihood ratios (LLRs) for a variety of bits generated by a polar encoder and received from a channel of a physical layer associated with a hybrid automatic repeat request (HARQ) transmission.
  • LLC log- likelihood ratios
  • the computer-readable storage medium having stored thereon instructions that, when implemented by a computing device, cause the computing device to initialize a second variety of LLRs for a variety of dangling edges, associated with the variety of bits, of a polar decoder.
  • the computer-readable storage medium having stored thereon instructions that, when implemented by a computing device, cause the computing device to perform a variety of operations on the first variety of LLRs and the second variety of LLRs to generate a third variety of LLRs.
  • the computer-readable storage medium having stored thereon instructions that, when implemented by a computing device, cause the computing device to determine an estimate of an information block including a first variety of bits and a second variety of bits including data bits based on the third variety of LLRs.
  • Example 1 1 is the computer-readable storage medium of Example 10, where a user equipment (UE) or an evolved node B (eNodeB) includes the computer-readable storage medium.
  • UE user equipment
  • eNodeB evolved node B
  • Example 12 is the computer-readable storage medium of Example 10, where the variety of operations include addition operations.
  • Example 13 is the computer-readable storage medium of Example 10, where each of the variety of operations include a minimum operation to determine a minimum LLR of an absolute value of a first LLR and an absolute value of a second
  • Example 14 is the computer-readable storage medium of Example 10, where the instructions designed to initialize the first variety of LLRs and initialize the second variety of LLRs further include instructions to initialize LLRs from the first variety of LLRs and the second variety of LLRs associated with frozen bits from the first variety of bits and the second variety of bits to a predefined value.
  • Example 10 where the instructions designed to initialize the first variety of LLRs and initialize the second variety of LLRs further include instructions to initialize each of the first variety of LLRs and the second variety of LLRs associated with non-frozen bits from the variety of bits to a sum of received LLRs of a corresponding one of the non-frozen bits, and initialize LLRs from the first variety of LLRs and the second variety of LLRs to zeros for bits that were not received.
  • Example 15 is the computer-readable storage medium of Example 10, where the estimate of information block includes which codeword was transmitted through the channel.
  • Example 16 is the computer-readable storage medium of Example 10, where zero or more of the variety of bits are associated with internal bits of a polar encode.
  • Example 17 is an apparatus for performing polar encoding.
  • the apparatus includes electronic memory to store a variety of information bits, to be encoded by a polar encoder module, with a length K.
  • the apparatus includes one or more processing units designed to select a length S of a number of shortened bits and a length P of a number of punctured bits based on a hybrid automatic repeat request (HARQ) scheme and encode the variety of information bits via the polar encoder module to generate a base codeword, with a length of N, minus the number of shortened bits.
  • HARQ hybrid automatic repeat request
  • the apparatus includes one or more processing units designed to interleave, via a interleaver module, a result of the polar encoder module to generate a codeword which includes the base codeword minus the shortened bits minus the number of punctured bits plus a number of extension bits with a length of E.
  • the apparatus includes one or more processing units designed to provide the codeword to a modulation module to generate a division of the codeword by a result of a multiplication of a number of spatial streams by a number of bits per modulation, and provide a result of the division to a channel of a physical layer to transmit a polar code to a receiving device.
  • Example 18 is the apparatus of Example 17, where the apparatus is one of a user equipment (UE) or an evolved node B (eNodeB).
  • UE user equipment
  • eNodeB evolved node B
  • Example 19 is the apparatus of Example 17, where the HARQ scheme includes a chase combining transmission.
  • Example 20 is the apparatus of Example 17, where the HARQ scheme includes a HARQ incremental redundancy (HARQ-IR) transmission.
  • Example 21 is the apparatus of Example 17, where the one or more processing units are further designed to set N to 2 A (ceil(log2(N C B)), where N C B is a length of the codeword, and E to zero.
  • Example 22 is the apparatus of Example 17, where the one or more processing units are further designed to set S to N-N C B, and P to zero.
  • Example 23 is the apparatus of Example 17, where the one or more processing units are further designed to set S to zero, and P to N-N C B-
  • Example 24 is the apparatus of Example 17, where the one or more processing units are further designed to set N to 2 A (floor(log2(N C B)), where N C B is a length of the codeword, and E to N C B-N.
  • Example 25 is the apparatus of Example 17, where the one or more processing units are further designed to set S to zero, and P to zero.
  • Example 26 is a method including generating at least a variety of internal bits in a first stage of the polar encoder by performing a variety of operations on a variety of data bits for use in the first stage of a polar encoder distinct from a second stage of the polar encoder, where the internal bits are internal to the polar encoder.
  • the method also includes generating a variety of codeword bits in the second stage of the polar encoder by performing a variety of operations on the internal bits, where the codeword bits correspond to the second stage of a polar encoder, and the internal bits correspond to the first stage of the polar encoder.
  • the method also includes for a hybrid automatic repeat request (HARQ) transmission, providing a subset of the data bits, the codeword bits, and the internal bits to a channel of a physical layer.
  • HARQ hybrid automatic repeat request
  • Example 27 is the method of Example 26, where providing includes providing, by an apparatus of a user equipment (UE), the subset of the data bits, the codeword bits, and the internal bits to the channel of a physical layer and where the channel is at least one of an uplink channel and a sidelink channel.
  • UE user equipment
  • Example 28 is the method of Example 26, where providing includes providing, by an apparatus of an evolved user node (eNodeB), the subset of the data bits, the codeword bits, and the internal bits to the channel of a physical layer and where the channel is at least one of a downlink channel.
  • eNodeB evolved user node
  • Example 29 is the method of Example 26, where the HARQ transmission is at least one of a Chase combining HARQ transmission and a HARQ incremental redundancy (HARQ-IR) transmission.
  • Example 30 is the method of Example 26, where the data bits for use in the first stage of the polar encoder include bits set to a predetermined value.
  • Example 31 is the method of Example 26, where a length of the data bits, a length of the internal bits, and a length of the codeword bits are a same length.
  • Example 32 is the method of Example 26, further including generating a subsequent HARQ transmission including a subsequent subset of the data bits, the internal bits, and the codeword bits that are different than the subset of the data bits, the internal bits, and the codeword bits.
  • Example 33 is the method of Example 26, where the HARQ transmission includes a circular buffer of the subset of the data bits, the internal bits, and the codeword bits.
  • Example 34 is the method of Example 26, where the subset of the data bits, the internal bits, and the codeword bits includes one of the codeword bits and the internal bits, the codeword bits and a portion of the internal bits, the internal bits and a portion of the codeword bits, and the internal bits.
  • Example 35 is a method which includes initializing a first variety of log- likelihood ratios (LLRs) for a variety of bits generated by a polar encoder and received from a channel of a physical layer associated with a hybrid automatic repeat request (HARQ) transmission.
  • the method also includes initializing a second variety of LLRs for a variety of dangling edges, associated with the variety of bits, of a polar decoder.
  • the methods also includes performing a variety of operations on the first variety of LLRs and the second variety of LLRs to generate a third variety of LLRs.
  • the methods also includes determining an estimate of an information block including a first variety of bits and a second variety of bits including data bits based on the third variety of LLRs.
  • Example 36 is the method of Example 35, where the initializing of the variety of LLRs, the initializing the second variety of LLRs, the performing the variety of operations, and the determining an estimate of the information block, are performed by a user equipment (UE) or an evolved node B (eNodeB).
  • UE user equipment
  • eNodeB evolved node B
  • Example 37 is the method of Example 35, where the variety of operations include addition operations.
  • Example 38 is the method of Example 35, where each of the variety of operations includes a minimum operation to determine a minimum LLR of an absolute value of a first LLR and an absolute value of a second LLR.
  • the variety of operations includes a multiplication operation to determine a sign by multiplying a sign of the first LLR and a sign of the second LLR, and providing the minimum LLR with the sign.
  • Example 39 is the method of Example 35, where initializing the first variety of LLRs and initializing the second variety of LLRs further includes initializing LLRs from the first variety of LLRs and the second variety of LLRs associated with frozen bits from the first variety of bits and the second variety of bits to a predefined value. Initializing the first variety of LLRs and initializing the second variety of LLRs further includes initializing each of the first variety of LLRs and the second variety of LLRs associated with non-frozen bits from the variety of bits to a sum of received LLRs of a corresponding one of the non-frozen bits, and initializing LLRs from the first variety of LLRs and the second variety of LLRs to zeros for bits that were not received.
  • Example 40 is the method of Example 35, where the estimate of information block includes which codeword was transmitted through the channel.
  • Example 41 is the method of Example 35, where zero or more of the variety of bits are associated with internal bits of a polar encode.
  • Example 42 is a method.
  • the method includes electronic memory to store a variety of information bits, to be encoded by a polar encoder module, with a length K.
  • the method also includes one or more processing units designed to selecting a length S of a number of shortened bits and a length P of a number of punctured bits based on a hybrid automatic repeat request (HARQ) scheme.
  • the method also includes one or more processing units designed to encoding a variety of information bits with a length K via the polar encoder module to generate a base codeword, with a length of N, minus the number of shortened bits.
  • HARQ hybrid automatic repeat request
  • the method also includes one or more processing units designed to interleaving, via a interleaver module, a result of the polar encoder module to generate a codeword which includes the base codeword minus the shortened bits minus the number of punctured bits plus a number of extension bits with a length of E.
  • the method also includes one or more processing units designed to providing the codeword to a modulation module to generate a division of the codeword by a result of a multiplication of a number of spatial streams by a number of bits per modulation, and providing a result of the division to a channel of a physical layer to transmit a polar code to a receiving device.
  • Example 43 is the method of Example 42, where the HARQ scheme includes a chase combining transmission.
  • Example 44 is the method of Example 42, where the HARQ scheme includes a HARQ incremental redundancy (HARQ-IR) transmission.
  • HARQ-IR HARQ incremental redundancy
  • Example 45 is the method of Example 42, further including setting N to
  • N C B is a length of the codeword, and E to zero.
  • Example 46 is the method of Example 42, further including setting S to N-
  • Example 47 is the method of Example 42, further including setting S to zero, and P to N-N C B-
  • Example 48 is the method of Example 42, further including setting N to 2 A (floor(log2(N C B)), where N C B is a length of the codeword, and E to N C B-N .
  • Example 49 is the method of Example 42, further including setting S to zero, and P to zero.
  • Example 50 is at least one computer-readable storage medium having stored thereon computer-readable instructions, when executed, to implement a method as exemplified in any of Examples 26-44.
  • Example 51 is an apparatus including means to perform a method as exemplified in any of Examples 26-44.
  • Example 52 is a means for performing a method as exemplified in any of Examples 26-44.
  • Various techniques, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, a non-transitory computer-readable storage medium, or any other machine-readable storage medium wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the various techniques.
  • the computing device may include a processor, a storage medium readable by the processor (including volatile and nonvolatile memory and/or storage elements), at least one input device, and at least one output device.
  • the volatile and non-volatile memory and/or storage elements may be a RAM, an EPROM, a flash drive, an optical drive, a magnetic hard drive, or another medium for storing electronic data.
  • the eNodeB (or other base station) and UE (or other mobile station) may also include a transceiver component, a counter component, a processing component, and/or a clock component or timer component.
  • One or more programs that may implement or utilize the various techniques described herein may use an application programming interface (API), reusable controls, and the like. Such programs may be implemented in a high-level procedural or an object-oriented programming language to communicate with a computer system. However, the program(s) may be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or an interpreted language, and combined with hardware implementations.
  • API application programming interface
  • a component may be implemented as a hardware circuit comprising custom very large scale integration (VLSI) circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components.
  • VLSI very large scale integration
  • a component may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like.
  • Components may also be implemented in software for execution by various types of processors.
  • An identified component of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions, which may, for instance, be organized as an object, a procedure, or a function.
  • executables of an identified component need not be physically located together, but may comprise disparate instructions stored in different locations that, when joined logically together, comprise the component and achieve the stated purpose for the component.
  • a component of executable code may be a single instruction, or many instructions, and may even be distributed over several different code
  • operational data may be identified and illustrated herein within components, and may be embodied in any suitable form and organized within any suitable type of data structure.
  • the operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices, and may exist, at least partially, merely as electronic signals on a system or network.
  • the components may be passive or active, including agents operable to perform desired functions.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

La présente invention concerne la réalisation d'un codage polaire. La réalisation d'un codage polaire peut consister à sélectionner une longueur S d'un nombre de bits raccourcis et une longueur P d'un nombre de bits poinçonnés sur la base d'un schéma HARQ, coder la pluralité de bits d'information pour générer un code de base, entrelacer un résultat du module de codeur polaire raccourci pour générer un mot de code qui comprend le code de base moins les bits raccourcis moins le nombre de bits poinçonnés plus un nombre de bits d'extension d'une longueur de E, et fournir le mot de code à un module de modulation pour générer une division du mot de code par un résultat d'une multiplication d'un nombre de flux spatiaux par un nombre de bits par modulation et fournir un résultat de la division à un canal pour transmettre un code polaire à un dispositif de réception.
PCT/US2016/053026 2016-04-08 2016-09-22 Codes polaires pour transmissions harq WO2017176309A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202210307415.8A CN114679242B (zh) 2016-04-08 2016-09-22 用于harq传输的极化码
CN201680083369.0A CN108886438B (zh) 2016-04-08 2016-09-22 用于harq传输的极化码
TW106106964A TWI717473B (zh) 2016-04-08 2017-03-03 用於混合式自動重送請求(harq)之傳輸的極化碼

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662320094P 2016-04-08 2016-04-08
US62/320,094 2016-04-08
US201662334772P 2016-05-11 2016-05-11
US62/334,772 2016-05-11

Publications (1)

Publication Number Publication Date
WO2017176309A1 true WO2017176309A1 (fr) 2017-10-12

Family

ID=57043037

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2016/053026 WO2017176309A1 (fr) 2016-04-08 2016-09-22 Codes polaires pour transmissions harq

Country Status (3)

Country Link
CN (2) CN108886438B (fr)
TW (1) TWI717473B (fr)
WO (1) WO2017176309A1 (fr)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019093855A1 (fr) * 2017-11-13 2019-05-16 엘지전자 주식회사 Procédé de codage sur la base d'un code polaire afin de prendre en charge une harq, et dispositif sans fil l'utilisant
WO2019128707A1 (fr) * 2017-12-26 2019-07-04 华为技术有限公司 Procédé et dispositif de codage par code polaire et d'adaptation de débit
WO2019190258A1 (fr) * 2018-03-30 2019-10-03 엘지전자 주식회사 Procédé de réalisation d'une communication en liaison latérale selon un code polaire et dispositif à cet effet
WO2020061684A1 (fr) * 2018-09-28 2020-04-02 Huawei Technologies Co., Ltd. Procédé et appareil pour communiquer sans fil sur un canal bruyant avec un code polaire de longueur de mot de code variable pour améliorer la capacité de transmission
CN111357221A (zh) * 2017-11-20 2020-06-30 高通股份有限公司 用于超可靠低延时通信的极化码的混合自动重传请求设计的技术和装置
CN111431675A (zh) * 2019-01-10 2020-07-17 华为技术有限公司 数据传输方法及装置
CN112313895A (zh) * 2018-06-25 2021-02-02 高通股份有限公司 超可靠的低延迟通信(urllc)的混合极化码设计
CN112425103A (zh) * 2018-04-30 2021-02-26 波拉兰哈伯雷斯姆技术公司 使用系统极化编码重传数据的方法和系统
US11050519B2 (en) * 2018-09-14 2021-06-29 Idac Holdings, Inc. Methods, apparatus, systems and procedures for hybrid automatic repeat requests (HARQs) using polar codes
US11070317B2 (en) 2017-03-22 2021-07-20 Idac Holdings, Inc. Sub-block wise interleaving for polar coding systems, procedures, and signaling
CN114095038A (zh) * 2021-10-12 2022-02-25 上海交通大学 编解码器及生成码字的方法和系统
US11418294B2 (en) 2019-09-20 2022-08-16 Qualcomm Incorporated Single step in-place operation method for 5G NR de-interleaving, de-rate matching, and HARQ combination
US11528040B2 (en) 2017-11-02 2022-12-13 Huawei Technologies Co., Ltd. Data retransmission method and apparatus to obtain information to be transmitted and to perform Polar encoding on the information
WO2023282366A1 (fr) * 2021-07-05 2023-01-12 엘지전자 주식회사 Procédé de transmission de signal basé sur une harq dans un système de communication sans fil et appareil associé
WO2024165143A1 (fr) * 2023-02-07 2024-08-15 Vestel Elektronik Sanayi ve Ticaret A. S. Demande de répétition automatique hybride avec versions de redondance pré-configurées
KR102725958B1 (ko) * 2017-11-20 2024-11-04 퀄컴 인코포레이티드 초-신뢰성 저 레이턴시 통신들을 위한 폴라 코드들의 하이브리드 자동 반복 요청 설계를 위한 기법들 및 장치들

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11121806B2 (en) * 2018-09-07 2021-09-14 Qualcomm Incorporated Decoding performance
JP7398476B2 (ja) * 2019-03-29 2023-12-14 中興通訊股▲ふん▼有限公司 Ｐｏｌａｒ符号に基づいてデータを送信するための方法、装置、およびシステム
CN112152754B (zh) 2019-06-28 2021-12-28 华为技术有限公司 一种极化码重传方法及装置
CN111865491B (zh) * 2020-06-15 2021-09-21 北京邮电大学 一种极化编码混合自动请求重传自解码方法、装置及系统

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015026148A1 (fr) * 2013-08-20 2015-02-26 엘지전자 주식회사 Procédé de transmission de données à l'aide d'un codage polaire dans un système d'accès sans fil

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100703287B1 (ko) * 2005-07-20 2007-04-03 삼성전자주식회사 통신 시스템에서 자원 할당 정보 송수신 시스템 및 방법
US8006163B2 (en) * 2006-12-27 2011-08-23 Nec Laboratories America, Inc. Polarization mode dispersion compensation using BCJR equalizer and iterative LDPC decoding
CN102164025B (zh) * 2011-04-15 2013-06-05 北京邮电大学 基于重复编码和信道极化的编码器及其编译码方法
CN102122966B (zh) * 2011-04-15 2012-11-14 北京邮电大学 基于信道极化的交错结构重复码的编码器及其编译码方法
KR101919934B1 (ko) * 2012-04-19 2018-11-20 삼성전자주식회사 불휘발성 메모리 장치를 제어하는 컨트롤러의 동작 방법 및 극 부호화된 부호어를 불휘발성 메모리 장치의 멀티 비트 데이터에 매핑하는 매핑 패턴을 선택하는 매핑 패턴 선택 방법
CN103281166B (zh) * 2013-05-15 2016-05-25 北京邮电大学 一种基于极化码的混合自动重传请求传输方法
EP2819327B1 (fr) * 2013-06-28 2018-04-11 Alcatel Lucent Procédé de transmission optique de données utilisant le multiplexage de division de polarisation et QPSK
CN105009541B (zh) * 2013-07-18 2018-06-05 华为技术有限公司 一种低码率的编码方法和设备
EP3057255B1 (fr) * 2013-11-04 2018-08-22 Huawei Technologies Co., Ltd. Procédé et appareil d'adaptation de débit pour codes polaires, et dispositif de communication sans fil
CN105164959B (zh) * 2014-02-21 2019-06-21 华为技术有限公司 用于极化码的速率匹配的方法和装置
WO2015139248A1 (fr) * 2014-03-19 2015-09-24 华为技术有限公司 Procede d'adaptation de debit de code polaire et dispositif d'adaptation de debit
CN105049061B (zh) * 2015-04-28 2018-06-01 北京邮电大学 基于超前计算的高维基极化码译码器和极化码译码方法
CN105227189B (zh) * 2015-09-24 2019-01-01 电子科技大学 分段crc辅助的极化码编译码方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015026148A1 (fr) * 2013-08-20 2015-02-26 엘지전자 주식회사 Procédé de transmission de données à l'aide d'un codage polaire dans un système d'accès sans fil
US20160182187A1 (en) * 2013-08-20 2016-06-23 Lg Electronics Inc. Method for transmitting data by using polar coding in wireless access system

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
CHEN KAI ET AL: "A Hybrid ARQ Scheme Based on Polar Codes", IEEE COMMUNICATIONS LETTERS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 17, no. 10, 1 October 2013 (2013-10-01), pages 1996 - 1999, XP011535616, ISSN: 1089-7798, [retrieved on 20131028], DOI: 10.1109/LCOMM.2013.090213.131670 *
SABER HAMID ET AL: "An Incremental Redundancy Hybrid ARQ Scheme via Puncturing and Extending of Polar Codes", IEEE TRANSACTIONS ON COMMUNICATIONS, IEEE SERVICE CENTER, PISCATAWAY, NJ. USA, vol. 63, no. 11, 1 November 2015 (2015-11-01), pages 3964 - 3973, XP011589911, ISSN: 0090-6778, [retrieved on 20151113], DOI: 10.1109/TCOMM.2015.2477082 *
VERA MILOSLAVSKAYA: "Shortened Polar Codes", IEEE TRANSACTIONS ON INFORMATION THEORY, vol. 61, no. 9, 1 September 2015 (2015-09-01), USA, pages 4852 - 4865, XP055337881, ISSN: 0018-9448, DOI: 10.1109/TIT.2015.2453312 *

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11683125B2 (en) 2017-03-22 2023-06-20 Interdigital Patent Holdings, Inc. Polar coding systems, procedures, and signaling
US11070317B2 (en) 2017-03-22 2021-07-20 Idac Holdings, Inc. Sub-block wise interleaving for polar coding systems, procedures, and signaling
US12028159B2 (en) 2017-03-22 2024-07-02 Interdigital Patent Holdings, Inc. Polar coding systems, procedures, and signaling
US11528040B2 (en) 2017-11-02 2022-12-13 Huawei Technologies Co., Ltd. Data retransmission method and apparatus to obtain information to be transmitted and to perform Polar encoding on the information
WO2019093855A1 (fr) * 2017-11-13 2019-05-16 엘지전자 주식회사 Procédé de codage sur la base d'un code polaire afin de prendre en charge une harq, et dispositif sans fil l'utilisant
US11239954B2 (en) 2017-11-13 2022-02-01 Lg Electronics Inc. Encoding method on basis of polar code in order to support HARQ, and wireless device using same
CN111357221A (zh) * 2017-11-20 2020-06-30 高通股份有限公司 用于超可靠低延时通信的极化码的混合自动重传请求设计的技术和装置
JP2021503825A (ja) * 2017-11-20 2021-02-12 クアルコム，インコーポレイテッド 超高信頼低レイテンシ通信のためのポーラコードのハイブリッド自動再送要求設計のための技法および装置
JP7366895B2 (ja) 2017-11-20 2023-10-23 クアルコム，インコーポレイテッド 超高信頼低レイテンシ通信のためのポーラコードのハイブリッド自動再送要求設計のための技法および装置
KR102725958B1 (ko) * 2017-11-20 2024-11-04 퀄컴 인코포레이티드 초-신뢰성 저 레이턴시 통신들을 위한 폴라 코드들의 하이브리드 자동 반복 요청 설계를 위한 기법들 및 장치들
EP3714563A4 (fr) * 2017-11-20 2021-08-04 QUALCOMM Incorporated Techniques et appareils de conception de demande de répétition automatique hybride de codes polaires à des fins de communications à faible latence ultra-fiables
US11184116B2 (en) 2017-11-20 2021-11-23 Qualcomm Incorporated Techniques and apparatuses for hybrid automatic repeat request design of polar codes for ultra-reliable low latency communications
WO2019128707A1 (fr) * 2017-12-26 2019-07-04 华为技术有限公司 Procédé et dispositif de codage par code polaire et d'adaptation de débit
US11265108B2 (en) 2017-12-26 2022-03-01 Huawei Technologies Co., Ltd. Method and device for rate matching and polar encoding
CN111954991A (zh) * 2018-03-30 2020-11-17 Lg 电子株式会社 基于极化码执行侧链路通信的方法及其设备
WO2019190258A1 (fr) * 2018-03-30 2019-10-03 엘지전자 주식회사 Procédé de réalisation d'une communication en liaison latérale selon un code polaire et dispositif à cet effet
US11588589B2 (en) 2018-03-30 2023-02-21 Lg Electronics Inc. Method for performing sidelink communication on basis of polar code and device therefor
CN112425103A (zh) * 2018-04-30 2021-02-26 波拉兰哈伯雷斯姆技术公司 使用系统极化编码重传数据的方法和系统
CN112425103B (zh) * 2018-04-30 2024-01-19 波拉兰哈伯雷斯姆技术公司 使用系统极化编码重传数据的方法和系统
CN112313895A (zh) * 2018-06-25 2021-02-02 高通股份有限公司 超可靠的低延迟通信(urllc)的混合极化码设计
US11050519B2 (en) * 2018-09-14 2021-06-29 Idac Holdings, Inc. Methods, apparatus, systems and procedures for hybrid automatic repeat requests (HARQs) using polar codes
US11581905B2 (en) 2018-09-28 2023-02-14 Huawei Technologies Co., Ltd. Method and apparatus for wirelessly communicating over a noisy channel with a variable codeword length polar code to improve transmission capacity
US11057053B2 (en) 2018-09-28 2021-07-06 Huawei Technologies Co., Ltd. Method and apparatus for wirelessly communicating over a noisy channel with a variable codeword length polar code to improve transmission capacity
WO2020061684A1 (fr) * 2018-09-28 2020-04-02 Huawei Technologies Co., Ltd. Procédé et appareil pour communiquer sans fil sur un canal bruyant avec un code polaire de longueur de mot de code variable pour améliorer la capacité de transmission
CN111431675B (zh) * 2019-01-10 2022-10-25 华为技术有限公司 数据传输方法及装置
CN111431675A (zh) * 2019-01-10 2020-07-17 华为技术有限公司 数据传输方法及装置
US11418294B2 (en) 2019-09-20 2022-08-16 Qualcomm Incorporated Single step in-place operation method for 5G NR de-interleaving, de-rate matching, and HARQ combination
WO2023282366A1 (fr) * 2021-07-05 2023-01-12 엘지전자 주식회사 Procédé de transmission de signal basé sur une harq dans un système de communication sans fil et appareil associé
CN114095038A (zh) * 2021-10-12 2022-02-25 上海交通大学 编解码器及生成码字的方法和系统
WO2024165143A1 (fr) * 2023-02-07 2024-08-15 Vestel Elektronik Sanayi ve Ticaret A. S. Demande de répétition automatique hybride avec versions de redondance pré-configurées

Also Published As

Publication number Publication date
CN114679242A (zh) 2022-06-28
CN108886438B (zh) 2022-03-18
TW201737651A (zh) 2017-10-16
TWI717473B (zh) 2021-02-01
CN114679242B (zh) 2024-02-02
CN108886438A (zh) 2018-11-23

Similar Documents

Publication Publication Date Title
CN108886438B (zh) 用于harq传输的极化码
US10999010B2 (en) Rate matching using low-density parity-check codes
US11784750B2 (en) HARQ for advanced channel codes
CN110495115B (zh) 一种用于无线通信中的速率匹配和交织的方法、设备、装置和介质
KR102131834B1 (ko) Qc ldpc 코드의 레이트 매칭 방법 및 이를 위한 장치
KR101909549B1 (ko) 폴라 코드 레이트 매칭 방법과 장치, 및 무선 통신 장치
US10447312B2 (en) Method of performing interleaving using LDPC and communication apparatus therefor
US10116332B2 (en) Method for configuring circular buffer including outer code parity and apparatus therefor
KR102541319B1 (ko) 무선 통신 시스템에서 극 부호를 이용한 부호화 및 복호화를 위한 장치 및 방법
US20190140663A1 (en) Data retransmission method for polar code, and device therefor
US20170279464A1 (en) Method of ldpc code encoding for reducing signal overhead and apparatus therefor
CN108370284B (zh) 使用低密度奇偶校验矩阵进行编码和解码
KR20190033588A (ko) 폴라 코드에 대한 레이트 매칭을 위한 시스템 및 방법
CN108432167B (zh) 对消息进行编码解码的装置、系统和计算机可读介质
CA3041251C (fr) Procede de transmission de code ldpc faisant appel a une structure orthogonale en rangee, et dispositif associe
CN108141312B (zh) 用于基站的装置
KR101998199B1 (ko) 다중 ldpc 코드에서 ldpc 베이스 코드를 선택하는 방법 및 이를 위한 장치
CN110383727B (zh) 用于ldpc码的分层解码方法及其装置
WO2018080569A1 (fr) Schémas de codage de canal pour dispositifs vestimentaires 5g
WO2017151175A1 (fr) Turbocodage avec un support pour de faibles rendements de codage

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16774801

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16774801

Country of ref document: EP

Kind code of ref document: A1