WO2017150671A1 - Élément de conversion photoélectrique et procédé de fabrication d'élément de conversion photoélectrique - Google Patents

Élément de conversion photoélectrique et procédé de fabrication d'élément de conversion photoélectrique Download PDF

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Publication number
WO2017150671A1
WO2017150671A1 PCT/JP2017/008287 JP2017008287W WO2017150671A1 WO 2017150671 A1 WO2017150671 A1 WO 2017150671A1 JP 2017008287 W JP2017008287 W JP 2017008287W WO 2017150671 A1 WO2017150671 A1 WO 2017150671A1
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Prior art keywords
semiconductor film
amorphous semiconductor
type amorphous
conductive
photoelectric conversion
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PCT/JP2017/008287
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English (en)
Japanese (ja)
Inventor
真人 石井
正道 小林
嘉高 銭谷
健史 森
親扶 岡本
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シャープ株式会社
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Publication of WO2017150671A1 publication Critical patent/WO2017150671A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a photoelectric conversion element and a method for manufacturing the photoelectric conversion element.
  • This application claims priority based on Japanese Patent Application No. 2016-042085, which is a Japanese patent application filed on Mar. 4, 2016. All the descriptions described in the Japanese patent application are incorporated herein by reference.
  • the back junction solar cell is an electrode provided on the light receiving surface side of the crystalline silicon substrate by forming the pn junction and the electrode provided on the light receiving surface side of the crystalline silicon substrate on the back surface side of the crystalline silicon substrate. It is a high-efficiency solar cell that eliminates the shadow caused by and absorbs more sunlight.
  • Such back junction solar cells are mass-produced by forming a pn junction by thermally diffusing impurities on the back surface of the crystalline silicon substrate.
  • development of a heterojunction back contact cell in which an amorphous silicon layer is formed on the back surface of a crystalline silicon substrate is underway.
  • Patent Document 1 describes a method for manufacturing the following back junction solar cell. First, after laminating an i-type amorphous semiconductor layer, an n-type amorphous semiconductor layer, and an insulating layer in this order on the back surface of the semiconductor substrate, a part of the insulating layer is removed, and the remaining insulating layer is used as a mask. A part of the back surface of the semiconductor substrate is exposed by performing alkali etching of the n-type amorphous semiconductor layer and the n-type amorphous semiconductor layer.
  • the i-type amorphous semiconductor layer and the p-type amorphous semiconductor layer are formed so as to cover the exposed back surface of the semiconductor substrate and the stacked body of the i-type amorphous semiconductor layer, the n-type amorphous semiconductor layer, and the insulating layer. Are stacked in this order.
  • a part of each of the i-type amorphous semiconductor layer and the p-type amorphous semiconductor layer a part of the insulating layer is exposed, and the exposed insulating layer is etched in the thickness direction.
  • the p-type amorphous semiconductor layer is exposed.
  • an electrode is formed on each of the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer to form a back junction solar cell.
  • the embodiment disclosed herein includes a first conductive type or second conductive type semiconductor substrate having a first surface and a second surface, and a first conductive type amorphous material on the first surface side of the semiconductor substrate.
  • the first conductive amorphous semiconductor film is a portion where the thickness of the first conductive amorphous semiconductor film is partially reduced.
  • the photoelectric conversion element has a thinned region which is a surface region of the film, and the first electrode is arranged in a part of the thinned region.
  • the embodiment disclosed herein includes a step of forming a first conductive amorphous semiconductor film on a first surface of a semiconductor substrate, and a part of the first conductive amorphous semiconductor film in a thickness direction.
  • the second conductivity type amorphous semiconductor film is covered so as to cover the first conductivity type amorphous semiconductor film on the semiconductor substrate after the removing step and the step of removing a part of the first conductivity type amorphous semiconductor film in the thickness direction.
  • Forming a porous semiconductor film removing a part of the second conductive amorphous semiconductor film in the thickness direction and leaving a part of the first conductive amorphous semiconductor film in the thickness direction
  • Forming a thinned region which is a surface region of the first conductive type amorphous semiconductor film in a portion where the thickness of the first conductive type amorphous semiconductor film is partially reduced by removing Forming a first electrode on a part of the thinned region; forming a second electrode on the second conductive amorphous semiconductor film; Including a method of manufacturing a photoelectric conversion element.
  • a photoelectric conversion element capable of improving the characteristics can be provided.
  • FIG. 2 is a schematic cross-sectional view of a heterojunction back contact cell according to Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing the heterojunction back contact cell of Embodiment 1.
  • FIG. 6 is a schematic cross-sectional view of a heterojunction back contact cell of Embodiment 2.
  • FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing the heterojunction back contact cell of Embodiment 2.
  • FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing the heterojunction back contact cell of Embodiment 2.
  • FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing the heterojunction back contact cell of Embodiment 2.
  • FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing the heterojunction back contact cell of Embodiment 2.
  • FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing the heterojunction back contact cell of Embodiment 2.
  • FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing the heterojunction back contact cell of Embodiment 2.
  • FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing the heterojunction back contact cell of Embodiment 2.
  • FIG. 6 is a schematic cross-sectional view for explaining an example of a method for manufacturing the heterojunction back contact cell of Embod
  • FIG. 1 is a schematic cross-sectional view of the heterojunction back contact cell of the first embodiment.
  • the heterojunction back contact cell of Embodiment 1 includes a p-type or n-type semiconductor substrate 1.
  • the semiconductor substrate 1 includes a light receiving surface 1a and a back surface 1b facing the light receiving surface 1a.
  • a dielectric film 6 is provided on the light receiving surface 1 a of the semiconductor substrate 1.
  • a first i-type amorphous semiconductor film 2 covering a part of the back surface 1 b of the semiconductor substrate 1 and a second portion covering the other part of the back surface 1 b of the semiconductor substrate 1.
  • An i-type amorphous semiconductor film 4 is provided.
  • a p-type amorphous semiconductor film 3 is provided on the first i-type amorphous semiconductor film 2.
  • An n-type amorphous semiconductor film 5 is provided on the second i-type amorphous semiconductor film 4.
  • the p-type amorphous semiconductor film 3 is an overlapping region 11 which is a surface region of the p-type amorphous semiconductor film 3 where the p-type amorphous semiconductor film 3 and the n-type amorphous semiconductor film 5 overlap. have. Between the overlapping region 11 of the p-type amorphous semiconductor film 3 and the n-type amorphous semiconductor film 5, the end of the second i-type amorphous semiconductor film 4 is located.
  • the p-type amorphous semiconductor film 3 has a thinned region 12 that is a surface region of the p-type amorphous semiconductor film 3 where the thickness of the p-type amorphous semiconductor film 3 is partially reduced. is doing.
  • the thickness T1 of the p-type amorphous semiconductor film 3 in the thinned region 12 is smaller than the thickness T2 of the p-type amorphous semiconductor film 3 in the overlapping region 11.
  • a p-electrode 7 is provided on the p-type amorphous semiconductor film 3, and an n-electrode 8 is provided on the n-type amorphous semiconductor film 5.
  • the p electrode 7 is disposed in a part of the thinned region 12 of the p-type amorphous semiconductor film 3.
  • a dielectric film 6 is formed on the light receiving surface 1 a of the semiconductor substrate 1.
  • the formation method of the dielectric film 6 is not particularly limited, but for example, a plasma CVD (Chemical Vapor Deposition) method can be used.
  • a first i-type amorphous semiconductor film 2 and a p-type amorphous semiconductor film 3 are stacked in this order on the entire back surface 1b of the semiconductor substrate 1.
  • a method for forming the first i-type amorphous semiconductor film 2 and the p-type amorphous semiconductor film 3 is not particularly limited, and for example, a plasma CVD method can be used.
  • a p-type or n-type single crystal silicon substrate can be suitably used, but is not limited thereto, and for example, a conventionally known p-type or n-type semiconductor substrate can be appropriately used.
  • an i-type amorphous silicon film can be preferably used, but is not limited to an i-type amorphous silicon film.
  • a quality semiconductor film can also be used.
  • i-type is not only a completely intrinsic state but also a sufficiently low concentration (the n-type impurity concentration is less than 1 ⁇ 10 15 / cm 3 and the p-type impurity concentration is 1).
  • ⁇ 10 15 / cm 3 means to include those in which n-type or p-type impurities are mixed.
  • amorphous silicon includes not only amorphous silicon in which dangling bonds of silicon atoms are not terminated with hydrogen, but also hydrogenated amorphous silicon and the like. Also included are those in which dangling bonds of silicon atoms are terminated with hydrogen or the like.
  • a p-type amorphous silicon film can be suitably used as the p-type amorphous semiconductor film 3.
  • the p-type amorphous semiconductor film is not limited to a p-type amorphous silicon film.
  • a conventionally known p-type amorphous semiconductor film is used. Can also be used.
  • p-type impurity contained in the p-type amorphous semiconductor film 3 for example, boron can be used.
  • p-type means a state in which the p-type impurity concentration is 1 ⁇ 10 15 / cm 3 or more.
  • an etching paste 9 is applied on a partial region of the p-type amorphous semiconductor film 3.
  • the etching paste 9 for example, an etching paste capable of removing the p-type amorphous semiconductor film 3 and the first i-type amorphous semiconductor film 2 in the thickness direction can be used.
  • the p-type amorphous semiconductor film 3 and the first i-type amorphous semiconductor film 2 in the portion where the etching paste 9 is installed are changed in the thickness direction.
  • the back surface 1 b of the semiconductor substrate 1 is exposed in the removed portion of the p-type amorphous semiconductor film 3 and the first i-type amorphous semiconductor film 2.
  • the second i-type amorphous semiconductor film 4 and the n-type amorphous semiconductor film so as to cover the i-type amorphous semiconductor film 2 and the p-type amorphous semiconductor film 3. 5 are stacked in this order.
  • a method for forming the second i-type amorphous semiconductor film 4 and the n-type amorphous semiconductor film 5 is not particularly limited, and for example, a plasma CVD method can be used.
  • an i-type amorphous silicon film can be suitably used, but is not limited to an i-type amorphous silicon film.
  • a conventionally known i-type amorphous silicon film is used.
  • a quality semiconductor film can also be used.
  • an n-type amorphous silicon film can be preferably used, but is not limited to an n-type amorphous silicon film.
  • a conventionally known n-type amorphous semiconductor film is used. Can also be used.
  • phosphorus can be used as an n-type impurity contained in the n-type amorphous silicon film constituting the n-type amorphous semiconductor film 5.
  • n-type means a state in which the n-type impurity concentration is 1 ⁇ 10 15 / cm 3 or more.
  • an etching paste 10 is applied on a partial region of the n-type amorphous semiconductor film 5.
  • the etching paste 10 for example, the second i-type amorphous semiconductor film 4 and the n-type amorphous semiconductor film 5 can be removed in the thickness direction, and the p-type amorphous semiconductor is used.
  • An etching paste capable of partially leaving (partially removing) the film 3 in the thickness direction can be used. In the etching technique using the conventional etching paste, the etching rate is too fast, and it is difficult to leave a part of the thin p-type amorphous semiconductor film 3 in the thickness direction (remove part of it).
  • the development of the etching technique using the etching paste has made it possible to adjust the etching paste so that the etching paste has a lower temperature and a lower etching rate. It is also possible to leave a part in the direction (remove a part).
  • the thickness of the second i-type amorphous semiconductor film 4 and the n-type amorphous semiconductor film 5 in the installation portion of the etching paste 10 is increased.
  • the p-type amorphous semiconductor film 3 is partially left in the thickness direction (partially removed).
  • the thickness T2 is maintained in the portion of the p-type amorphous semiconductor film 3 where the etching paste 10 is not applied, and the thickness is maintained in the portion of the p-type amorphous semiconductor film 3 where the etching paste 10 is applied. Decreases from T2 to T1.
  • the surface region of the p-type amorphous semiconductor film 3 where the thickness T2 of the p-type amorphous semiconductor film 3 is maintained becomes an overlapping region 11, and the thickness of the p-type amorphous semiconductor film 3 is changed from T2 to T1.
  • the surface region of the p-type amorphous semiconductor film 3 in the portion reduced to the thickness becomes the thinned region 12.
  • a p-electrode 7 is formed on a part of the thinned region 12 having a thickness T ⁇ b> 1 of the p-type amorphous semiconductor film 3, and n on the n-type amorphous semiconductor film 5.
  • the electrode 8 the heterojunction back contact cell of Embodiment 1 can be manufactured.
  • the back junction solar cell of Patent Document 1 is completed by forming electrodes on the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer stacked on the back surface of the semiconductor substrate. As a result, a resistance proportional to the thickness of the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer under the electrode is generated, which leads to the deterioration of the characteristics of the back junction solar cell of Patent Document 1. It was.
  • the thickness T1 of the p-type amorphous semiconductor film 3 in the thinned region 12 is equal to the thickness T2 of the p-type amorphous semiconductor film 3 in the overlapping region 11. Therefore, the electrical resistance of the p-electrode 7 to the p-type amorphous semiconductor film 3 can be kept low. Therefore, the characteristics of the heterojunction back contact cell of Embodiment 1 can be improved.
  • the p electrode 7 is disposed in a part of the thinned region 12 of the p type amorphous semiconductor film 3, so that the positional deviation of the p electrode 7 is shifted. Even if it occurs, there is a high possibility that the p-electrode 7 is disposed within the range of the thinned region 12, so that the characteristics of the heterojunction back contact cell of Embodiment 1 deteriorate due to the positional deviation of the p-electrode 7. Can be suppressed.
  • the heterojunction back contact cell of Embodiment 1 does not need to use an expensive process such as photolithography, and can be manufactured at a reduced cost.
  • the p-type amorphous semiconductor is used.
  • the surface of the film 3 may be damaged.
  • the surface of the p-type amorphous semiconductor film 3 was damaged by partially removing the p-type amorphous semiconductor film 3 in the thickness direction. The part can be removed.
  • FIG. 9 is a schematic cross-sectional view of the heterojunction back contact cell of the second embodiment.
  • the n-type non-crystalline semiconductor film 5 is an n-type non-contact portion where the p-type amorphous semiconductor film 3 and the n-type amorphous semiconductor film 5 overlap.
  • the overlapping region 13 which is the surface region of the crystalline semiconductor film 5 and the thin region which is the surface region of the n-type amorphous semiconductor film 5 where the thickness of the n-type amorphous semiconductor film 5 is partially reduced.
  • the n-electrode 8 is arranged in a part of the thinned region 14.
  • the second i-type amorphous semiconductor film 4 and the n-type amorphous semiconductor film 5 are formed on the back surface 1b of the semiconductor substrate 1 on which the dielectric film 6 is formed on the light receiving surface 1a. Laminate in this order.
  • an etching paste 10 is applied on a partial region of the n-type amorphous semiconductor film 5.
  • the etching paste 10 is heated, so that the n-type amorphous semiconductor film 5 and the second i-type amorphous semiconductor film 4 in the installation portion of the etching paste 10 are in the thickness direction as shown in FIG. To remove. Thereby, the back surface of the semiconductor substrate 1 is exposed in the removed portion of the n-type amorphous semiconductor film 5 and the second i-type amorphous semiconductor film 4.
  • the first i-type amorphous semiconductor film 2 and the p-type non-conductive layer are formed so as to cover the second i-type amorphous semiconductor film 4 and the n-type amorphous semiconductor film 5.
  • the crystalline semiconductor film 3 is laminated in this order.
  • an etching paste 9 is applied on a partial region of the p-type amorphous semiconductor film 3.
  • the thickness of the first i-type amorphous semiconductor film 2 and the p-type amorphous semiconductor film 3 in the installation portion of the etching paste 9 is increased.
  • the entire n-type amorphous semiconductor film 5 is left in the thickness direction (partially removed).
  • the thickness T2 is maintained in the portion of the n-type amorphous semiconductor film 5 where the etching paste 9 is not applied, and the thickness is maintained in the portion of the n-type amorphous semiconductor film 5 where the etching paste 9 is applied. Decreases from T2 to T1.
  • the surface region of the n-type amorphous semiconductor film 5 where the thickness T2 of the n-type amorphous semiconductor film 5 is maintained becomes an overlapping region 13, and the thickness of the n-type amorphous semiconductor film 5 changes from T2 to T1.
  • the surface region of the n-type amorphous semiconductor film 5 in the reduced portion becomes the thinned region 14.
  • the etching rate is too fast, and it is difficult to leave a part of the thin p-type amorphous semiconductor film 3 in the thickness direction (remove part of it).
  • the development of the etching technique using the etching paste has made it possible to adjust the etching paste so that the etching paste has a low temperature and a low etching rate, so that the thickness of the thin n-type amorphous semiconductor film 5 is reduced. It is also possible to leave a part in the direction (remove a part).
  • an n-electrode 8 is formed on a part of the thinned region 12 having a thickness T 1 of the n-type amorphous semiconductor film 5, and a p-type is formed on the p-type amorphous semiconductor film 3.
  • the electrode 7 the heterojunction back contact cell of Embodiment 2 can be manufactured.
  • An embodiment disclosed herein includes a first conductivity type or second conductivity type semiconductor substrate having a first surface and a second surface, and a first conductivity type on the first surface side of the semiconductor substrate.
  • the photoelectric conversion element has a thinned region which is a surface region of a crystalline semiconductor film, and a first electrode is arranged in a part of the thinned region.
  • the first conductive amorphous semiconductor film overlaps the first conductive amorphous semiconductor film and the second conductive amorphous semiconductor film.
  • the thickness of the first conductive type amorphous semiconductor film in the thinned region is equal to the first conductive type amorphous semiconductor film in the thinned region. It may be thinner than the thickness of the quality semiconductor film. Also in this case, a photoelectric conversion element capable of improving characteristics can be provided.
  • the photoelectric conversion element of the embodiment disclosed herein may further include a second i-type amorphous semiconductor film between the overlapping region and the second conductive amorphous semiconductor film. Also in this case, a photoelectric conversion element capable of improving characteristics can be provided.
  • the photoelectric conversion element of the embodiment disclosed herein may further include a first i-type amorphous semiconductor film between the semiconductor substrate and the first conductive amorphous semiconductor film. Also in this case, a photoelectric conversion element capable of improving characteristics can be provided.
  • An embodiment disclosed herein includes a step of forming a first conductive amorphous semiconductor film on a first surface of a semiconductor substrate, and a thickness of a part of the first conductive amorphous semiconductor film.
  • the second conductive layer so as to cover the first conductive type amorphous semiconductor film on the semiconductor substrate after the step of removing in the vertical direction and the step of removing a part of the first conductive type amorphous semiconductor film in the thickness direction.
  • a thinned region which is a surface region of the first conductive type amorphous semiconductor film in a portion where the thickness of the first conductive type amorphous semiconductor film is partially reduced is formed Forming a first electrode on a part of the thinned region, and forming a second electrode on the second conductive amorphous semiconductor film.
  • Including a degree, and a method of manufacturing a photoelectric conversion element By setting it as such a structure, the photoelectric conversion element which can improve a characteristic can be manufactured.
  • At least the step of removing a part of the first conductive type amorphous semiconductor film in the thickness direction and the step of forming a thinned region One may be performed by etching using an etching paste. Also in this case, a photoelectric conversion element capable of improving the characteristics can be manufactured.
  • the step of forming the first conductive type amorphous semiconductor film includes the first i-type amorphous semiconductor film and the first conductive type non-conductive film.
  • a step of forming the crystalline semiconductor film in this order may be included.
  • a photoelectric conversion element capable of improving the characteristics can be manufactured.
  • the step of forming the second conductive type amorphous semiconductor film includes the second i type amorphous semiconductor film and the second conductive type non-conductive film.
  • a step of forming the crystalline semiconductor film in this order may be included.
  • a photoelectric conversion element capable of improving the characteristics can be manufactured.
  • Embodiment disclosed here can be utilized for the manufacturing method of a photoelectric conversion element and a photoelectric conversion element, The possibility of being applicable to the manufacturing method of a heterojunction type back contact cell and a heterojunction type back contact cell suitably There is.

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  • Sustainable Energy (AREA)
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Abstract

La présente invention concerne un élément de conversion photoélectrique qui comporte un film semi-conducteur amorphe (3, 5) d'un premier type de conductivité et un film semi-conducteur amorphe (3, 5) d'un second type de conductivité sur un côté première surface (1b) d'un substrat à semi-conducteurs (1). Une première électrode (7, 8) est placée sur le film semi-conducteur amorphe (3, 5) d'un premier type de conductivité. Le film semi-conducteur amorphe (3, 5) d'un premier type de conductivité présente une région amincie (12, 14) qui est une région de surface d'une partie du film semi-conducteur amorphe (3, 5) d'un premier type de conductivité, l'épaisseur du film semi-conducteur amorphe (3, 5) d'un premier type de conductivité étant partiellement réduite. La première électrode (7, 8) est agencée dans une partie de la région amincie (12, 14).
PCT/JP2017/008287 2016-03-04 2017-03-02 Élément de conversion photoélectrique et procédé de fabrication d'élément de conversion photoélectrique WO2017150671A1 (fr)

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Application Number Priority Date Filing Date Title
JP2016042085 2016-03-04
JP2016-042085 2016-03-04

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WO2017150671A1 true WO2017150671A1 (fr) 2017-09-08

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012132595A1 (fr) * 2011-03-25 2012-10-04 三洋電機株式会社 Cellule solaire
JP2013131586A (ja) * 2011-12-21 2013-07-04 Sharp Corp 裏面電極型太陽電池の製造方法
JP2013191657A (ja) * 2012-03-13 2013-09-26 Sharp Corp 光電変換素子およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012132595A1 (fr) * 2011-03-25 2012-10-04 三洋電機株式会社 Cellule solaire
JP2013131586A (ja) * 2011-12-21 2013-07-04 Sharp Corp 裏面電極型太陽電池の製造方法
JP2013191657A (ja) * 2012-03-13 2013-09-26 Sharp Corp 光電変換素子およびその製造方法

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