WO2017143646A1 - 栅极驱动电路 - Google Patents

栅极驱动电路 Download PDF

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Publication number
WO2017143646A1
WO2017143646A1 PCT/CN2016/078726 CN2016078726W WO2017143646A1 WO 2017143646 A1 WO2017143646 A1 WO 2017143646A1 CN 2016078726 W CN2016078726 W CN 2016078726W WO 2017143646 A1 WO2017143646 A1 WO 2017143646A1
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WIPO (PCT)
Prior art keywords
electrically connected
output
transistor
control
control node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/078726
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English (en)
French (fr)
Inventor
石龙强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/034,691 priority Critical patent/US10008166B2/en
Publication of WO2017143646A1 publication Critical patent/WO2017143646A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2290/00—Indexing scheme relating to details of a display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the invention relates to the field of liquid crystal displays, in particular to a gate driver (Gate driver on A liquid crystal display of an array, GOA) circuit.
  • GOA gate driver on A liquid crystal display of an array, GOA
  • the GOA circuit uses a thin film transistor liquid crystal display Array process to fabricate a gate driver with a thin film transistor (Thin film). Transistor, TFT) on the substrate of the array to implement a progressive scan driving method.
  • the GOA circuit contains several GOA circuit units.
  • a conventional GOA circuit unit outputs a scan signal by controlling a gate voltage of an output transistor (that is, a voltage at a Q point).
  • Traditional GOA The circuit unit uses the clock signal as the input source for the pull-down sustain block, so the pull-down sustain block will only operate during the pulse generation of the clock signal. During the period when the clock signal is not pulsed, the pull-down sustain block will not function, so that the scan signal at the output cannot maintain a low potential.
  • the pull-down sustaining module can still pull down the scan signal to maintain it low during the period when the clock signal is not pulsed.
  • the technical solution of the present invention provides a gate driving circuit including a plurality of GOA circuit units. a plurality of the GOA circuit units are coupled in series, and each stage of the GOA circuit unit is configured to use a scan signal output by the GOA circuit unit of the previous stage, a scan signal output by the next-stage GOA circuit unit, a first clock signal, and The second clock signal outputs a scan signal at the output.
  • Each level of the GOA circuit unit includes: an input control module configured to be turned on when receiving a scan signal output by the previous stage GOA circuit unit to control a level of the first control node; an output control module, an electrical connection a first control node, configured to control the output of the scan signal according to a voltage applied to the first control node; and a pull-down module electrically connected to the output control module for determining a level according to the second control node Pulling down the level of the scan signal; and pulling down the sustaining module, electrically connecting the pull-down module to maintain the level of the second control node during the non-scan period to maintain the low level of the scan signal.
  • the pull-down maintaining module includes: a first transistor, wherein the first control end and the first input end are electrically connected to the first clock signal; and the second transistor has a second control end and a second input end electrically connected a third clock signal; a third transistor, wherein the third control terminal and the third input terminal are electrically connected to the first output end of the first transistor; and the fourth transistor has a fourth control terminal electrically connected to the a fourth control terminal electrically connected to the third output end of the third transistor, the fourth output end of which is electrically connected to a fixed voltage; and a fifth transistor whose fifth control end is electrically connected to the a third output end of the third transistor, the fifth input end is electrically connected to the first output end of the first transistor, the fifth output end is electrically connected to the second control node; and the sixth transistor is The sixth control terminal is electrically connected to the first control node, and the sixth input end is electrically connected to the second control node, and the sixth output end is electrically connected to the fixed voltage.
  • the pull-down module includes: a seventh transistor, the seventh control electrode is electrically connected to the second control node, and the seventh input is electrically connected to the first control node, and the seventh The output terminal electrically connects the fixed voltage; the eighth transistor has an eighth control electrode electrically connected to the second control node, an eighth input pole electrically connected to the output end, and an eighth output pole electrically connected
  • the ninth transistor is electrically connected to the scan signal output by the next-stage GOA circuit unit, and the ninth input is electrically connected to the output terminal, and the ninth output is electrically The fixed voltage is connected.
  • the input control module comprises a tenth transistor, wherein the tenth control electrode and the tenth input electrode are electrically connected to the scan signal output by the previous stage GOA circuit unit, and the tenth output is extremely The first control node is connected to the first.
  • the output control module includes: an eleventh transistor, an eleventh control electrode electrically connected to the first control node, and an eleventh input terminal electrically connected to the first clock signal
  • the eleventh output is electrically connected to the output end;
  • the twelfth transistor is electrically connected to the first control node, and the twelfth input is electrically connected to the first clock
  • a capacitor the two ends of which are electrically connected to the first control node and the output end.
  • the first clock signal and the second clock signal are mutually inverted.
  • the technical solution of the present invention further provides a gate driving circuit including a plurality of GOA circuit units. a plurality of the GOA circuit units are coupled in series, and each stage of the GOA circuit unit is configured to use a scan signal output by the GOA circuit unit of the previous stage, a scan signal output by the next-stage GOA circuit unit, a first clock signal, and The second clock signal outputs a scan signal at the output.
  • Each level of the GOA circuit unit includes: an input control module configured to be turned on when receiving a scan signal output by the previous stage GOA circuit unit to control a level of the first control node; an output control module, an electrical connection a first control node, configured to control the output of the scan signal according to a voltage applied to the first control node; and a pull-down module electrically connected to the output control module for determining a level according to the second control node Pulling down the level of the scan signal; and pulling down the sustaining module, electrically connecting the pull-down module to maintain the level of the second control node during the non-scan period to maintain the low level of the scan signal.
  • the pull-down maintaining module includes: a first transistor, wherein the first control end and the first input end are electrically connected to the first clock signal; and the second transistor has a second control end and a second input end electrically connected
  • the second clock signal is electrically connected to the second control node
  • the third transistor has a third control terminal and a third input terminal electrically connected to the second clock signal
  • the fourth transistor The fourth control terminal is electrically connected to the first control node, the fourth input end is electrically connected to the third output end of the third transistor, and the fourth output end is electrically connected to a fixed voltage
  • the fifth transistor The fifth control terminal and the fifth input terminal are electrically connected to the second clock signal, the fifth output terminal is electrically connected to the second control node, and the sixth transistor is electrically connected to the sixth control terminal.
  • the sixth control terminal is electrically connected to the second control node, and the sixth output terminal is electrically connected to the fixed voltage.
  • the pull-down module includes: a seventh transistor, the seventh control electrode is electrically connected to the second control node, and the seventh input is electrically connected to the first control node, and the seventh The output terminal electrically connects the fixed voltage; the eighth transistor has an eighth control electrode electrically connected to the second control node, an eighth input pole electrically connected to the output end, and an eighth output pole electrically connected
  • the ninth transistor is electrically connected to the scan signal output by the next-stage GOA circuit unit, and the ninth input is electrically connected to the output terminal, and the ninth output is electrically The fixed voltage is connected.
  • the input control module comprises a tenth transistor, wherein the tenth control electrode and the tenth input electrode are electrically connected to the scan signal output by the previous stage GOA circuit unit, and the tenth output is extremely The first control node is connected to the first.
  • the output control module includes: an eleventh transistor, an eleventh control electrode electrically connected to the first control node, and an eleventh input terminal electrically connected to the first clock signal
  • the eleventh output is electrically connected to the output end;
  • the twelfth transistor is electrically connected to the first control node, and the twelfth input is electrically connected to the first clock
  • a capacitor the two ends of which are electrically connected to the first control node and the output end.
  • the first clock signal and the second clock signal are mutually inverted.
  • the GOA circuit unit of the present invention uses the first transistor and the second transistor to cooperate with the design of the first clock signal and the second clock signal, so that the pull-down maintaining module does not need to output a pulse during the scan signal.
  • the output signal can still be continuously turned on to enable the pull-down module. Therefore, the scan signal is pulled down to a low level due to the action of the pull-down module that is turned on during the period when the output pulse is not required. Therefore, the present invention solves the technical problem that the prior art pull-down maintenance module cannot continue to operate, and has the beneficial effect of improving the stability of the output scan signal of the GOA circuit unit.
  • Figure 1 is a functional block diagram of a liquid crystal display of the present invention.
  • Fig. 2 is a circuit diagram of a GOA circuit unit of the first embodiment of the present invention.
  • FIG. 3 is a timing diagram of various input signals, output signals, and node voltages shown in FIG. 2.
  • Figure 4 is a circuit diagram of a GOA circuit unit of a second embodiment of the present invention.
  • Figure 5 is a timing diagram of the various input signals, output signals, and node voltages shown in Figure 4.
  • FIG. 1 is a functional block diagram of a liquid crystal display device 10 of the present invention.
  • the liquid crystal display 10 includes a glass substrate 14, a timing controller 30, and a source driver (source) Driver)16.
  • a plurality of pixels arranged in a matrix and a gate driving (GOA) circuit 12 are disposed on the glass substrate 14, and each pixel includes three pixel units 20 respectively representing three primary colors of red, green and blue (RGB).
  • the timing controller 30 is used to generate the clock signals CK1-CK2 and the start signal STV.
  • the GOA circuit 12 outputs the scan signals at regular intervals such that the transistors 22 of each row are sequentially turned on, while the source driver 16 outputs corresponding data signals to an entire column of pixel cells 20 to charge them to respective required voltages. Show different gray levels.
  • the GOA circuit 12 turns off the scan signal of the row, and then the GOA circuit 12 outputs the scan signal to turn on the transistor 22 of the next row, and then the source driver 16 charges the pixel unit 20 of the next row. Discharge. This is continued until all the pixel units 20 are fully charged, and charging starts from the first line.
  • the GOA circuit 12 shown in FIG. The control includes N GOA circuit units SR(1), ..., SR(N), N equal to 768.
  • FIG. 2 is a circuit diagram of a GOA circuit unit SR(n) according to a first embodiment of the present invention.
  • the GOA circuit 12 is directly disposed on the glass substrate 14.
  • each stage of the GOA circuit unit SR(n) is used to scan the signal G(n-1) output from the previous stage GOA circuit unit SR(n-1), and the next stage GOA circuit unit SR(n+1)
  • the output scan signal G(n+1), the first clock signal CK1, and the second clock signal CK2 output a scan signal G(n) at the output terminal OUT.
  • the first clock signal CK1 and the second clock signal CK2 are inverted from each other.
  • Each level of the GOA circuit unit SR(n) includes an input control module 100, an output control module 200, a pull-down module 300, and a pull-down maintenance module 400.
  • the input control module 100 is configured to be turned on when receiving the scan signal G(n-1) output by the previous stage GOA circuit unit SR(n-1) to control the level of the first control node Q.
  • the output control module 200 is electrically connected to a control node Q for controlling the output scan signal G(n) according to the voltage applied to the first control node Q.
  • the pull-down module 300 is electrically connected to the output control module 200 for pulling down the level of the scan signal G(n) according to the level of the second control node P.
  • the pull-down maintaining module 400 is electrically connected to the pull-down module 300 for maintaining the level of the second control node P during the non-scanning period to maintain the low level of the scan signal G(n).
  • the pull-down maintaining module 400 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.
  • the first control terminal and the first input terminal of the first transistor T1 are electrically connected to the first clock signal CK1.
  • the second control terminal and the second output terminal of the second transistor T2 are electrically connected to the second clock signal CK2.
  • the third control terminal and the third input terminal of the third transistor T3 are electrically connected to the first output end of the first transistor T1.
  • the fourth control terminal of the fourth transistor T4 is electrically connected to the first control node Q, the fourth input terminal thereof is electrically connected to the third output terminal of the third transistor T3, and the fourth output terminal thereof is electrically connected to the fixed low voltage Vss.
  • the fifth control terminal of the fifth transistor T5 is electrically connected to the third output end of the third transistor T3, the fifth input end thereof is electrically connected to the first output end of the first transistor T1, and the fifth output end thereof is electrically connected to the second output end.
  • the sixth control terminal of the sixth transistor T6 is electrically connected to the first control node Q, the sixth input terminal is electrically connected to the second control node P, and the sixth output terminal is electrically connected to the fixed low voltage Vss.
  • the pull-down module 300 includes a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.
  • the seventh control electrode of the seventh transistor T7 is electrically connected to the second control node P, and the seventh input is electrically connected to the first control node Q, and the seventh output is electrically connected to the fixed low voltage Vss.
  • the eighth control electrode of the eighth transistor T8 is electrically connected to the second control node P, and the eighth input is electrically connected to the output terminal OUT, and the eighth output is electrically connected to the fixed low voltage Vss.
  • the ninth control electrode of the ninth transistor T9 is electrically connected to the scan signal G(n+1) outputted by the next-stage GOA circuit unit SR(n+1), and the ninth input pole is electrically connected to the output terminal OUT, and the ninth thereof The output is electrically connected to a fixed low voltage Vss.
  • the input control module 100 includes a tenth transistor T10.
  • the tenth control electrode and the tenth input electrode of the tenth transistor T10 are electrically connected to the scan signal G(n-1) outputted by the previous stage GOA circuit unit SR(n-1), and the tenth output is electrically connected.
  • a control node Q is electrically connected.
  • the output control module 200 includes an eleventh transistor T11, a twelfth transistor T12, and a capacitor Cbt.
  • the eleventh control electrode of the eleventh transistor T11 is electrically connected to the first control node Q, and the eleventh input terminal is electrically connected to the first clock signal CK1, and the eleventh output terminal is electrically connected to the output terminal OUT.
  • the twelfth control electrode of the twelfth transistor T12 is electrically connected to the first control node Q, and the twelfth input terminal is electrically connected to the first clock signal CK1. Both ends of the capacitor Cbt are electrically connected to the first control node Q and the output terminal OUT.
  • All the transistors of the GOA circuit unit SR(n) of FIG. 2 are N-type metal oxides. Semiconductor, NMOS) transistor.
  • the control, input and output terminals of all of the transistors T1-T12 are the gate, drain and source of the transistors T1-T12, respectively.
  • the input and output of the transistors T1-T12 can also be the source and drain of the transistor, respectively.
  • FIG. 3 is a timing diagram of various input signals, output signals and node voltages shown in FIG.
  • the period during which each GOA circuit unit SR(n) receives the scan signal G(n-1) to output the scan signal G(n), that is, t2-t3 shown in FIG. 3, is called a scan period, and the rest Time is called a non-scanning period.
  • the scanning period is further divided into a precharge period (t2) and an output pulse period (t3).
  • the transistor T1 is turned on to cause the first clock signal CK1 of the high level to be transferred to the third control electrode of the transistor T3.
  • the transistor T3 is turned on to cause the first clock signal CK1 of the high level to be transferred to the fifth control electrode of the transistor T5.
  • the transistor T5 is turned on to cause the first clock signal CK1 of a high level to be transmitted to the second control node P.
  • the transistor T8 turns on the fixed low voltage Vss to the output terminal OUT so that the scan signal G(n) is at a low level.
  • the transistor T10 is turned on so that the first control node Q is at the high level, so that the transistors T4, T6, T11, T12 Open.
  • the transistor T11 turns on the first clock signal CK1 of the low level to the output terminal OUT, and thus the scan signal G(n) is also at the low level.
  • the transistor T6 turns on the fixed low voltage Vss to the second control node P.
  • the capacitor Cbt stores the charge so that the first control node Q remains at the high level.
  • the transistor T11 turns on the first clock signal CK1 of the high level to the output terminal OUT, and thus the scan signal G(n) is at the high level.
  • the transistor T2 is turned on to cause the second clock signal CK2 of the high level to be transferred to the third control electrode of the transistor T3.
  • the transistor T3 is turned on to cause the second clock signal CK2 of the high level to be transferred to the fifth gate of the transistor T5.
  • the transistor T5 is turned on to cause the second clock signal CK2 of the high level to be transmitted to the second control node P.
  • the transistor T8 turns on the fixed low voltage Vss to the output terminal OUT so that the scan signal G(n) is at a low level.
  • the GOA circuit unit of the present invention uses the first transistor T1 and the second transistor T2 to cooperate with the design of the first clock signal CK1 and the second clock signal CK2, so that the pull-down maintaining module 400 is in the scan signal G(n).
  • the output signal can be continuously output to enable the pull-down module 300 during the period when the pulse is not required to be output. Therefore, the scan signal G(n) will still pull down to a low level due to the action of the open pull-down module 300 during the period when the output pulse is not required. Therefore, the present invention solves the technical problem that the prior art pull-down maintenance module cannot continue to operate, and has the beneficial effect of improving the stability of the output scan signal of the GOA circuit unit.
  • FIG. 4 is a circuit diagram of a GOA circuit unit SR(n) according to a second embodiment of the present invention.
  • the difference between the embodiment of FIG. 4 and the embodiment of FIG. 2 is that the circuit configuration of the pull-down maintaining module 400 is different.
  • the pull-down maintaining module 400 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.
  • the first control terminal and the first input terminal of the first transistor T1 are electrically connected to the first clock signal CK1.
  • the second control terminal and the second input terminal of the second transistor T2 are electrically connected to the first clock signal CK1, and the second output terminal thereof is electrically connected to the second control node P.
  • the third control terminal and the third input terminal of the third transistor T3 are electrically connected to the second clock signal CK2.
  • the fourth control terminal of the fourth transistor T4 is electrically connected to the first control node Q, the fourth input terminal thereof is electrically connected to the third output terminal of the third transistor T3, and the fourth output terminal thereof is electrically connected to the fixed low voltage Vss.
  • the fifth control terminal and the fifth input terminal of the fifth transistor T5 are electrically connected to the second clock signal CK2, and the fifth output terminal is electrically connected to the second control node P.
  • the sixth control terminal of the sixth transistor T6 is electrically connected to the first control node Q, the sixth input terminal is electrically connected to the second control node P, and the sixth output terminal is electrically connected to the fixed low voltage Vss.
  • FIG. 5 is a timing diagram of various input signals, output signals, and node voltages shown in FIG.
  • the transistor T1 is turned on to cause the first clock signal CK1 of the high level to be transferred to the second control electrode of the transistor T2.
  • the transistor T2 is turned on to cause the first clock signal CK1 of a high level to be transmitted to the second control node P.
  • the transistor T8 turns on the fixed low voltage Vss to the output terminal OUT so that the scan signal G(n) is at a low level.
  • the transistor T10 is turned on so that the first control node Q is at the high level, so that the transistors T4, T6, T11, T12 Open.
  • the transistor T11 turns on the first clock signal CK1 of the low level to the output terminal OUT, and thus the scan signal G(n) is also at the low level.
  • the transistor T6 turns on the fixed low voltage Vss to the second control node P.
  • the capacitor Cbt stores the charge so that the first control node Q remains at the high level.
  • the transistor T11 turns on the first clock signal CK1 of the high level to the output terminal OUT, and thus the scan signal G(n) is at the high level.
  • the transistor T3 is turned on to cause the second clock signal CK2 of the high level to be transmitted to the fifth control electrode of the transistor T5.
  • the transistor T5 is turned on to cause the second clock signal CK2 of the high level to be transmitted to the second control node P.
  • the transistor T8 turns on the fixed low voltage Vss to the output terminal OUT so that the scan signal G(n) is at a low level.
  • the GOA circuit unit of the present invention uses the first transistor T1 and the second transistor T2 to cooperate with the design of the first clock signal CK1 and the second clock signal CK2, so that the pull-down maintaining module 400 is in the scan signal G(n).
  • the output signal can be continuously output to enable the pull-down module 300 during the period when the pulse is not required to be output. Therefore, the scan signal G(n) will still pull down to a low level due to the action of the open pull-down module 300 during the period when the output pulse is not required. Therefore, the present invention solves the technical problem that the prior art pull-down maintenance module cannot continue to operate, and has the beneficial effect of improving the stability of the output scan signal of the GOA circuit unit.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种栅极驱动电路，其包含数个GOA电路单元。每一级GOA电路单元包含下拉维持模块（400），用来维持第二控制节点P在非扫描期间的电平，以维持扫描信号的低电平。所述G OA电路单元的下拉维持模块（400）利用第一晶体管T1和第二晶体管T2配合第一时钟信号CK1和第二时钟信号CK2，使得所述下拉维持模块（400）在该扫描信号不需输出脉冲期间，仍能持续输出信号以开启下拉模块（300）。因此该扫描信号在不需输出脉冲期间，仍会因所述开启的下拉模块（300）作用而下拉至低电平。解决了现有技术中下拉维持模块无法持续运作的技术问题，提升了GOA电路单元输出扫描信号的稳定性。

Description

栅极驱动电路 技术领域
本发明是有关于一种液晶显示器领域，尤指一种使用栅极驱动(Gate driver on array，GOA)电路的液晶显示器。
 背景技术
GOA电路是利用薄膜晶体管液晶显示器Array制程将栅极驱动器制作在具有薄膜晶体管(Thin film transistor，TFT)阵列的基板上，以实现逐行扫描的驱动方式。
GOA电路包含数个GOA电路单元。传统的GOA电路单元通过控制输出晶体管的栅极电压(亦即Q点电压)来输出扫描信号。传统GOA 电路单元是使用时钟信号作为下拉维持模块的输入源，因此下拉维持模块只有在时钟信号产生脉冲期间才会运作。在时钟信号没有产生脉冲期间，下拉维持模块将没有发挥作用，使得输出端的扫描信号不能维持低电位。
因此有必要对现有技术采用进行改良，使得在时钟信号没有产生脉冲期间，下拉维持模块仍能下拉扫描信号使其维持在低电平。
 技术问题
本发明的目的是提供一种栅极驱动电路，以解决现有技术的问题。
 技术解决方案
本发明的技术方案提供一种栅极驱动电路，其包含数个GOA电路单元。数个所述GOA电路单元以串联的方式耦接，每一级GOA电路单元用来依据前一级GOA电路单元输出的扫描信号、下一级GOA电路单元输出的扫描信号、第一时钟信号以及第二时钟信号，在输出端输出扫描信号。每一级GOA电路单元包含：输入控制模块，用来于接收所述前一级GOA电路单元输出的扫描信号时导通，以控制第一控制节点的电平；输出控制模块，电性连接所述第一控制节点，用来依据施加于所述第一控制节点的电压，控制输出的所述扫描信号；下拉模块，电性连接所述输出控制模块，用来依据第二控制节点的电平下拉所述扫描信号的电平；及下拉维持模块，电性连接所述下拉模块，用来维持所述第二控制节点在非扫描期间的电平，以维持所述扫描信号的低电平。所述下拉维持模块包含：第一晶体管，其第一控制端和第一输入端皆电性连接所述第一时钟信号；第二晶体管，其第二控制端和第二输入端皆电性连接所述第二时钟信号；第三晶体管，其第三控制端和第三输入端皆电性连接所述第一晶体管的第一输出端；第四晶体管，其第四控制端电性连接所述第一控制节点，其第四输入端电性连接所述第三晶体管的第三输出端，其第四输出端电性连接一固定电压；第五晶体管，其第五控制端电性连接所述第三晶体管的第三输出端，其第五输入端电性连接所述第一晶体管的第一输出端，其第五输出端电性连接所述第二控制节点；及第六晶体管，其第六控制端电性连接所述第一控制节点，其第六输入端电性连接所述第二控制节点，其第六输出端电性连接所述固定电压。
依据本发明的实施例，所述下拉模块包含：第七晶体管，其第七控制极电性连接所述第二控制节点，其第七输入极电性连接所述第一控制节点，其第七输出极电性连接所述固定电压；第八晶体管，其第八控制极电性连接所述第二控制节点，其第八输入极电性连接所述输出端，其第八输出极电性连接所述固定电压；第九晶体管，其第九控制极电性连接所述下一级GOA电路单元输出的扫描信号，其第九输入极电性连接所述输出端，其第九输出极电性连接所述固定电压。
依据本发明的实施例，所述输入控制模块包含第十晶体管，其第十控制极和第十输入极皆电性连接所述前一级GOA电路单元输出的扫描信号，其第十输出极电性连接所述第一控制节点。
依据本发明的实施例，所述输出控制模块包含：第十一晶体管，其第十一控制极电性连接所述第一控制节点，其第十一输入极电性连接所述第一时钟信号，其第十一输出极电性连接所述输出端；第十二晶体管，其第十二控制极电性连接所述第一控制节点，其第十二输入极电性连接所述第一时钟信号；及电容，其两端电性连接所述第一控制节点和所述输出端。
依据本发明的实施例，所述第一时钟信号和所述第二时钟信号互为反相。
本发明的技术方案另提供一种栅极驱动电路，其包含数个GOA电路单元。数个所述GOA电路单元以串联的方式耦接，每一级GOA电路单元用来依据前一级GOA电路单元输出的扫描信号、下一级GOA电路单元输出的扫描信号、第一时钟信号以及第二时钟信号，在输出端输出扫描信号。每一级GOA电路单元包含：输入控制模块，用来于接收所述前一级GOA电路单元输出的扫描信号时导通，以控制第一控制节点的电平；输出控制模块，电性连接所述第一控制节点，用来依据施加于所述第一控制节点的电压，控制输出的所述扫描信号；下拉模块，电性连接所述输出控制模块，用来依据第二控制节点的电平下拉所述扫描信号的电平；及下拉维持模块，电性连接所述下拉模块，用来维持所述第二控制节点在非扫描期间的电平，以维持所述扫描信号的低电平。所述下拉维持模块包含：第一晶体管，其第一控制端和第一输入端皆电性连接所述第一时钟信号；第二晶体管，其第二控制端和第二输入端皆电性连接所述第一时钟信号，其第二输出端电性连接所述第二控制节点；第三晶体管，其第三控制端和第三输入端皆电性连接所述第二时钟信号；第四晶体管，其第四控制端电性连接所述第一控制节点，其第四输入端电性连接所述第三晶体管的第三输出端，其第四输出端电性连接一固定电压；第五晶体管，其第五控制端和第五输入端皆电性连接所述第二时钟信号，其第五输出端电性连接所述第二控制节点；及第六晶体管，其第六控制端电性连接所述第一控制节点，其第六输入端电性连接所述第二控制节点，其第六输出端电性连接所述固定电压。
依据本发明的实施例，所述下拉模块包含：第七晶体管，其第七控制极电性连接所述第二控制节点，其第七输入极电性连接所述第一控制节点，其第七输出极电性连接所述固定电压；第八晶体管，其第八控制极电性连接所述第二控制节点，其第八输入极电性连接所述输出端，其第八输出极电性连接所述固定电压；第九晶体管，其第九控制极电性连接所述下一级GOA电路单元输出的扫描信号，其第九输入极电性连接所述输出端，其第九输出极电性连接所述固定电压。
依据本发明的实施例，所述输入控制模块包含第十晶体管，其第十控制极和第十输入极皆电性连接所述前一级GOA电路单元输出的扫描信号，其第十输出极电性连接所述第一控制节点。
依据本发明的实施例，所述输出控制模块包含：第十一晶体管，其第十一控制极电性连接所述第一控制节点，其第十一输入极电性连接所述第一时钟信号，其第十一输出极电性连接所述输出端；第十二晶体管，其第十二控制极电性连接所述第一控制节点，其第十二输入极电性连接所述第一时钟信号；及电容，其两端电性连接所述第一控制节点和所述输出端。
依据本发明的实施例，所述第一时钟信号和所述第二时钟信号互为反相。
 有益效果
相较于现有技术，本发明的GOA电路单元利用第一晶体管和第二晶体管配合第一时钟信号和第二时钟信号的设计，使得所述下拉维持模块在该扫描信号不需输出脉冲期间，仍能持续输出信号以开启该下拉模块。因此该扫描信号在不需输出脉冲期间，仍会因开启的该下拉模块作用而下拉至低电平。所以本发明解决现有技术下拉维持模块无法持续运作的技术问题，具有提升GOA电路单元输出扫描信号稳定性的有益效果。
 附图说明
图1是本发明的液晶显示器的功能方块图。
图2是本发明第一实施例的GOA电路单元的电路图。
图3是图2所示各种输入信号、输出信号和节点电压的时序图。
图4是本发明第二实施例的GOA电路单元的电路图。
图5是图4所示各种输入信号、输出信号和节点电压的时序图。
 本发明的最佳实施方式
请参阅图1，图1是本发明的液晶显示器10的功能方块图。液晶显示器10包含玻璃基板14、时序控制器30以及源极驱动器(source driver)16。玻璃基板14上设置数个呈矩阵排列的像素(pixel)和栅极驱动(GOA)电路12，而每一个像素包含三个分别代表红绿蓝(RGB)三原色的像素单元20构成。时序控制器30用来产生时钟信号CK1-CK2以及起始信号STV。GOA电路12每隔一固定间隔输出扫描信号使得每一行的晶体管22依序开启，同时源极驱动器16则输出对应的数据信号至一整列的像素单元20使其充电到各自所需的电压，以显示不同的灰阶。当同一行充电完毕后，GOA电路12便将该行的扫描信号关闭，然后GOA电路12再输出扫描信号将下一行的晶体管22打开，再由源极驱动器16对下一行的像素单元20进行充放电。如此依序下去，直到所有像素单元20都充电完成，再从第一行开始充电。以一个1024 × 768分辨率的液晶显示器10以及60Hz的更新频率为例，共需要1024 × 768 × 3个像素单元20组合而成，每一个画面的显示时间约为1/60=16.67ms。图1所示的GOA电路12 控制包含N个GOA电路单元SR(1)、…、SR(N)，N等于768。
请参阅图1和图2，图2是本发明第一实施例的GOA电路单元SR(n)的电路图。为了让液晶显示器10的非显示区(也就是玻璃基板14放置GOA电路12的区域)变窄，GOA电路12直接设置在玻璃基板14上。GOA电路12包含数个串接(cascade-connected)的GOA电路单元SR(n)， n=0~N。当GOA电路单元SR(1)接收到启始信号STV时，就会依据时钟信号CK1和CK2产生扫描信号G(1)。接下来，每一级GOA电路单元SR(n)用来依据前一级GOA电路单元SR(n-1)输出的扫描信号G(n-1)、下一级GOA电路单元SR(n+1)输出的扫描信号G(n+1)、第一时钟信号CK1、第二时钟信号CK2，在输出端OUT输出扫描信号G(n)。第一时钟信号CK1和第二时钟信号CK2互为反相。
每一级GOA电路单元SR(n)包含输入控制模块100、输出控制模块200、下拉模块300和下拉维持模块400。输入控制模块100用来于接收前一级GOA电路单元SR(n-1)输出的扫描信号G(n-1)时导通，以控制第一控制节点Q的电平。输出控制模块200电性连接所一控制节点Q，用来依据施加于第一控制节点Q的电压，控制输出的扫描信号G(n)。下拉模块300电性连接输出控制模块200，用来依据第二控制节点P的电平下拉扫描信号G(n)的电平。
下拉维持模块400电性连接下拉模块300，用来维持第二控制节点P在非扫描期间的电平，以维持扫描信号G(n)的低电平。下拉维持模块400包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6。第一晶体管T1的第一控制端和第一输入端皆电性连接第一时钟信号CK1。第二晶体管T2的第二控制端和第二输出端皆电性连接第二时钟信号CK2。第三晶体管T3的第三控制端和第三输入端皆电性连接第一晶体管T1的第一输出端。第四晶体管T4的第四控制端电性连接第一控制节点Q，其第四输入端电性连接第三晶体管T3的第三输出端，其第四输出端电性连接固定低电压Vss。第五晶体管T5的第五控制端电性连接第三晶体管T3的第三输出端，其第五输入端电性连接第一晶体管T1的第一输出端，其第五输出端电性连接第二控制节点P。第六晶体管T6的第六控制端电性连接第一控制节点Q，其第六输入端电性连接第二控制节点P，其第六输出端电性连接固定低电压Vss。
下拉模块300包含第七晶体管T7、第八晶体管T8和第九晶体管T9。第七晶体管T7的第七控制极电性连接第二控制节点P，其第七输入极电性连接第一控制节点Q，其第七输出极电性连接固定低电压Vss。第八晶体管T8的第八控制极电性连接第二控制节点P，其第八输入极电性连接输出端OUT，其第八输出极电性连接固定低电压Vss。第九晶体管T9的第九控制极电性连接下一级GOA电路单元SR(n+1)输出的扫描信号G(n+1)，其第九输入极电性连接输出端OUT，其第九输出极电性连接固定低电压Vss。
输入控制模块100包含第十晶体管T10。第十晶体管T10的第十控制极和第十输入极皆电性连接前一级GOA电路单元SR(n-1)输出的扫描信号G(n-1)，其第十输出极电性连接第一控制节点Q。
输出控制模块200包含第十一晶体管T11、第十二晶体管T12和电容Cbt。第十一晶体管T11的第十一控制极电性连接第一控制节点Q，其第十一输入极电性连接第一时钟信号CK1，其第十一输出极电性连接输出端OUT。第十二晶体管T12的第十二控制极电性连接第一控制节点Q，其第十二输入极电性连接第一时钟信号CK1。电容Cbt的两端电性连接第一控制节点Q和输出端OUT。
图2的GOA电路单元SR(n)的所有晶体管皆为N型金氧半导体(N-type metal oxide semiconductor，NMOS)晶体管。较佳地，所有晶体管T1-T12的控制极、输入极和输出极分别是晶体管T1-T12的栅极、漏极和源极。晶体管T1-T12的输入极和输出极也分别可以是晶体管的源极和漏极。
请一并参阅图3，图3是图2所示各种输入信号、输出信号和节点电压的时序图。每一GOA电路单元SR(n)自接收到扫描信号G(n-1)起到输出扫描信号G(n)的期间，亦即图3所示的t2-t3，称之为扫描期间，其余时间称为非扫描期间。扫描期间又分为预充电期间(t2)及输出脉冲期间(t3)。
在时段t1时，晶体管T1的第一控制极接收高电平的第一时钟信号CK1时，晶体管T1开启使得高电平的第一时钟信号CK1传送至晶体管T3的第三控制极。晶体管T3开启使得高电平的第一时钟信号CK1传送至晶体管T5的第五控制极。晶体管T5开启使得高电平的第一时钟信号CK1传送至第二控制节点P。晶体管T8开启导通固定低电压Vss至输出端OUT，使得扫描信号G(n)处于低电平。
在时段t2时，晶体管T10的第十控制极接收高电平的扫描信号G(n-1)时，晶体管T10开启使得第一控制节点Q处于高电平，使得晶体管T4、T6、T11、T12开启。此时，晶体管T11导通低电平的第一时钟信号CK1至输出端OUT，因此扫描信号G(n)亦处于低电平。同时，晶体管T6导通固定低电压Vss至第二控制节点P。
在时段t3时，虽然晶体管T10因接收低电平的扫描信号G(n-1)而关闭，但是电容Cbt存储电荷之故，使得第一控制节点Q仍维持高电平。此时，晶体管T11导通高电平的第一时钟信号CK1至输出端OUT，因此扫描信号G(n)处于高电平。
在时段t4时，晶体管T2的第二控制极接收高电平的第二时钟信号CK2时，晶体管T2开启使得高电平的第二时钟信号CK2传送至晶体管T3的第三控制极。晶体管T3开启使得高电平的第二时钟信号CK2传送至晶体管T5的第五控制极。晶体管T5开启使得高电平的第二时钟信号CK2传送至第二控制节点P。晶体管T8开启导通固定低电压Vss至输出端OUT，使得扫描信号G(n)处于低电平。
相较于现有技术，本发明的GOA电路单元利用第一晶体管T1和第二晶体管T2配合第一时钟信号CK1和第二时钟信号CK2的设计，使得下拉维持模块400在扫描信号G(n)不需输出脉冲期间，仍能持续输出信号以开启下拉模块300。因此扫描信号G(n)在不需输出脉冲期间，仍会因开启的下拉模块300作用而下拉至低电平。所以本发明解决现有技术下拉维持模块无法持续运作的技术问题，具有提升GOA电路单元输出扫描信号稳定性的有益效果。
请参阅图4，图4是本发明第二实施例的GOA电路单元SR(n)的电路图。图4的实施例与图2的实施例差异在于下拉维持模块400的电路结构不同。下拉维持模块400包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6。第一晶体管T1的第一控制端和第一输入端皆电性连接第一时钟信号CK1。第二晶体管T2的第二控制端和第二输入端皆电性连接第一时钟信号CK1，其第二输出端电性连接第二控制节点P。第三晶体管T3的第三控制端和第三输入端皆电性连接第二时钟信号CK2。第四晶体管T4的第四控制端电性连接第一控制节点Q，其第四输入端电性连接第三晶体管T3的第三输出端，其第四输出端电性连接固定低电压Vss。第五晶体管T5的第五控制端和第五输入端皆电性连接第二时钟信号CK2，其第五输出端电性连接第二控制节点P。第六晶体管T6的第六控制端电性连接第一控制节点Q，其第六输入端电性连接第二控制节点P，其第六输出端电性连接固定低电压Vss。
请一并参阅图5，图5是图4所示各种输入信号、输出信号和节点电压的时序图。在时段t1时，晶体管T1的第一控制极接收高电平的第一时钟信号CK1时，晶体管T1开启使得高电平的第一时钟信号CK1传送至晶体管T2的第二控制极。晶体管T2开启使得高电平的第一时钟信号CK1传送至第二控制节点P。晶体管T8开启导通固定低电压Vss至输出端OUT，使得扫描信号G(n)处于低电平。
在时段t2时，晶体管T10的第十控制极接收高电平的扫描信号G(n-1)时，晶体管T10开启使得第一控制节点Q处于高电平，使得晶体管T4、T6、T11、T12开启。此时，晶体管T11导通低电平的第一时钟信号CK1至输出端OUT，因此扫描信号G(n)亦处于低电平。同时，晶体管T6导通固定低电压Vss至第二控制节点P。
在时段t3时，虽然晶体管T10因接收低电平的扫描信号G(n-1)而关闭，但是电容Cbt存储电荷之故，使得第一控制节点Q仍维持高电平。此时，晶体管T11导通高电平的第一时钟信号CK1至输出端OUT，因此扫描信号G(n)处于高电平。
在时段t4时，晶体管T3的第三控制极接收高电平的第二时钟信号CK2时，晶体管T3开启使得高电平的第二时钟信号CK2传送至晶体管T5的第五控制极。晶体管T5开启使得高电平的第二时钟信号CK2传送至第二控制节点P。晶体管T8开启导通固定低电压Vss至输出端OUT，使得扫描信号G(n)处于低电平。
相较于现有技术，本发明的GOA电路单元利用第一晶体管T1和第二晶体管T2配合第一时钟信号CK1和第二时钟信号CK2的设计，使得下拉维持模块400在扫描信号G(n)不需输出脉冲期间，仍能持续输出信号以开启下拉模块300。因此扫描信号G(n)在不需输出脉冲期间，仍会因开启的下拉模块300作用而下拉至低电平。所以本发明解决现有技术下拉维持模块无法持续运作的技术问题，具有提升GOA电路单元输出扫描信号稳定性的有益效果。
本领域技术人员可以根据本发明的电路将其中全部或是部分NMOS晶体管以PMOS晶体管取代，以实现同样功能的GOA电路单元。
综上所述，虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种栅极驱动电路，其包含：
    数个GOA电路单元，数个所述GOA电路单元以串联的方式耦接，每一级GOA电路单元用来依据前一级GOA电路单元输出的扫描信号、下一级GOA电路单元输出的扫描信号、第一时钟信号以及第二时钟信号，在输出端输出扫描信号，其中每一级GOA电路单元包含：
    输入控制模块，用来于接收所述前一级GOA电路单元输出的扫描信号时导通，以控制第一控制节点的电平；
    输出控制模块，电性连接所述第一控制节点，用来依据施加于所述第一控制节点的电压，控制输出的所述扫描信号；
    下拉模块，电性连接所述输出控制模块，用来依据第二控制节点的电平下拉所述扫描信号的电平；及
    下拉维持模块，电性连接所述下拉模块，用来维持所述第二控制节点在非扫描期间的电平，以维持所述扫描信号的低电平，其包含：
    第一晶体管，其第一控制端和第一输入端皆电性连接所述第一时钟信号；
    第二晶体管，其第二控制端和第二输入端皆电性连接所述第二时钟信号；
    第三晶体管，其第三控制端和第三输入端皆电性连接所述第一晶体管的第一输出端；
    第四晶体管，其第四控制端电性连接所述第一控制节点，其第四输入端电性连接所述第三晶体管的第三输出端，其第四输出端电性连接一固定电压；
    第五晶体管，其第五控制端电性连接所述第三晶体管的第三输出端，其第五输入端电性连接所述第一晶体管的第一输出端，其第五输出端电性连接所述第二控制节点；及
    第六晶体管，其第六控制端电性连接所述第一控制节点，其第六输入端电性连接所述第二控制节点，其第六输出端电性连接所述固定电压，
    其中所述第一时钟信号和所述第二时钟信号互为反相，且所述下拉模块包含：
    第七晶体管，其第七控制极电性连接所述第二控制节点，其第七输入极电性连接所述第一控制节点，其第七输出极电性连接所述固定电压；
    第八晶体管，其第八控制极电性连接所述第二控制节点，其第八输入极电性连接所述输出端，其第八输出极电性连接所述固定电压；
    第九晶体管，其第九控制极电性连接所述下一级GOA电路单元输出的扫描信号，其第九输入极电性连接所述输出端，其第九输出极电性连接所述固定电压。
  2. 如权利要求1所述的栅极驱动电路，其中所述输入控制模块包含第十晶体管，其第十控制极和第十输入极皆电性连接所述前一级GOA电路单元输出的扫描信号，其第十输出极电性连接所述第一控制节点。
  3. 如权利要求2所述的栅极驱动电路，其中所述输出控制模块包含：
    第十一晶体管，其第十一控制极电性连接所述第一控制节点，其第十一输入极电性连接所述第一时钟信号，其第十一输出极电性连接所述输出端；
    第十二晶体管，其第十二控制极电性连接所述第一控制节点，其第十二输入极电性连接所述第一时钟信号；及
    电容，其两端电性连接所述第一控制节点和所述输出端。
  4. 一种栅极驱动电路，其包含：
    数个GOA电路单元，数个所述GOA电路单元以串联的方式耦接，每一级GOA电路单元用来依据前一级GOA电路单元输出的扫描信号、下一级GOA电路单元输出的扫描信号、第一时钟信号以及第二时钟信号，在输出端输出扫描信号，其中每一级GOA电路单元包含：
    输入控制模块，用来于接收所述前一级GOA电路单元输出的扫描信号时导通，以控制第一控制节点的电平；
    输出控制模块，电性连接所述第一控制节点，用来依据施加于所述第一控制节点的电压，控制输出的所述扫描信号；
    下拉模块，电性连接所述输出控制模块，用来依据第二控制节点的电平下拉所述扫描信号的电平；及
    下拉维持模块，电性连接所述下拉模块，用来维持所述第二控制节点在非扫描期间的电平，以维持所述扫描信号的低电平，其包含：
    第一晶体管，其第一控制端和第一输入端皆电性连接所述第一时钟信号；
    第二晶体管，其第二控制端和第二输入端皆电性连接所述第二时钟信号；
    第三晶体管，其第三控制端和第三输入端皆电性连接所述第一晶体管的第一输出端；
    第四晶体管，其第四控制端电性连接所述第一控制节点，其第四输入端电性连接所述第三晶体管的第三输出端，其第四输出端电性连接一固定电压；
    第五晶体管，其第五控制端电性连接所述第三晶体管的第三输出端，其第五输入端电性连接所述第一晶体管的第一输出端，其第五输出端电性连接所述第二控制节点；及
    第六晶体管，其第六控制端电性连接所述第一控制节点，其第六输入端电性连接所述第二控制节点，其第六输出端电性连接所述固定电压。
  5. 如权利要求4所述的栅极驱动电路，其中所述下拉模块包含：
    第七晶体管，其第七控制极电性连接所述第二控制节点，其第七输入极电性连接所述第一控制节点，其第七输出极电性连接所述固定电压；
    第八晶体管，其第八控制极电性连接所述第二控制节点，其第八输入极电性连接所述输出端，其第八输出极电性连接所述固定电压；
    第九晶体管，其第九控制极电性连接所述下一级GOA电路单元输出的扫描信号，其第九输入极电性连接所述输出端，其第九输出极电性连接所述固定电压。
  6. 如权利要求5所述的栅极驱动电路，其中所述输入控制模块包含第十晶体管，其第十控制极和第十输入极皆电性连接所述前一级GOA电路单元输出的扫描信号，其第十输出极电性连接所述第一控制节点。
  7. 如权利要求6所述的栅极驱动电路，其中所述输出控制模块包含：
    第十一晶体管，其第十一控制极电性连接所述第一控制节点，其第十一输入极电性连接所述第一时钟信号，其第十一输出极电性连接所述输出端；
    第十二晶体管，其第十二控制极电性连接所述第一控制节点，其第十二输入极电性连接所述第一时钟信号；及
    电容，其两端电性连接所述第一控制节点和所述输出端。
  8. 如权利要求4所述的栅极驱动电路，其中所述第一时钟信号和所述第二时钟信号互为反相。
  9. 一种栅极驱动电路，其包含：
    数个GOA电路单元，数个所述GOA电路单元以串联的方式耦接，每一级GOA电路单元用来依据前一级GOA电路单元输出的扫描信号、下一级GOA电路单元输出的扫描信号、第一时钟信号以及第二时钟信号，在输出端输出扫描信号，其中每一级GOA电路单元包含：
    输入控制模块，用来于接收所述前一级GOA电路单元输出的扫描信号时导通，以控制第一控制节点的电平；
    输出控制模块，电性连接所述第一控制节点，用来依据施加于所述第一控制节点的电压，控制输出的所述扫描信号；
    下拉模块，电性连接所述输出控制模块，用来依据第二控制节点的电平下拉所述扫描信号的电平；及
    下拉维持模块，电性连接所述下拉模块，用来维持所述第二控制节点在非扫描期间的电平，以维持所述扫描信号的低电平，其包含：
    第一晶体管，其第一控制端和第一输入端皆电性连接所述第一时钟信号；
    第二晶体管，其第二控制端和第二输入端皆电性连接所述第一时钟信号，其第二输出端电性连接所述第二控制节点；
    第三晶体管，其第三控制端和第三输入端皆电性连接所述第二时钟信号；
    第四晶体管，其第四控制端电性连接所述第一控制节点，其第四输入端电性连接所述第三晶体管的第三输出端，其第四输出端电性连接一固定电压；
    第五晶体管，其第五控制端和第五输入端皆电性连接所述第二时钟信号，其第五输出端电性连接所述第二控制节点；及
    第六晶体管，其第六控制端电性连接所述第一控制节点，其第六输入端电性连接所述第二控制节点，其第六输出端电性连接所述固定电压。
  10. 如权利要求9所述的栅极驱动电路，其中所述下拉模块包含：
    第七晶体管，其第七控制极电性连接所述第二控制节点，其第七输入极电性连接所述第一控制节点，其第七输出极电性连接所述固定电压；
    第八晶体管，其第八控制极电性连接所述第二控制节点，其第八输入极电性连接所述输出端，其第八输出极电性连接所述固定电压；
    第九晶体管，其第九控制极电性连接所述下一级GOA电路单元输出的扫描信号，其第九输入极电性连接所述输出端，其第九输出极电性连接所述固定电压。
  11. 如权利要求10所述的栅极驱动电路，其中所述输入控制模块包含第十晶体管，其第十控制极和第十输入极皆电性连接所述前一级GOA电路单元输出的扫描信号，其第十输出极电性连接所述第一控制节点。
  12. 如权利要求11所述的栅极驱动电路，其中所述输出控制模块包含：
    第十一晶体管，其第十一控制极电性连接所述第一控制节点，其第十一输入极电性连接所述第一时钟信号，其第十一输出极电性连接所述输出端；
    第十二晶体管，其第十二控制极电性连接所述第一控制节点，其第十二输入极电性连接所述第一时钟信号；及
    电容，其两端电性连接所述第一控制节点和所述输出端。
  13. 如权利要求9所述的栅极驱动电路，其中所述第一时钟信号和所述第二时钟信号互为反相。
PCT/CN2016/078726 2016-02-26 2016-04-07 栅极驱动电路 Ceased WO2017143646A1 (zh)

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