WO2017140056A1 - 层堆叠结构、阵列基板和显示装置 - Google Patents

层堆叠结构、阵列基板和显示装置 Download PDF

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Publication number
WO2017140056A1
WO2017140056A1 PCT/CN2016/083119 CN2016083119W WO2017140056A1 WO 2017140056 A1 WO2017140056 A1 WO 2017140056A1 CN 2016083119 W CN2016083119 W CN 2016083119W WO 2017140056 A1 WO2017140056 A1 WO 2017140056A1
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Prior art keywords
layer
conductive
stack structure
via hole
conductive layer
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PCT/CN2016/083119
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English (en)
French (fr)
Inventor
程鸿飞
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京东方科技集团股份有限公司
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Priority to US15/538,289 priority Critical patent/US20180053718A1/en
Publication of WO2017140056A1 publication Critical patent/WO2017140056A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor

Definitions

  • Embodiments of the present disclosure relate to a layer stack structure, an array substrate including the layer stack structure, and a display device including the array substrate.
  • connection structure has a large occupied area and a relatively complicated structure.
  • Embodiments of the present disclosure provide a layer stack structure, an array substrate including the layer stack structure, and a display device including the array substrate, which can solve the problem that the connection structure between different conductive layers in the prior art has a large occupied area and a relatively complicated structure. Technical problem.
  • At least one embodiment of the present disclosure provides a layer stack structure including: a substrate; a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer sequentially stacked in a direction away from the substrate a layer, wherein the first conductive layer and the second conductive layer overlap each other in an overlapping region; the recess portion disposed in the overlapping region includes: a first via penetrating through the first insulating layer a second via hole penetrating the second conductive layer; and a third via hole penetrating the second insulating layer, wherein the first via hole, the second via hole, and the third via hole Connected to each other; and a conductive connecting member extending through the third via, the second via, and the first via of the recess, wherein the first conductive layer and the second conductive
  • the layers are electrically connected to each other by the conductive connecting members, wherein the second conductive layer has at least one protrusion protruding toward the inside of the
  • the conductive connecting member is in the The sidewall of the second via is in direct contact with the second conductive layer, and the conductive connection member is in direct contact with the upper surface of the first conductive layer at the bottom of the first via.
  • a vertical projection of the second via hole on the substrate substrate is located within a vertical projection of the third via hole on the substrate substrate, And the conductive connection member is in direct contact with the upper surface of the second conductive layer at the bottom of the third via.
  • a vertical projection of the second via hole on the substrate substrate is located within a vertical projection of the first via hole on the substrate substrate, And the conductive connection member is in direct contact with the lower surface of the second conductive layer at the top of the first via.
  • the recess portion further includes a fourth via hole penetrating the first conductive layer, and the fourth via hole and the first via hole communicate with each other,
  • the conductive connection member extends through the fourth via to directly contact the upper surface of the base substrate at the bottom of the fourth via.
  • the first via hole, the second via hole, and the third via hole are completely filled by the conductive connection member.
  • the second via has first and second sidewalls opposite to each other, and the at least one protrusion is included in the first sidewall At least one of the upper protrusions protruding toward the second side wall and at least one second protrusion protruding toward the first side wall on the second side wall.
  • the second via hole further has a third sidewall and a fourth sidewall opposite to each other, and the at least one boss portion is further included in the third At least one third protrusion protruding toward the fourth side wall and at least one fourth protrusion protruding toward the third side wall on the fourth side wall.
  • the first protrusion portion, the second protrusion portion, the third protrusion portion, and the fourth protrusion portion do not contact each other.
  • a vertical projection of the first via hole on the substrate substrate and a vertical projection of the second via hole on the substrate substrate coincide with each other.
  • the conductive connecting member is transparent A conductive metal oxide is formed.
  • a planar shape of the at least one convex portion is a square, a rectangle, a semicircle, or a polygon.
  • the first via hole, the second via hole, and the third via hole are partially filled by the conductive connection member.
  • At least one embodiment of the present disclosure further provides an array substrate including any one of the above stacked layers, and a pixel unit formed on the base substrate, wherein the pixel unit is located in a display area of the base substrate
  • the layer stack structure is located in a peripheral circuit region surrounding the display area.
  • the pixel unit includes a thin film transistor including a gate electrode and a gate insulating layer sequentially stacked in a direction away from the substrate.
  • the layer is the same layer
  • the second conductive layer is disposed in the same layer as the source and drain electrodes and is formed of the same material
  • the second insulating layer is the same layer as the passivation layer
  • the conductive layer The connection member and the pixel electrode are formed of the same material.
  • a semiconductor pattern layer is further disposed between the second conductive layer and the first insulating layer, and the semiconductor pattern layer is disposed in the same layer as the active layer.
  • the recessed portion further includes a fifth via hole penetrating the semiconductor pattern layer, the fifth via hole and the first via hole and the second via hole communicating with each other, the conductive A connecting member extends through the fifth via.
  • At least one embodiment of the present disclosure also provides a display device including any of the above array substrates.
  • the two conductive layers located in different layers are electrically connected to each other via the conductive connecting members extending through the same recess The connection thus enables a reliable electrical connection by means of a simpler and smaller footprint.
  • FIG. 1 is a schematic plan view of a layer stack structure according to Embodiment 1 of the present disclosure
  • FIG. 2 is a schematic cross-sectional view of the layer stack structure shown in FIG. 1 taken along line A1-A2;
  • FIG. 3 is a schematic cross-sectional view showing a modification of the layer stack structure according to Embodiment 1 of the present disclosure
  • FIG. 4 is a schematic cross-sectional view showing another modification of the layer stack structure according to Embodiment 1 of the present disclosure
  • FIG. 5 is a schematic plan view of a layer stack structure according to Embodiment 2 of the present disclosure.
  • Figure 6 is a schematic cross-sectional view of the layer stack structure shown in Figure 5 taken along line A1-A2;
  • Figure 7 is a schematic cross-sectional view of the layer stack structure shown in Figure 5 taken along line B1-B2;
  • FIG. 8 is a schematic plan view of a layer stack structure provided by an example of Embodiment 2 of the present disclosure.
  • Figure 9 is a schematic cross-sectional view of the layer stack structure shown in Figure 8 taken along line A1-A2;
  • FIG. 10 is a schematic plan view showing a layer stack structure according to Embodiment 3 of the present disclosure.
  • FIG. 11 is a schematic plan view showing a layer stack structure according to Embodiment 4 of the present disclosure.
  • Figure 12 is a schematic cross-sectional view of the layer stack structure shown in Figure 11 taken along B1-B2;
  • FIG. 13 is a schematic plan view of an array substrate according to Embodiment 5 of the present disclosure.
  • FIG. 14 is a schematic cross-sectional view of the array substrate shown in FIG. 13 taken along line C1-C2.
  • At least one embodiment of the present disclosure provides a layer stack structure, an array substrate including the layer stack structure, and a display device including the array substrate.
  • the layer stack structure includes: a base substrate; a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer sequentially stacked in a direction away from the base substrate, wherein the first conductive layer And the second conductive layer overlaps each other in an overlapping region; the recess portion disposed in the overlapping region includes: a first via penetrating through the first insulating layer; and a second pass through the second conductive layer And a third via hole penetrating through the second insulating layer, wherein the first via, the second via, and the third via are in communication with each other; and a conductive connecting member extending through the recess a third via, the second via, and the first via, wherein the first conductive layer and the second conductive layer are electrically connected to each other through the conductive connecting member.
  • the two conductive layers located in different layers are electrically connected to each other via the conductive connecting members extending through the same recess. Therefore, a reliable electrical connection is achieved by a relatively simple and small footprint structure.
  • FIG. 1 is a schematic plan view of a layer stack structure according to Embodiment 1 of the present disclosure
  • FIG. 2 is a schematic cross-sectional view of the layer stack structure of FIG. 1 taken along line A1-A2.
  • the layer stack structure 100 includes: a base substrate 101; a first conductive layer 102, a first insulating layer 103, and a second conductive layer 104 which are sequentially stacked in a direction away from the base substrate 101.
  • the recess 107 includes: a first via 108 penetrating the first insulating layer 103; a second via 109 penetrating the second conductive layer 104; and a third via 110 penetrating the second insulating layer 105, wherein The first via 108, the second via 109, and the third via 110 are connected to each other And a conductive connecting member 111 extending through the third via 110, the second via 109, and the first via 108 of the recess 107, wherein the first conductive layer 102 and the second conductive layer
  • the electrically conductive connecting members 111 are electrically connected to each other.
  • each of the first via 108, the second via 109, and the third via 110 may be square, rectangular, circular, elliptical, polygonal, or other irregular shape.
  • the first insulating layer 103 may include only one insulating layer or include a plurality of insulating layers.
  • the second insulating layer 105 may include only one insulating layer or include a plurality of insulating layers.
  • the conductive connecting member 111 completely fills the first via hole 109, the second via hole 109, and the third via hole 110.
  • the conductive connection member 111 is in direct contact with the second conductive layer 104 at the sidewall of the second via 109.
  • the conductive connection member 111 comprehensively covers the sidewall of the second via 109 in the second conductive layer 104.
  • the conductive connection member 111 is in direct contact with the upper surface of the first conductive layer 102 at the bottom of the first via 108.
  • the conductive connection member 111 comprehensively covers the upper surface of the first conductive layer 102 exposed by the first via 108 in the first insulating layer 103.
  • the vertical projection of the first via 108 on the substrate 101 and the vertical projection of the second via 109 on the substrate 101 coincide with each other. That is, the size of the vertical projection of the first via 108 on the substrate 101 is equal to the size of the vertical projection of the second via 109 on the substrate 101, and the second via 109 is on the substrate 101.
  • the vertical projection completely coincides with the range of vertical projection of the first via 108 on the substrate 101.
  • the vertical projection of the second via hole 109 in the second conductive layer 104 on the substrate substrate 101 is located in the second insulating layer 105.
  • the three via holes 110 are within a vertical projection on the base substrate 101. That is, the size of the vertical projection of the second via 109 on the substrate 101 is smaller than the size of the vertical projection of the third via 110 on the substrate 101, and the second via 109 is on the substrate 101.
  • the vertical projection on the whole is located in the range of the vertical projection of the third via 110 on the base substrate 101.
  • the edge of the vertical projection of the second via 109 on the substrate 101 is completely separated from the edge of the vertical projection of the third via 110 on the substrate 101.
  • the conductive connection member 111 is in direct contact with the upper surface of the second conductive layer 104, for example, at the bottom of the third via hole 110 in the second insulating layer 105.
  • the second conductive layer 104 is in direct contact with the conductive connecting member 111 on both the upper surface and the side surface, which is advantageous for improving the electrical connection performance of the second conductive layer 104 and the conductive connecting member 111.
  • FIG. 3 is a schematic cross-sectional view showing a modification of the layer stack structure provided by the above-described first embodiment of the present disclosure.
  • the layer stack structure shown in FIG. 3 may have substantially the same configuration as the layer stack structure provided in the embodiment 1 shown in FIGS. 1 and 2 except for the first opening 108. Therefore, the repeated description of the same components will be omitted herein, and the same reference numerals will be used to refer to the same components.
  • the first via hole 108 of the second via hole 109 in the second conductive layer 104 on the base substrate 101 is located in the first insulating layer 103 on the base substrate 101.
  • the size of the vertical projection of the second via 109 on the substrate 101 is smaller than the size of the vertical projection of the first via 108 on the substrate 101, and the second via 109 is on the substrate 101.
  • the vertical projection on the whole is located in the range of the vertical projection of the third via 110 on the base substrate 101.
  • the edge of the vertical projection of the second via 109 on the substrate 101 is completely separated from the edge of the vertical projection of the first via 108 on the substrate 101.
  • the conductive connection member 111 is in direct contact with the lower surface of the second conductive layer 104, for example, at the top of the first via hole 108 in the first insulating layer 103.
  • the second conductive layer 104 is in direct contact with the conductive connecting member 111 on the upper surface, the lower surface, and the side surface, which is advantageous for improving the electric power of the second conductive layer 104 and the conductive connecting member 111. Connection performance.
  • FIG. 4 shows a schematic cross-sectional view of another variation of the layer stack structure provided by the above-described first embodiment of the present disclosure.
  • the layer stack structure shown in FIG. 4 may have substantially the same configuration as the layer stack structure provided in the embodiment 1 shown in FIGS. 1 and 2 except for the fourth opening 112 and the recess 107'. Therefore, the repeated description of the same components will be omitted herein, and the same reference numerals will be used to refer to the same components.
  • the recess 107' includes, in addition to the first via 108 in the first insulating layer 103, the second via 109 in the first conductive layer 104, and the second insulating layer 105.
  • a fourth via hole 112 penetrating the first conductive layer 102 is further included.
  • the fourth via hole 112 and the first via hole 108 communicate with each other, that is, the first via hole 108, the second via hole 109, the third via hole 110, and the fourth via hole 112 communicate with each other.
  • the depressed portion 107' refers to, for example, a recessed region formed by the first via 108, the second via 109, the third via 110, and the fourth via 112 that communicate with each other.
  • the conductive connection member 111 extends through the third via 110, the second via 109, the first via 108, and the fourth via 112 to directly contact the upper surface of the base substrate 102 at the bottom of the fourth via 112.
  • the conductive connecting member 111 completely fills the recess 107' composed of the first via 108, the second via 109, the third via 110, and the fourth via 112.
  • the base substrate 101 is glass
  • the first conductive layer 102 is a metal layer
  • the material of the conductive connection member 111 is a transparent conductive oxide (eg, indium tin oxide).
  • the adhesion stability of the conductive connecting member 111 to the base substrate 101 is superior to the adhesion stability of the conductive connecting member 111 and the first conductive layer. Therefore, in this case, in the layer stack structure shown in FIG. 4, the adhesion stability of the conductive connecting member 111 on the base substrate 101 can be effectively improved due to the presence of the fourth via hole 112.
  • FIG. 5 is a schematic plan view showing a layer stack structure provided in Embodiment 2 of the present disclosure
  • FIG. 6 is a cross-sectional view showing the layer stack structure of FIG. 5 along the line A1-A2
  • FIG. 7 is a view showing the layer stack structure of FIG. 5 along the B1-B2 line. Schematic diagram of the section;
  • the layer stack structure provided by the second embodiment of the present disclosure may have substantially the same configuration as the layer stack structure provided in the first embodiment except for the first boss portion 115. Therefore, the repeated description of the same components will be omitted herein, and the same reference numerals will be used to refer to the same components.
  • the second via 109 in the second conductive layer 104 has a first sidewall 109-1, a second sidewall 109-2, and a third sidewall. 109-3 and fourth side wall 109-4.
  • the first side wall 109-1 and the second side wall 109-2 of the second via 109 are opposed to each other; the third side wall 109-3 and the fourth side wall 109-4 of the second via 109 are opposed to each other.
  • the second conductive layer 104 has a first protrusion 115 protruding toward the inside of the second via 109 on the first sidewall 109-1 of the second via 109.
  • the first raised portion 115 of the second conductive layer 109 on the first sidewall 109-1 protrudes toward the second sidewall 109-2.
  • the presence of the first raised portion 115 increases the contact area between the conductive connecting member 111 and the second conductive layer 104, and thus the electrical connection performance of the conductive connecting member 111 and the second conductive layer 104 can be improved.
  • the planar shape of the first raised portion 115 may be, for example, a square, a rectangle, a semicircle, a polygon, or other irregular shape.
  • the second conductive layer 104 has only one first boss 115 on the first sidewall 109-1 of the second via 109, It is understood that the number of the first convex portions 115 of the second conductive layer 104 on the first side wall 109-1 is not limited in this embodiment. That is, the second conductive layer 104 may have multiple on the first sidewall 109-1 of the second via 109.
  • the first raised portion 115 In one example, as shown in FIGS. 8 and 9, the second conductive layer 104 is provided on the first sidewall 109-1 of the second via 109 with two first protrusions toward the second sidewall 109-2. Raised portion 115.
  • the two first bosses 115 both protrude toward the inside of the second via 109, for example.
  • the contact area between the conductive connecting member 111 and the second conductive layer 104 is further increased, or the contact point between the conductive connecting member 111 and the second conductive layer is further increased, thereby improving the conductive connecting member 111 and the second.
  • the second conductive layer 104 may further disposed on the first sidewall 109-1 of the second via 109 to protrude from the first protrusion 115 protruding toward the second sidewall 109-2.
  • the layer stack structure provided in Embodiment 3 of the present disclosure may have substantially the same configuration as the layer stack structure provided in Embodiment 2 except for the second bump.
  • the portion 118, the third raised portion 119 and the fourth raised portion 120 are outside. Therefore, the repeated description of the same components will be omitted herein, and the same reference numerals will be used to refer to the same components.
  • the four sidewalls are in accordance with "the first sidewall 109-1, the third sidewall 109-3, and the second sidewall 109-2.
  • the order of the fourth side wall 109-4 and the first side wall 109-1" is sequentially connected.
  • the third sidewall 109-3 connects the first sidewall 109-1 and the second sidewall 109-2 on one side of the first sidewall 109-1 and the second sidewall 109-2.
  • the third side wall 109-3 connects the first side wall 109-1 and the second side wall 109-2 on the left side of the first side wall 109-1 and the second side wall 109-2;
  • the four side walls 109-4 connect the first side wall 109-1 and the second side wall 109-2 on the other side of the first side wall 109-1 and the second side wall 109-2.
  • the fourth side wall 109-4 connects the first side wall 109-1 and the second side wall 109-2 to the right side of the first side wall 109-1 and the second side wall 109-2.
  • the second conductive layer 104 has a second protrusion 118 protruding toward the first sidewall 109-1 on the second sidewall 109-2; the second conductive layer 104 has an orientation on the third sidewall 109-3 The third side wall 109-4 protrudes from the third protrusion 119; the second conductive layer 104 has a fourth protrusion 120 protruding toward the third side wall 109-3 on the fourth side wall 109-4.
  • the first boss portion 115, the second boss portion 118, the third boss portion 119, and the fourth boss portion 120 all protrude toward the inside of the second via hole 109.
  • the second conductive layer 104 is on the four sides of the second via 109 There is a raised portion on each wall.
  • the second conductive layer 104 may have one or more protrusions on each of the four sidewalls of the second via 109.
  • the planar shape of each of the raised portions 115, 118, 119, and 120 may be square, rectangular, semi-circular, polygonal, or other irregular shape.
  • embodiments of the present disclosure do not limit the form and number of sidewalls of the second via 109.
  • the second via 109 may have three sequentially connected sidewalls, or six sequentially connected sidewalls.
  • the second conductive layer 104 has a convex portion protruding toward the inside thereof on each side wall of the second via hole 108.
  • Each side wall of the second via 109 may be a flat surface or a curved surface (eg, a curved surface, a curved surface).
  • the first boss portion 115, the second boss portion 118, the third boss portion 119, and the fourth boss portion 120 are not in contact with each other, thereby facilitating the conductive connecting member 111 and the second conductive portion.
  • the electrical connection performance of layer 104 is improved.
  • FIG. 11 is a schematic plan view of a layer stack structure according to Embodiment 4 of the present disclosure
  • FIG. 12 is a schematic cross-sectional view of the layer stack structure shown in FIG. 11 along B1-B2.
  • the layer stack structure provided in Embodiment 4 of the present disclosure may have the same embodiment.
  • the layer stack structure provided by the two is substantially the same configuration except for the conductive connecting member 111. Therefore, the repeated description of the same components will be omitted herein, and the same reference numerals will be used to refer to the same components.
  • the conductive connecting member 111 partially covers the recess 107.
  • the recess 107 is formed, for example, by the first via 108 in the first insulating layer 103, the second via 109 in the second conductive layer 104, and the third via 110 in the second insulating layer 105.
  • the conductive connection member 111 extends through the third via hole 110, the second via hole 109, and the first via hole 108 to partially fill the recess portion 107.
  • the embodiments of the present disclosure do not limit the degree of filling of the conductive connecting member 111 in the recess, nor restrict the connection manner of the conductive connecting member 111 with the first conductive layer 102 and the second conductive layer 104, as long as the passage is satisfied.
  • the conductive connecting member 111 may be electrically connected to the first conductive layer 102 and the second conductive layer 104.
  • the embodiment provides an array substrate, including the layer stack structure provided by any of the above embodiments. And a pixel unit formed on the base substrate, wherein the pixel unit is located in a display area of the base substrate, the layer stack structure being located in a peripheral circuit area surrounding the display area.
  • the array substrate provided by the embodiment of the present disclosure is used, for example, to constitute a display device.
  • the array substrate includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel units arranged in a matrix.
  • Each of the pixel units includes, for example, a thin film transistor as a switching element and a pixel electrode for controlling alignment of the liquid crystal.
  • the pixel electrode of each pixel unit of the array substrate serves as an anode or a cathode for driving the organic light-emitting material to emit light for a display operation.
  • FIG. 13 is a schematic plan view of an array substrate according to Embodiment 5 of the present disclosure
  • FIG. 14 is a schematic cross-sectional view of the array substrate shown in FIG. 13 along a line C1-C2.
  • the array substrate 200 provided in this embodiment includes a layer stack structure 100' and a plurality of pixel units 400 arranged in a matrix.
  • the layer stack structure 100' may have substantially the same configuration as the layer stack structure 100 shown in FIGS. 1 and 2 except for the semiconductor pattern layer 121. Therefore, the repeated description of the same components will be omitted herein, and the same reference numerals will be used to refer to the same components.
  • the pixel unit 400 is formed on the base substrate 101.
  • the pixel unit 400 is located in the display region 300 of the base substrate 101, and the layer stack structure 100' is located in the peripheral circuit region 500 surrounding the display region 300.
  • the display area 300 refers to a distribution area of the pixel unit 400.
  • the pixel unit 400 includes a thin film transistor TFT and a pixel electrode 207.
  • the thin film transistor TFT includes a gate electrode 202, a gate insulating layer 203, an active layer 204, a source and a drain 205, and a passivation layer 206 which are sequentially stacked in a direction away from the substrate 101.
  • the first conductive layer 102 and the gate electrode 202 are disposed in the same layer and are formed of the same material; the first insulating layer 103 and the gate insulating layer 203 are the same layer; the second conductive layer 104 is disposed in the same source and drain electrode 205
  • the layers are formed of the same material; the second insulating layer 105 is the same layer as the passivation layer 206; the conductive connecting member 111 and the pixel electrode 207 are formed of the same material.
  • a semiconductor pattern layer 121 is further disposed between the second conductive layer 104 and the first insulating layer 103, and the semiconductor pattern layer 121 is disposed in the same layer as the active layer 204 and is formed of the same material.
  • the recessed portion 107" further includes a fifth via hole 122 penetrating the semiconductor pattern layer 121.
  • the fifth via hole 122 and the first via hole 108 and the second via hole 109 communicate with each other, and the conductive connection member 111 Extending through the fifth via 122.
  • the semiconductor pattern layer 121 is not required.
  • the array substrate may include the layer stack provided by any of the above embodiments of the present disclosure. structure.
  • the manufacturing method optionally includes the following steps, optionally in sequence:
  • a first metal thin film is sputter deposited on the base substrate 101, and the material of the first metal thin film is, for example, Cu, Al, Mo, Ti, Cr, W or an alloy of these metal materials. Then performing a patterning process (including photoresist coating, exposure, development, etching, and photoresist stripping) on the first metal film to form the first conductive layer 102 and the gate electrode 202 of the same layer and the same material.
  • the first conductive layer 102 and the gate electrode 202 may be a single layer structure or a multilayer structure such as Mo/Al/Mo, Ti/Cu/Ti, MoTi/Cu, Ti/Cu/Mo, or the like.
  • a first insulating film such as silicon nitride or silicon oxide is deposited on the base substrate 101 on which the first conductive layer 102 and the gate electrode 202 are formed, for example, by Plasma Enhanced Chemical Vapor Deposition (PECVD).
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • the first insulating film can serve as the gate insulating layer 203 and for further forming the first insulating layer 103.
  • the first insulating film has not formed the first via hole 108 at the position of the first insulating layer 103.
  • the first insulating layer 103 and the gate insulating layer 203 may be a single layer structure or a multilayer structure such as silicon oxide/silicon nitride.
  • a semiconductor film is deposited on the base substrate on which the first insulating film is formed, and the material of the semiconductor film is, for example, amorphous silicon, polycrystalline silicon or metal oxide. Then, a patterning process (including photoresist coating, exposure, development, etching, and photoresist stripping) is performed on the semiconductor film to form a semiconductor pattern layer 121 and an active layer 204 of the same layer.
  • the semiconductor pattern layer 121 includes a fifth via hole 122 formed therein.
  • S104 forming a second conductive layer and a source and a drain on the base substrate on which the semiconductor pattern layer and the active layer are formed;
  • a second metal thin film is sputter deposited on the base substrate 101 on which the semiconductor pattern layer 121 and the active layer 204 are formed, and the material of the second metal thin film is, for example, Cu, Al, Mo, Ti, Cr, W Or an alloy of these metal materials; then, performing a patterning process (including photoresist coating, exposure, development, etching, and photoresist stripping) on the second metal film to form the same layer of the same material
  • the second conductive layer 104 and the source and drain electrodes 205 The second conductive layer 104 and the source and drain electrodes 205.
  • the second conductive layer 104 includes, for example, a second via 109.
  • the second conductive layer 104 and the source and drain electrodes 205 may be a single layer structure or a multilayer structure such as Mo/Al/Mo, Ti/Cu/Ti, MoTi/Cu, Ti/Cu/Mo, or the like.
  • S105 forming a second insulating film on the base substrate on which the second conductive layer and the source and the drain are formed.
  • a second insulating film is formed on the base substrate 101 on which the second conductive layer 104 and the source and drain electrodes 205 are formed.
  • the second insulating film can also be formed by depositing silicon nitride or silicon oxide by a PECVD process.
  • the second insulating film can be used for further forming the passivation layer 206 and for further forming the second insulating layer 105.
  • the second insulating film has not formed the third via hole 110 at the position of the second insulating layer 105, and the passivation layer via hole H has not been formed over the drain electrode 205.
  • the second insulating layer 105 and the passivation layer 206 formed by the second insulating film may be a single layer structure or a multilayer structure, such as silicon oxide/silicon nitride, and an organic insulating layer such as an organic resin material or the like may also be used.
  • a patterning process is performed on the base substrate 101 on which the second insulating film is formed to form a passivation layer via hole H and a recess 107" above the drain electrode 206.
  • the second conductive layer 104 is formed
  • the second via hole 109 and the fifth via hole in the semiconductor pattern layer 121 have been formed.
  • the third via hole 110 in the second insulating layer 105 may be formed by using the same etching liquid or using different etching liquids as needed.
  • a first via hole 108 in the first insulating layer 103; a dry etching process may be used to form the passivation layer via hole H, the third via hole 110 in the second insulating layer 105, and the first insulation
  • the first via 108 in the layer 103 After this step is performed, a portion of the upper surface of the first conductive layer 102 is exposed, and a portion of the upper surface of the drain 205 is exposed.
  • a conductive connection member 111 and a pixel electrode 207 are formed on the base substrate 101 on which the passivation layer via hole H and the recess portion 107" above the drain electrode 206 are formed.
  • a transparent metal oxide conductive material layer can be sputtered, such as Indium tin oxide (ITO) or the like is then subjected to a patterning process to form the conductive connecting member 111 and the pixel electrode 207.
  • ITO Indium tin oxide
  • the layer stack structure provided by the embodiment of the present disclosure can be correspondingly formed by the process of forming the pixel unit 400.
  • the embodiment provides a display device, including the array substrate provided by any of the above embodiments.
  • An example of the display device is a liquid crystal display device in which the array substrate and the opposite substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the array substrate is used to apply an electric field to control the orientation of the liquid crystal material, that is, to control the degree of rotation of the liquid crystal molecules, the degree of tilt, or the degree of rotation and tilt to perform a display operation.
  • the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.
  • Another example of the display device is an organic electroluminescence display device in which a pixel electrode of each pixel unit of the array substrate serves as an anode or a cathode for driving the organic light-emitting material to emit light for a display operation.
  • the layer stack structure provided by the present disclosure is not limited to being applied to an array substrate of a display device.
  • the layer stack structure can be applied to any case where it is required to electrically connect two conductive layers located in different layers.
  • the layer stack structure provided by the present disclosure can be used to connect two conductive layers located in different layers.

Abstract

提供一种层堆叠结构(100)、包括该层堆叠结构(100)的阵列基板(200)以及包括该阵列基板的显示装置。该层堆叠结构(100)，包括：衬底基板(101)；在远离所述衬底基板(101)的方向上依次堆叠的第一导电层(102)、第一绝缘层(103)、第二导电层(104)和第二绝缘层(105)，其中，所述第一导电层(102)与所述第二导电层(104)在一重叠区域(106)中彼此重叠，设置在所述重叠区域中的凹陷部(107)，包括：贯通所述第一绝缘层(103)的第一过孔(108)；贯通所述第二导电层(104)的第二过孔(109)；以及贯通所述第二绝缘层(105)的第三过孔(110)，其中，所述第一过孔(108)、所述第二过孔(109)和所述第三过孔(110)彼此连通，以及导电连接构件(111)，延伸通过所述凹陷部(107)的所述第三过孔(110)、所述第二过孔(109)和所述第一过孔(108)，其中，所述第一导电层(102)和所述第二导电层(104)通过所述导电连接构件彼此电性连接。所述第二导电层(104)在所述第二过孔(109)的侧壁上具有朝向所述第二过孔(109)的内部突出的至少一个凸起部(115；118；119；120)。这样，通过较简单且占用面积较小的结构实现可靠的电连接。

Description

层堆叠结构、阵列基板和显示装置 技术领域
本公开的实施例涉及一种层堆叠结构、包括该层堆叠结构的阵列基板以及包括该阵列基板的显示装置。
背景技术
通常，在电子产品的制造过程中通常需要将位于不同层的两导电层电性连接。例如，在显示装置的阵列基板的周边电路区域中，例如采用两个过孔和一个连接导电层来电性连接位于不同层的两导电层，其中一个过孔暴露出两导电层中的一个导电层，另一个过孔暴露出两导电层中的另一个导电层，连接导电层通过两个过孔而电性连接位于不同层的两导电层，但这种连接结构占用面积大且结构相对复杂。
发明内容
本公开的实施例提供一种层堆叠结构、包括该层堆叠结构的阵列基板以及包括该阵列基板的显示装置，能够解决现有技术中不同导电层之间的连接结构占用面积大且结构相对复杂的技术问题。
本公开至少一实施例提供一种层堆叠结构，包括：衬底基板；在远离所述衬底基板的方向上依次堆叠的第一导电层、第一绝缘层、第二导电层和第二绝缘层，其中，所述第一导电层与所述第二导电层在一重叠区域中彼此重叠；设置在所述重叠区域中的凹陷部，包括：贯通所述第一绝缘层的第一过孔；贯通所述第二导电层的第二过孔；以及贯通所述第二绝缘层的第三过孔，其中，所述第一过孔、所述第二过孔和所述第三过孔彼此连通；以及导电连接构件，延伸通过所述凹陷部的所述第三过孔、所述第二过孔和所述第一过孔，其中，所述第一导电层和所述第二导电层通过所述导电连接构件彼此电性连接，其中，所述第二导电层在所述第二过孔的侧壁上具有朝向所述第二过孔的内部突出的至少一个凸起部。
例如，在本公开一实施例提供的层堆叠结构中，所述导电连接构件在所 述第二过孔的侧壁与所述第二导电层直接接触，所述导电连接构件在所述第一过孔的底部与所述第一导电层的上表面直接接触。
例如，在本公开一实施例提供的层堆叠结构中，所述第二过孔在所述衬底基板上的垂直投影位于所述第三过孔在所述衬底基板上的垂直投影以内，且所述导电连接构件在所述第三过孔的底部与所述第二导电层的上表面直接接触。
例如，在本公开一实施例提供的层堆叠结构中，所述第二过孔在所述衬底基板上的垂直投影位于所述第一过孔在所述衬底基板上的垂直投影以内，且所述导电连接构件在所述第一过孔的顶部与所述第二导电层的下表面直接接触。
例如，在本公开一实施例提供的层堆叠结构中，所述凹陷部还包括贯通所述第一导电层的第四过孔，所述第四过孔与所述第一过孔彼此连通，所述导电连接构件延伸通过所述第四过孔以在所述第四过孔底部与所述衬底基板的上表面直接接触。
例如，在本公开一实施例提供的层堆叠结构中，所述第一过孔、所述第二过孔和所述第三过孔被所述导电连接构件完全填满。
例如，在本公开一实施例提供的层堆叠结构中，所述第二过孔具有彼此相对的第一侧壁和第二侧壁，所述至少一个凸起部包括在所述第一侧壁上的至少一个朝向所述第二侧壁突出的第一凸起部，以及在所述第二侧壁上的至少一个朝向所述第一侧壁突出的第二凸起部。
例如，在本公开一实施例提供的层堆叠结构中，所述第二过孔还具有彼此相对的第三侧壁和第四侧壁，所述至少一个凸起部还包括在所述第三侧壁上的至少一个朝向所述第四侧壁突出的第三凸起部，以及在所述第四侧壁上的至少一个朝向所述第三侧壁突出的第四凸起部。
例如，在本公开一实施例提供的层堆叠结构中，所述第一凸起部、所述第二凸起部、所述第三凸起部和所述第四凸起部互不接触。
例如，在本公开一实施例提供的层堆叠结构中，所述第一过孔在所述衬底基板上的垂直投影与所述第二过孔在所述衬底基板上的垂直投影彼此重合。
例如，在本公开一实施例提供的层堆叠结构中，所述导电连接构件由透 明导电金属氧化物形成。
例如，在本公开一实施例提供的层堆叠结构中，所述至少一个凸起部的平面形状为正方形、长方形、半圆形或多边形。
例如，在本公开一实施例提供的层堆叠结构中，所述第一过孔、所述第二过孔和所述第三过孔被所述导电连接构件部分填充。
本公开至少一个实施例还提供一种阵列基板，包括上述任一层堆叠结构，以及形成在所述衬底基板上的像素单元，其中所述像素单元位于所述衬底基板的一显示区域中，所述层堆叠结构位于围绕所述显示区域的周边电路区域中。
例如，在本公开一实施例提供的阵列基板中，所述像素单元包括薄膜晶体管和像素电极，所述薄膜晶体管包括在远离所述衬底基板的方向上依次堆叠的栅极、栅极绝缘层、有源层、源极和漏极、以及钝化层，所述第一导电层与所述栅极设置在同一层且由相同的材料形成，所述第一绝缘层与所述栅极绝缘层为同一层，所述第二导电层与所述源极和漏极设置在同一层且由相同的材料形成，所述第二绝缘层与所述钝化层为同一层，且所述导电连接构件和所述像素电极由相同的材料形成。
例如，在本公开一实施例提供的阵列基板中，所述第二导电层与第一绝缘层之间还设置有半导体图案层，所述半导体图案层与所述有源层设置在同一层且由相同的材料形成，所述凹陷部还包括贯通所述半导体图案层的第五过孔，所述第五过孔与所述第一过孔和所述第二过孔彼此连通，所述导电连接构件延伸通过所述第五过孔。
本公开至少一个实施例还提供一种显示装置，包括上述任一阵列基板。
本公开的实施例提供的层堆叠结构、包括该层堆叠结构的阵列基板以及包括该阵列基板的显示装置中，位于不同层的两导电层经由延伸通过同一个凹陷部的导电连接构件而彼此电连接，因此通过较简单且占用面积较小的结构实现可靠的电连接。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单的介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例， 而非对本公开的限制。附图中各个膜层并非按实际比例绘制。且附图只示出了与本公开实施例的紧密相关的结构，其他结构可在本公开实施例的基础上参考通常设计。
图1为本公开实施例一提供的层堆叠结构的平面示意图；
图2为图1所示的层堆叠结构沿A1-A2线的截面示意图；
图3为本公开实施例一提供的层堆叠结构的一变型的截面示意图；
图4为本公开实施例一提供的层堆叠结构的另一变型的截面示意图；
图5为本公开实施例二提供的层堆叠结构的平面示意图；
图6为图5所示的层堆叠结构沿A1-A2线的截面示意图；
图7为图5所示的层堆叠结构沿B1-B2线的截面示意图；
图8为本公开实施例二的一个示例提供的层堆叠结构的平面示意图；
图9为图8所示的层堆叠结构沿A1-A2线的截面示意图；
图10为本公开实施例三提供的层堆叠结构平面示意图；
图11为本公开实施例四提供的层堆叠结构平面示意图；
图12为图11所示的层堆叠结构沿B1-B2的截面示意图；
图13为本公开实施例五提供的阵列基板的平面示意图；
图14为图13所示的阵列基板沿C1-C2线的截面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。在彼此不冲突的情况下，本公开的不同实施例中的特征可以相互组合。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词 语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”、“顶”、“底”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开至少一实施例提供一种层堆叠结构、包括该层堆叠结构的阵列基板以及包括该阵列基板的显示装置。该层堆叠结构，包括：衬底基板；在远离该衬底基板的方向上依次堆叠的第一导电层、第一绝缘层、第二导电层和第二绝缘层，其中，该第一导电层与该第二导电层在一重叠区域中彼此重叠；设置在该重叠区域中的凹陷部，包括：贯通该第一绝缘层中的第一过孔；贯通该第二导电层中的第二过孔；以及贯通该第二绝缘层中的第三过孔，其中，该第一过孔、该第二过孔和该第三过孔彼此连通；以及导电连接构件，延伸通过该凹陷部的该第三过孔、该第二过孔和该第一过孔，其中，该第一导电层和该第二导电层通过该导电连接构件彼此电性连接。
上述实施例提供的层堆叠结构、包括该层堆叠结构的阵列基板以及包括该阵列基板的显示装置中，位于不同层的两导电层经由延伸通过同一个凹陷部的导电连接构件而彼此电连接，因此通过较简单且占用面积较小的结构实现可靠的电连接。
实施例一
图1为本公开实施例一提供的层堆叠结构的平面示意图；图2为图1的层堆叠结构沿A1-A2线的截面示意图。
参见图1和图2，该层堆叠结构100，包括：衬底基板101；在远离该衬底基板101的方向上依次堆叠的第一导电层102、第一绝缘层103、第二导电层104和第二绝缘层105，其中，该第一导电层102与该第二导电层104在区域106中彼此重叠(区域106可称为重叠区域)；设置在该重叠区域106中的凹陷部107，该凹陷部107包括：贯通该第一绝缘层103的第一过孔108；贯通该第二导电层104的第二过孔109；以及贯通该第二绝缘层105的第三过孔110，其中，该第一过孔108、该第二过孔109和该第三过孔110彼此连 通；以及导电连接构件111，延伸通过该凹陷部107的该第三过孔110、该第二过孔109和该第一过孔108，其中，该第一导电层102和该第二导电层104通过该导电连接构件111彼此电性连接。例如，第一过孔108、第二过孔109和第三过孔110各自的平面形状可以为正方形、长方形、圆形、椭圆形、多边形，或其他不规则形状。这里，第一绝缘层103可以仅包括一层绝缘层或者包括多层绝缘层。类似地，第二绝缘层105可以仅包括一层绝缘层或者包括多层绝缘层。
例如，在本实施例提供的层堆叠结构中，参见图1和图2，例如，导电连接构件111完全填满由第一过孔108、的第二过孔109以及第三过孔110构成的凹陷部107。导电连接构件111在第二过孔109的侧壁与第二导电层104直接接触。例如，导电连接构件111全面性覆盖第二导电层104中的第二过孔109的侧壁。导电连接构件111在第一过孔108的底部与第一导电层102的上表面直接接触。例如，导电连接构件111全面性覆盖第一导电层102的由第一绝缘层103中的第一过孔108暴露的上表面。
例如，如图2所示，第一过孔108在衬底基板101上的垂直投影与第二过孔109在衬底基板101上的垂直投影彼此重合。也就是，第一过孔108在衬底基板101上的垂直投影的尺寸等于第二过孔109在衬底基板101上的垂直投影的尺寸，且第二过孔109在衬底基板101上的垂直投影与第一过孔108在衬底基板101上的垂直投影的范围完全重合。
例如，在本实施例提供的层堆叠结构中，参见图1和图2，第二导电层104中的第二过孔109在衬底基板101上的垂直投影位于第二绝缘层105中的第三过孔110在衬底基板101上的垂直投影以内。也就是说，第二过孔109的在衬底基板101上的垂直投影的尺寸小于第三过孔110在衬底基板101上的垂直投影的尺寸，且第二过孔109在衬底基板101上的垂直投影整体位于第三过孔110在衬底基板101上的垂直投影的范围之中。例如，第二过孔109在衬底基板101上的垂直投影的边缘与第三过孔110在衬底基板101上的垂直投影的边缘完全分离。在此情况下，导电连接构件111例如在第二绝缘层105中的第三过孔110的底部与第二导电层104的上表面直接接触。这样，第二导电层104在上表面和侧面均与导电连接构件111直接接触，有利于改善第二导电层104与导电连接构件111的电连接性能。
例如，图3示出了本公开上述实施例一提供的层堆叠结构的一变型的截面示意图。图3示出的层堆叠结构可具有与图1和图2示出的实施例一提供的层堆叠结构基本上相同的构造，除了第一开口108之外。因此，这里将省略相同部件的重复描述，并且相同的术语和相同的附图标记用于表示相同的部件。
在图3所示的层堆叠结构中，第二导电层104中的第二过孔109在衬底基板101上的垂直投影位于第一绝缘层103中的第一过孔108在衬底基板101上的垂直投影以内。也就是说，第二过孔109的在衬底基板101上的垂直投影的尺寸小于第一过孔108在衬底基板101上的垂直投影的尺寸，且第二过孔109在衬底基板101上的垂直投影整体位于第三过孔110在衬底基板101上的垂直投影的范围之中。例如，第二过孔109在衬底基板101上的垂直投影的边缘与第一过孔108在衬底基板101上的垂直投影的边缘完全分离。在此情况下，导电连接构件111例如在第一绝缘层103中的第一过孔108的顶部与第二导电层104的下表面直接接触。这样，在图3所示的层堆叠结构中，第二导电层104在上表面、下表面和侧面均与导电连接构件111直接接触，有利于改善第二导电层104与导电连接构件111的电连接性能。
例如，图4示出了本公开上述实施例一提供的层堆叠结构的另一变型的截面示意图。图4示出的层堆叠结构可具有与图1和图2示出的实施例一提供的层堆叠结构基本上相同的构造，除了第四开口112和凹陷部107'之外。因此，这里将省略相同部件的重复描述，并且相同的术语和相同的附图标记用于表示相同的部件。
在图4所示的层堆叠结构中，凹陷部107'除了包括第一绝缘层103中的第一过孔108、第一导电层104中的第二过孔109和第二绝缘层105中的第三过孔110之外，还包括贯通第一导电层102的第四过孔112。第四过孔112与第一过孔108彼此连通，也就是，第一过孔108、第二过孔109、第三过孔110和第四过孔112彼此连通。在本实施例中，凹陷部107'例如是指彼此连通的第一过孔108、第二过孔109、第三过孔110和第四过孔112构成的凹陷区域。
导电连接构件111延伸通过第三过孔110、第二过孔109、第一过孔108和第四过孔112以在第四过孔112底部与衬底基板102的上表面直接接触。 例如，导电连接构件111完全填满由第一过孔108、的第二过孔109、第三过孔110以及第四过孔112构成的凹陷部107'。例如，在一个示例中，衬底基板101为玻璃，第一导电层102为金属层，导电连接构件111的材料为透明导电氧化物(例如，氧化铟锡)。在此情况下，例如导电连接构件111与衬底基板101的附着稳定性优于导电连接构件111与第一导电层的附着稳定性。因此，在此情况下，图4所示的层堆叠结构中，由于第四过孔112的存在可有效改善导电连接构件111在衬底基板101上的附着稳定性。
实施例二
图5示出本公开实施例二提供的层堆叠结构的平面示意图；图6示出图5中层堆叠结构沿A1-A2线的截面示意图；图7示出图5中层堆叠结构沿B1-B2线的截面示意图；
本公开实施例二提供的层堆叠结构可具有与实施例一提供的层堆叠结构基本上相同的构造，除了第一凸起部115之外。因此，这里将省略相同部件的重复描述，并且相同的术语和相同的附图标记用于表示相同的部件。
在本实施例提供的层堆叠结构中，如图5所示，第二导电层104中的第二过孔109具有第一侧壁109-1、第二侧壁109-2、第三侧壁109-3和第四侧壁109-4。第二过孔109的第一侧壁109-1和第二侧壁109-2彼此相对；第二过孔109的第三侧壁109-3和第四侧壁109-4彼此相对。如图5至图7所示，第二导电层104在第二过孔109的第一侧壁109-1上具有朝向第二过孔109的内部突出的一个第一凸起部115。例如，第二导电层109在第一侧壁109-1上的第一凸起部115朝向第二侧壁109-2突出。
第一凸起部115的存在增大了导电连接构件111与第二导电层104之间的接触面积，因此可以改善导电连接构件111与第二导电层104的电连接性能。该第一凸起部115的平面形状例如可以为正方形、长方形、半圆形、多边形，或其他不规则形状。
尽管在图5、图6和图7示出的层堆叠结构中，第二导电层104在第二过孔109的第一侧壁109-1上仅具有一个第一凸起部115，但应理解本实施例中并不限制第二导电层104在第一侧壁109-1上的第一凸起部115的个数。也就是，第二导电层104在第二过孔109的第一侧壁109-1上可以具有多个 第一凸起部115。在一个示例中，如图8和图9所示，第二导电层104在第二过孔109的第一侧壁109-1上设置有两个朝向第二侧壁109-2突出的第一凸起部115。该两个第一凸起部115例如均朝向第二过孔109的内部突出。这样，进一步增加了导电连接构件111与第二导电层104之间的接触面积，或者进一步增加了导电连接构件111与第二导电层之间的接触点，进而改善了导电连接构件111与第二导电层104的电连接性能。类似的，第二导电层104在第二过孔109第一侧壁109-1上还可以设置更多的朝向第二侧壁109-2突出的第一凸起部115。
实施例三
图10示出了本公开实施例三提供的层堆叠结构平面示意图；本公开实施例三提供的层堆叠结构可具有与实施例二提供的层堆叠结构基本上相同的构造，除了第二凸起部118、第三凸起部119和第四凸起部120之外。因此，这里将省略相同部件的重复描述，并且相同的术语和相同的附图标记用于表示相同的部件。
如图10所示，在本实施例提供的层堆叠结构中，例如，上述四个侧壁按照“第一侧壁109-1、第三侧壁109-3、第二侧壁109-2、第四侧壁109-4、第一侧壁109-1”的顺序依次连接。第三侧壁109-3在第一侧壁109-1和第二侧壁109-2的一侧连接第一侧壁109-1和第二侧壁109-2。如图10所示，第三侧壁109-3在第一侧壁109-1和第二侧壁109-2的左侧连接第一侧壁109-1和第二侧壁109-2；第四侧壁109-4在第一侧壁109-1和第二侧壁109-2的另一侧连接第一侧壁109-1和第二侧壁109-2。如图10所示，第四侧壁109-4在第一侧壁109-1和第二侧壁109-2的右侧连接第一侧壁109-1和第二侧壁109-2。第二导电层104在第二侧壁109-2上具有一个朝向第一侧壁109-1突出的第二凸起部118；第二导电层104在第三侧壁109-3上具有一个朝向第四侧壁109-4突出的第三凸起部119；第二导电层104在第四侧壁109-4上具有一个朝向第三侧壁109-3突出的第四凸起部120。第一凸起部115、第二凸起部118、第三凸起部119和第四凸起部120均朝向第二过孔109的内部突出。
在图10示出的层堆叠结构中，第二导电层104在第二过孔109的四个侧 壁上各有一个凸起部。在另一示例中，第二导电层104在第二过孔109的四个侧壁上可以各有一个或多个凸起部。各个凸起部115、118、119和120的平面形状可以为正方形，长方形，半圆形、多边形，或其他不规则形状。
此外，本公开的实施例并不限制第二过孔109的侧壁的形式和个数，例如，第二过孔109可以具有三个依次连接的侧壁，或六个顺次连接的侧壁。例如，第二导电层104在第二过孔108的每个侧壁上具有一个朝向其内部突出的凸起部。第二过孔109的每个侧壁可以为平坦表面或弯曲表面(例如弧形表面、弯折表面)。
例如，如图10所示，第一凸起部115、第二凸起部118、第三凸起部119和第四凸起部120互不接触，从而有利于导电连接构件111与第二导电层104的电连接性能的改善。
实施例四
图11为本公开实施例四提供的层堆叠结构平面示意图；图12为图11所示的层堆叠结构沿B1-B2的截面示意图；本公开实施例四提供的层堆叠结构可具有与实施例二提供的层堆叠结构基本上相同的构造，除了导电连接构件111之外。因此，这里将省略相同部件的重复描述，并且相同的术语和相同的附图标记用于表示相同的部件。
例如，如图11和图12所示，导电连接构件111部分覆盖凹陷部107。在本实施例中，凹陷部107例如由第一绝缘层103中的第一过孔108、第二导电层104中的第二过孔109以及第二绝缘层105中的第三过孔110构成。导电连接构件111延伸通过第三过孔110、第二过孔109和第一过孔108而部分地填充该凹陷部107。
应理解，本公开的实施例并不限制导电连接构件111在凹陷部中的填充程度，也并不限制导电连接构件111与第一导电层102和第二导电层104的连接方式，只要满足通过导电连接构件111实现第一导电层102和第二导电层104的电性连接即可。
实施例五
本实施例提供一种阵列基板，包括上述任一实施例提供的层堆叠结构， 以及形成在所述衬底基板上的像素单元，其中所述像素单元位于所述衬底基板的一显示区域中，所述层堆叠结构位于围绕所述显示区域的周边电路区域中。
本公开的实施例提供的阵列基板例如用于构成显示装置。该阵列基板包括多条栅线和多条数据线，这些栅线和数据线彼此交叉由此限定了排列为矩阵的像素单元。每个像素单元例如包括作为开关元件的薄膜晶体管和用于控制液晶的排列的像素电极。或者，阵列基板的每个像素单元的像素电极作为阳极或阴极用于驱动有机发光材料发光以进行显示操作。
图13示出了本公开实施例五提供的阵列基板的平面示意图；图14为图13所示的阵列基板沿C1-C2线的截面示意图。本实施例提供的阵列基板200，例如，如图13所示，包括层堆叠结构100'和呈矩阵排列的多个像素单元400。层堆叠结构100'可具有与图1和2所示的层堆叠结构100基本上相同的构造，除了半导体图案层121之外。因此，这里将省略相同部件的重复描述，并且相同的术语和相同的附图标记用于表示相同的部件。像素单元400形成在衬底基板101上。该像素单元400位于衬底基板101的显示区域300中，层堆叠结构100'位于围绕显示区域300的周边电路区域500中。这里，显示区域300是指所述像素单元400的分布区域。
例如，如图14所示，像素单元400包括薄膜晶体管TFT和像素电极207。薄膜晶体管TFT包括在远离衬底基板101的方向上依次堆叠设置的栅极202、栅极绝缘层203、有源层204、源极和漏极205、和钝化层206。第一导电层102与栅极202设置在同一层且由相同的材料形成；第一绝缘层103与栅极绝缘层203为同一层；第二导电层104与源极和漏极205设置在同一层且由相同的材料形成；第二绝缘层105与钝化层206为同一层；导电连接构件111和像素电极207由相同的材料形成。
如图14所示，第二导电层104与第一绝缘层103之间还设置有半导体图案层121，该半导体图案层121与有源层204设置在同一层且由相同的材料形成。凹陷部107”还包括贯通所述半导体图案层121的第五过孔122。所述第五过孔122与所述第一过孔108和所述第二过孔109彼此连通，导电连接构件111延伸通过第五过孔122。可以理解的是，半导体图案层121并不是必须的。此外，该阵列基板可以包括本公开的上述任一实施例提供的层堆叠 结构。
以下，描述一种图13和14所示的阵列基板的制造方法。该制造方法例如可选地顺次包括如下步骤：
S101：在衬底基板101上形成第一导电层与栅极；
在衬底基板101上溅射沉积第一金属薄膜，该第一金属薄膜的材料例如为Cu、Al、Mo、Ti、Cr、W或者这些金属材料的合金。然后对该第一金属薄膜执行一次图案化工艺(包括光刻胶涂覆、曝光、显影、刻蚀及光刻胶剥离等步骤)以形成同层同材料的第一导电层102与栅极202。第一导电层102与栅极202可以是单层结构，也可以是多层结构，如Mo/Al/Mo,Ti/Cu/Ti,MoTi/Cu,Ti/Cu/Mo等。
S102：在形成有第一导电层与栅极的衬底基板上形成第一绝缘薄膜；
在形成有第一导电层102与栅极202的衬底基板101上例如通过等离子体增强化学气相沉积工艺(Plasma Enhanced Chemical Vapor Deposition,PECVD)沉积例如氮化硅或氧化硅的第一绝缘薄膜。该第一绝缘薄膜可以作为栅极绝缘层203以及用于后续进一步形成第一绝缘层103。在此步骤完成时，该第一绝缘薄膜在第一绝缘层103的位置处尚未形成第一过孔108。第一绝缘层103和栅极绝缘层203可以是单层结构，也可以是多层结构，例如氧化硅/氮化硅。
S103：在形成有第一绝缘薄膜的衬底基板上形成半导体图案层和有源层；
在形成有上述第一绝缘薄膜的衬底基板上形成半导体图案层和有源层；
在形成有上述第一绝缘薄膜的衬底基板上沉积一半导体薄膜，该半导体薄膜的材料例如为非晶硅、多晶硅或金属氧化物等。然后对该半导体薄膜执行一次图案化工艺(包括光刻胶涂覆、曝光、显影、刻蚀及光刻胶剥离等步骤)以形成同层同材料的半导体图案层121和有源层204。这里，半导体图案层121包括形成在其中的第五过孔122。
S104：在形成有所述半导体图案层和有源层的衬底基板上形成第二导电层以及源极和漏极；
在形成有所述半导体图案层121和有源层204的衬底基板101上溅射沉积第二金属薄膜，该第二金属薄膜的材料例如为Cu、Al、Mo、Ti、Cr、W 或者这些金属材料的合金；然后，对该第二金属薄膜执行一次图案化工艺(包括光刻胶涂覆、曝光、显影、刻蚀及光刻胶剥离等步骤)以形成同层同材料的第二导电层104以及源极和漏极205。这里，第二导电层104例如包括第二过孔109。第二导电层104以及源极和漏极205可以是单层结构，也可以是多层结构，如Mo/Al/Mo,Ti/Cu/Ti,MoTi/Cu,Ti/Cu/Mo等。
S105：在形成有第二导电层与源极和漏极的衬底基板上形成第二绝缘薄膜。
在形成有第二导电层104与源极和漏极205的衬底基板101上形成第二绝缘薄膜。该第二绝缘薄膜也可通过PECVD工艺沉积氮化硅或氧化硅而形成。该第二绝缘薄膜可以用于后续进一步形成钝化层206以及用于后续进一步形成第二绝缘层105。在此步骤完成时，该第二绝缘薄膜在第二绝缘层105的位置处尚未形成第三过孔110，且在漏极205上方尚未形成钝化层过孔H。该第二绝缘薄膜形成的第二绝缘层105与钝化层206可以是单层结构或多层结构，例如氧化硅/氮化硅,也可以采用有机绝缘层，例如有机树脂材料等。
S106：在形成有第二绝缘薄膜的衬底基板上形成钝化层过孔和凹陷部；
对形成有上述第二绝缘薄膜的衬底基板101执行图案化工艺以形成漏极206上方的钝化层过孔H和凹陷部107”。在执行该图案化工艺之前，第二导电层104中的第二过孔109和半导体图案层121中的第五过孔已经形成。可以根据需要采用同一种刻蚀液或者采用不同的刻蚀液形成第二绝缘层105中的第三过孔110以及第一绝缘层103中的第一过孔108；执行该图案化工艺时也可以采用干刻工艺，形成钝化层过孔H、第二绝缘层105中的第三过孔110以及第一绝缘层103中的第一过孔108。执行完此步骤之后，第一导电层102的部分上表面被暴露，漏极205的部分上表面被暴露。
S107：在形成有钝化层过孔和凹陷部的衬底基板上形成导电连接构件和像素电极；
在形成有漏极206上方的钝化层过孔H和凹陷部107”的衬底基板101上形成导电连接构件111和像素电极207。例如，可通过溅射透明金属氧化物导电材料层，如氧化铟锡(Indium tin oxide，ITO)等，然后执行一次图案化工艺来形成导电连接构件111和像素电极207。
从上述描述可知，形成本实施例的阵列基板不需额外增加其他工艺步骤， 通过形成像素单元400的工艺即可对应形成本公开的实施例提供的层堆叠结构。
实施例六
本实施例提供一种显示装置，包括上述任一实施例提供的阵列基板。
该显示装置的一个示例为液晶显示装置，其中，所述阵列基板与对置基板彼此对置以形成液晶盒，在液晶盒中填充有液晶材料。该对置基板例如为彩膜基板。所述阵列基板的每个像素单元的像素电极用于施加电场对液晶材料的取向进行控制，即对液晶分子的旋转的程度、倾斜的程度或旋转和倾斜的程度进行控制从而进行显示操作。在一些示例中，该液晶显示装置还包括为阵列基板提供背光的背光源。
该显示装置的另一个示例为有机电致发光显示装置，其中，阵列基板的每个像素单元的像素电极作为阳极或阴极用于驱动有机发光材料发光以进行显示操作。
可以理解的是，本公开提供的层堆叠结构不仅限于应用到显示装置的阵列基板上。事实上该层堆叠结构可应用到任何需要电性连接位于不同层的两导电层的情况。例如，在印刷电路板中，可以采用本公开提供的层堆叠结构来连接位于不同层的两导电层。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2016年2月17日递交的中国专利申请第201620126200.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (17)

  1. 一种层堆叠结构，包括：
    衬底基板；
    在远离所述衬底基板的方向上依次堆叠的第一导电层、第一绝缘层、第二导电层和第二绝缘层，其中，所述第一导电层与所述第二导电层在一重叠区域中彼此重叠；
    设置在所述重叠区域中的凹陷部，包括：
    贯通所述第一绝缘层的第一过孔；
    贯通所述第二导电层的第二过孔；以及
    贯通所述第二绝缘层的第三过孔，
    其中，所述第一过孔、所述第二过孔和所述第三过孔彼此连通；以及
    导电连接构件，延伸通过所述凹陷部的所述第三过孔、所述第二过孔和所述第一过孔，其中，所述第一导电层和所述第二导电层通过所述导电连接构件彼此电性连接，
    其中，所述第二导电层在所述第二过孔的侧壁上具有朝向所述第二过孔的内部突出的至少一个凸起部。
  2. 如权利要求1所述的层堆叠结构，其中，所述导电连接构件在所述第二过孔的侧壁与所述第二导电层直接接触，所述导电连接构件在所述第一过孔的底部与所述第一导电层的上表面直接接触。
  3. 如权利要求1或2所述的层堆叠结构，其中，所述第二过孔在所述衬底基板上的垂直投影位于所述第三过孔在所述衬底基板上的垂直投影以内，且所述导电连接构件在所述第三过孔的底部与所述第二导电层的上表面直接接触。
  4. 如权利要求1至3中任一项所述的层堆叠结构，其中，所述第二过孔在所述衬底基板上的垂直投影位于所述第一过孔在所述衬底基板上的垂直投影以内，且所述导电连接构件在所述第一过孔的顶部与所述第二导电层的下表面直接接触。
  5. 如权利要求1至4中任一项所述的层堆叠结构，其中，所述凹陷部还包括贯通所述第一导电层的第四过孔，所述第四过孔与所述第一过孔彼此连 通，所述导电连接构件延伸通过所述第四过孔以在所述第四过孔底部与所述衬底基板的上表面直接接触。
  6. 如权利要求1至5中任一项所述的层堆叠结构，其中，所述第一过孔、所述第二过孔和所述第三过孔被所述导电连接构件完全填满。
  7. 如权利要求1至6中任一项所述的层堆叠结构，其中，所述第二过孔具有彼此相对的第一侧壁和第二侧壁，所述至少一个凸起部包括在所述第一侧壁上的至少一个朝向所述第二侧壁突出的第一凸起部，以及在所述第二侧壁上的至少一个朝向所述第一侧壁突出的第二凸起部。
  8. 如权利要求7所述的层堆叠结构，其中，所述第二过孔还具有彼此相对的第三侧壁和第四侧壁，所述至少一个凸起部还包括在所述第三侧壁上的至少一个朝向所述第四侧壁突出的第三凸起部，以及在所述第四侧壁上的至少一个朝向所述第三侧壁突出的第四凸起部。
  9. 如权利要求8所述的层堆叠结构，其中，所述第一凸起部、所述第二凸起部、所述第三凸起部和所述第四凸起部互不接触。
  10. 如权利要求1至9中任一项所述的层堆叠结构，其中，所述第一过孔在所述衬底基板上的垂直投影与所述第二过孔在所述衬底基板上的垂直投影彼此重合。
  11. 如权利要求1至10中任一项所述的层堆叠结构，其中，所述导电连接构件由透明导电金属氧化物形成。
  12. 如权利要求1至11中任一项所述的层堆叠结构，其中，所述至少一个凸起部的平面形状为正方形、长方形、半圆形或多边形。
  13. 如权利要求1至12中任一项所述的层堆叠结构，其中，所述第一过孔、所述第二过孔和所述第三过孔被所述导电连接构件部分填充。
  14. 一种阵列基板，包括权利要求1至13中任一项所述的层堆叠结构，以及形成在所述衬底基板上的像素单元，其中所述像素单元位于所述衬底基板的一显示区域中，所述层堆叠结构位于围绕所述显示区域的周边电路区域中。
  15. 如权利要求14所述的阵列基板，其中，所述像素单元包括薄膜晶体管和像素电极，所述薄膜晶体管包括在远离所述衬底基板的方向上依次堆叠的栅极、栅极绝缘层、有源层、源极和漏极、以及钝化层，所述第一导电层 与所述栅极设置在同一层且由相同的材料形成，所述第一绝缘层与所述栅极绝缘层为同一层，所述第二导电层与所述源极和漏极设置在同一层且由相同的材料形成，所述第二绝缘层与所述钝化层为同一层，且所述导电连接构件和所述像素电极由相同的材料形成。
  16. 如权利要求15所述的阵列基板，其中，所述第二导电层与第一绝缘层之间还设置有半导体图案层，所述半导体图案层与所述有源层设置在同一层且由相同的材料形成，所述凹陷部还包括贯通所述半导体图案层的第五过孔，所述第五过孔与所述第一过孔和所述第二过孔彼此连通，所述导电连接构件延伸通过所述第五过孔。
  17. 一种显示装置，包括权利要求14至16中任一项所述的阵列基板。
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