WO2017140004A1 - 阵列基板及液晶显示装置 - Google Patents

阵列基板及液晶显示装置 Download PDF

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Publication number
WO2017140004A1
WO2017140004A1 PCT/CN2016/075475 CN2016075475W WO2017140004A1 WO 2017140004 A1 WO2017140004 A1 WO 2017140004A1 CN 2016075475 W CN2016075475 W CN 2016075475W WO 2017140004 A1 WO2017140004 A1 WO 2017140004A1
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Prior art keywords
thin film
film transistor
electrostatic protection
protection circuit
data line
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Ceased
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PCT/CN2016/075475
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English (en)
French (fr)
Inventor
徐向阳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/033,637 priority Critical patent/US10288960B2/en
Publication of WO2017140004A1 publication Critical patent/WO2017140004A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/921—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to an array substrate and a liquid crystal display device having the array substrate.
  • the array substrate is a thin film transistor liquid crystal display device such as a thin film transistor liquid crystal display and an important component of the TFT-LCD.
  • the array substrate usually includes a peripheral circuit region and a display region.
  • Static electricity is inevitably generated by factors such as design, and in particular, the static electricity generated in the peripheral circuit region of the array substrate is usually high-voltage static electricity.
  • the problem of static electricity directly affects the yield of the array substrate, which in turn affects the yield of the liquid crystal display device.
  • high-voltage static electricity is released, if there is no effective path on the array substrate to discharge the static electricity in time, it is easy to break down the precision components on the array substrate, especially the components in the display area are extremely precise, and are more easily broken by high-voltage static electricity.
  • thin film transistor arrays which are extremely precise, are easily broken down by high voltage static electricity in the peripheral circuit area, and thin film transistor arrays are key components of the array substrate, which, once broken down, cause poor quality or failure of the liquid crystal display.
  • an ESD ring is usually disposed at the beginning of the lines of the array substrate (for example, the gate lines and the data lines), the electrostatic discharge ring is connected to the short wires, and all the lines in the array substrate are passed.
  • the electrostatic discharge ring is connected to a short wire so that static electricity can be discharged to the ground through a short wire when the static electricity is released.
  • the electrostatic discharge ring and the short wiring connect the circuit in the peripheral circuit region of the array substrate to the circuit in the display region of the array substrate, and the peripheral circuit region of the array substrate is most likely to generate high-voltage static electricity.
  • the precision device located in the display area may still be broken down or damaged.
  • the technical problem to be solved by the present invention is to provide an array substrate, wherein the electrostatic protection circuit of the array substrate can effectively discharge static electricity, and can separate static electricity of the peripheral circuit region from static electricity of the display region, thereby avoiding the periphery.
  • the high voltage electrostatic charge accumulation in the circuit region is excessive or the high voltage electrostatic discharge point breaks through the device in the display region as it approaches the display region.
  • the present invention also provides a liquid crystal display device having the array substrate.
  • the present invention provides an array substrate including a substrate and a plurality of data lines and a plurality of scan lines disposed on the substrate;
  • the substrate includes a display area and is disposed on a circumference of the display area a peripheral circuit area
  • each of the data lines includes a data line outer segment and a data line inner segment
  • each of the scan lines includes a scan line outer segment and a scan line inner segment
  • the data line outer segment and the scan line The outer segment is disposed in the peripheral circuit region, and the inner portion of the data line and the inner segment of the scan line extend from the peripheral circuit region to the display region;
  • the peripheral circuit area is further provided with a short wiring, an enable signal line, a plurality of first thin film transistors, a plurality of second thin film transistors, a plurality of first electrostatic protection circuits, a plurality of second electrostatic protection circuits, and a plurality of third An electrostatic protection circuit and a plurality of fourth electrostatic protection circuits, wherein a gate of each of the first thin film transistors and each of the second thin film transistors is connected to the enable signal line, and the drain of the first thin film transistor a pole is connected to an outer portion of the data line of the data line, a source of the first thin film transistor is connected to a data line inner segment of the same data line; and a drain of each of the second thin film transistors is connected to An outer portion of the scan line of the scan line, a source of the second thin film transistor is connected to a scan line inner segment of the same scan line; and one end of the first electrostatic protection circuit is connected to the data line The other end is connected to the short wire; one end of the second
  • the first electrostatic protection circuit comprises a third thin film transistor, the third thin film transistor a gate and a drain are connected to the outer portion of the data line, a source is connected to the short wire, and the second electrostatic protection circuit includes a fourth thin film transistor, and a gate and a drain of the fourth thin film transistor are connected In the inner segment of the data line, a source is connected to the short wiring.
  • the first electrostatic protection circuit further includes a seventh thin film transistor, the seventh thin film transistor is connected in parallel or in series with the third thin film transistor; the second electrostatic protection circuit further includes an eighth thin film transistor, the first Eight thin film transistors are connected in parallel or in series with the fourth thin film transistor.
  • the third electrostatic protection circuit includes a fifth thin film transistor, a gate and a drain of the fifth thin film transistor are connected to the outer portion of the scan line, and a source of the fifth thin film transistor is connected to the short Wiring
  • the fourth electrostatic protection circuit includes a sixth thin film transistor, a gate and a drain of the sixth thin film transistor are connected to the inner portion of the scan line, and a source of the sixth thin film transistor is connected to the short wiring.
  • the third electrostatic protection circuit further includes a ninth thin film transistor, the ninth thin film transistor is connected in parallel or in series with the fifth thin film transistor; the fourth electrostatic protection circuit further includes a tenth thin film transistor, the Ten thin film transistors are connected in parallel or in series with the sixth thin film transistor.
  • the first thin film transistor and the second thin film transistor are in an on state
  • the enable signal line is in a low level state
  • the first The thin film transistor and the second thin film transistor are in an off state.
  • the display area when the first thin film transistor and the second thin film transistor are in an on state, the display area operates, and when the first thin film transistor and the second thin film transistor are in an off state, the display The district stopped working.
  • the present invention further provides a liquid crystal display device, the liquid crystal display device comprising an array substrate, the array substrate comprising a substrate and a plurality of data lines and a plurality of scan lines disposed on the substrate;
  • the display area and the peripheral circuit area disposed on the circumference side of the display area, each of the data lines includes a data line outer segment and a data line inner segment, and each of the scan lines includes a scan line outer segment and a scan line inner segment
  • the outer portion of the data line and the outer portion of the scan line are disposed in the peripheral circuit region, and the inner portion of the data line and the inner portion of the scan line extend from the peripheral circuit region to the display region;
  • the peripheral circuit area is further provided with a short wiring, an enable signal line, a plurality of first thin film transistors, a plurality of second thin film transistors, a plurality of first electrostatic protection circuits, a plurality of second electrostatic protection circuits, and a plurality of third An electrostatic protection circuit and a plurality of fourth electrostatic protection circuits, each of the first thin film transistors and each of the a gate of the second thin film transistor is connected to the enable signal line, a drain of the first thin film transistor is connected to an outer portion of a data line of the data line, and a source of the first thin film transistor is connected a data line inner segment of the same data line; a drain of each of the second thin film transistors is connected to an outer portion of a scan line of the scan line, and a source of the second thin film transistor is connected to the same strip An inner segment of the scan line of the scan line; one end of the first electrostatic protection circuit is connected to the outer segment of the data line, and the other end is connected to the short wire;
  • the first electrostatic protection circuit includes a third thin film transistor, a gate and a drain of the third thin film transistor are connected to an outer portion of the data line, a source is connected to the short wiring, and the second static electricity
  • the protection circuit includes a fourth thin film transistor having a gate and a drain connected to the inner portion of the data line and a source connected to the short wiring.
  • the first electrostatic protection circuit further includes a seventh thin film transistor, the seventh thin film transistor is connected in parallel or in series with the third thin film transistor; the second electrostatic protection circuit further includes an eighth thin film transistor, the first Eight thin film transistors are connected in parallel or in series with the fourth thin film transistor.
  • the third electrostatic protection circuit includes a fifth thin film transistor, a gate and a drain of the fifth thin film transistor are connected to the outer portion of the scan line, and a source of the fifth thin film transistor is connected to the short Wiring
  • the fourth electrostatic protection circuit includes a sixth thin film transistor, a gate and a drain of the sixth thin film transistor are connected to the inner portion of the scan line, and a source of the sixth thin film transistor is connected to the short wiring.
  • the third electrostatic protection circuit further includes a ninth thin film transistor, the ninth thin film transistor is connected in parallel or in series with the fifth thin film transistor; the fourth electrostatic protection circuit further includes a tenth thin film transistor, the Ten thin film transistors are connected in parallel or in series with the sixth thin film transistor.
  • the first thin film transistor and the second thin film transistor are in an on state
  • the enable signal line is in a low level state
  • the first The thin film transistor and the second thin film transistor are in an off state.
  • the display area when the first thin film transistor and the second thin film transistor are in an on state, The display area operates, and when the first thin film transistor and the second thin film transistor are in an off state, the display area stops working.
  • the drain of the first thin film transistor is connected to the outer portion of the data line of one of the data lines
  • a source of a thin film transistor is connected to a data line inner segment of the same data line
  • a gate of each of the second thin film transistors is connected to the enable signal line
  • a drain of the second thin film transistor is connected to An outer segment of the scan line of the scan line
  • the source of the second thin film transistor is connected to the inner portion of the scan line of the same scan line, that is, the outer segment of the data line is connected to the inner portion of the data line
  • a first thin film transistor is used as a switch
  • a second thin film transistor is connected as a switch between the outer portion of the scan line and the inner portion of the scan line, thereby dividing the data line and the scan line into two parts, a part of which is located in the a peripheral circuit area, another portion is mainly located in the display area, that is,
  • one end of the first electrostatic protection circuit is connected to the outer portion of the data line, and the other end is connected to the short wire.
  • One end of the second electrostatic protection circuit is connected to the inner segment of the data line, and the other end is connected.
  • the third electrostatic protection circuit has one end connected to the outer portion of the scan line, the other end connected to the short wire, and one end of the fourth electrostatic protection circuit is connected to the inner portion of the scan line The other end is connected to the short wire.
  • the outer portion of the data line and the outer portion of the scan line are respectively connected to the short wire, and the inner portion of the data line and the inner portion of the scan line are also respectively connected to The short wiring, wherein the outer portion of the data line and the outer portion of the scan line are located in the peripheral circuit region, and when high voltage static electricity is present in the peripheral circuit region, the high voltage static electricity is directly from the first
  • the electrostatic protection circuit and the third electrostatic protection circuit are transmitted to the short wiring and transmitted to the ground without affecting components in the display area, thereby avoiding accumulation of high voltage electrostatic charge in the peripheral circuit area. Point from electrostatic discharge or high pressure area near the display of the display member sometimes cause breakdown zone.
  • FIG. 1 is a schematic structural view of an array substrate in an embodiment of the present invention.
  • FIG. 2 is a schematic structural view corresponding to part I of FIG. 1 in the first embodiment of the present invention
  • Figure 3 is a schematic structural view corresponding to the portion II of Figure 1 in the first embodiment of the present invention.
  • FIG. 4 is a schematic structural view corresponding to part I of FIG. 1 in the second embodiment of the present invention.
  • Figure 5 is a schematic structural view corresponding to the portion II of Figure 1 in the second embodiment of the present invention.
  • FIG. 6 is a schematic structural view corresponding to part I of FIG. 1 in a third embodiment of the present invention.
  • Figure 7 is a schematic view showing the structure corresponding to the portion II of Figure 1 in the third embodiment of the present invention.
  • connection In the description of the present invention, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined.
  • the ground connection, or the integral connection may be a mechanical connection; it may be directly connected, or may be indirectly connected through an intermediate medium, and may be internal communication between the two elements.
  • the specific meaning of the above terms in the present invention can be understood in a specific case by those skilled in the art.
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view corresponding to the portion I of FIG. 1 in the first embodiment of the present invention
  • It is a schematic structural view corresponding to the portion II of FIG. 1 in the first embodiment of the present invention.
  • the array substrate includes a substrate 100, a plurality of data lines 200 disposed on the substrate 100, and a plurality of scan lines 300 disposed on the substrate 100.
  • the substrate 100 includes a display area 110 and a peripheral circuit area 120 disposed on a peripheral side of the display area 110.
  • the display area 110 is an area for displaying an image when the liquid crystal display device operates, and the display area 110 is provided with a plurality of A pixel area (not shown) is provided, and each pixel area is provided with a precision component such as a thin film transistor, a pixel electrode, a common electrode, or the like.
  • each of the data lines 200 includes a data line outer segment 210 and a data line inner segment 220, each of the scan lines 300 including a scan line outer segment 310 and a scan line inner segment 320.
  • the data line outer segment 210 and the scan line outer segment 310 are both disposed in the peripheral circuit region 120, and the data line inner segment 220 and the scan line inner segment 320 both extend from the peripheral circuit region 120.
  • the peripheral circuit region 120 is further provided with a short wire 121, an enable signal line 122, a plurality of first thin film transistors T1, a plurality of second thin film transistors T2, and a plurality of first electrostatic protection circuits. 123.
  • Each of the data lines 200 is connected to a first thin film transistor T1, a first electrostatic protection circuit 123 and a second electrostatic protection circuit 124.
  • Each of the scan lines 300 is connected to a second thin film transistor T2, a third electrostatic protection circuit 125, and a fourth electrostatic protection circuit 126.
  • Each of the first thin film transistor T1 and each of the second thin film transistors T2 includes a gate, a drain, and a source.
  • Each of the data lines 200 is connected to a first thin film transistor T1.
  • a gate of each of the first thin film transistors T1 is connected to the enable signal line 122, and each of the first thin film transistors T1
  • the drain is connected to a data line outer segment 210 of a corresponding data line 200
  • each The source of the first thin film transistor T1 is connected to the data line inner segment 220 of the same data line 200.
  • Each of the scan lines 300 is connected to a second thin film transistor T2.
  • a gate of each of the second thin film transistors T2 is connected to the enable signal line 122, and each of the second thin film transistors T2
  • the drain is connected to a scan line outer segment 310 of a corresponding scan line 300
  • the source of each of the second thin film transistors T2 is connected to the scan line inner segment 320 of the same scan line 300. Therefore, the conduction or disconnection between the data line outer segment 210 and the data line inner segment 220 of the data line 200 is controlled to be turned on or off by the first thin film transistor T1, and the scan line 300 is
  • the conduction or disconnection between the scanning line outer segment 310 and the scanning line inner segment 320 is controlled by turning on or off the second thin film transistor T2.
  • the turning on or off of the first thin film transistor T1 and the second thin film transistor T2 is controlled by the enable signal line 122, specifically, when the enable signal line 122 is in a high level state, The first thin film transistor T1 and the second thin film transistor T2 are both turned on. When the enable signal line 122 is in a low level state, the first thin film transistor T1 and the second thin film transistor T2 are both disconnect.
  • each of the first electrostatic protection circuits 123 is connected to the outer portion 210 of the data line, and the other end is connected to the short wiring 121.
  • One end of each of the second electrostatic protection circuits 124 is connected to the inner portion 220 of the data line, and the other end is connected to the short wiring 121.
  • One end of the third electrostatic protection circuit 125 is connected to the outer portion 310 of the scanning line, and the other end is connected to the short wiring 121.
  • One end of the fourth electrostatic protection circuit 126 is connected to the inner portion 320 of the scan line, and the other end is connected to the short line 121.
  • the enable signal line 122 is configured to control the first thin film transistor T1 and the second thin film transistor T2 to be turned on or off, specifically by transmitting a voltage signal to control the first thin film transistor T1 and the first The second thin film transistor T2 is turned on or off.
  • the display region 110 operates, and when the first thin film transistor T1 and the second thin film transistor T2 are in an off state, The display area 110 stops working. Therefore, since the enable signal line 122 is not powered during the manufacturing process of the array substrate, the first thin film transistor T1 and the second thin film transistor T2 are in an off state, so the data line is outside.
  • the segment 210 and the data line inner segment 220 are in an open state, and the scan line outer segment 310 and the scan line inner segment 320 are also in an open state, so that the data line 200 and the scan line are 300 does not conduct during the manufacturing process of the array substrate, when the peripheral circuit area 120 has static electricity transmission
  • static electricity flows directly from the first electrostatic protection circuit 123 and the third electrostatic protection circuit 125 to the short wiring 121, thereby electrostatically Discharged to the ground (not shown) without passing through the display area 110, so that static electricity cannot affect the display area 110, thereby avoiding electrostatic breakdown or damage to the device located in the display area 110;
  • static electricity flows directly from the second electrostatic protection circuit 124 and the fourth electrostatic protection circuit 126 to the short wiring 121, thereby discharging static electricity to the ground.
  • the first electrostatic protection circuit 123 and the third electrostatic protection circuit 125 are used to derive the static electricity of the peripheral circuit region 120, thereby independently discharging the static electricity of the peripheral circuit region 120 to the short wiring 121, and then The static electricity of the peripheral circuit region 120 is discharged to the ground.
  • the second electrostatic protection circuit 124 and the fourth electrostatic protection circuit 126 are configured to derive static electricity of the display area 110, thereby independently discharging static electricity of the display area 110 to the short wiring 121, thereby displaying the display.
  • the static electricity of the zone 110 is discharged to the ground.
  • FIG. 2 is a schematic structural diagram corresponding to part I of FIG. 1 in the first embodiment of the present invention.
  • the first electrostatic protection circuit 123 includes a third thin film transistor T3, a gate and a drain of the third thin film transistor T3 are connected to the outer portion 210 of the data line, and a source of the third thin film transistor T3 is connected to The short wiring 121 forms a switch between the outer portion 210 of the data line and the short wiring 121.
  • the second electrostatic protection circuit 124 includes a fourth thin film transistor T4.
  • the gate and the drain of the fourth thin film transistor T4 are connected to the data line inner segment 220, and the source of the fourth thin film transistor T4 is connected to The short wiring 121 forms a switch between the inner portion 220 of the data line and the short wiring 121.
  • FIG. 3 is a schematic structural view corresponding to the portion II of FIG. 1 in the first embodiment of the present invention.
  • the third electrostatic protection circuit 125 includes a fifth thin film transistor T5, a gate and a drain of the fifth thin film transistor T5 are connected to the outer portion 310 of the scan line, and a source of the fifth thin film transistor T5 is connected to The short wiring 121 forms a switch between the scanning line outer section 310 and the short wiring 121.
  • the fourth electrostatic protection circuit 126 includes a sixth thin film transistor T6.
  • the gate and the drain of the sixth thin film transistor T6 are connected to the inner portion 320 of the scan line, and the source of the sixth thin film transistor T6 is connected to The short wiring 121 forms a switch between the inner portion 320 of the scanning line and the short wiring 121.
  • electrostatic protection process of the array substrate will be described in detail below. For convenience and clarity Clearly, in the following description of the electrostatic protection process, the electrostatic protection process corresponding to the data line and the electrostatic protection process corresponding to the scan line are separately described, corresponding to FIG. 2 and FIG. 3 respectively, but the electrostatic protection corresponding to the data line The electrostatic protection process corresponding to the process and the scan line can be performed simultaneously.
  • a gate of each of the first thin film transistors T1 is connected to the enable signal line 122
  • the enable signal line 122 is in a high state
  • the first thin film transistor TI is in an on state
  • the peripheral circuit region 120 is
  • the high voltage static electricity is transmitted to the outer portion 210 of the data line, since the gate of the first thin film transistor TI is connected to the enable signal line 122 and the resistance is large, the high voltage static electricity preferentially flows to the third film of the first electrostatic protection circuit 123.
  • the enable signal line 122 When the display area 110 is inactive, the enable signal line 122 is in a low state, the first thin film transistor TI is in an off state, and the high voltage static electricity of the peripheral circuit area 120 is transmitted to the outer portion 210 of the data line.
  • the first thin film transistor TI When the first thin film transistor TI is in the off state, the high voltage static electricity preferentially flows to the gate of the third thin film transistor T3 of the first electrostatic protection circuit 123, and rapidly turns on the gate of the third thin film transistor T3, and the electrostatic charge Flowing to the drain of the third thin film transistor T3, since the gate of the third thin film transistor T3 is in an open state, the electrostatic charge flowing to the drain of the third thin film transistor T3 continues to be transmitted to the source of the third thin film transistor T3. And then transmitted to the short wiring 121 to discharge the static electricity to the ground without passing through the display area 110.
  • the third thin film transistor T3 (ie, the first electrostatic protection circuit 123) can treat the peripheral circuit region 120 regardless of whether the display region 110 is in an active state, that is, whether the array substrate is in a use state.
  • the static electricity is led to the ground, so that the static electricity of the peripheral circuit region 120 is prevented from entering the display region 110, thereby preventing the high voltage electrostatic charge accumulation of the peripheral circuit region 120 from being excessive or the high voltage electrostatic discharge point being close to the display region 110.
  • the components within the display area 110 are broken down.
  • the electrostatic charge flows to the gate and the drain of the fourth thin film transistor T4 of the second static electricity protection circuit 124 through the data line inner segment 220, and turns on the fourth thin film transistor T4.
  • the gate is turned on, thereby causing electrostatic charge from the fourth thin film transistor
  • the drain of T4 flows to the source of the fourth thin film transistor T4, and is further transmitted to the short wiring 121 to discharge the electrostatic charge to the ground.
  • the enable signal line 122 is in a high state
  • the second thin film transistor T2 is in an on state
  • the peripheral circuit area 120 is
  • the high voltage static electricity is transmitted to the outer portion 310 of the scanning line, since the gate of the second thin film transistor T2 is connected to the enable signal line 122 and the resistance is large, the high voltage static electricity preferentially flows to the fifth thin film transistor T5 of the third electrostatic protection circuit 125.
  • the enable signal line 122 is in a low level state
  • the second thin film transistor T2 is in an off state
  • the high voltage static electricity of the peripheral circuit area 120 is transmitted to the scan line outer section 310.
  • the second thin film transistor T2 is in the off state
  • the high voltage static electricity preferentially flows to the gate of the fifth thin film transistor T5, and rapidly turns on the gate of the fifth thin film transistor T5, and the electrostatic charge flows to the fifth thin film transistor T5.
  • the drain since the gate of the fifth thin film transistor T5 is in an open state, the electrostatic charge flowing to the drain of the fifth thin film transistor T5 is further transmitted to the source of the fifth thin film transistor T5, and then transmitted to the short wiring. 121, thereby discharging static electricity to the ground terminal without passing through the display area 110.
  • the fifth thin film transistor T3 ie, the third electrostatic protection circuit 125
  • the fifth thin film transistor T3 can mark the peripheral circuit region 120 regardless of whether the display region 110 is in an active state, that is, whether the array substrate is in a use state.
  • the static electricity is led to the ground, so that the static electricity of the peripheral circuit region 120 is prevented from entering the display region 110, thereby preventing the high voltage electrostatic charge accumulation of the peripheral circuit region 120 from being excessive or the high voltage electrostatic discharge point being close to the display region 100.
  • the components within the display area 110 are broken down.
  • the electrostatic charge flows to the gate and the drain of the sixth thin film transistor T6 of the fourth electrostatic protection circuit 126 through the scanning line inner section 320, and turns on the sixth thin film transistor T6.
  • the gate is brought into an open state, so that electrostatic charges flow from the drain of the sixth thin film transistor T6 to the source of the sixth thin film transistor T6, and then to the short wiring 121, and the electrostatic charge is led to the ground.
  • the drain of the first thin film transistor is connected to the outer portion of the data line of one of the data lines, and the first film a source of the transistor is connected to the inner portion of the data line of the same data line, and a gate of each of the second thin film transistors is connected to the enable signal line, and a drain of the second thin film transistor is connected to one of the ends
  • An outer portion of the scan line of the scan line a source of the second thin film transistor is connected to an inner segment of the scan line of the same scan line, that is, an outer segment of the data line is connected to an inner segment of the data line a thin film transistor is used as a switch, and a second thin film transistor is connected as a switch between the outer portion of the scan line and the inner portion of the scan line, thereby dividing the data line and the scan line into two parts, a part of which is located in the peripheral circuit Another portion is located in the display area, that is, the outer portion of the
  • one end of the first electrostatic protection circuit is connected to the outer portion of the data line, and the other end is connected to the short wire.
  • One end of the second electrostatic protection circuit is connected to the inner segment of the data line, and the other end is connected.
  • the third electrostatic protection circuit has one end connected to the outer portion of the scan line, the other end connected to the short wire, and one end of the fourth electrostatic protection circuit is connected to the inner portion of the scan line The other end is connected to the short wire.
  • the outer portion of the data line and the outer portion of the scan line are respectively connected to the short wire, and the inner portion of the data line and the inner portion of the scan line are also respectively connected to The short wiring, wherein the outer portion of the data line and the outer portion of the scan line are located in the peripheral circuit region, and when high voltage static electricity is present in the peripheral circuit region, the high voltage static electricity is directly from the first
  • the electrostatic protection circuit and the third electrostatic protection circuit are transmitted to the short wiring and transmitted to the ground without affecting components in the display area, thereby avoiding accumulation of high voltage electrostatic charge in the peripheral circuit area. Point from electrostatic discharge or high pressure area near the display of the display member sometimes cause breakdown zone.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention
  • FIG. 4 is a schematic structural view corresponding to part I of FIG. 1 according to a second embodiment of the present invention
  • 5 is a schematic structural view corresponding to the portion II of FIG. 1 in the second embodiment of the present invention.
  • the structure of the array substrate in the second embodiment of the present invention is substantially the same as that of the array substrate in the first embodiment, except that the first static electricity of the array substrate in this embodiment (second embodiment)
  • the protection circuit 123 further includes a seventh thin film transistor T7, and the seventh thin film transistor T7 and the third thin film transistor T3
  • the second electrostatic protection circuit 124 further includes an eighth thin film transistor T8, the eighth thin film transistor T8 is connected in parallel with the fourth thin film transistor T4;
  • the third electrostatic protection circuit 125 further includes a ninth thin film transistor T9.
  • the ninth thin film transistor T9 is connected in parallel with the fifth thin film transistor T5; the fourth electrostatic protection circuit 126 further includes a tenth thin film transistor T10, and the tenth thin film transistor T10 is connected in parallel with the sixth thin film transistor. Therefore, the first electrostatic protection circuit 123, the second electrostatic protection circuit 124, the third electrostatic protection circuit 125, and the fourth electrostatic protection circuit 126 each include two thin film transistors connected in parallel.
  • the first electrostatic protection circuit 123, the second electrostatic protection circuit 124, the third electrostatic protection circuit 125, and the fourth electrostatic protection circuit 126 each include more A parallel thin film transistor.
  • the first electrostatic protection circuit 123, the second electrostatic protection circuit 124, the third electrostatic protection circuit 125, and the fourth electrostatic protection circuit 126 each include at least two parallel films. a transistor, therefore, when one of the thin film crystals of each of the electrostatic protection circuits can only be in an open state due to damage, the other thin film transistor can operate normally, thereby causing the first electrostatic protection circuit 123 and the second static electricity
  • the protection circuit 124, the third electrostatic protection circuit 125, and the fourth electrostatic protection circuit 126 can all maintain the original functions.
  • the third thin film transistor T3 of the first electrostatic protection circuit 123 can only be in an off state due to damage, if the high voltage static electricity of the peripheral circuit region 120 is transmitted to the outer portion 210 of the data line, although the third The thin film transistor T3 cannot work due to damage, but the high voltage static electricity can still activate the gate of the seventh thin film transistor T7, so that the electrostatic charge flows from the drain of the seventh thin film transistor T7 to the source of the seventh thin film transistor T7, and then The source of the seventh thin film transistor T7 flows to the short wiring 121, thereby discharging the high voltage static electricity of the peripheral circuit region 120 to the ground. It can be seen that the first electrostatic protection circuit 123 still does not lose its original function. Compared with the first embodiment, the second embodiment of the present invention can further prevent the high voltage electrostatic charge accumulation of the peripheral circuit region 120 from being excessively large or The high voltage electrostatic discharge point is near the display area resulting in breakdown of components within the display area.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention
  • FIG. 6 is a schematic structural view corresponding to part I of FIG. 1 according to a third embodiment of the present invention
  • 7 is a schematic structural view corresponding to the portion II of FIG. 1 in the third embodiment of the present invention.
  • the structure of the array substrate in the example is substantially the same as that of the array substrate in the first embodiment, except that the first electrostatic protection circuit 123 of the array substrate in the third embodiment further includes a thin film transistor T7, the seventh thin film transistor T7 is connected in series with the third thin film transistor T3; the second electrostatic protection circuit 124 further includes an eighth thin film transistor T8, the eighth thin film transistor T8 and the fourth The thin film transistor T4 is connected in series; the third electrostatic protection circuit 125 further includes a ninth thin film transistor T9, the ninth thin film transistor T9 is connected in series with the fifth thin film transistor T5; the fourth electrostatic protection circuit 126 further includes a tenth The thin film transistor T10 is connected in series with the sixth thin film transistor T10. Therefore, the first electrostatic protection circuit 123, the second electrostatic protection circuit 124, the third electrostatic protection circuit 125, and the fourth electrostatic protection circuit 126 each include two thin film transistors connected in series.
  • the first electrostatic protection circuit 123, the second electrostatic protection circuit 124, the third electrostatic protection circuit 125, and the fourth electrostatic protection circuit 126 each include more A series of thin film transistors.
  • the first electrostatic protection circuit 123, the second electrostatic protection circuit 124, the third electrostatic protection circuit 125, and the fourth electrostatic protection circuit 126 each include at least two films connected in series. Transistor, therefore, when one of the thin film crystals of each electrostatic protection circuit can only be in a short-circuit state due to damage, another thin film transistor can operate normally to prevent occurrence of the outer portion 210 of the data line and the short wiring 121 The short circuit causes the array substrate to be inoperable, and can still function as an electrostatic protection, so that the first electrostatic protection circuit 123, the second electrostatic protection circuit 124, the third electrostatic protection circuit 125, and the The fourth electrostatic protection circuit 126 can maintain the original function.
  • the third thin film transistor T3 of the first electrostatic protection circuit 123 can only be in a short circuit state due to damage, if the high voltage static electricity of the peripheral circuit region 120 is transmitted to the outer portion 210 of the data line, although the third film The transistor T3 cannot work due to damage, but the high voltage static electricity can still activate the gate of the seventh thin film transistor T7, so that the electrostatic charge flows from the drain of the seventh thin film transistor T7 to the source of the seventh thin film transistor T7, and then from the first The source of the seven thin film transistor T7 flows to the short wiring 121, thereby discharging the high voltage static electricity of the peripheral circuit region 120 to the ground. It can be seen that the first electrostatic protection circuit 123 still does not lose its original function, and prevents the data line outer segment 210 from being short-circuited with the short wire 121 to cause the array substrate to be inoperable.
  • the present invention also provides a liquid crystal display device comprising the array substrate according to any one of the embodiments or embodiments shown in FIGS. 1 to 7 described above.

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Abstract

一种阵列基板和具有该阵列基板的液晶显示装置，所述阵列基板包括基板（100）、设置于所述基板（100）上的多条数据线（200）及设置于所述基板（100）上的多条扫描线（300）；基板（100）包括显示区（110）及显示区（110）周侧的外围电路区（120），每条数据线（200）包括数据线外段（210）和数据线内段（220），每条扫描线（300）包括扫描线外段（310）和扫描线内段（320）；外围电路区（120）还设置有短接线（121）、使能信号线（122）、多个第一薄膜晶体管（T1）、多个第二薄膜晶体管（T2）、多个第一静电保护电路（123）、多个第二静电保护电路（124）、多个第三静电保护电路（125）及多个第四静电保护电路（126）。所述阵列基板可有效排走静电，将外围电路区（120）的静电与显示区（110）的静电分开，避免外围电路区（120）的高压静电电荷累积过大或高压静电释放点离显示区（110）近时击穿显示区（110）内的器件。

Description

阵列基板及液晶显示装置
本申请要求于2016年02月18日提交中国专利局、申请号为201610090983.1、发明名称为“阵列基板及液晶显示装置”的中国专利申请的优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示领域，尤其涉及一种阵列基板及一种具有该阵列基板的液晶显示装置。
背景技术
阵列基板是薄膜晶体管液晶显示装置如薄膜晶体管液晶显示器，TFT-LCD的重要部件，阵列基板通常包括外围电路区和显示区，在阵列基板的制造和使用过程中，由于带电粒子、工程条件、原材料及设计等因素，不可避免地会产生静电，尤其是产生于阵列基板的外围电路区的静电通常为高压静电。
静电问题直接影响着阵列基板的良品率，进而影响液晶显示装置的产品良率。高压静电释放时，如果阵列基板上没有有效路径及时将静电排走，则极易将阵列基板上的精密器件击穿，尤其是显示区内的各个部件都极为精密，更容易被高压静电击穿。例如，薄膜晶体管阵列，其极为精密，很容易被外围电路区的高压静电击穿，而薄膜晶体管阵列是阵列基板的关键部件，一旦被击穿则导致液晶显示器的品质低劣或失效。
现有技术中，通常在阵列基板的线路(例如，栅线和数据线)的始末端设置静电释放环(ESD ring)，将静电释放环与短接线连接，并使阵列基板中所有的线路通过静电释放环与短接线连接，从而在静电释放时可以通过短接线将静电排放到接地端。然而，在这样的设计中，静电释放环与短接线会将阵列基板的外围电路区内的电路与阵列基板的显示区内的电路连接起来，而阵列基板的外围电路区最容易产生高压静电，在阵列基板的制造过程中或使用过程中，当外围电路区的高压静电电荷累积过大时和/或高压静电释放点离所述显示区 近时，则位于该显示区的精密器件仍有可能被击穿或损坏。
发明内容
本发明所要解决的技术问题在于，提供一种阵列基板，所述阵列基板的静电保护电路可以有效将静电排走，且可以将外围电路区的静电与显示区的静电分开，从而避免所述外围电路区的高压静电电荷累积过大或高压静电释放点离所述显示区近时击穿所述显示区内的器件。
另外，本发明还提供一种具有该阵列基板的液晶显示装置。
为了解决上述技术问题，本发明采用以下技术方案：
一方面，本发明提供一种阵列基板，所述阵列基板包括基板及设置于所述基板上的多条数据线和多条扫描线；所述基板包括显示区及设置于所述显示区周侧的外围电路区，每条所述数据线包括数据线外段和数据线内段，每条所述扫描线包括扫描线外段和扫描线内段，所述数据线外段和所述扫描线外段设置于所述外围电路区，所述数据线内段及所述扫描线内段均从所述外围电路区延伸至所述显示区；
所述外围电路区还设置有短接线、使能信号线、多个第一薄膜晶体管、多个第二薄膜晶体管、多个第一静电保护电路、多个第二静电保护电路、多个第三静电保护电路及多个第四静电保护电路，每个所述第一薄膜晶体管及每个所述第二薄膜晶体管的栅极均连接于所述使能信号线，所述第一薄膜晶体管的漏极连接于一条所述数据线的数据线外段，所述第一薄膜晶体管的源极连接于同一条所述数据线的数据线内段；每个所述第二薄膜晶体管的漏极连接于一条所述扫描线的扫描线外段，所述第二薄膜晶体管的源极连接于同一条所述扫描线的扫描线内段；所述第一静电保护电路的一端连接于所述数据线外段，另一端连接于所述短接线；所述第二静电保护电路的一端连接于所述数据线内段，另一端连接于所述短接线；所述第三静电保护电路的一端连接于所述扫描线外段，另一端连接于所述短接线；所述第四静电保护电路的一端连接于所述扫描线内段，另一端连接于所述短接线；所述使能信号线控制所述第一薄膜晶体管和所述第二薄膜晶体管导通或断开。
其中，所述第一静电保护电路包括第三薄膜晶体管，所述第三薄膜晶体管 的栅极和漏极连接于所述数据线外段，源极连接于所述短接线，所述第二静电保护电路包括第四薄膜晶体管，所述第四薄膜晶体管的栅极和漏极连接于所述数据线内段，源极连接于所述短接线。
其中，所述第一静电保护电路还包括第七薄膜晶体管，所述第七薄膜晶体管与所述第三薄膜晶体管并联或串联；所述第二静电保护电路还包括第八薄膜晶体管，所述第八薄膜晶体管与所述第四薄膜晶体管并联或串联。
其中，所述第三静电保护电路包括第五薄膜晶体管，所述第五薄膜晶体管的栅极和漏极连接于所述扫描线外段，所述第五薄膜晶体管的源极连接于所述短接线，所述第四静电保护电路包括第六薄膜晶体管，所述第六薄膜晶体管的栅极和漏极连接于所述扫描线内段，所述第六薄膜晶体管的源极连接于所述短接线。
其中，所述第三静电保护电路还包括第九薄膜晶体管，所述第九薄膜晶体管与所述第五薄膜晶体管并联或串联；所述第四静电保护电路还包括第十薄膜晶体管，所述第十薄膜晶体管与所述第六薄膜晶体管并联或串联。
其中，所述使能信号线处于高电平状态时，所述第一薄膜晶体管及所述第二薄膜晶体管处于导通状态，所述使能信号线处于低电平状态时，所述第一薄膜晶体管及所述第二薄膜晶体管处于断开状态。
其中，所述第一薄膜晶体管及所述第二薄膜晶体管处于导通状态时，所述显示区进行工作，所述第一薄膜晶体管及所述第二薄膜晶体管处于断开状态时，所述显示区停止工作。
另一方面，本发明还提供一种液晶显示装置，所述液晶显示装置包括阵列基板，所述阵列基板包括基板及设置于所述基板上的多条数据线和多条扫描线；所述基板包括显示区及设置于所述显示区周侧的外围电路区，每条所述数据线包括数据线外段和数据线内段，每条所述扫描线包括扫描线外段和扫描线内段，所述数据线外段和所述扫描线外段设置于所述外围电路区，所述数据线内段及所述扫描线内段均从所述外围电路区延伸至所述显示区；
所述外围电路区还设置有短接线、使能信号线、多个第一薄膜晶体管、多个第二薄膜晶体管、多个第一静电保护电路、多个第二静电保护电路、多个第三静电保护电路及多个第四静电保护电路，每个所述第一薄膜晶体管及每个所 述第二薄膜晶体管的栅极均连接于所述使能信号线，所述第一薄膜晶体管的漏极连接于一条所述数据线的数据线外段，所述第一薄膜晶体管的源极连接于同一条所述数据线的数据线内段；每个所述第二薄膜晶体管的漏极连接于一条所述扫描线的扫描线外段，所述第二薄膜晶体管的源极连接于同一条所述扫描线的扫描线内段；所述第一静电保护电路的一端连接于所述数据线外段，另一端连接于所述短接线；所述第二静电保护电路的一端连接于所述数据线内段，另一端连接于所述短接线；所述第三静电保护电路的一端连接于所述扫描线外段，另一端连接于所述短接线；所述第四静电保护电路的一端连接于所述扫描线内段，另一端连接于所述短接线；所述使能信号线控制所述第一薄膜晶体管和所述第二薄膜晶体管导通或断开。
其中，所述第一静电保护电路包括第三薄膜晶体管，所述第三薄膜晶体管的栅极和漏极连接于所述数据线外段，源极连接于所述短接线，所述第二静电保护电路包括第四薄膜晶体管，所述第四薄膜晶体管的栅极和漏极连接于所述数据线内段，源极连接于所述短接线。
其中，所述第一静电保护电路还包括第七薄膜晶体管，所述第七薄膜晶体管与所述第三薄膜晶体管并联或串联；所述第二静电保护电路还包括第八薄膜晶体管，所述第八薄膜晶体管与所述第四薄膜晶体管并联或串联。
其中，所述第三静电保护电路包括第五薄膜晶体管，所述第五薄膜晶体管的栅极和漏极连接于所述扫描线外段，所述第五薄膜晶体管的源极连接于所述短接线，所述第四静电保护电路包括第六薄膜晶体管，所述第六薄膜晶体管的栅极和漏极连接于所述扫描线内段，所述第六薄膜晶体管的源极连接于所述短接线。
其中，所述第三静电保护电路还包括第九薄膜晶体管，所述第九薄膜晶体管与所述第五薄膜晶体管并联或串联；所述第四静电保护电路还包括第十薄膜晶体管，所述第十薄膜晶体管与所述第六薄膜晶体管并联或串联。
其中，所述使能信号线处于高电平状态时，所述第一薄膜晶体管及所述第二薄膜晶体管处于导通状态，所述使能信号线处于低电平状态时，所述第一薄膜晶体管及所述第二薄膜晶体管处于断开状态。
其中，所述第一薄膜晶体管及所述第二薄膜晶体管处于导通状态时，所述 显示区进行工作，所述第一薄膜晶体管及所述第二薄膜晶体管处于断开状态时，所述显示区停止工作。
与现有技术相比，本发明的技术方案具有以下有益效果：
本发明的技术方案中，由于每个所述第一薄膜晶体管的栅极连接于所述使能信号线，第一薄膜晶体管的漏极连接于其中一条所述数据线的数据线外段，第一薄膜晶体管的源极连接于同一条所述数据线的数据线内段，而且每个所述第二薄膜晶体管的栅极连接于所述使能信号线，第二薄膜晶体管的漏极连接于其中一条所述扫描线的扫描线外段，第二薄膜晶体管的源极连接于同一条所述扫描线的扫描线内段，即所述数据线外段与所述数据线内段之间连接了第一薄膜晶体管作为开关，所述扫描线外段与所述扫描线内段之间连接了第二薄膜晶体管作为开关，从而将数据线及扫描线都分成了两部分，其中一部分位于所述外围电路区，另一部分主要位于所述显示区，即所述数据线外段及所述扫描线外段位于所述外围电路区，所述数据线内段及所述扫描线内段从所述外围电路区延伸至所述显示区。又由于所述第一静电保护电路的一端连接于所述数据线外段，另一端连接于所述短接线，所述第二静电保护电路的一端连接于所述数据线内段，另一端连接于所述短接线；所述第三静电保护电路的一端连接于所述扫描线外段，另一端连接于所述短接线，所述第四静电保护电路的一端连接于所述扫描线内段，另一端连接于所述短接线，因此，所述数据线外段及所述扫描线外段分别连接到所述短接线，所述数据线内段及所述扫描线内段也分别连接到所述短接线，而所述数据线外段及所述扫描线外段位于所述外围电路区，则当所述外围电路区存在有高压静电的情况下，该高压静电直接从所述第一静电保护电路及所述第三静电保护电路传输至所述短接线，并传输至接地端，而不会影响到所述显示区内的部件，从而避免所述外围电路区的高压静电电荷累积过大或高压静电释放点离所述显示区近时而导致击穿所述显示区内的部件。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述 中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的变形形式。
图1是本发明的实施例中阵列基板的结构示意图；
图2是本发明第一实施例中对应图1中I部分的结构示意图；
图3是本发明第一实施例中对应图1中II部分的结构示意图；
图4是本发明第二实施例中对应图1中I部分的结构示意图；
图5是本发明第二实施例中对应图1中II部分的结构示意图；
图6是本发明第三实施例中对应图1中I部分的结构示意图；及
图7是本发明第三实施例中对应图1中II部分的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
此外，以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明中所提到的方向用语，例如，“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向，因此，使用的方向用语是为了更好、更清楚地说明及理解本发明，而不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸地连接，或者一体地连接；可以是机械连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
此外，在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。若本说明书中出现“工序”的用语，其不仅是指独立的工序，在与其它工序无法明确区别时，只要能实现该工序所预期的作用则也包括在本用语中。 另外，本说明书中用“～”表示的数值范围是指将“～”前后记载的数值分别作为最小值及最大值包括在内的范围。在附图中，结构相似或相同的单元用相同的标号表示。
请一并参阅图1、图2及图3，图1是本发明的实施例中阵列基板的结构示意图；图2是本发明第一实施例中对应图1中I部分的结构示意图；图3是本发明第一实施例中对应图1中II部分的结构示意图。
本发明的第一实施例中，所述阵列基板包括基板100、设置于所述基板100上的多条数据线200及设置于所述基板100上的多条扫描线300。
所述基板100包括显示区110及设置于所述显示区110周侧的外围电路区120，所述显示区110是液晶显示装置工作时显示图像的区域，所述显示区110内设置有多个像素区域(图中未示出)，每个像素区域设置有精密部件，例如，薄膜晶体管、像素电极、公共电极等。
在本发明的实施例中，每一所述数据线200包括数据线外段210和数据线内段220，每一所述扫描线300包括扫描线外段310和扫描线内段320。所述数据线外段210和所述扫描线外段310均设置于所述外围电路区120，所述数据线内段220及所述扫描线内段320均从所述外围电路区120向延伸至所述显示区110。
在本发明的实施例中，所述外围电路区120还设置有短接线121、使能信号线122、多个第一薄膜晶体管T1、多个第二薄膜晶体管T2、多个第一静电保护电路123、多个第二静电保护电路124、多个第三静电保护电路125及多个第四静电保护电路126。每条所述数据线200对应连接一个第一薄膜晶体管T1、一个第一静电保护电路123及一个第二静电保护电路124。每条所述扫描线300对应连接一个第二薄膜晶体管T2、一个第三静电保护电路125及一个第四静电保护电路126。
每个所述第一薄膜晶体管T1及每个所述第二薄膜晶体管T2均包括栅极、漏极和源极。每条所述数据线200对应连接一个第一薄膜晶体管T1，具体为，每个所述第一薄膜晶体管T1的栅极连接于所述使能信号线122，每个所述第一薄膜晶体管T1的漏极连接于一条对应的数据线200的数据线外段210，每 个所述第一薄膜晶体管T1的源极连接于同一条所述数据线200的数据线内段220。每条所述扫描线300对应连接一个第二薄膜晶体管T2，具体为，每个所述第二薄膜晶体管T2的栅极连接于所述使能信号线122，每个所述第二薄膜晶体管T2的漏极连接于一条对应的扫描线300的扫描线外段310，每个所述第二薄膜晶体管T2的源极连接于同一条所述扫描线300的扫描线内段320。因此，所述数据线200的数据线外段210和数据线内段220之间的导通或断路由所述第一薄膜晶体管T1的导通或断开来控制，而所述扫描线300的扫描线外段310与扫描线内段320之间的导通或断路由所述第二薄膜晶体管T2的导通或断开来控制。所述第一薄膜晶体管T1及所述第二薄膜晶体管T2的导通或断开则由所述使能信号线122控制，具体为，当所述使能信号线122处于高电平状态时，所述第一薄膜晶体管T1及所述第二薄膜晶体管T2均导通，当所述使能信号线122处于低电平状态时，所述第一薄膜晶体管T1及所述第二薄膜晶体管T2均断开。
在本发明的实施例中，每一所述第一静电保护电路123的一端连接于所述数据线外段210，另一端连接于所述短接线121。每一所述第二静电保护电路124的一端连接于所述数据线内段220，另一端连接于所述短接线121。所述第三静电保护电路125的一端连接于所述扫描线外段310，另一端连接于所述短接线121。所述第四静电保护电路126的一端连接于所述扫描线内段320，另一端连接于所述短接线121。
所述使能信号线122用于控制所述第一薄膜晶体管T1和所述第二薄膜晶体管T2导通或断开，具体可通过发送电压信号以控制所述第一薄膜晶体管T1和所述第二薄膜晶体管T2导通或断开。所述第一薄膜晶体管T1及所述第二薄膜晶体管T2处于导通状态时，所述显示区110进行工作，所述第一薄膜晶体管T1及所述第二薄膜晶体管T2处于断开状态时，所述显示区110停止工作。因此，由于在阵列基板的制造过程中，所述使能信号线122不上电，必然使所述第一薄膜晶体管T1及所述第二薄膜晶体管T2处于断开状态，故而所述数据线外段210与所述数据线内段220之间处于断路状态，所述扫描线外段310与所述扫描线内段320之间也处于断路状态，从而使所述数据线200及所述扫描线300在阵列基板的制造过程中不导通，当外围电路区120有静电传输 至所述数据线外段210和所述扫描线外段310时，静电分别直接从所述第一静电保护电路123和所述第三静电保护电路125流到所述短接线121，从而将静电排出至接地端(图中未示出)，而不会经过所述显示区110，从而使得静电无法影响到所述显示区110，进而避免静电击穿或损坏位于该显示区110的器件；当所述显示区110有静电时，静电直接从所述第二静电保护电路124和所述第四静电保护电路126流到所述短接线121，从而将静电排出至接地端。
所述第一静电保护电路123及第三静电保护电路125用于导出所述外围电路区120的静电，从而独立地将所述外围电路区120的静电导出到所述短接线121，进而将所述外围电路区120的静电排到接地端。所述第二静电保护电路124及第四静电保护电路126用于导出所述显示区110的静电，从而独立地将所述显示区110的静电导出到所述短接线121，进而将所述显示区110的静电排到接地端。
进一步地，请参阅图2，图2是本发明第一实施例中对应图1中I部分的结构示意图。所述第一静电保护电路123包括第三薄膜晶体管T3，所述第三薄膜晶体管T3的栅极和漏极连接于所述数据线外段210，所述第三薄膜晶体管T3的源极连接于所述短接线121，形成所述数据线外段210与所述短接线121之间的开关。所述第二静电保护电路124包括第四薄膜晶体管T4，所述第四薄膜晶体管T4的栅极和漏极连接于所述数据线内段220，所述第四薄膜晶体管T4的源极连接于所述短接线121，形成所述数据线内段220与所述短接线121之间的开关。
进一步地，请参阅图3，图3是本发明第一实施例中对应图1中II部分的结构示意图。所述第三静电保护电路125包括第五薄膜晶体管T5，所述第五薄膜晶体管T5的栅极和漏极连接于所述扫描线外段310，所述第五薄膜晶体管T5的源极连接于所述短接线121，形成所述扫描线外段310与所述短接线121之间的开关。所述第四静电保护电路126包括第六薄膜晶体管T6，所述第六薄膜晶体管T6的栅极和漏极连接于所述扫描线内段320，所述第六薄膜晶体管T6的源极连接于所述短接线121，形成所述扫描线内段320与所述短接线121之间的开关。
下面对所述阵列基板的静电保护过程进行详细描述。为了便于简便且清 晰，下面对静电保护过程的描述中，将数据线所对应的静电保护过程和扫描线所对应的静电保护过程分开描述，分别对应图2和图3，但是，数据线所对应的静电保护过程和扫描线所对应的静电保护过程是可以同时进行的。每个所述第一薄膜晶体管T1的栅极连接于所述使能信号线122
请一并参阅图1及图2，当所述显示区110处于工作状态时，所述使能信号线122处于高电平状态，第一薄膜晶体管TI处于导通状态，当外围电路区120的高压静电传输至所述数据线外段210时，由于第一薄膜晶体管TI的栅极与使能信号线122相连，电阻大，则高压静电优先流向所述第一静电保护电路123的第三薄膜晶体管T3的栅极，并迅速开启第三薄膜晶体管T3的栅极，且静电电荷流向所述第三薄膜晶体管T3的漏极，由于第三薄膜晶体管T3的栅极处于打开状态，则流向第三薄膜晶体管T3的漏极的静电电荷会继续传输至第三薄膜晶体管T3的源极，进而传输至所述短接线121，从而将静电排出至接地端，无需经过显示区110。
当所述显示区110不工作时，所述使能信号线122处于低电平状态，第一薄膜晶体管TI处于断开状态，当外围电路区120的高压静电传输至所述数据线外段210时，由于第一薄膜晶体管TI处于断开状态，高压静电优先流向所述第一静电保护电路123的第三薄膜晶体管T3的栅极，并迅速开启第三薄膜晶体管T3的栅极，且静电电荷流向所述第三薄膜晶体管T3的漏极，由于第三薄膜晶体管T3的栅极处于打开状态，则流向第三薄膜晶体管T3的漏极的静电电荷会继续传输至第三薄膜晶体管T3的源极，进而传输至所述短接线121，从而将静电排出至接地端，无需经过所述显示区110。
可见，无论所述显示区110是否处于工作状态，即无论所述阵列基板是否处于使用状态，所述第三薄膜晶体管T3(即第一静电保护电路123)均可将所述外围电路区120的静电导出至接地端，从而避免所述外围电路区120的静电进入所述显示区110，进而避免所述外围电路区120的高压静电电荷累积过大或高压静电释放点离所述显示区110近时击穿所述显示区110内的部件。
当所述显示区110内产生静电时，静电电荷会通过数据线内段220流向所述第二静电保护电路124的第四薄膜晶体管T4的栅极和漏极，并开启第四薄膜晶体管T4的栅极，使其处于打开状态，从而使静电电荷从第四薄膜晶体管 T4的漏极流向该第四薄膜晶体管T4的源极，进而传输至所述短接线121，将静电电荷导出至接地端。
请一并参阅图1及图3，当所述显示区110处于工作状态时，所述使能信号线122处于高电平状态，第二薄膜晶体管T2处于导通状态，当外围电路区120的高压静电传输至所述扫描线外段310时，由于第二薄膜晶体管T2的栅极与使能信号线122相连，电阻大，则高压静电优先流向第三静电保护电路125的第五薄膜晶体管T5的栅极，并迅速开启第五薄膜晶体管T5的栅极，且静电电荷流向所述第五薄膜晶体管T5的漏极，且由于五薄膜晶体管T5的栅极处于打开状态，则流向第五薄膜晶体管T5的漏极的静电电荷会继续传输至第五薄膜晶体管T5的源极，进而传输至所述短接线121，从而将静电排出至接地端，无需经过显示区110。
当所述显示区110不工作时，所述使能信号线122处于低电平状态，第二薄膜晶体管T2处于断开状态，当外围电路区120的高压静电传输至所述扫描线外段310时，由于第二薄膜晶体管T2处于断开状态，高压静电优先流向第五薄膜晶体管T5的栅极，并迅速开启第五薄膜晶体管T5的栅极，且静电电荷流向所述第五薄膜晶体管T5的漏极，由于该第五薄膜晶体管T5的栅极处于打开状态，则流向第五薄膜晶体管T5的漏极的静电电荷会继续传输至第五薄膜晶体管T5的源极，进而传输至所述短接线121，从而将静电排出至接地端，无需经过所述显示区110。
可见，无论所述显示区110是否处于工作状态，即无论所述阵列基板是否处于使用状态，所述第五薄膜晶体管T3(即第三静电保护电路125)均可将所述外围电路区120的静电导出至接地端，从而避免所述外围电路区120的静电进入所述显示区110，进而避免所述外围电路区120的高压静电电荷累积过大或高压静电释放点离所述显示区100近时击穿所述显示区110内的部件。
当所述显示区110内产生静电时，静电电荷会通过扫描线内段320流向所述第四静电保护电路126的第六薄膜晶体管T6的栅极和漏极，并开启第六薄膜晶体管T6的栅极，使其处于打开状态，从而使静电电荷从第六薄膜晶体管T6的漏极流向第六薄膜晶体管T6的源极，进而传输至所述短接线121，将静电电荷导出至接地端。
本实施例中，由于每个所述第一薄膜晶体管的栅极连接于所述使能信号线，第一薄膜晶体管的漏极连接于其中一条所述数据线的数据线外段，第一薄膜晶体管的源极连接于同一条所述数据线的数据线内段，而且每个所述第二薄膜晶体管的栅极连接于所述使能信号线，第二薄膜晶体管的漏极连接于其中一条所述扫描线的扫描线外段，第二薄膜晶体管的源极连接于同一条所述扫描线的扫描线内段，即所述数据线外段与所述数据线内段之间连接了第一薄膜晶体管作为开关，所述扫描线外段与所述扫描线内段之间连接了第二薄膜晶体管作为开关，从而将数据线及扫描线都分成了两部分，其中一部分位于所述外围电路区，另一部分主要位于所述显示区，即所述数据线外段及所述扫描线外段位于所述外围电路区，所述数据线内段及所述扫描线内段从所述外围电路区延伸至所述显示区。又由于所述第一静电保护电路的一端连接于所述数据线外段，另一端连接于所述短接线，所述第二静电保护电路的一端连接于所述数据线内段，另一端连接于所述短接线；所述第三静电保护电路的一端连接于所述扫描线外段，另一端连接于所述短接线，所述第四静电保护电路的一端连接于所述扫描线内段，另一端连接于所述短接线，因此，所述数据线外段及所述扫描线外段分别连接到所述短接线，所述数据线内段及所述扫描线内段也分别连接到所述短接线，而所述数据线外段及所述扫描线外段位于所述外围电路区，则当所述外围电路区存在有高压静电的情况下，该高压静电直接从所述第一静电保护电路及所述第三静电保护电路传输至所述短接线，并传输至接地端，而不会影响到所述显示区内的部件，从而避免所述外围电路区的高压静电电荷累积过大或高压静电释放点离所述显示区近时而导致击穿所述显示区内的部件。
请参阅一并参阅图1、图4和图5，图1是本发明的实施例中阵列基板的结构示意图，图4是本发明第二实施例中对应图1中I部分的结构示意图，图5是本发明第二实施例中对应图1中II部分的结构示意图。本发明的第二实施例中的阵列基板的结构与第一实施例中所述阵列基板的结构基本相同，不同之处在于：本实施例(第二实施例)中的阵列基板的第一静电保护电路123还包括第七薄膜晶体管T7，所述第七薄膜晶体管T7与所述第三薄膜晶体管T3并 联；所述第二静电保护电路124还包括第八薄膜晶体管T8，所述第八薄膜晶体管T8与所述第四薄膜晶体管T4并联；所述第三静电保护电路125还包括第九薄膜晶体管T9，所述第九薄膜晶体管T9与所述第五薄膜晶体管T5并联；所述第四静电保护电路126还包括第十薄膜晶体管T10，所述第十薄膜晶体管T10与所述第六薄膜晶体管并联。因此，所述第一静电保护电路123、所述第二静电保护电路124、所述第三静电保护电路125及所述第四静电保护电路126均包括两个并联的薄膜晶体管。
在本实施例的另外的实施方式中，所述第一静电保护电路123、所述第二静电保护电路124、所述第三静电保护电路125及所述第四静电保护电路126均包括更多个并联的薄膜晶体管。
在本实施例中，由于所述第一静电保护电路123、所述第二静电保护电路124、所述第三静电保护电路125及所述第四静电保护电路126均包括至少两个并联的薄膜晶体管，因此，当每一静电保护电路的其中一个薄膜晶体因损坏而只能处于断开状态时，另一个薄膜晶体管可以正常工作，从而使所述第一静电保护电路123、所述第二静电保护电路124、所述第三静电保护电路125及所述第四静电保护电路126均能保持原有的作用。例如，当所述第一静电保护电路123的第三薄膜晶体管T3因损坏而只能处于断开状态时，若外围电路区120的高压静电传输至所述数据线外段210时，虽然第三薄膜晶体管T3因损坏而无法工作，但高压静电仍可以启动第七薄膜晶体管T7的栅极，从而使静电电荷从第七薄膜晶体管T7的漏极流到第七薄膜晶体管T7的源极，再从第七薄膜晶体管T7的源极流到所述短接线121，从而将所述外围电路区120的高压静电导出至接地端。可见，所述第一静电保护电路123仍然未丧失原有的作用，与第一实施例相比，本发明的第二实施例可进一步避免所述外围电路区120的高压静电电荷累积过大或高压静电释放点离所述显示区近时而导致击穿所述显示区内的部件。
请参阅一并参阅图1、图6和图7，图1是本发明的实施例中阵列基板的结构示意图，图6是本发明第三实施例中对应图1中I部分的结构示意图，图7是本发明第三实施例中对应图1中II部分的结构示意图。本发明的第三实施 例中的阵列基板的结构与第一实施例中所述阵列基板的结构基本相同，不同之处在于：本实施例(第三实施例)中的阵列基板的第一静电保护电路123还包括第七薄膜晶体管T7，所述第七薄膜晶体管T7与所述第三薄膜晶体管T3串联；所述第二静电保护电路124还包括第八薄膜晶体管T8，所述第八薄膜晶体管T8与所述第四薄膜晶体管T4串联；所述第三静电保护电路125还包括第九薄膜晶体管T9，所述第九薄膜晶体管T9与所述第五薄膜晶体管T5串联；所述第四静电保护电路126还包括第十薄膜晶体管T10，所述第十薄膜晶体管T10与所述第六薄膜晶体管串联。因此，所述第一静电保护电路123、所述第二静电保护电路124、所述第三静电保护电路125及所述第四静电保护电路126均包括两个串联的薄膜晶体管。
在本实施例的另外的实施方式中，所述第一静电保护电路123、所述第二静电保护电路124、所述第三静电保护电路125及所述第四静电保护电路126均包括更多个串联的薄膜晶体管。
在本实施例中，由于所述第一静电保护电路123、所述第二静电保护电路124、所述第三静电保护电路125及所述第四静电保护电路126均包括至少两个串联的薄膜晶体管，因此，当每一静电保护电路的其中一个薄膜晶体因损坏而只能处于短路状态时，另一个薄膜晶体管可以正常工作，以防止因所述数据线外段210与所述短接线121发生短路而引起阵列基板无法工作的情况，并且仍然可起到静电保护的作用，从而使所述第一静电保护电路123、所述第二静电保护电路124、所述第三静电保护电路125及所述第四静电保护电路126均能保持原有的作用。例如，当所述第一静电保护电路123的第三薄膜晶体管T3因损坏而只能处于短路状态时，若外围电路区120的高压静电传输至所述数据线外段210时，虽然第三薄膜晶体管T3因损坏而无法工作，但高压静电仍可以启动第七薄膜晶体管T7的栅极，从而使静电电荷从第七薄膜晶体管T7的漏极流到第七薄膜晶体管T7的源极，再从第七薄膜晶体管T7的源极流到所述短接线121，从而将所述外围电路区120的高压静电导出至接地端。可见，所述第一静电保护电路123仍然未丧失原有的作用，并且防止所述数据线外段210与所述短接线121短路而引起阵列基板无法工作的情况。
本发明还提供一种液晶显示装置，所述液晶显示装置包括上述图1至图7所示的任一实施例或实施方式所述的阵列基板。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述的实施方式，并不构成对该技术方案保护范围的限定。任何在上述实施方式的精神和原则之内所作的修改、等同替换和改进等，均应包含在该技术方案的保护范围之内。

Claims (20)

  1. 一种阵列基板，包括基板及设置于所述基板上的多条数据线和多条扫描线；其中，所述基板包括显示区及设置于所述显示区周侧的外围电路区，每条所述数据线包括数据线外段和数据线内段，每条所述扫描线包括扫描线外段和扫描线内段，所述数据线外段和所述扫描线外段设置于所述外围电路区，所述数据线内段及所述扫描线内段均从所述外围电路区延伸至所述显示区；
    所述外围电路区还设置有短接线、使能信号线、多个第一薄膜晶体管、多个第二薄膜晶体管、多个第一静电保护电路、多个第二静电保护电路、多个第三静电保护电路及多个第四静电保护电路，每个所述第一薄膜晶体管及每个所述第二薄膜晶体管的栅极均连接于所述使能信号线，所述第一薄膜晶体管的漏极连接于一条所述数据线的数据线外段，所述第一薄膜晶体管的源极连接于同一条所述数据线的数据线内段；每个所述第二薄膜晶体管的漏极连接于一条所述扫描线的扫描线外段，所述第二薄膜晶体管的源极连接于同一条所述扫描线的扫描线内段；所述第一静电保护电路的一端连接于所述数据线外段，另一端连接于所述短接线；所述第二静电保护电路的一端连接于所述数据线内段，另一端连接于所述短接线；所述第三静电保护电路的一端连接于所述扫描线外段，另一端连接于所述短接线；所述第四静电保护电路的一端连接于所述扫描线内段，另一端连接于所述短接线；所述使能信号线控制所述第一薄膜晶体管和所述第二薄膜晶体管导通或断开。
  2. 如权利要求1所述的阵列基板，其中，所述第一静电保护电路包括第三薄膜晶体管，所述第三薄膜晶体管的栅极和漏极连接于所述数据线外段，源极连接于所述短接线，所述第二静电保护电路包括第四薄膜晶体管，所述第四薄膜晶体管的栅极和漏极连接于所述数据线内段，源极连接于所述短接线。
  3. 如权利要求2所述的阵列基板，其中，所述第一静电保护电路还包括第七薄膜晶体管，所述第七薄膜晶体管与所述第三薄膜晶体管并联或串联；所述第二静电保护电路还包括第八薄膜晶体管，所述第八薄膜晶体管与所述第四薄膜晶体管并联或串联。
  4. 如权利要求1所述的阵列基板，其中，所述第三静电保护电路包括第五 薄膜晶体管，所述第五薄膜晶体管的栅极和漏极连接于所述扫描线外段，所述第五薄膜晶体管的源极连接于所述短接线，所述第四静电保护电路包括第六薄膜晶体管，所述第六薄膜晶体管的栅极和漏极连接于所述扫描线内段，所述第六薄膜晶体管的源极连接于所述短接线。
  5. 如权利要求4所述的阵列基板，其中，所述第三静电保护电路还包括第九薄膜晶体管，所述第九薄膜晶体管与所述第五薄膜晶体管并联或串联；所述第四静电保护电路还包括第十薄膜晶体管，所述第十薄膜晶体管与所述第六薄膜晶体管并联或串联。
  6. 如权利要求1所述的阵列基板，其中，所述使能信号线处于高电平状态时，所述第一薄膜晶体管及所述第二薄膜晶体管处于导通状态，所述使能信号线处于低电平状态时，所述第一薄膜晶体管及所述第二薄膜晶体管处于断开状态。
  7. 如权利要求2所述的阵列基板，其中，所述使能信号线处于高电平状态时，所述第一薄膜晶体管及所述第二薄膜晶体管处于导通状态，所述使能信号线处于低电平状态时，所述第一薄膜晶体管及所述第二薄膜晶体管处于断开状态。
  8. 如权利要求3所述的阵列基板，其中，所述使能信号线处于高电平状态时，所述第一薄膜晶体管及所述第二薄膜晶体管处于导通状态，所述使能信号线处于低电平状态时，所述第一薄膜晶体管及所述第二薄膜晶体管处于断开状态。
  9. 如权利要求4所述的阵列基板，其中，所述使能信号线处于高电平状态时，所述第一薄膜晶体管及所述第二薄膜晶体管处于导通状态，所述使能信号线处于低电平状态时，所述第一薄膜晶体管及所述第二薄膜晶体管处于断开状态。
  10. 如权利要求5所述的阵列基板，其中，所述使能信号线处于高电平状态时，所述第一薄膜晶体管及所述第二薄膜晶体管处于导通状态，所述使能信号线处于低电平状态时，所述第一薄膜晶体管及所述第二薄膜晶体管处于断开状态。
  11. 如权利要求1所述的阵列基板，其中，所述第一薄膜晶体管及所述 第二薄膜晶体管处于导通状态时，所述显示区进行工作，所述第一薄膜晶体管及所述第二薄膜晶体管处于断开状态时，所述显示区停止工作。
  12. 如权利要求2所述的阵列基板，其中，所述第一薄膜晶体管及所述第二薄膜晶体管处于导通状态时，所述显示区进行工作，所述第一薄膜晶体管及所述第二薄膜晶体管处于断开状态时，所述显示区停止工作。
  13. 如权利要求3所述的阵列基板，其中，所述第一薄膜晶体管及所述第二薄膜晶体管处于导通状态时，所述显示区进行工作，所述第一薄膜晶体管及所述第二薄膜晶体管处于断开状态时，所述显示区停止工作。
  14. 一种液晶显示装置，其中，所述液晶显示装置包括阵列基板，所述阵列基板包括基板及设置于所述基板上的多条数据线和多条扫描线；所述基板包括显示区及设置于所述显示区周侧的外围电路区，每条所述数据线包括数据线外段和数据线内段，每条所述扫描线包括扫描线外段和扫描线内段，所述数据线外段和所述扫描线外段设置于所述外围电路区，所述数据线内段及所述扫描线内段均从所述外围电路区延伸至所述显示区；
    所述外围电路区还设置有短接线、使能信号线、多个第一薄膜晶体管、多个第二薄膜晶体管、多个第一静电保护电路、多个第二静电保护电路、多个第三静电保护电路及多个第四静电保护电路，每个所述第一薄膜晶体管及每个所述第二薄膜晶体管的栅极均连接于所述使能信号线，所述第一薄膜晶体管的漏极连接于一条所述数据线的数据线外段，所述第一薄膜晶体管的源极连接于同一条所述数据线的数据线内段；每个所述第二薄膜晶体管的漏极连接于一条所述扫描线的扫描线外段，所述第二薄膜晶体管的源极连接于同一条所述扫描线的扫描线内段；所述第一静电保护电路的一端连接于所述数据线外段，另一端连接于所述短接线；所述第二静电保护电路的一端连接于所述数据线内段，另一端连接于所述短接线；所述第三静电保护电路的一端连接于所述扫描线外段，另一端连接于所述短接线；所述第四静电保护电路的一端连接于所述扫描线内段，另一端连接于所述短接线；所述使能信号线控制所述第一薄膜晶体管和所述第二薄膜晶体管导通或断开。
  15. 如权利要求14所述的液晶显示装置，其中，所述第一静电保护电路包括第三薄膜晶体管，所述第三薄膜晶体管的栅极和漏极连接于所述数据线外 段，源极连接于所述短接线，所述第二静电保护电路包括第四薄膜晶体管，所述第四薄膜晶体管的栅极和漏极连接于所述数据线内段，源极连接于所述短接线。
  16. 如权利要求15所述的液晶显示装置，其中，所述第一静电保护电路还包括第七薄膜晶体管，所述第七薄膜晶体管与所述第三薄膜晶体管并联或串联；所述第二静电保护电路还包括第八薄膜晶体管，所述第八薄膜晶体管与所述第四薄膜晶体管并联或串联。
  17. 如权利要求14所述的液晶显示装置，其中，所述第三静电保护电路包括第五薄膜晶体管，所述第五薄膜晶体管的栅极和漏极连接于所述扫描线外段，所述第五薄膜晶体管的源极连接于所述短接线，所述第四静电保护电路包括第六薄膜晶体管，所述第六薄膜晶体管的栅极和漏极连接于所述扫描线内段，所述第六薄膜晶体管的源极连接于所述短接线。
  18. 如权利要求17所述的液晶显示装置，其中，所述第三静电保护电路还包括第九薄膜晶体管，所述第九薄膜晶体管与所述第五薄膜晶体管并联或串联；所述第四静电保护电路还包括第十薄膜晶体管，所述第十薄膜晶体管与所述第六薄膜晶体管并联或串联。
  19. 如权利要求14所述的液晶显示装置，其中，所述使能信号线处于高电平状态时，所述第一薄膜晶体管及所述第二薄膜晶体管处于导通状态，所述使能信号线处于低电平状态时，所述第一薄膜晶体管及所述第二薄膜晶体管处于断开状态。
  20. 如权利要求14所述的液晶显示装置，其中，所述第一薄膜晶体管及所述第二薄膜晶体管处于导通状态时，所述显示区进行工作，所述第一薄膜晶体管及所述第二薄膜晶体管处于断开状态时，所述显示区停止工作。
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