WO2017133466A1 - 高速低功耗触发器 - Google Patents

高速低功耗触发器 Download PDF

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Publication number
WO2017133466A1
WO2017133466A1 PCT/CN2017/071645 CN2017071645W WO2017133466A1 WO 2017133466 A1 WO2017133466 A1 WO 2017133466A1 CN 2017071645 W CN2017071645 W CN 2017071645W WO 2017133466 A1 WO2017133466 A1 WO 2017133466A1
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Prior art keywords
nmos transistor
drain
output
gate
pmos transistor
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PCT/CN2017/071645
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English (en)
French (fr)
Inventor
徐代果
胡刚毅
李儒章
王健安
陈光炳
王育新
付东兵
刘涛
刘璐
邓民明
石寒夫
王旭
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中国电子科技集团公司第二十四研究所
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Priority to US16/064,658 priority Critical patent/US10425065B2/en
Publication of WO2017133466A1 publication Critical patent/WO2017133466A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
    • H03K3/356139—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356165—Bistable circuits using complementary field-effect transistors using additional transistors in the feedback circuit
    • H03K3/356173—Bistable circuits using complementary field-effect transistors using additional transistors in the feedback circuit with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356182—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the master-slave type
    • H03K3/35625—Bistable circuits of the master-slave type using complementary field-effect transistors

Definitions

  • the invention belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed low-power trigger.
  • flip-flops are widely used in digital, analog and analog-to-digital hybrid circuits.
  • the demand for high-speed low-power flip-flops has gradually increased.
  • the power supply voltage is further reduced.
  • a high-speed, low-power flip-flop structure including a SAFF (sense amplifier based flip-flop) structure, a MSAFF (modified sense amplifier based flip-flop), and a SBFF (self-blocking flip-flop) structure.
  • SAFF sense amplifier based flip-flop
  • MSAFF modified sense amplifier based flip-flop
  • SBFF self-blocking flip-flop
  • FIG. 1 shows the SAFF structure flip-flop.
  • the SAFF structure flip-flop consists of two stages of latches.
  • the first stage latch consists of NMOS transistors M0 to M3 and PMOS transistors M4 to M9.
  • the source of M0 is grounded.
  • the drain of M0 is connected to the source of M1 and M2, the gate of M0 is connected to the clock signal CLK, the gate of M3 is connected to the power supply vdd, the source and drain are respectively connected to the drains of M1 and M2, and the drains of M1 and M2 are simultaneously Connected to the source of M4 and M5 respectively, the gates of M1 and M2 are connected to the input signal D and its inverted signal DB, and the M3 tube is normally open, acting as a resistor to prevent large voltage fluctuations at both ends, M4/M5/M6 /M7 constitutes the input/output connected latch structure, M8 and M9 act as enable tubes, connect the power supply vdd and the output of the
  • the second stage latch is composed of NMOS transistors M10 to M13 and PMOS transistors M14 to M17, wherein the sources of M10 and M11 are grounded, the drains thereof are respectively connected to the sources of M12 and M13, and the gates thereof are respectively connected to the first stage lock.
  • the register output signals SB and RB, M12/M13/M14/M17 constitute the input/output latch structure, M15 and M16 act as the enable tubes, connect the power supply vdd and the output of the second stage latch, their gates The outputs SB and RB of the first stage latch are respectively connected.
  • the delay time td1 between the rising edge of the clock CLK and the data refresh is the delay time of the flip-flop of Figure 1, which is the sum of the delay times of the two-stage latches.
  • the advantage of FIG. 1 is that the structure of each stage of the latch is relatively simple, and the circuit design is easy to implement.
  • the disadvantage is that the structure of the two-stage latch is relatively slow, and the speed of the second stage latch is relatively slow.
  • Figure 3 shows the MSAFF structure flip-flop.
  • the SAFF structure flip-flop is composed of two-stage latches.
  • the schematic diagram of the first-stage latch is the same as that of Figure 1, and the working principle is the same.
  • the memory is composed of an inverter 11 and an I2, an NMOS transistor M10/M11/M12/M16/M17/M18, and a PMOS transistor M13/M14/M15/M19/M20/M21, wherein the output SB of the first-stage latch /RB is the input signal of the second-stage latch.
  • the input terminals of the inverters I1 and I2 are respectively connected to RB and SB, and the output terminals thereof are respectively connected to the gates of M10 and M17, and the sources of M10 and M17 are grounded.
  • the drains are respectively connected to the drains of M14 and M21, and the drains of M13/M12, the gates of M16/M20 and the drains of M18/M19, the gates of M11/M15, and the sources of M11 and M16 are grounded.
  • the drains are connected to the sources of M12 and M18, the sources of M15 and M20 are connected to the power supply vdd, and their drains are connected to M13 respectively.
  • the gates of M12 and M14 are connected to SB, the gates of M18 and M21 are connected to RB, the gate of M13 is connected to R, and the gate of M19 is connected to S.
  • the clock signal CLK is low, M0 is turned off, M8 and M9 are turned on, the first stage latch is in the reset state, and the output signals SB and RB of the first stage latch are both high level, the second stage In the latch, M10/M17/M14/M21 are turned off, M12/M13/M18/M19 is turned on, and the second stage latch is in the latched state.
  • the delay time td2 between the rising edge of the clock CLK and the data refresh is the delay time of the flip-flop of Figure 2, which is also the sum of the delay times of the two-stage latches.
  • the second-stage flip-flop of Figure 2 has an upper pull-down path consisting of M10 and M14, and M17 and M21, which makes the second-stage latch of Figure 2 and the structure [1]
  • the second stage latch is faster than the second stage.
  • the advantage of Figure 2 is that the second-stage latch is faster, but the structure is more complicated and the power consumption is higher. At the same time, the structure of the two-stage latch is relatively slow.
  • Figure 5 shows the SBFF structure flip-flop.
  • the SBFF structure flip-flop is composed of a control signal generating circuit and a first-level latch, wherein the NMOS transistors M0 to M4 and the PMOS transistor M5 constitute a control signal generating circuit, and the NMOS transistor M6 to M11 and PMOS transistors M12 to M16 constitute a latch.
  • the source of M0 is grounded, the drain is connected to the sources of M1 and M2, the drains of M1 and M2 are connected to the sources of M3 and M4, the drains of M3 and M4 are connected to the drain of M5, and the source of M5 is connected to the power supply vdd.
  • the gates of M0 and M5 are connected to the clock signal CLK, the gate of M1 is connected to the output signal Q, the gate of M3 is connected to the input signal D, the gate of M2 is connected to the inverted signal QB of the output signal Q, and the gate of M4 is connected to the input signal.
  • the source of M10 is grounded, the drain is connected to the source of M11, the drain of M11 is connected to the source of M7 and M8, and the output of the flip-flop is M6/M9/M12/M13.
  • Output connected latch structure its output also serves as the output of the latch, the gate of M16 is grounded, the drains of M12 and M13 are connected to the ends of M16, and the drains of M14 and M15 are respectively connected, M14 and M15
  • the source is connected to the power supply vdd, the gates of M10 and M11 are respectively connected to the control signal X and the clock signal CLK, the gates of M8 and M14 are connected to the input signal D, and the gates of M7 and M15 are connected to the inverted signal DB of the input signal D.
  • the flip-flop has a pull-down path composed of M7 and M8, so its speed is compared to that of Figures 1 and 3.
  • the structure has improved.
  • the control signal generating circuit and the enable tube of the latch are all connected in series by the NMOS transistor, and the on-resistance is large, and the parasitic capacitance at the output end of the flip-flop is also large, which is not suitable for high-speed circuit design.
  • the present invention provides a high-speed low-power flip-flop, which is composed of a control signal generating circuit and a primary latch without increasing the design cost, and the structure reduces the parasitic capacitance at the output end, thereby Achieved the design goal of high-speed low-power triggers.
  • a high-speed low-power flip-flop including a control signal generating circuit, an enabling unit and a latch structure, the latch structure including a first input end and a second An input terminal, a first output terminal, a second output terminal, a first enable terminal, a second enable terminal, and a ground terminal
  • the enabling unit includes a first enabling circuit and a second enabling circuit
  • the control signal Generating an output signal X of the circuit and an external control signal D as an input signal of the first enabling circuit, the output of the first enabling circuit is connected to the first enabling end, and the output of the control signal generating circuit
  • the output signal X and the inverted signal DB of the external control signal D are used as input signals of the second enable circuit, and the output end of the second enable circuit is connected to the second enable terminal; meanwhile, the external control signal D is used as the first An input signal of an input, the inverted signal DB of the external control signal D serves as an input
  • control signal generating circuit is an inverter
  • the input signal of the inverter is a clock signal CLK
  • the output signal of the inverter is X.
  • the inverter includes an NMOS transistor M132 and a PMOS transistor M22.
  • the source of the PMOS transistor M22 is connected to the power supply
  • the drain of the PMOS transistor M22 is connected to the drain of the NMOS transistor M132
  • the source of the NMOS transistor M132 is grounded.
  • the gate of the NMOS transistor M132 is connected to the gate of the PMOS transistor M22, and is connected to the clock signal CLK.
  • the drain of the NMOS transistor M132 and the pole of the PMOS transistor M22 serve as the output terminal of the control signal generating circuit and generate an output signal X.
  • the latch structure includes NMOS transistors M32-M72 and PMOS transistors M82-M122.
  • the source of the PMOS transistor M102 is connected to the source of the PMOS transistor M112, and the drain of the PMOS transistor M102 is connected to the PMOS transistor M82.
  • a source a source of the PMOS transistor M122 is connected, a drain of the PMOS transistor M112 is respectively connected to a source of the PMOS transistor M192, a drain of the PMOS transistor M122, and a gate of the PMOS transistor M122 is grounded; the PMOS The drain of the transistor M82 is respectively connected to the drain of the NMOS transistor M52, the drain of the NMOS transistor M42, the gate of the PMOS transistor M92, and the gate of the NMOS transistor M62; the drain of the PMOS transistor M92 is respectively connected to the NMOS transistor M62.
  • the second enable end, the source of the NMOS transistor M42, the source of the NMOS transistor M72 are respectively connected to the drain of the NMOS transistor M32, the source of the NMOS transistor M32 is grounded, and the gate of the NMOS transistor M32 is connected to the clock signal CLK;
  • the drain of the NMOS transistor M52 is grounded to the drain of the NMOS transistor M62; the drain of the NMOS transistor M42 serves as a first output of the flip-flop and generates an output signal QB, the NMOS
  • the drain of transistor M72 acts as the second output of the flip flop and produces an output signal Q.
  • the first enabling circuit comprises an AND gate AND1, an output of the AND gate AND1 is connected to a gate of the NMOS transistor M42, and the second enabling circuit comprises an AND gate AND2, an output terminal of the AND gate AND2 and an NMOS transistor The gate of the M72 is connected.
  • the present invention has the following beneficial technical effects:
  • the invention provides a control signal generating circuit for a flip-flop, which can adjust the delay time between the falling edge of the control signal X and the rising edge of the clock CLK by adjusting the aspect ratio of the NMOS transistor M1. This time is the latch.
  • the latch time of the device can be designed according to the actual application. Compared with the conventional control signal generating circuit, it is not realized by the series structure of the MOS tube, and the speed of the control signal generating circuit is improved.
  • the invention provides a latch structure, the enabling tube of the structure is composed of a NMOS tube to the ground, and at the same time, the input signal is enabled by the control signal X, thereby avoiding the serial connection to the ground through two in the conventional structure.
  • the NMOS transistor acts as an enable transistor structure, thereby increasing the speed of the latch, while the structure has no static power dissipation.
  • the present invention proposes a flip-flop circuit composed of the above-mentioned control signal generating circuit and latch.
  • the flip-flop structure proposed by the present invention has a simple circuit structure and a small parasitic capacitance at the output end of the latch. , the speed of the trigger is increased, and there is no static power consumption.
  • Figure 1 is a schematic diagram of a SAFF (sense amplifier based flip-flop) structure
  • FIG. 2 is a timing diagram of a SAFF (sense amplifier based flip-flop) structure
  • Figure 3 is a schematic diagram of the MSAFF (modify sense amplifier based flip-flop) structure
  • FIG. 4 is a timing diagram of a MSAFF (modify sense amplifier based flip-flop) structure
  • Figure 5 is a schematic diagram of a SBFF (self-blocking flip-flop) structure
  • SBFF self-blocking flip-flop
  • FIG. 7 is a schematic structural diagram of a high-speed low-power flip-flop structure proposed by the present invention.
  • FIG. 8 is a timing diagram of a high speed low power flip-flop structure proposed by the present invention.
  • Figure 9 is a comparison of the four structural properties.
  • a high-speed low-power flip-flop includes a control signal generating circuit, an enabling unit and a latch structure, and the latch structure
  • the enabling unit includes a first enabling circuit and a second An enable circuit, an output signal X of the control signal generating circuit and an external control signal D as an input signal of the first enable circuit, the output end of the first enable circuit being connected to the first enable end, the control
  • the output signal X of the signal generating circuit and the inverted signal DB of the external control signal D serve as input signals of the second enabling circuit, and the output of the second enabling circuit is connected to the second enabling terminal; meanwhile, external control The signal D serves as an input signal to the first input, and the inverted signal DB of the external control signal D serves as an input signal to the second input.
  • the control signal generating circuit is an inverter, the input signal of the inverter is a clock signal CLK, and the output signal of the inverter is X.
  • the inverter includes an NMOS transistor M132 and a PMOS transistor M22.
  • the source of the PMOS transistor M22 is connected to a power source
  • the drain of the PMOS transistor M22 is connected to the drain of the NMOS transistor M132
  • the source of the NMOS transistor M132 is grounded.
  • the gate of the M132 is connected to the gate of the PMOS transistor M22, and is connected to the clock signal CLK.
  • the drain of the NMOS transistor M132 and the pole of the PMOS transistor M22 serve as the output of the control signal generating circuit and generate an output signal X.
  • the latch structure includes NMOS transistors M32-M72 and PMOS transistors M82-M122.
  • the source of the PMOS transistor M102 is connected to the source of the PMOS transistor M112, and the drain of the PMOS transistor M102 is respectively connected to the source of the PMOS transistor M82.
  • the drain of the PMOS transistor M122 is connected to the source of the PMOS transistor M192 and the drain of the PMOS transistor M122, and the gate of the PMOS transistor M122 is grounded; the PMOS transistor M82 The drain is connected to the drain of the NMOS transistor M52, the drain of the NMOS transistor M42, the gate of the PMOS transistor M92, and the gate of the NMOS transistor M62; the drain of the PMOS transistor M92 and the drain of the NMOS transistor M62, respectively.
  • the drain of the NMOS transistor M72, the gate of the PMOS transistor M82, and the gate of the NMOS transistor M52 are connected; the gate of the NMOS transistor M42 serves as a first enable terminal, and the gate of the NMOS transistor M72 serves as a second
  • the source, the source of the NMOS transistor M42, the source of the NMOS transistor M72 are respectively connected to the drain of the NMOS transistor M32, the source of the NMOS transistor M32 is grounded, and the gate of the NMOS transistor M32 is connected to the clock signal CLK;
  • the drain of the transistor M52 is grounded to the drain of the NMOS transistor M62; the drain of the NMOS transistor M42 serves as the first output of the flip-flop and generates an output signal QB, the drain of the NMOS transistor M72
  • the pole acts as a second output of the flip flop and produces an output signal Q.
  • the first enable circuit includes an AND gate AND1, the output of the AND gate AND1 is connected to the gate of the NMOS transistor M42, and the second enable circuit includes an AND gate AND2, an output of the AND gate AND2, and an NMOS transistor M72. Gate connection.
  • the inverter structure consisting of M132 and M22, by adjusting the width-to-length ratio of M132 to design the delay of the falling edge of the output signal X with respect to the rising edge of the clock signal CLK, the width-to-length ratio of the M22 tube is designed to be relatively large, and can be approximated.
  • Output signal X The rising edge has no delay with respect to the falling edge of the clock signal CLK. Based on the above analysis, the signal X can be temporarily held at a high level after the clock signal CLK changes from a low level to a high level. In this short period of time, the signals D and DB pass through the AND gates AND1 and AND2, respectively. Since CLK is high, M32 turns on, the latch is triggered and the signal is quickly latched.
  • the output signals Q and QB are quickly latched; when the control signal X changes from a high level to a low level, at this time, although M32 is still turned on, the AND gates AND1 and AND2 both output a low level, so that M42 and M72 is turned off, so, during the t2 period, the entire flip-flop has no static power consumption; when the clock signal CLK goes low, the control signal X goes high, M32 turns off, AND gates AND1 and AND2 The inverted signals DB of the input signals D and D are respectively output. Since M32 is turned off, the entire flip-flop is still in the latched state during the t3 period, and there is no static power consumption.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种高速低功耗触发器，包括控制信号生成电路、使能单元和锁存器结构，所述锁存器结构包括两输入端、两输出端、两使能端、第二使能端和接地端，所述使能单元包括两使能电路，所述控制信号生成电路的输出信号X和外部控制信号D作为第一使能电路的输入信号，所述第一使能电路的输出端与第一使能端连接，所述控制信号生成电路的输出信号X和外部控制信号D的反相信号DB作为第二使能电路的输入信号，所述第二使能电路的输出端与第二使能端连接；该触发器结构和传统结构相比，电路结构简单，并且锁存器的输出端寄生电容很小，提高了触发器的速度，并且没有静态功耗。

Description

高速低功耗触发器 技术领域
本发明属于模拟或数模混合集成电路技术领域，涉及一种高速低功耗触发器。
背景技术
触发器作为一种重要的时序电路结构，被广泛的应用于数字、模拟和模数混合集成电路之中。近年来，随着集成电路制造技术的不断发展，对高速低功耗触发器的需要逐渐增加，为了适应低功耗的要求，电源电压进一步降低，针对这一趋势，为了保证触发器的工作性能，发展出来一些高速低功耗触发器结构，其中，包括SAFF(sense amplifier based flip-flop)结构、MSAFF(modified sense amplifier based flip-flop)和SBFF(self-blocking flip-flop)结构，上述三种结构有着其各自的优缺点，但上述三种结构很难同时满足结构简单，并且实现高速低功耗触发器的特点。
为了更详细的描述上述问题，先来分析上述三种触发器的工作原理和优缺点。
图1给出了SAFF结构触发器，SAFF结构触发器由两级锁存器构成，第一级锁存器由NMOS管M0到M3，以及PMOS管M4到M9构成，其中，M0的源极接地，M0的漏极接M1和M2的源极，M0的栅极接时钟信号CLK，M3的栅极接电源vdd，其源漏分别接M1和M2的漏极，同时，M1和M2的漏极分别接M4和M5的源极，M1和M2的栅极接输入信号D和其反相信号DB，M3管常开，作为一个电阻，防止其两端出现大的电压波动，M4/M5/M6/M7构成输入/输出相连的锁存器结构，M8和M9作为使能管，连接电源vdd和第一级锁存器的输出，它们的栅极接时钟信号CLK。第二级锁存器由NMOS管M10到M13和PMOS管M14到M17构成，其中M10和M11的源极接地，其漏极分别接M12和M13的源极，其栅极分别接第一级锁存器输出信号SB和RB，M12/M13/M14/M17构成输入/输出相连的锁存器结构，M15和M16作为使能管，连接电源vdd和第二级锁存器的输出，它们的栅极分别接第一级锁存器的输出SB和RB。当时钟信号CLK为低电平时，M0关断，M8和M9导通，第一级锁存器处于复位状态，其输出SB和RB都为高电平，第二级锁存器处于锁存状态，其输出Q和QB保持上一个状态的值。当时钟信号CLK出低电平变为高电平时，M0导通，M8和M9关断，第一级锁存器根据输入信号D和其反相信号DB进行翻转，输出信号SB和RB之中，一个为高电平，一个为低电平，第二级锁存器的输出Q和QB被刷新一次。其工作时序图如图2所示，时钟CLK的上升沿和数据刷新之间的延迟时间td1是图1触发器的延迟时间，这个延迟时间是两级锁存器延迟时间之和。图1的优点在于，每一级锁存器结构比较简单，电路设计很易实现，但是，缺点在于两级锁存器结构速度相对比较慢，第二级锁存器速度也比较慢。
图3给出了MSAFF结构触发器，如图所示，SAFF结构触发器由两级锁存器构成，其第一级锁存器原理图和图1相同，工作原理也相同，第二级锁存器由反相器11和I2、NMOS管M10/M11/M12/M16/M17/M18和PMOS管M13/M14/M15/M19/M20/M21构成，其中，第一级锁存器的输出SB/RB作为第二级锁存器的输入信号，反相器I1、I2的输入端分别接RB和SB，其输出端分别接M10和M17的栅极，M10和M17的源极接地，它们的漏极分别接M14和M21的漏极，同时接M13/M12的漏极、M16/M20的栅极和M18/M19的漏极、M11/M15的栅极，M11和M16的源极接地，它们的漏极分别接M12和M18的源极，M15和M20的源极接电源vdd，它们的漏极分别接M13 和M19的漏极，M12和M14的栅极接SB，M18和M21的栅极接RB，M13的栅极接R，M19的栅极接S。当时钟信号CLK为低电平时，M0关断，M8和M9导通，第一级锁存器处于复位状态，第一级锁存器的输出信号SB和RB均为高电平，第二级锁存器中，M10/M17/M14/M21关断，M12/M13/M18/M19导通，第二级锁存器处于锁存状态。当时钟信号CLK由低电平变为高电平时，M0导通，M8和M9关断，第一级锁存器根据输入信号D和DB进行翻转，输出信号SB和RB之中，一个为高电平，一个为低电平，第二级锁存器的输出Q和QB被刷新一次。其工作时序图如图4所示，时钟CLK的上升沿和数据刷新之间的延迟时间td2是图2触发器的延迟时间，这个延迟时间同样是两级锁存器延迟时间之和。和图1相比，图2的第二级触发器多了一条由M10和M14，以及M17和M21构成的上下拉通路，这会使得图2的第二级锁存器和结构[1]的第二级锁存器相比，速度更快。图2的优点在于，第二级锁存器速度比较快，但结构比较复杂，功耗较高，同时，两级锁存器结构速度相对比较慢。
图5给出了SBFF结构触发器，如图所示，SBFF结构触发器由控制信号生成电路和一级锁存器构成，其中NMOS管M0到M4和PMOS管M5构成控制信号生成电路，NMOS管M6到M11和PMOS管M12到M16构成锁存器。M0源极接地，漏极接M1和M2的源极，M1和M2的漏极分别接M3和M4的源极，M3和M4的漏极接M5的漏极，M5的源极接电源vdd，M0和M5的栅极接时钟信号CLK，M1的栅极接输出信号Q，M3的栅极接输入信号D，M2的栅极接输出信号Q的反相信号QB，M4的栅极接输入信号D的反相信号DB。锁存器中，M10的源极接地，其漏极接M11的源极，M11的漏极接M7和M8的源极，同时作为触发器的输出端，M6/M9/M12/M13构成输入/输出相连的锁存器结构，其输出也作为锁存器的输出端，M16的栅极接地，M12和M13的漏极接M16的两端，同时分别接M14和M15的漏极，M14和M15的源极接电源vdd，M10和M11的栅极分别接控制信号X和时钟信号CLK，M8和M14的栅极接输入信号D，M7和M15的栅极接输入信号D的反相信号DB。当时钟信号CLK为低电平时，控制信号X为高电平，锁存器处于锁存状态，当时钟信号CLK由低电平变为高电平时，如果此时的输入信号D和前一状态输出信号Q同为高电平或者同为低电平，控制信号X变为低电平，锁存器仍然保持前一状态不变，其时序图如图6(a)所示，否则，控制信号X会保持为高电平，锁存器中，M10和M11同时导通，锁存器的输出信号Q会发生翻转，其时序图如图6(b)所示。图5的优点在于，其结构由一个控制信号生成电路和一级锁存器构成，同时，触发器多了一条由M7和M8构成的下拉通路，所以，其速度相比于图1和图3结构有所提高。但是，控制信号生成电路和锁存器的使能管都是由NMOS管串联而成，导通电阻较大，同时，触发器输出端的寄生电容也比较大，不适用于高速电路设计。
发明内容
鉴于此，本发明提供一种高速低功耗触发器，该结构在不增加设计成本的情况下，由控制信号生成电路和一级锁存器构成，该结构减小了输出端的寄生电容，从而实现了高速低功耗触发器的设计目标。
为达到上述目的，本发明提供如下技术方案：一种高速低功耗触发器，包括控制信号生成电路、使能单元和锁存器结构，所述锁存器结构包括第一输入端、第二输入端、第一输出端、第二输出端、第一使能端、第二使能端和接地端，所述使能单元包括第一使能电路和第二使能电路，所述控制信号生成电路的输出信号X和外部控制信号D作为第一使能电路的输入信号，所述第一使能电路的输出端与第一使能端连接，所述控制信号生成电路的输 出信号X和外部控制信号D的反相信号DB作为第二使能电路的输入信号，所述第二使能电路的输出端与第二使能端连接；同时，所外部控制信号D作为第一输入端的输入信号，所述外部控制信号D的反相信号DB作为第二输入端的输入信号。
进一步，所述控制信号生成电路为反相器，所述反相器的输入信号为时钟信号CLK，反相器的输出信号为X。
进一步，所述反相器包括NMOS管M132和PMOS管M22，所述PMOS管M22的源极接电源，PMOS管M22的漏极与NMOS管M132的漏极连接，NMOS管M132的源极接地，NMOS管M132的栅极与PMOS管M22的栅极连接，并接时钟信号CLK，所述NMOS管M132的漏极与PMOS管M22的极作为控制信号生成电路的输出端并产生输出信号X。
进一步，所述锁存器结构包括NMOS管M32～M72以及PMOS管M82～M122，所述PMOS管M102的源极与PMOS管M112的源极接电源，PMOS管M102的漏极分别与PMOS管M82的源极、PMOS管M122的源极连接，所述PMOS管M112的漏极分别与PMOS管M192的源极、PMOS管M122的漏极连接，所述PMOS管M122的栅极接地；所述PMOS管M82的漏极分别与NMOS管M52的漏极、NMOS管M42的漏极、PMOS管M92的栅极和NMOS管M62的栅极连接；所述PMOS管M92的漏极分别与NMOS管M62的漏极、NMOS管M72的漏极、PMOS管M82的栅极和NMOS管M52的栅极连接；所述NMOS管M42的栅极作为第一使能端，所述NMOS管M72的栅极作为第二使能端，所述NMOS管M42的源极、NMOS管M72的源极分别与NMOS管M32的漏极连接，NMOS管M32的源极接地，NMOS管M32的栅极接时钟信号CLK；所述NMOS管M52的漏极与NMOS管M62的漏极接地；所述NMOS管M42的漏极作为触发器的第一输出端并产生输出信号QB，所述NMOS管M72的漏极作为触发器的第二输出端并产生输出信号Q。
进一步，所述第一使能电路包括与门AND1，与门AND1的输出端与NMOS管M42的栅极连接，所述第二使能电路包括与门AND2，与门AND2的输出端与NMOS管M72的栅极连接。
由于采用了以上技术方案，本发明具有以下有益技术效果：
本发明提出了一种触发器的控制信号生成电路，可以通过调整NMOS管M1的宽长比，从而调整控制信号X的下降沿和时钟CLK的上升沿之间的延迟时间，这个时间就是锁存器的锁存时间，可以根据实际应用的不同来设计M1的宽长比。和传统控制信号生成电路相比，不用通过MOS管的串联结构来实现，提高了控制信号生成电路的速度。
本发明提出了一种锁存器结构，该结构的使能管由一个到地的NMOS管构成，同时，通过控制信号X来对输入信号进行使能，避免了传统结构中通过两个串联到地的NMOS管作为使能管的结构，从而提高了锁存器的速度，同时，该结构没有静态功耗。
本发明提出了一个由上述控制信号生成电路和锁存器构成的触发器电路，本发明所提出的触发器结构和传统结构相比，电路结构简单，并且锁存器的输出端寄生电容很小，提高了触发器的速度，并且没有静态功耗。
附图说明
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步的详细描述，其中：
图1为SAFF(sense amplifier based flip-flop)结构原理图；
图2为SAFF(sense amplifier based flip-flop)结构时序图；
图3为MSAFF(modify sense amplifier based flip-flop)结构原理图；
图4为MSAFF(modify sense amplifier based flip-flop)结构时序图；
图5为SBFF(self-blocking flip-flop)结构原理图；
图6为SBFF(self-blocking flip-flop)结构时序图；
图7为本发明所提出的高速低功耗触发器结构原理图；
图8为本发明所提出的高速低功耗触发器结构时序图；
图9为四种结构性能对比图。
具体实施方式
以下将结合附图，对本发明的优选实施例进行详细的描述；应当理解，优选实施例仅为了说明本发明，而不是为了限制本发明的保护范围。
本发明所提出的高速低功耗触发器结构原理图如图7所示，一种高速低功耗触发器，包括控制信号生成电路、使能单元和锁存器结构，所述锁存器结构包括第一输入端、第二输入端、第一输出端、第二输出端、第一使能端、第二使能端和接地端，所述使能单元包括第一使能电路和第二使能电路，所述控制信号生成电路的输出信号X和外部控制信号D作为第一使能电路的输入信号，所述第一使能电路的输出端与第一使能端连接，所述控制信号生成电路的输出信号X和外部控制信号D的反相信号DB作为第二使能电路的输入信号，所述第二使能电路的输出端与第二使能端连接；同时，所外部控制信号D作为第一输入端的输入信号，所述外部控制信号D的反相信号DB作为第二输入端的输入信号。
所述控制信号生成电路为反相器，所述反相器的输入信号为时钟信号CLK，反相器的输出信号为X。所述反相器包括NMOS管M132和PMOS管M22，所述PMOS管M22的源极接电源，PMOS管M22的漏极与NMOS管M132的漏极连接，NMOS管M132的源极接地，NMOS管M132的栅极与PMOS管M22的栅极连接，并接时钟信号CLK，所述NMOS管M132的漏极与PMOS管M22的极作为控制信号生成电路的输出端并产生输出信号X。
所述锁存器结构包括NMOS管M32～M72以及PMOS管M82～M122，所述PMOS管M102的源极与PMOS管M112的源极接电源，PMOS管M102的漏极分别与PMOS管M82的源极、PMOS管M122的源极连接，所述PMOS管M112的漏极分别与PMOS管M192的源极、PMOS管M122的漏极连接，所述PMOS管M122的栅极接地；所述PMOS管M82的漏极分别与NMOS管M52的漏极、NMOS管M42的漏极、PMOS管M92的栅极和NMOS管M62的栅极连接；所述PMOS管M92的漏极分别与NMOS管M62的漏极、NMOS管M72的漏极、PMOS管M82的栅极和NMOS管M52的栅极连接；所述NMOS管M42的栅极作为第一使能端，所述NMOS管M72的栅极作为第二使能端，所述NMOS管M42的源极、NMOS管M72的源极分别与NMOS管M32的漏极连接，NMOS管M32的源极接地，NMOS管M32的栅极接时钟信号CLK；所述NMOS管M52的漏极与NMOS管M62的漏极接地；所述NMOS管M42的漏极作为触发器的第一输出端并产生输出信号QB，所述NMOS管M72的漏极作为触发器的第二输出端并产生输出信号Q。
所述第一使能电路包括与门AND1，与门AND1的输出端与NMOS管M42的栅极连接，所述第二使能电路包括与门AND2，与门AND2的输出端与NMOS管M72的栅极连接。
由M132和M22构成的反相器结构，通过调整M132的宽长比来设计输出信号X的下降沿相对于时钟信号CLK上升沿的延迟，M22管的宽长比设计得比较大，可近似认为输出信号X 的上升沿相对于时钟信号CLK的下降沿没有延迟。基于上述分析，信号X在时钟信号CLK由低电平变为高电平之后，能够短暂的保持高电平，在这个短暂的时间内，信号D和DB分别通过与门AND1和AND2，同时，由于CLK为高电平，M32导通，锁存器被触发并且迅速锁存信号，随后，信号X由高电平变为低电平，与门AND1和AND2输出低电平，M42和M72关断，整个触发器保持锁存状态，直至时钟信号CLK下一次变为高电平。其时序图如图8所示，时钟信号CLK的上升沿和控制信号X的下降沿之间存在一个延时t1，在这个时间段内，锁存器根据输入信号D和其反相信号DB，迅速将输出信号Q和QB锁存；当控制信号X由高电平变为低电平后，此时，虽然M32仍然导通，但是，与门AND1和AND2都输出低电平，使得M42和M72关断，所以，在t2时间段内，整个触发器并没有静态功耗；当时钟信号CLK变为低电平后，控制信号X变为高电平，M32关断，与门AND1和AND2分别输出输入信号D和D的反相信号DB，由于M32关断，所以在t3时间段内，整个触发器仍然处于锁存状态，同样没有静态功耗。
以上所述仅为本发明的优选实施例，并不用于限制本发明，显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (5)

  1. 一种高速低功耗触发器，其特征在于：包括控制信号生成电路、使能单元和锁存器结构，所述锁存器结构包括第一输入端、第二输入端、第一输出端、第二输出端、第一使能端、第二使能端和接地端，所述使能单元包括第一使能电路和第二使能电路，所述控制信号生成电路的输出信号X和外部控制信号D作为第一使能电路的输入信号，所述第一使能电路的输出端与第一使能端连接，所述控制信号生成电路的输出信号X和外部控制信号D的反相信号DB作为第二使能电路的输入信号，所述第二使能电路的输出端与第二使能端连接；同时，所外部控制信号D作为第一输入端的输入信号，所述外部控制信号D的反相信号DB作为第二输入端的输入信号。
  2. 根据权利要求1所述的高速低功耗触发器，其特征在于：所述控制信号生成电路为反相器，所述反相器的输入信号为时钟信号CLK，反相器的输出信号为X。
  3. 根据权利要求2所述的高速低功耗触发器，其特征在于：所述反相器包括NMOS管M132和PMOS管M22，所述PMOS管M22的源极接电源，PMOS管M22的漏极与NMOS管M132的漏极连接，NMOS管M132的源极接地，NMOS管M132的栅极与PMOS管M22的栅极连接，并接时钟信号CLK，所述NMOS管M132的漏极与PMOS管M22的极作为控制信号生成电路的输出端并产生输出信号X。
  4. 根据权利要求3所述的高速低功耗触发器，其特征在于：所述锁存器结构包括NMOS管M32～M72以及PMOS管M82～M122，所述PMOS管M102的源极与PMOS管M112的源极接电源，PMOS管M102的漏极分别与PMOS管M82的源极、PMOS管M122的源极连接，所述PMOS管M112的漏极分别与PMOS管M192的源极、PMOS管M122的漏极连接，所述PMOS管M122的栅极接地；所述PMOS管M82的漏极分别与NMOS管M52的漏极、NMOS管M42的漏极、PMOS管M92的栅极和NMOS管M62的栅极连接；所述PMOS管M92的漏极分别与NMOS管M62的漏极、NMOS管M72的漏极、PMOS管M82的栅极和NMOS管M52的栅极连接；所述NMOS管M42的栅极作为第一使能端，所述NMOS管M72的栅极作为第二使能端，所述NMOS管M42的源极、NMOS管M72的源极分别与NMOS管M32的漏极连接，NMOS管M32的源极接地，NMOS管M32的栅极接时钟信号CLK；所述NMOS管M52的漏极与NMOS管M62的漏极接地；所述NMOS管M42的漏极作为触发器的第一输出端并产生输出信号QB，所述NMOS管M72的漏极作为触发器的第二输出端并产生输出信号Q。
  5. 根据权利要求4所述的高速低功耗触发器，其特征在于：所述第一使能电路包括与门AND1，与门AND1的输出端与NMOS管M42的栅极连接，所述第二使能电路包括与门AND2，与门AND2的输出端与NMOS管M72的栅极连接。
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