WO2017133094A1 - 一种阵列基板的制造方法 - Google Patents

一种阵列基板的制造方法 Download PDF

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WO2017133094A1
WO2017133094A1 PCT/CN2016/081040 CN2016081040W WO2017133094A1 WO 2017133094 A1 WO2017133094 A1 WO 2017133094A1 CN 2016081040 W CN2016081040 W CN 2016081040W WO 2017133094 A1 WO2017133094 A1 WO 2017133094A1
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active layer
array substrate
manufacturing
substrate according
siox film
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French (fr)
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张占东
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/109,341 priority Critical patent/US20180097100A1/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0229—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials characterised by control of the annealing or irradiation parameters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/30—Diffusion for doping of conductive or resistive layers
    • H10P32/302—Doping polycrystalline silicon or amorphous silicon layers

Definitions

  • the present invention relates to the field of liquid crystal display manufacturing, and in particular to a method of fabricating an array substrate.
  • the display panel manufactured by Low Temperature Poly-silicon has the advantages of high resolution, fast response speed, high brightness, high aperture ratio, and the high electron mobility due to the characteristics of LTPS;
  • the peripheral driving circuit can be simultaneously fabricated on the glass substrate to achieve the goal of system integration, space saving and cost of driving the IC, and reduce product defect rate.
  • a buffer is first deposited on the glass substrate.
  • a layer followed by depositing amorphous silicon a-Si on the entire surface of the buffer layer, and forming a polysilicon layer by a dehydrogenation process and a low temperature crystallization process.
  • an active layer is formed by using a mask to perform pattern exposure, development, etching, and lift-off of the active layer, and then the formed active layer is ion-implanted.
  • the surface of the active layer is not damaged by ion implantation, and the surface of the active layer is usually coated with a photoresist to protect the surface, and the implanted ions pass through the photolithography.
  • the glue enters the active layer to achieve the final ion implantation effect.
  • the crystalline silicon layer is exposed, which causes certain ion pollution to the crystalline silicon layer.
  • the photoresist itself will cause some pollution to the crystalline silicon layer. The quality of the array substrate and the processing yield are seriously affected, and the existing manufacturing methods need to be improved.
  • An object of the present invention is to provide a method for fabricating an array substrate, which can reduce the array base
  • the board is contaminated during the manufacturing process to improve the quality of the array substrate and the processing yield.
  • the present invention provides a method of fabricating an array substrate, comprising the steps of: depositing an active layer including amorphous silicon on a substrate; covering an SiOx film on the active layer; and amorphous in the active layer Converting silicon into polysilicon; etching the active layer to form a pattern; implanting ions into the active layer; cleaning and removing the SiOx film.
  • the thickness of the SiOx film is less than 100 nm.
  • the SiOx film is covered on the active layer by chemical vapor deposition.
  • washing with hydrofluoric acid is performed to remove the SiOx film.
  • hydrofluoric acid concentration is less than 5%.
  • direction of ion implantation is perpendicular to the plane in which the substrate is located.
  • the amorphous silicon in the active layer is converted into polycrystalline silicon, and the amorphous silicon in the active layer is converted into polycrystalline silicon by excimer laser annealing or solid phase crystallization.
  • the active layer is laser annealed using a XeCl laser.
  • the active layer comprising amorphous silicon is formed on the substrate, comprising: providing a substrate; forming a buffer layer on the substrate; forming the active layer on the buffer layer.
  • the buffer layer is formed on the base substrate by a chemical vapor deposition method or a sputtering method.
  • the method for fabricating an array substrate of the present invention first covers an SiOx film on an active layer, and then performs conversion of amorphous silicon to polysilicon, active layer etching, ion implantation, and after ion implantation into the active layer,
  • the SiOx film enables the active layer to be in a film covering state during processing to achieve the technical effect of reducing active layer contamination.
  • FIG. 1 is a flow chart of a method for fabricating an array substrate of the present invention
  • FIG. 2 is a schematic structural view of the array substrate of the present invention after covering the SiOx film
  • FIG. 3 is a schematic structural view of the array substrate polycrystalline silicon after conversion according to the present invention.
  • FIG. 4 is a schematic structural view of the array substrate of the present invention after etching
  • FIG. 5 is a schematic structural view of the array substrate of the present invention after ion implantation
  • FIG. 6 is a schematic view showing the structure of the array substrate of the present invention after removing the SiOx film.
  • FIG. 1 is a flow chart of a method for fabricating an array substrate according to the present invention.
  • Step S101 First, an active layer 12 is deposited on the substrate 11, and the active layer 12 includes amorphous silicon.
  • the active layer 12 includes amorphous silicon a-Si.
  • the substrate 11 includes a base substrate 111 and a buffer layer 112, and in order to prevent adverse effects of the harmful substances in the base substrate 111 (usually using a glass material) on the performance of the active layer 12, it is necessary to first adopt PECVD, low pressure chemistry.
  • a buffer layer 112 is formed on the base substrate 111 by vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), electron cyclotron resonance chemical vapor deposition (ECR-CVD) or sputtering to block the inclusion in the glass.
  • LPCVD vapor deposition
  • APCVD atmospheric pressure chemical vapor deposition
  • ECR-CVD electron cyclotron resonance chemical vapor deposition
  • sputtering to block the inclusion in the glass.
  • the impurities diffuse into the active layer 12.
  • pre-cleaning of the substrate substrate 111 is required before the buffer layer 112 is deposited, improving the cleanliness of the substrate substrate 111.
  • the buffer layer 112 may be made of an oxide, a nitride or an oxynitride or the like.
  • the buffer layer 112 may be a single layer, a double layer, or a multilayer structure.
  • the buffer layer 31 may be SiNx, SiOx or Si(ON)x.
  • Step S103 The SiOx film 13 is then covered on the active layer 12.
  • the SiOx film 13 may be covered on the active layer 12 by chemical vapor deposition, so that the active layer 12 is isolated from the outside to prevent external ion pair active. Layer 12 causes contamination. Further, in order to ensure the subsequent processing quality, the thickness of the SiOx film 13 cannot be excessively large. Preferably, the thickness of the SiOx film 13 is less than 100 nm.
  • Step S105 The amorphous silicon in the active layer 12 is then converted into polysilicon.
  • the conversion of amorphous silicon a-Si into polysilicon poly-Si in the active layer 12 may be performed by Excimer Laser Annealing (ELA) or Solid Phase Crystallization (SPC).
  • ELA Excimer Laser Annealing
  • SPC Solid Phase Crystallization
  • the general excimer lasers include XeCl laser, ArF laser, KrF laser and XeF laser. These excimer lasers generate laser beams in the ultraviolet band and pass short-pulse laser beams in the ultraviolet band. Irradiating the amorphous silicon in the active layer 12, the amorphous silicon rapidly absorbs the laser energy to be melted and recrystallized.
  • the surface of the SiOx film 13 can be directly irradiated by a laser, and since the thickness of the SiOx film 13 is small, it is equivalent to direct irradiation on the active layer 12. Therefore, the excimer laser annealing effect is better.
  • the active layer 12 may be irradiated on the base substrate 111 by irradiation with an excimer laser.
  • the present invention is not limited thereto and may be selected according to actual needs.
  • the lasers usable in this step include, for example, ArF, KrF, and XeCl, and the respective laser wavelengths are, for example, 193 nm, 248 nm, and 308 nm, respectively, and the pulse width is, for example, between 10 and 50 ns.
  • the laser wavelength of the XeCl laser is long, the laser energy is injected into the amorphous silicon to be deep, and the crystallization effect is good, and a XeCl laser is preferably used.
  • the annealing process can also be obtained by other methods such as metal-induced crystallization (MIC).
  • MIC metal-induced crystallization
  • Step S107 The active layer is then etched to form a pattern.
  • the active layer 12 is exposed, developed, etched, and stripped using an active layer mask to form a mask pattern on the active layer 12 ( As shown in Figure 4).
  • Step S109 Again, referring to FIG. 5, ions are implanted into the active layer 12.
  • the ions in the ion implantation process may be one or more of the following: B ion, P ion, As ion, PHx ion.
  • Ion implantation is a commonly used doping technique. Ion implantation technology can use ion implantation with mass analyzer, ion cloud implantation without mass analyzer, plasma implantation or solid state diffusion implantation. In this embodiment, an ion cloud injection method is employed. Preferably, the direction of ion implantation should be perpendicular to the plane in which the substrate is located.
  • Step S111 Finally, the SiOx film 13 is removed by washing.
  • the SiOx film 13 is not required after the end of ion implantation and should be removed.
  • the SiOx film 13 can be washed with a low concentration of hydrofluoric acid (DHF). It is usually necessary to rinse the array substrate with hydrofluoric acid before covering the insulating layer. Therefore, the manufacturing method of the present invention does not add another process. Further preferably, the hydrofluoric acid concentration should be less than 5%.
  • an operation of covering the active layer 13 and the buffer layer 12 with an insulating layer or the like can be performed.
  • the method for fabricating an array substrate of the present invention first covers an SiOx film on an active layer, and then performs conversion of amorphous silicon to polysilicon, active layer etching, ion implantation, and after ion implantation into the active layer,
  • the SiOx film enables the active layer to be in a film covering state during processing to achieve the technical effect of reducing active layer contamination.

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Abstract

一种阵列基板的制造方法，包括如下步骤：在衬底上沉积包括非晶硅的有源层（S101）；在所述有源层上覆盖SiOx薄膜（S103）；将所述有源层中的非晶硅转化为多晶硅（S105）；对所述有源层进行蚀刻处理，以形成图形（S107）；将离子注入所述有源层（S109）；清洗去除所述SiOx薄膜（S111）。可防止有源层污染。

Description

一种阵列基板的制造方法
本发明要求2016年2月1日递交的发明名称为“一种阵列基板的制造方法”的申请号201610068636.9的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示器制造领域，尤其涉及一种阵列基板的制造方法。
背景技术
低温多晶硅技术(Low Temperature Poly-silicon，LTPS)制造的显示面板具有高分辨率、反应速度快、高亮度、高开口率等优点，加上由于LTPS的特点，使得其具有高的电子移动率；此外，还可以将外围驱动电路同时制造在玻璃基板上，达到系统整合的目标、节省空间及驱动IC的成本，并可减少产品不良率。
LTPS TFT阵列基板制造过程中，为提高TFT特性，对有源层进行离子注入是不可缺少的一个重要步骤，现有技术的LTPS TFT阵列基板制造工艺中，首先需要在玻璃基板上沉积一层缓冲层，之后在缓冲层的整个表面上沉积非晶硅a-Si，通过脱氢工艺以及低温晶化工艺形成多晶硅层。晶化结束后利用掩膜板进行有源层图形曝光、显影、刻蚀、剥离等工艺形成有源层，再对形成的有源层进行离子注入。
现有技术中，进行有源层离子注入时，为保护有源层的表面不被离子注入轰击所损伤，通常会在有源层表面涂覆光刻胶保护其表面，注入的离子通过光刻胶进入到有源层中，达到最终的离子注入效果。但是从沉积非晶硅a–Si到形成有源层的过程中，晶硅层都处于裸露状态，对晶硅层会造成一定的离子污染。此外，光刻胶本身也会对晶硅层造成一定的污染。严重影响了阵列基板的品质和加工良率，现有的制造方法亟待改进。
发明内容
本发明的目的在于提供一种阵列基板的制造方法，该方法可以减小阵列基 板在制造过程中受到的污染，提高阵列基板品质和加工良率。
为了实现上述目的，本发明实施方式提供如下技术方案：
本发明提供一种阵列基板的制造方法，包括如下步骤：在衬底上沉积包括非晶硅的有源层；在所述有源层上覆盖SiOx薄膜；将所述有源层中的非晶硅转化为多晶硅；对所述有源层进行蚀刻处理，以形成图形；将离子注入所述有源层；清洗去除所述SiOx薄膜。
其中，所述SiOx薄膜的厚度小于100nm。
其中，所述SiOx薄膜通过化学气相沉积法覆盖到所述有源层上。
其中，使用氢氟酸清洗以去除所述SiOx薄膜。
其中，所述氢氟酸浓度小于5％。
其中，离子的注入方向垂直于所述衬底所在的平面。
其中，所述有源层中的非晶硅转化为多晶硅，包括，使用准分子激光退火或者固相结晶的方法将所述有源层中的非晶硅转化为多晶硅。
其中，采用XeCl激光器对有源层进行激光退火。
其中，在衬底上形成包括非晶硅的有源层，包括：提供一衬底基板；在所述衬底基板上形成缓冲层；在所述缓冲层上形成所述有源层。
其中，所述缓冲层通过化学气相沉积法或溅射法形成于所述衬底基板上。
本发明实施例具有如下优点或有益效果：
本发明的阵列基板制造方法，先在有源层上覆盖SiOx薄膜，然后再进行非晶硅到多晶硅的转化、有源层蚀刻、离子注入过程，并在离子注入所述有源层后，除去所述SiOx薄膜，使得有源层在加工过程中始终处于薄膜覆盖状态，达到降低有源层污染的技术效果。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明阵列基板制造方法流程图；
图2是本发明阵列基板覆盖SiOx薄膜后结构示意图；
图3是本发明阵列基板多晶硅转换后结构示意图；
图4是本发明阵列基板蚀刻后结构示意图；
图5是本发明阵列基板注入离子后结构示意图；
图6是本发明阵列基板去除SiOx薄膜后结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明提供一种阵列基板的制造方法，请参阅图1，图1为本发明提供的阵列基板制造方法流程图。
步骤S101：首先在衬底11上沉积有源层12，所述有源层12中包括非晶硅。
所述有源层12中包括非晶硅a-Si。所述衬底11包括衬底基板111和缓冲层112，并且为了防止衬底基板111(通常采用玻璃材料)中有害物质对有源层12的性能产生不良影响，需要先采用以PECVD、低压化学气相沉积(LPCVD)、大气压化学气相沉积(APCVD)、电子回旋谐振化学气相沉积(ECR-CVD)或者溅射等方法在衬底基板111上形成一层缓冲层112，用于阻挡玻璃中所含的杂质扩散进入有源层12。此外，在沉积缓冲层112之前需要进行衬底基板111的预清洗，提高衬底基板111的清洁度。
进一步的，缓冲层112材料可选用氧化物、氮化物或者氮氧化物等。缓冲层112可以为单层、双层或者多层结构。具体地，缓冲层31可以是SiNx，SiOx或Si(ON)x。
步骤S103：然后在所述有源层12上覆盖SiOx薄膜13。
具体的，请参阅图2，所述SiOx薄膜13可以通过化学气相沉积法覆盖到所述有源层12上，使得所述有源层12与外界隔离开，防止外界的离子对有源 层12造成污染。进一步的，为了保证后续加工质量，所述SiOx薄膜13的厚度不能过大。优选的，SiOx薄膜13的厚度小于100nm。
步骤S105：接着将所述有源层12中的非晶硅转化为多晶硅。
请参阅图3，具体的，有源层12中非晶硅a-Si转化为多晶硅poly-Si可以通过准分子激光退火(Excimer Laser Annealing，ELA)或者固相结晶(Solid Phase Crystallization，SPC)的方法得到。采用准分子激光退火晶化法时，一般用的准分子激光有XeCl激光、ArF激光、KrF激光和XeF激光等，这类准分子激光器产生紫外波段的激光束，通过紫外波段的短脉冲激光束照射有源层12中的非晶硅，非晶硅会快速吸收激光能量而融化和再结晶。通过激光可以直接照射在SiOx薄膜13表面，由于SiOx薄膜13厚度小，相当于直接照射在有源层12上。因此准分子激光退火效果较好。应说明的是，对有源层12采用准分子激光进行照射还可以在衬底基板111上进行照射，本发明不对其进行限定，可根据实际需要选择。
优选的，本步骤中可采用的激光器例如包括：ArF、KrF和XeCl，相应的激光波长例如分别为193nm、248nm和308nm，脉宽例如在10～50ns之间。可选地，由于XeCl激光器的激光波长较长，激光能量注入非晶硅较深，晶化效果较好，优选采用XeCl激光器。
当然本发明中退火过程还可以采用其他方法，例如金属诱导晶化(Metal-Induced Crystallization，MIC)等退火方式得到。
步骤S107：紧接着对所述有源层进行蚀刻处理，以形成图形。
具体的，在晶化结束得到多晶硅层后，利用有源层掩膜板对有源层12进行曝光、显影、刻蚀以及剥离等工艺，以在有源层12上形成掩膜板的图形(如图4所示)。
步骤S109：再者，请参阅图5，将离子注入所述有源层12。
离子注入程序中的离子可为下述的一种或多种：B离子、P离子、As离子、PHx离子。离子注入为常用的一种掺杂技术，离子注入技术可釆用具有质量分析仪的离子注入、不具有质量分析仪的离子云式注入、等离子注入或者固态扩散式注入等方法。在本实施例，采用离子云式注入方法。优选的，离子的注入方向应当垂直于所述衬底所在的平面。
步骤S111：最后，清洗去除所述SiOx薄膜13。
具体的，请参阅图6，在离子注射结束后，还需要覆盖绝缘层的。因此SiOx薄膜13在离子注射结束后就不需要了，应当去除。此时，可以采用低浓度氢氟酸(DHF)冲洗所述SiOx薄膜13。通常在覆盖绝缘层之前，都需要使用氢氟酸进行冲洗阵列基板。因此，本发明的制造方法未增加另外的工序。进一步优选的，所述氢氟酸浓度应当小于5％。
完成上述步骤之后，便可以在所述有源层13和所述缓冲层12上覆盖绝缘层等操作了。
本发明的阵列基板制造方法，先在有源层上覆盖SiOx薄膜，然后再进行非晶硅到多晶硅的转化、有源层蚀刻、离子注入过程，并在离子注入所述有源层后，除去所述SiOx薄膜，使得有源层在加工过程中始终处于薄膜覆盖状态，达到降低有源层污染的技术效果。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述的实施方式，并不构成对该技术方案保护范围的限定。任何在上述实施方式的精神和原则之内所作的修改、等同替换和改进等，均应包含在该技术方案的保护范围之内。

Claims (11)

  1. 一种阵列基板的制造方法，其中，包括如下步骤：在衬底上沉积包括非晶硅的有源层；在所述有源层上覆盖SiOx薄膜；将所述有源层中的非晶硅转化为多晶硅；对所述有源层进行蚀刻处理，以形成图形；将离子注入所述有源层；清洗去除所述SiOx薄膜。
  2. 如权利要求1所述的阵列基板的制造方法，其中，所述SiOx薄膜通过化学气相沉积法覆盖到所述有源层上。
  3. 如权利要求1所述的阵列基板的制造方法，其中，所述SiOx薄膜的厚度小于100nm。
  4. 如权利要求3所述的阵列基板的制造方法，其中，所述SiOx薄膜通过化学气相沉积法覆盖到所述有源层上。
  5. 如权利要求1所述的阵列基板的制造方法，其中，使用氢氟酸清洗以去除所述SiOx薄膜。
  6. 如权利要求6所述的阵列基板的制造方法，其中，所述氢氟酸浓度小于5％。
  7. 如权利要求1所述的阵列基板的制造方法，其中，离子的注入方向垂直于所述衬底所在的平面。
  8. 如权利要求1所述的阵列基板的制造方法，其中，所述有源层中的非晶硅转化为多晶硅，包括，使用准分子激光退火或者固相结晶的方法将所述有源层中的非晶硅转化为多晶硅。
  9. 如权利要求8所述的阵列基板的制造方法，其中，采用XeCl激光器对有源层进行激光退火。
  10. 如权利要求1所述的阵列基板的制造方法，其中，在衬底上形成包括非晶硅的有源层，包括：提供一衬底基板；在所述衬底基板上形成缓冲层；在所述缓冲层上形成所述有源层。
  11. 如权利要求10所述的阵列基板的制造方法，其中，所述缓冲层通过化学气相沉积法或溅射法形成于所述衬底基板上。
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