WO2017133026A1 - 高可靠低读电压一次性编程存储器 - Google Patents

高可靠低读电压一次性编程存储器 Download PDF

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WO2017133026A1
WO2017133026A1 PCT/CN2016/074007 CN2016074007W WO2017133026A1 WO 2017133026 A1 WO2017133026 A1 WO 2017133026A1 CN 2016074007 W CN2016074007 W CN 2016074007W WO 2017133026 A1 WO2017133026 A1 WO 2017133026A1
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mos transistor
connection
voltage
mos
terminal
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French (fr)
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廖旭阳
毛军华
彭泽忠
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四川凯路威电子有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components

Definitions

  • SB Selected Bit line, selected bit line, column selection
  • the first connection end of the second MOS tube is connected to the fourth connection line BR, and the second connection end is connected to the third connection line BL;
  • a voltage limiting device (3) having a control terminal and two connection terminals, the control terminal of which is connected to a control signal line WB, one of which is connected to the connection point of the anti-fuse device and the first MOS transistor, and A connection terminal is connected to the gate end of the second MOS transistor.
  • the first connection end of the second MOS tube is a drain end, and the second connection end is a source end;
  • the first MOS transistor, the second MOS transistor, and the third MOS transistor are all symmetric MOS transistors.
  • the invention solves the problem of device damage and degradation of the critical path caused by the high voltage impact of the prior art, avoids the potential leakage leakage (the impact of the high voltage on the gate end of the second MOS tube), and improves the reliability of the device.
  • Highly reliable low read voltage one-time programming memory comprising a first MOS transistor 1, a second MOS transistor 2, and an anti-fuse component 4;
  • the first MOS transistor 1 is connected to the second connection line WS, the first connection end is connected to the first connection line WP through the anti-fuse element 4, and the second connection end is connected to the third connection line BL;
  • the voltage limiting device is a third MOS transistor 3.
  • the third MOS tube in unit B is used to protect the second MOS tube of unit B.
  • the anti-fuse device is turned on.
  • the working state of the second MOS tube in the unit B is the voltage at the gate terminal 2V, the source end and The drain terminal is 2.5V, which greatly reduces the voltage stress on the gate oxide of the second MOS transistor compared to the prior art (such as 5.2V as exemplified in the background section). High voltage impact.

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  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

高可靠低读电压一次性编程存储器，涉及集成电路技术，包括第一MOS管（1）、第二MOS管（2）、反熔丝元件（4）；第一MOS管（1）的栅端接第二连接线（WS），其第一连接端通过反熔丝元件（4）连接第一连接线（WP），第二连接端接第三连接线（BL）；第二MOS管（2）的第一连接端接第四连接线（BR），第二连接端接第三连接线（BL）；还包括一个限压器件，其具有一个控制端和两个连接端，其控制端连接一条控制信号线（WB），其一个连接端连接反熔丝元件（4）和第一MOS管（1）的连接点，另一个连接端连接第二MOS管（2）的栅端。该方案解决了现有技术的高压冲击所引起的关键路径的器件损坏、退化而难题，避免了可能导致的漏电隐患(高压对第二MOS管（2）栅端的冲击)，提高了器件的可靠性。

Description

高可靠低读电压一次性编程存储器 技术领域
本发明涉及集成电路技术，特别是不挥发存储(NVM)器件和存储单元电路，可应用于高频和超高频RFID(Radio Frequency Identification，射频识别)的高可靠、低读取电压、低功耗的一次性可编程(One Time Programmable，简称OTP)存储器单元和存储器阵列。
背景技术
中国专利201080067067.7公开了一种低电压低功耗存储器，其存储单元和存储单元构成的存储器阵列如图1、2所示。
图2所示现有技术构成的存储器阵列中，对单元A编程和读取的电压表如表一：
Figure PCTCN2016074007-appb-000001
表一
SW:Selected Word line,所选字线，行选择；
SB:Selected Bit line,所选位线，列选择；
UW:Unselected Word line,未被选择的字线；
UB:Unselected Bit line,未被选择的位线。
设第m行、t列的单元B已经编程，接着编程第m行、第s列的单元A。当单元B已经编程,在编程单元A时，由于WPm处于高压Vpp，结点gmt有一个较高的电压(约Vpp‐Vt，其中Vt是单元B中，导通状态的反融丝器件两端电压差)。此高压对MOS管NMt会产生一定的破坏，有可能导致漏电。如果NMt被破坏，则灵敏放大器读出数据会受到影响。
以上的分析，说明现有技术的明显不足：
如果单元B是已编程单元，反熔丝器件成导通状态。在编程单元A时，单元B的第二MOS管的各点工作状态为，栅端接近5.5V电压(例如5.2V)，源端和漏端为2.5V电压，如此就有接近3V的差值作用在第二MOS管的栅氧上，这对于标准工作电压为1.8V或者更低的MOS管来说，器件的损坏和退化速度将大大提高。特别是第二MOS管是电压放大的关键器件。因此，需要有一种方式来限制第二MOS管栅端电压。
发明内容
本发明所要解决的技术问题是，提供一种解决现有技术的高压冲击问题的存储器。
本发明解决所述技术问题采用的技术方案是，高可靠低读电压一次性编程存储器，包括第一MOS管(1)、第二MOS管(2)、反熔丝元件(4)；
第一MOS管的栅端接第二连接线WS，其第一连接端通过反熔丝元件连接第一连接线WP，第二连接端接第三连接线BL；
第二MOS管的第一连接端接第四连接线BR，第二连接端接第三连接线BL；
还包括一个限压器件(3)，其具有一个控制端和两个连接端，其控制端连接一条控制信号线WB，其一个连接端连接反熔丝器件和第一MOS管的连接点，另一个连接端连接第二MOS管的栅端。
所述限压器件为第三MOS管(3)。
第一MOS管的第一连接端为漏端，第二连接端为源端；
第二MOS管的第一连接端为漏端，第二连接端为源端；
第三MOS管的第一连接端为漏端，第二连接端为源端。
所述第一MOS管、第二MOS管、第三MOS管皆为NMOS管，或者皆为PMOS管。
所述第一MOS管、第二MOS管、第三MOS管皆为对称型MOS管。
本发明解决了现有技术的高压冲击所引起的关键路径的器件损坏、退化而难题，避免了可能导致的漏电隐患(高压对第二MOS管栅端的冲击)，提高了器件的可靠性。
附图说明
图1是现有技术的存储器单元结构示意图。
图2是现有技术的存储器阵列示意图。
图3是本发明的实施例1的存储器单元结构示意图。
图4是本发明的实施例1的存储器阵列示意图
图5是本发明的实施例2的存储器阵列示意图。
具体实施方式
实施例1：参见图3。
高可靠低读电压一次性编程存储器，包括第一MOS管1、第二MOS管2、反熔丝元件4；
第一MOS管1的栅端接第二连接线WS，其第一连接端通过反熔丝元件4连接第一连接线WP，第二连接端接第三连接线BL；
第二MOS管2的第一连接端接第四连接线BR，第二连接端接第三连接线BL；
还包括一个限压器件，其具有一个控制端和两个连接端，其控制端连接一条控制信号线，其一个连接端连接反熔丝器件4和第一MOS管1的连接点，另一个连接端连接第二MOS管2的栅端。
所述限压器件为第三MOS管3。
第一MOS管1的第一连接端为漏端，第二连接端为源端；
第二MOS管2的第一连接端为漏端，第二连接端为源端；
第三MOS管3的第一连接端为漏端，第二连接端为源端。
所述第一MOS管1、第二MOS管2、第三MOS管3皆为NMOS管，或者皆为PMOS管。
本实施方式采用对称型的MOS管，源极和漏极可以互换，本文中的连接端是指源极或者漏极，控制端为栅极。
本发明的第三MOS管处于常开状态，在编程时需要在栅端提供一个合适的电压就能限制第二MOS管栅端电压，
图4所示的存储器阵列结构，由图3所示本发明实施例1的存储器单元构成。图4中，单元A编程和读取的电压表，如表二所列：
Figure PCTCN2016074007-appb-000002
表二
如表二，当单元B是已编程的单元，在编程单元A时，单元B中的第三MOS管用来保护单元B的第二MOS管。进一步的解释是：如果单元B是已编程单元，反熔丝器件成导通状态，在编程单元A时，单元B中第二MOS管的各点工作状态为，栅端2V电压，源端和漏端为2.5V电压，相对于现有技术(如背景技术部分所例举的5.2V)，大大降低了第二MOS管栅氧上的电压应力，使其在编程时不受 高压影响。
实施例2：参见图5。
本实施例与实施例1的区别在于，本实施例系以PMOS管实现。具体的存储器阵列结构如图5，当其中单元A编程和读取时，电压表如表三。
  存储单元 V(WP) V(WS) V(WB) V(BL) V(BR)
编程 A SW/SB -5.5V -2.5V -2.5V 0V 浮置
  B SW/UB -5.5V -2.5V -2.5V -2.5V 浮置
  C UW/SB -2.5V 0V -2.5V 0V 浮置
  D UW/UB -2.5V 0V -2.5V -2.5V 浮置
             
             
读取 A SW/SB 1V 1V,脉冲 0V 0V 检测电压
  B SW/UB 1V 1V,脉冲 0V 浮置 0V,浮置
  C UW/SB 0V 1V,脉冲 0V 0V 检测电压
  D UW/UB 0V 1V,脉冲 0V 浮置 0V,浮置
表三

Claims (5)

  1. 高可靠低读电压一次性编程存储器，包括第一MOS管(1)、第二MOS管(2)、反熔丝元件(4)；
    第一MOS管(1)的栅端接第二连接线(WS)，其第一连接端通过反熔丝元件(4)连接第一连接线(WP)，第二连接端接第三连接线(BL)；
    第二MOS管(2)的第一连接端接第四连接线(BR)，第二连接端接第三连接线(BL)；
    其特征在于，还包括一个限压器件，其具有一个控制端和两个连接端，其控制端连接一条控制信号线，其一个连接端连接反熔丝器件(4)和第一MOS管(1)的连接点，另一个连接端连接第二MOS管(2)的栅端。
  2. 如权利要求1所述的高可靠低读电压一次性编程存储器，其特征在于，所述限压器件为第三MOS管(3)。
  3. 如权利要求2所述的高可靠低读电压一次性编程存储器，其特征在于，
    第一MOS管(1)的第一连接端为漏端，第二连接端为源端；
    第二MOS管(2)的第一连接端为漏端，第二连接端为源端；
    第三MOS管(3)的第一连接端为漏端，第二连接端为源端。
  4. 如权利要求2所述的高可靠低读电压一次性编程存储器，其特征在于，所述第一MOS管(1)、第二MOS管(2)、第三MOS管 (3)皆为NMOS管，或者皆为PMOS管。
  5. 如权利要求2所述的高可靠低读电压一次性编程存储器，其特征在于，所述第一MOS管(1)、第二MOS管(2)、第三MOS管(3)皆为对称型MOS管。
PCT/CN2016/074007 2016-02-05 2016-02-18 高可靠低读电压一次性编程存储器 WO2017133026A1 (zh)

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CN102646450A (zh) * 2011-02-17 2012-08-22 台湾积体电路制造股份有限公司 一次性可编程位单元
CN203325475U (zh) * 2012-04-25 2013-12-04 半导体元件工业有限责任公司 一次性可编程存储器和含一次性可编程存储器的集成电路
CN103219046A (zh) * 2013-04-08 2013-07-24 成都凯路威电子有限公司 Otp存储器
CN106024064A (zh) * 2016-02-05 2016-10-12 四川凯路威电子有限公司 高可靠低读电压一次性编程存储器

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