CN106024064A - 高可靠低读电压一次性编程存储器 - Google Patents
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
- H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
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- G—PHYSICS
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- G11C—STATIC STORES
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- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
- G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
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- G—PHYSICS
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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- G—PHYSICS
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- G11C8/00—Arrangements for selecting an address in a digital store
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
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Abstract
高可靠低读电压一次性编程存储器,涉及集成电路技术,本发明包括第一MOS管、第二MOS管、反熔丝元件;第一MOS管的栅端接第二连接线WS,其第一连接端通过反熔丝元件连接第一连接线WP,第二连接端接第三连接线BL;第二MOS管的第一连接端接第四连接线BR,第二连接端接第三连接线BL;还包括一个限压器件,其具有一个控制端和两个连接端,其控制端连接一条控制信号线WB,其一个连接端连接反熔丝器件和第一MOS管的连接点,另一个连接端连接第二MOS管的栅端。本发明解决了现有技术的高压冲击所引起的关键路径的器件损坏、退化而难题,避免了可能导致的漏电隐患(高压对第二MOS管栅端的冲击),提高了器件的可靠性。
Description
技术领域
本发明涉及集成电路技术,特别是不挥发存储(NVM)器件和存储单元电路,可应用于高频和超高频RFID(Radio Frequency Identification,射频识别)的高可靠、低读取电压、低功耗的一次性可编程(One Time Programmable,简称OTP)存储器单元和存储器阵列。
背景技术
中国专利201080067067.7公开了一种低电压低功耗存储器,其存储单元和存储单元构成的存储器阵列如图1、2所示。
图2所示现有技术构成的存储器阵列中,对单元A编程和读取的电压表如表一:
表一
SW:Selected Word line,所选字线,行选择;
SB:Selected Bit line,所选位线,列选择;
UW:Unselected Word line,未被选择的字线;
UB:Unselected Bit line,未被选择的位线。
设第m行、t列的单元B已经编程,接着编程第m行、第s列的单元A。当单元B已经编程,在编程单元A时,由于WPm处于高压Vpp,结点gmt有一个较高的电压(约Vpp‐Vt,其中Vt是单元B中,导通状态的反融丝器件两端电压差)。此高压对MOS管NMt会产生一定的破坏,有可能导致漏电。如果NMt被破坏,则灵敏放大器读出数据会受到影响。
以上的分析,说明现有技术的明显不足:
如果单元B是已编程单元,反熔丝器件成导通状态。在编程单元A时,单元B的第二MOS管的各点工作状态为,栅端接近5.5V电压(例如5.2V),源端和漏端为2.5V电压,如此就有接近3V的差值作用在第二MOS管的栅氧上,这对于标准工作电压为1.8V或者更低的MOS管来说,器件的损坏和退化速度将大大提高。特别是第二MOS管是电压放大的关键器件。因此,需要有一种方式来限制第二MOS管栅端电压。
发明内容
本发明所要解决的技术问题是,提供一种解决现有技术的高压冲击问题的存储器。
本发明解决所述技术问题采用的技术方案是,高可靠低读电压一次性编程存储器,包括第一MOS管(1)、第二MOS管(2)、反熔丝元件(4);
第一MOS管的栅端接第二连接线WS,其第一连接端通过反熔丝元件连接第一连接线WP,第二连接端接第三连接线BL;
第二MOS管的第一连接端接第四连接线BR,第二连接端接第三连接线BL;
还包括一个限压器件(3),其具有一个控制端和两个连接端,其控制端连接一条控制信号线WB,其一个连接端连接反熔丝器件和第一MOS管的连接点,另一个连接端连接第二MOS管的栅端。
所述限压器件为第三MOS管(3)。
第一MOS管的第一连接端为漏端,第二连接端为源端;
第二MOS管的第一连接端为漏端,第二连接端为源端;
第三MOS管的第一连接端为漏端,第二连接端为源端。
所述第一MOS管、第二MOS管、第三MOS管皆为NMOS管,或者皆为PMOS管。
所述第一MOS管、第二MOS管、第三MOS管皆为对称型MOS管。
本发明解决了现有技术的高压冲击所引起的关键路径的器件损坏、退化而难题,避免了可能导致的漏电隐患(高压对第二MOS管栅端的冲击),提高了器件的可靠性。
附图说明
图1是现有技术的存储器单元结构示意图。
图2是现有技术的存储器阵列示意图。
图3是本发明的实施例1的存储器单元结构示意图。
图4是本发明的实施例1的存储器阵列示意图
图5是本发明的实施例2的存储器阵列示意图。
具体实施方式
实施例1:参见图3。
高可靠低读电压一次性编程存储器,包括第一MOS管1、第二MOS管2、反熔丝元件4;
第一MOS管1的栅端接第二连接线WS,其第一连接端通过反熔丝元件4连接第一连接线WP,第二连接端接第三连接线BL;
第二MOS管2的第一连接端接第四连接线BR,第二连接端接第三连接线BL;
还包括一个限压器件,其具有一个控制端和两个连接端,其控制端连接一条控制信号线,其一个连接端连接反熔丝器件4和第一MOS管1的连接点,另一个连接端连接第二MOS管2的栅端。
所述限压器件为第三MOS管3。
第一MOS管1的第一连接端为漏端,第二连接端为源端;
第二MOS管2的第一连接端为漏端,第二连接端为源端;
第三MOS管3的第一连接端为漏端,第二连接端为源端。
所述第一MOS管1、第二MOS管2、第三MOS管3皆为NMOS管,或者皆为PMOS管。
本实施方式采用对称型的MOS管,源极和漏极可以互换,本文中的连接端是指源极或者漏极,控制端为栅极。
本发明的第三MOS管处于常开状态,在编程时需要在栅端提供一个合适的电压就能限制第二MOS管栅端电压,
图4所示的存储器阵列结构,由图3所示本发明实施例1的存储器单元构成。
图4中,单元A编程和读取的电压表,如表二所列:
表二
如表二,当单元B是已编程的单元,在编程单元A时,单元B中的第三MOS管用来保护单元B的第二MOS管。进一步的解释是:如果单元B是已编程单元,反熔丝器件成导通状态,在编程单元A时,单元B中第二MOS管的各点工作状态为,栅端2V电压,源端和漏端为2.5V电压,相对于现有技术(如背景技术部分所例举的5.2V),大大降低了第二MOS管栅氧上的电压应力,使其在编程时不受 高压影响。
实施例2:参见图5。
本实施例与实施例1的区别在于,本实施例系以PMOS管实现。具体的存储器阵列结构如图5,当其中单元A编程和读取时,电压表如表三。
存储单元 | V(WP) | V(WS) | V(WB) | V(BL) | V(BR) | |
编程 | A SW/SB | -5.5V | -2.5V | -2.5V | 0V | 浮置 |
B SW/UB | -5.5V | -2.5V | -2.5V | -2.5V | 浮置 | |
C UW/SB | -2.5V | 0V | -2.5V | 0V | 浮置 | |
D UW/UB | -2.5V | 0V | -2.5V | -2.5V | 浮置 | |
读取 | A SW/SB | 1V | 1V,脉冲 | 0V | 0V | 检测电压 |
B SW/UB | 1V | 1V,脉冲 | 0V | 浮置 | 0V,浮置 | |
C UW/SB | 0V | 1V,脉冲 | 0V | 0V | 检测电压 | |
D UW/UB | 0V | 1V,脉冲 | 0V | 浮置 | 0V,浮置 |
表三。
Claims (5)
1.高可靠低读电压一次性编程存储器,包括第一MOS管(1)、第二MOS管(2)、反熔丝元件(4);
第一MOS管(1)的栅端接第二连接线(WS),其第一连接端通过反熔丝元件(4)连接第一连接线(WP),第二连接端接第三连接线(BL);
第二MOS管(2)的第一连接端接第四连接线(BR),第二连接端接第三连接线(BL);
其特征在于,还包括一个限压器件,其具有一个控制端和两个连接端,其控制端连接一条控制信号线,其一个连接端连接反熔丝器件(4)和第一MOS管(1)的连接点,另一个连接端连接第二MOS管(2)的栅端。
2.如权利要求1所述的高可靠低读电压一次性编程存储器,其特征在于,所述限压器件为第三MOS管(3)。
3.如权利要求2所述的高可靠低读电压一次性编程存储器,其特征在于,
第一MOS管(1)的第一连接端为漏端,第二连接端为源端;
第二MOS管(2)的第一连接端为漏端,第二连接端为源端;
第三MOS管(3)的第一连接端为漏端,第二连接端为源端。
4.如权利要求2所述的高可靠低读电压一次性编程存储器,其特征在于,所述第一MOS管(1)、第二MOS管(2)、第三MOS管(3)皆为NMOS管,或者皆为PMOS管。
5.如权利要求2所述的高可靠低读电压一次性编程存储器,其特征在于,所述第一MOS管(1)、第二MOS管(2)、第三MOS管(3)皆为对称型MOS管。
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WO2017133026A1 (zh) * | 2016-02-05 | 2017-08-10 | 四川凯路威电子有限公司 | 高可靠低读电压一次性编程存储器 |
CN111696613A (zh) * | 2019-03-13 | 2020-09-22 | 中芯国际集成电路制造(上海)有限公司 | 一种电可编程熔丝单元、阵列、存储单元和电子装置 |
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TWI817725B (zh) * | 2022-06-23 | 2023-10-01 | 大陸商成都銳成芯微科技股份有限公司 | 一次性編程記憶單元及其記憶體 |
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CN111696613A (zh) * | 2019-03-13 | 2020-09-22 | 中芯国际集成电路制造(上海)有限公司 | 一种电可编程熔丝单元、阵列、存储单元和电子装置 |
CN113963738A (zh) * | 2020-07-20 | 2022-01-21 | 华邦电子股份有限公司 | 反熔丝装置及反熔丝单元的编程方法 |
TWI817725B (zh) * | 2022-06-23 | 2023-10-01 | 大陸商成都銳成芯微科技股份有限公司 | 一次性編程記憶單元及其記憶體 |
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