WO2017133002A1 - 场效应晶体管及场效应晶体管的制备方法 - Google Patents

场效应晶体管及场效应晶体管的制备方法 Download PDF

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Publication number
WO2017133002A1
WO2017133002A1 PCT/CN2016/073680 CN2016073680W WO2017133002A1 WO 2017133002 A1 WO2017133002 A1 WO 2017133002A1 CN 2016073680 W CN2016073680 W CN 2016073680W WO 2017133002 A1 WO2017133002 A1 WO 2017133002A1
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Prior art keywords
end surface
layer
gate
substrate
effect transistor
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PCT/CN2016/073680
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English (en)
French (fr)
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WO2017133002A9 (zh
Inventor
徐慧龙
秦旭东
张臣雄
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华为技术有限公司
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Priority to CN201680077935.7A priority Critical patent/CN108475680A/zh
Priority to PCT/CN2016/073680 priority patent/WO2017133002A1/zh
Publication of WO2017133002A1 publication Critical patent/WO2017133002A1/zh
Publication of WO2017133002A9 publication Critical patent/WO2017133002A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a method for fabricating a field effect transistor and a field effect transistor.
  • FET Field Effect Transistor
  • S source
  • D drain
  • CH channel layer
  • G gate
  • Graphene is a two-dimensional material composed of carbon atoms and has attracted extensive attention due to its unique physical and chemical properties such as high mobility.
  • G-FET Graphene Field Effect Transistor
  • the graphene layer is disposed adjacent to a substrate, the seed layer is disposed on a surface of the graphene layer facing away from the substrate, the gate dielectric layer is disposed on the seed layer, and the seed layer is disposed on the graphene layer to promote the gate dielectric The layer grows better.
  • the seed layer is an organic material
  • the dielectric constant of the organic substance is small
  • the seed layer affects the size of the gate capacitance, thereby affecting the regulation effect of the gate electric field on the channel layer.
  • the seed layer is an inorganic substance (for example, an alumina nanoparticle)
  • the dielectric constant of the inorganic substance is larger than the dielectric constant of the organic substance, but when the gate dielectric layer is subsequently formed on the seed layer, the seed layer and the gate are formed.
  • There are many interface defects in the interface formed between the dielectric layers which in turn affects the performance of the G-FET.
  • the performance of the G-FET in the prior art is not good.
  • the invention provides a field effect transistor, the field effect transistor comprising:
  • the substrate including a first surface
  • the gate is embedded in the substrate from the first surface, and an end surface of the gate is flush with the first surface;
  • a gate dielectric layer covering the first surface and an end surface of the gate that is flush with the first surface
  • a drain is disposed on a surface of the graphene layer facing away from the gate dielectric layer, and a gap is provided between the drain and the source.
  • the gate includes a first end surface, a second end surface, and a third end surface, and an end surface flush with the first surface is defined as the first end surface, and the second end surface
  • the third end surface is oppositely disposed, the second end surface and the third end surface respectively intersect the first end surface, and the second end surface is coplanar with the end surface of the source facing the drain.
  • the third end surface is coplanar with the end surface of the drain facing the source.
  • the material of the substrate includes any one or more of electrical insulating materials such as quartz, mica, alumina or transparent plastic.
  • the material of the gate electrode includes any one or more of materials such as Pt, Au, Al, Cu, Ti, Ag, Sc, Y, Cr, Ni, and the like.
  • the gate dielectric layer includes any one or more of materials such as HfO 2 , ZrO 2 , Al 2 O 3 , SiO 2 , and Si 3 N 4 .
  • the graphene layer includes any one of a single layer of graphene, a double layer graphene, or a multilayer graphene.
  • the source and the drain include any one or more of metal materials such as Pt, Au, Al, Ni, Cu, Ag, Ti, Sc, Y, or the source and the The drain can also be multilayer graphite or indium tin oxide.
  • the substrate is an insulating substrate having a transmittance to ultraviolet light exceeding a predetermined transmittance.
  • the graphene layer comprises any one of a single layer of graphene, a double layer of graphene, or a plurality of layers of graphene.
  • the thickness of the gate is greater than 10 nm.
  • a gate dielectric layer is directly formed on the first surface, and a high quality gate dielectric layer can be obtained.
  • the graphene layer is disposed on the surface of the gate dielectric layer facing away from the substrate, thereby eliminating the technical problem that it is difficult to form the gate dielectric layer when the gate dielectric layer is disposed on the surface of the graphene layer in the prior art.
  • the graphene layer provided on the gate dielectric layer of the present invention has one seed layer less than the prior art, and therefore, the field effect transistor of the present invention is thinner.
  • the graphene layer is directly disposed on the gate dielectric layer, and there is no seed layer between the graphene layer and the gate dielectric layer.
  • the seed layer introduced by the seed layer affects the size of the gate capacitance and the seed layer. The technical problem of forming interface defects with the gate dielectric layer is solved, thereby improving the performance of the field effect transistor of the present invention.
  • the gate electrode in the field effect transistor of the present invention is embedded in the substrate from the middle portion of the first surface, high frequency loss due to the substrate can be suppressed.
  • the third end surface of the gate is coplanar with the end surface of the drain facing the source Therefore, there is no insulating medium spacer between the gate and the source, and there is no insulating medium spacer between the gate and the drain, thereby suppressing the channel in the field effect transistor Part of the possible parasitic resistance effect.
  • the third end surface of the gate and the end surface of the drain facing the source are a surface, the gate and the source do not overlap, and there is no overlap between the gate and the drain, so that a parasitic capacitance between the gate and the source is small, The parasitic capacitance between the gate and the drain is small.
  • the gate, the source and the drain in the field effect transistor of the present invention can be made thicker without significantly increasing the parasitic capacitance.
  • the thicker gate, source and thicker drain can reduce the resistance of these electrodes themselves and also suppress the parasitic resistance generated by these electrodes.
  • the present invention provides a method of fabricating a field effect transistor, the method of fabricating the field effect transistor comprising:
  • Step S110 providing a substrate, the substrate includes a first surface and a second surface disposed opposite to each other;
  • Step S120 forming a gate, the gate is embedded in the substrate from the first surface, and an end surface of the gate is flush with the first surface;
  • Step S130 forming a gate dielectric layer covering the first surface and an end surface of the gate flush with the first surface;
  • Step S140 forming a graphene layer, the graphene layer being disposed on a surface of the gate dielectric layer facing away from the substrate;
  • Step S150 forming a source and a drain, the source and the drain being disposed on a surface of the graphene layer facing away from the gate dielectric layer, and a gap between the source and the drain .
  • the step S120 includes:
  • Step S121 coating a first photoresist layer on the first surface
  • Step S122 patterning the first photoresist layer to remove a portion of the first photoresist layer covering the first surface
  • Step S123 performing plasma etching on the first surface with the remaining first photoresist layer as a mask to form a groove on the first surface;
  • Step S124 forming a first metal layer covering the first photoresist layer and filling the recess, wherein a thickness of the first metal layer is greater than or equal to a depth of the recess ;
  • Step S125 peeling off the remaining first photoresist layer, and removing a portion of the first metal layer higher than the recess, so that an end surface of the first metal layer located in the recess and the first A first metal layer located in the recess and having an end face flush with the first surface is the gate.
  • the step S140 includes:
  • Step S141 providing a substrate
  • Step S142 forming a graphene layer on a surface of the substrate
  • Step S143 transferring the substrate on which the graphene layer is formed to a surface of the gate dielectric layer facing away from the first surface, transferring the graphene layer onto a surface of the gate dielectric layer, and removing The substrate.
  • the gate includes a first end surface, a second end surface, and a third end surface, and an end surface flush with the first surface is defined as a first end surface, and the second end surface and the first end surface
  • the three end faces are oppositely disposed, the second end face and the third end face respectively intersect the first end face, and the second end face is coplanar with the end face of the source facing the drain, the The three end faces are coplanar with the end face of the drain facing the source.
  • the substrate in conjunction with the third embodiment, in a fourth embodiment, includes a third surface and a fourth surface, the third surface is disposed opposite the fourth surface, the third surface and the The fourth surface is respectively intersected with the first surface, and the third surface is disposed adjacent to the second surface of the fourth surface, and the step S150 includes:
  • Step S151 applying a second photoresist layer on a surface of the graphene layer facing away from the gate dielectric layer;
  • Step S152 patterning the second photoresist layer to retain the first portion, the second portion, and the third portion, the first portion being disposed between the second portion and the third portion, and Forming a first gap between the first portion and the second portion, and forming a shape between the first portion and the third portion a second gap, the first gap and the second gap are used to expose a portion of the graphene layer, and an end surface of the first portion facing the second portion is coplanar with the second end surface, An end surface facing a portion of the third portion is coplanar with the third end surface, an end surface of the second portion facing away from the first portion is coplanar with the third surface, and the third portion faces away from the first portion An end face is coplanar with the fourth surface;
  • Step S153 forming a second metal layer covering the first portion, the second portion, and the third portion, and covering the exposed portion through the first gap and the second gap Graphene layer;
  • Step S154 peeling off the first portion, the second portion, and the third portion, and the second metal layer disposed on the graphene layer through the first gap is the source, A second metal layer disposed on the graphene layer is a drain.
  • the method of fabricating the field effect transistor of the present invention forms the gate dielectric layer directly on the first surface, and thus, a high quality gate dielectric layer can be obtained.
  • the graphene layer is disposed on the surface of the gate dielectric layer facing away from the substrate, thereby bypassing the technical problem that it is difficult to form a high quality gate dielectric layer when the gate dielectric layer is disposed on the surface of the graphene layer in the prior art.
  • the graphene layer provided on the gate dielectric layer of the present invention has one seed layer less than the prior art, and therefore, the field effect transistor of the present invention is thinner.
  • the graphene layer in the field effect transistor of the present invention is directly disposed on the gate dielectric layer, there is no seed layer between the graphene layer and the gate dielectric layer, and the seed layer is affected by the introduction of the seed layer in the prior art.
  • the size of the capacitor and the technical problem of forming interface defects between the seed layer and the gate dielectric layer are solved, thereby improving the performance of the prepared field effect transistor.
  • the third end surface of the gate is coplanar with the end surface of the drain facing the source, an insulating medium spacer is not present between the gate and the source, and an insulating dielectric spacer is not present between the gate and the drain, thereby suppressing a possible channel portion of the field effect transistor The parasitic resistance effect that exists.
  • the third end surface of the gate and the end surface of the drain facing the source are a surface, the gate and the source do not overlap, and there is no overlap between the gate and the drain, so that a parasitic capacitance between the gate and the source is small, The parasitic capacitance between the gate and the drain is small.
  • the method of fabricating the field effect transistor of the present invention may use the gate, the source The drain and the drain can be made thicker without significantly increasing the parasitic capacitance.
  • the thicker gate, source and thicker drain can reduce the resistance of these electrodes themselves and also suppress the parasitic resistance generated by these electrodes.
  • the method for fabricating the field effect transistor of the present invention transfers the graphene layer onto a gate dielectric layer after being prepared on a substrate, and it is difficult to form a gate dielectric layer on the surface of the graphene layer. The problem, which improves the performance of the prepared field effect transistor.
  • FIG. 1 is a cross-sectional structural view of a field effect transistor according to a preferred embodiment of the present invention
  • FIG. 2 is a flow chart of a method of fabricating a field effect transistor according to a preferred embodiment of the present invention
  • 3 to 17 are schematic views showing respective preparation steps in a method of fabricating a field effect transistor according to a preferred embodiment of the present invention.
  • FIG. 1 is a cross-sectional structural view of a field effect transistor according to a preferred embodiment of the present invention.
  • the field effect transistor 10 includes:
  • the substrate 110 includes a first surface 110a; the substrate 110 further includes a second surface 110b disposed opposite the first surface 110a;
  • the gate 120 is embedded in the substrate 110 from the first surface 110a, and an end surface of the gate 120 is flush with the first surface 110a;
  • a gate dielectric layer 130 covering the first surface 110a and the gate 120 and the first surface 110a flush end face;
  • a graphene layer 140 disposed on a surface of the gate dielectric layer 130 facing away from the substrate 110;
  • a source 150 disposed on a surface of the graphene layer 140 facing away from the gate dielectric layer 130;
  • the drain electrode 160 is disposed on a surface of the graphene layer 140 facing away from the gate dielectric layer 130 and is provided with a gap between the source 150 and the source 150.
  • the gate dielectric layer 130 of the field effect transistor 10 of the present invention is directly formed on the first surface 110a, and a high quality gate dielectric layer 130 can be obtained.
  • the graphene layer 140 is disposed on the surface of the gate dielectric layer 130 facing away from the substrate 110. Therefore, the technical problem that it is difficult to form the gate dielectric layer when the gate dielectric layer is disposed on the surface of the graphene layer in the prior art is eliminated.
  • the graphene layer 140 is provided on the gate dielectric layer 130 of the present invention, which is one less layer than the prior art. Therefore, the field effect transistor 10 of the present invention is thinner.
  • the graphene layer 140 of the field effect transistor 10 of the present invention is directly disposed on the gate dielectric layer 130, there is no seed layer between the graphene layer 140 and the gate dielectric layer 130, and the seed layer is introduced in the prior art.
  • the problem that the seed layer affects the size of the gate capacitance and the formation of interface defects of the seed layer and the gate dielectric layer is solved, thereby improving the performance of the field effect transistor 10 of the present invention.
  • the gate electrode 120 in the field effect transistor 10 of the present invention is embedded in the substrate 110 from the first surface 110a, high frequency loss due to the substrate 110 can be suppressed.
  • the gate electrode 120 includes a first end surface 121, a second end surface 122, and a third end surface 123.
  • An end surface flush with the first surface 110a is defined as the first end surface 121
  • the second end surface 122 is The third end surface 123 and the third end surface 123 respectively intersect the first end surface 121
  • the second end surface 122 and the source 150 face the drain 160 .
  • the end faces are coplanar
  • the third end face 123 is coplanar with the end face of the drain 160 facing the source 150.
  • the substrate 110 further includes a third surface 110c and a fourth surface 110d.
  • the third surface 110c and the fourth surface 110d are oppositely disposed, and the third surface 110c and the fourth surface 110d are respectively Intersecting with the first surface 110a, and the third surface 110c is disposed adjacent to the second end surface 122 of the fourth surface 110d.
  • the third end surface 123 of the gate 120 and the drain 160 face the source
  • the end faces of the poles 150 are coplanar. Therefore, there is no insulating medium spacer between the gate 120 and the source 150, and there is no insulating medium spacer between the gate 120 and the drain 160, thereby The parasitic resistance effect that may exist in the channel portion of the field effect transistor 10 is suppressed.
  • the third end surface 123 of the gate 120 faces the drain 160
  • the end faces of the source 150 are coplanar, the gate 120 and the source 150 do not overlap, and there is no overlap between the gate 120 and the drain 160. Therefore, the gate 120 and The parasitic capacitance C GS between the source 150 is small, and the parasitic capacitance C SD between the gate 120 and the drain 160 is small.
  • the gate 120, the source 150 and the drain 160 in the field effect transistor 10 of the present invention can be made thicker without significantly increasing the parasitic capacitances C GS and C SD .
  • the thicker gate 120, the source 150 and the thicker drain 160 can reduce the resistance of the electrodes themselves and also suppress the parasitic resistance generated by these electrodes.
  • the substrate 110 is an insulating substrate having a transmittance to ultraviolet light exceeding a predetermined transmittance.
  • the material of the substrate 110 includes any one or more of an electrically insulating material such as quartz, mica, alumina or transparent plastic.
  • the substrate 110 is an insulating layer substrate capable of reducing high frequency loss of the substrate 110.
  • the material of the gate electrode 120 includes any one or more of materials such as Pt, Au, Al, Cu, Ti, Ag, Sc, Y, Cr, Ni, and the like.
  • the thickness of the gate 120 is greater than 10 nm.
  • the gate dielectric layer 130 includes any one or more of materials such as HfO 2 , ZrO 2 , Al 2 O 3 , SiO 2 , and Si 3 N 4 .
  • the graphene layer 140 includes any one of a single layer of graphene, a double layer graphene, or a multilayer of graphene.
  • the source 150 and the drain 160 are preferably formed simultaneously in the same process, and the source 150 and the drain 160 include Pt, Au, Al, Ni, Cu, Ag, Ti, Sc, Y, and the like. Any one or more of metal materials.
  • the source 150 and the drain 160 may also be multi-layer graphite or Indium Tin Oxide (ITO).
  • FIG. 2 is a flow chart of a method for fabricating a field effect transistor according to a preferred embodiment of the present invention.
  • the method of fabricating the field effect transistor 10 includes the following steps.
  • Step S110 providing a substrate 110, the substrate 110 including the first surface 110a disposed opposite to each other And a second surface 110b.
  • the substrate 110 is an insulating substrate whose transmittance to ultraviolet light exceeds a preset transmittance.
  • the material of the substrate 110 includes any one or more of an electrically insulating material such as quartz, mica, alumina or transparent plastic.
  • the substrate 110 is an insulating layer substrate capable of reducing high frequency loss of the substrate 110.
  • a gate electrode 120 is formed.
  • the gate electrode 120 is embedded in the substrate 110 from the first surface 110a, and an end surface of the gate electrode 120 is flush with the first surface 110a.
  • the material of the gate electrode 120 includes any one or more of materials such as Pt, Au, Al, Cu, Ti, Ag, Sc, Y, Cr, Ni, and the like.
  • the thickness of the gate 120 is greater than 10 nm.
  • the gate electrode 120 includes a first end surface 121, a second end surface 122, and a third end surface 123.
  • An end surface flush with the first surface 110a is defined as the first end surface 121
  • the second end surface 122 is The third end surface 123 and the third end surface 123 respectively intersect the first end surface 121
  • the second end surface 122 and the source 150 face the drain 160 .
  • the end faces are coplanar
  • the third end face 123 is coplanar with the end face of the drain 160 facing the source 150.
  • the step S120 includes the following steps.
  • Step S121 applying a first photoresist layer 181 on the first surface 110a, please refer to FIG. 4 together.
  • Step S122 patterning the first photoresist layer 181 to remove a portion of the first photoresist layer 181 covering the first surface 110a. Please refer to FIG. 5 together.
  • Step S123 plasma etching the first surface 110a with the remaining first photoresist layer 181 as a mask to form a recess 111 on the first surface 110a.
  • the reactive gas for plasma etching the first surface 110a may be a fluorine-based gas such as carbon tetrafluoride or sulfur hexafluoride.
  • Step S124 forming a first metal layer 182 covering the first photoresist layer 181 and filling the recess 111, wherein the thickness of the first metal layer 182 is greater than or equal to The depth of the groove 111 is described.
  • the first metal layer 182 may be formed by thermal evaporation, electron beam evaporation or sputtering.
  • Step S125 peeling off the remaining first photoresist layer 181, and partially removing the first metal layer 182 higher than the groove 111, so that the first metal layer located in the groove 111 An end surface of the 182 is flush with the first surface 110a, is located in the groove 111 and is opposite to the first surface and the first table
  • the first metal layer 182 whose face 110a is flush is the gate electrode 120.
  • the remaining first photoresist layer 181 may be stripped with an organic solvent such as acetone to remove the first metal layer 182 higher than the recess 111. Chemical mechanical polishing can be used. It can be seen that the method of fabricating the field effect transistor of the present invention is compatible with existing CMOS processes. Further, the gate electrode 120 of the present invention is embedded in the substrate 110 from the middle of the first surface 110a, and high frequency loss due to the substrate 10 can be suppressed.
  • a gate dielectric layer 130 is formed.
  • the gate dielectric layer 130 covers the first surface 110a and an end surface of the gate 130 that is flush with the first surface 110a.
  • the gate dielectric layer 130 includes any one or more of materials such as HfO 2 , ZrO 2 , Al 2 O 3 , SiO 2 , and Si 3 N 4 .
  • the gate dielectric layer 130 may be formed by a method such as chemical vapor deposition, atomic layer deposition, or physical vapor deposition.
  • a graphene layer 140 is formed, and the graphene layer 140 is disposed on a surface of the gate dielectric layer 130 facing away from the substrate 110.
  • the graphene layer 140 includes any one of a single layer of graphene, a double layer graphene, or a multilayer of graphene.
  • the step S140 includes the following steps.
  • a substrate 183 is provided.
  • the material of the substrate 183 may be polymethyl methacrylate (PMMA).
  • Step S142 forming a graphene layer 140 on one surface of the substrate 183, please refer to FIG. 11 together.
  • Step S143 transferring the substrate on which the graphene 184 is formed to a surface of the gate dielectric layer 130 facing away from the first surface 110a, and transferring the graphene layer 140 to the surface of the gate dielectric layer 130 To remove the substrate 183, please refer to FIG. 12 together.
  • Step S150 forming a source 150 and a drain 160, the source 150 and the drain 160 being disposed on a surface of the graphene layer 140 facing away from the gate dielectric layer 130, and the source 150 and the A gap is provided between the drain electrodes 160.
  • the substrate 110 includes a third surface 110c and a fourth surface 110d.
  • the third surface 110c is disposed opposite to the fourth surface 110d, and the third surface 110c and the fourth surface 110d are respectively associated with the first surface A surface 110a intersects, and the third surface 110c is disposed adjacent to the second end surface 122 than the fourth surface 110d.
  • the step S150 includes the following steps.
  • Step S151 applying a second photoresist layer 184 on the surface of the graphene layer 140 facing away from the gate dielectric layer 130. Please refer to FIG. 13 together.
  • Step S152 patterning the second photoresist layer 184 to retain the first portion 184a, the second portion 184b, and the third portion 184c, the first portion 184a being disposed on the second portion 184b and the third portion
  • a first gap 184d is formed between the first portion 184a and the second portion 184b
  • a second gap 184e is formed between the first portion 184a and the third portion 184c
  • the first gap 184d and the second gap 184e are used to expose a portion of the graphene layer 140
  • an end surface of the first portion 184a facing the second portion 184b is coplanar with the second end surface 122
  • the first portion 184a faces
  • An end surface of the third portion 184c is coplanar with the third end surface 123
  • an end surface of the second portion 184b facing away from the first portion 184a is coplanar with the third surface 110c
  • the substrate 110 is an insulating substrate having a transmittance for ultraviolet light exceeding a preset light transmittance
  • the second photoresist layer 184 is an ultraviolet light-sensitive photoresist layer. That is, a portion of the second photoresist layer 184 that is irradiated with ultraviolet light disappears, and a portion of the second photoresist layer 184 that is not irradiated with ultraviolet light remains.
  • the step S152 includes the following steps.
  • a light source 186 and a mask 187 are provided.
  • the light source 186 and the mask 187 are disposed adjacent to the second surface 110b, and the mask 186 is disposed on the light source 186 and the second Between the surfaces 110b, the light source 186 is used to emit ultraviolet light
  • the mask plate 187 includes a first light transmitting portion 187a, a second light transmitting portion 187b, and a third light transmitting portion 187c
  • the first light transmitting portion 187a is disposed corresponding to the gate 120 and the length of the first transparent portion 187a is greater than the length of the gate 120
  • the second transparent portion 187b and the third transparent portion 187c are respectively disposed on the first An opposite end of the light transmitting portion 187a
  • the second light transmitting portion 187b is disposed adjacent to the third surface 110c than the third light transmitting portion 187c, and the second light transmitting portion 187b faces away from the An end surface of the first portion 184a is coplanar with the third surface
  • Said ultraviolet transmittance is less than or equal to the second transmittance, the first light transmittance is greater than the second light transmittance.
  • the first light transmittance is 95% or even higher, and the second light transmittance is 5% or less.
  • the ultraviolet light emitted by the light source 186 can penetrate the first light transmitting portion 187a, and The ultraviolet light emitted by the light source 186 is hardly able to penetrate the second light transmitting portion 187b and the third light transmitting portion 187c. Please refer to FIG. 14 together.
  • Step S152b using the mask 187 as a mask to expose the second photoresist layer 184 by using the ultraviolet light emitted by the light source 186 to form the first portion 184a and the second portion. 184b and the third portion 184c.
  • the second photoresist layer 184 Portions corresponding to the second light transmitting portion 187b and the third light transmitting portion 187c are retained to form the second portion 184b and the third portion 184c, respectively.
  • the gate 120 is not transparent to ultraviolet light, and therefore, the second photoresist layer 184 corresponding to the gate 120 is left to form the first portion 184a.
  • Step S153 forming a second metal layer 185 covering the first portion 184a, the second portion 184b, and the third portion 184c, and passing through the first gap 184d and the first
  • the second gap 184e covers the exposed graphene layer 140, please refer to FIG. 16 together.
  • Step S154 peeling off the first portion 184a, the second portion 184b, and the third portion 184c, and the second metal layer 185 disposed on the graphene layer 140 through the first gap 184d is the source
  • the pole 150, the second metal layer 185 disposed on the graphene layer 140 through the second gap 184e is the drain 160, please refer to FIG. 17 together.
  • the method of fabricating the field effect transistor of the present invention forms the gate dielectric layer 130 directly on the first surface 110, and thus, a high quality gate dielectric layer 130 can be obtained.
  • the graphene layer 140 is disposed on the surface of the gate dielectric layer 130 facing away from the substrate 110, thereby bypassing the prior art that it is difficult to form a high quality gate dielectric layer when the gate dielectric layer is disposed on the surface of the graphene layer. technical problem.
  • the graphene layer 140 is provided on the gate dielectric layer 130 of the present invention, which is one less layer than the prior art. Therefore, the field effect transistor 10 of the present invention is thinner.
  • the graphene layer 140 in the field effect transistor 10 of the present invention is directly disposed further, since the graphene layer 140 in the field effect transistor 10 of the present invention is directly disposed on the gate dielectric layer 130, the graphene layer 140 and the gate are provided. There is no seed layer between the dielectric layers 130.
  • the seed layer caused by the introduction of the seed layer in the prior art affects the size of the gate capacitance and the technical problem of forming interface defects of the seed layer and the gate dielectric layer, thereby improving the prepared field.
  • the third end surface 123 of the gate 120 and the drain 160 face the source
  • the end faces of the poles 150 are coplanar. Therefore, there is no insulating medium spacer between the gate 120 and the source 150, and there is no insulating medium spacer between the gate 120 and the drain 160, thereby The parasitic resistance effect that may exist in the channel portion of the field effect transistor 10 is suppressed.
  • the third end surface 123 of the gate 120 faces the drain 160
  • the end faces of the source 150 are coplanar, the gate 120 and the source 150 do not overlap, and there is no overlap between the gate 120 and the drain 160. Therefore, the gate 120 and The parasitic capacitance C GS between the source 150 is small, and the parasitic capacitance C SD between the gate 120 and the drain 160 is small.
  • the method of fabricating the field effect transistor of the present invention can make the gate 120, the source 150, and the drain 160 thicker without significantly increasing the parasitic capacitances C GS and C SD . .
  • the thicker gate 120, the source 150 and the thicker drain 160 can reduce the resistance of the electrodes themselves and also suppress the parasitic resistance generated by these electrodes.
  • the method for fabricating the field effect transistor of the present invention transfers the graphene layer 140 onto a gate dielectric layer 130 after being prepared on a substrate, which is difficult to form on the surface of the graphene layer 140.
  • the problem of the gate dielectric layer 130 improves the performance of the fabricated field effect transistor.

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Abstract

提供一种场效应晶体管（10）及场效应晶体管的制备方法。场效应晶体管包括衬底（110），衬底包括第一表面（110a）；栅极（120），栅极自第一表面嵌设于衬底，且栅极的一端面与第一表面平齐；栅介质层（130），覆盖第一表面及栅极与第一表面平齐的端面；石墨烯层（140），设置在栅介质层背离衬底的表面；源极（150），设置在石墨烯层背离栅介质层的表面；及漏极（160），设置在石墨烯层背离栅介质层的表面，且与源极之间设有间隙。

Description

场效应晶体管及场效应晶体管的制备方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种场效应晶体管及场效应晶体管的制备方法。
背景技术
场效应晶体管(Field Effect Transistor,FET)是目前集成电路中最为重要的基本元件之一，其结构主要由源极(S)、漏极(D)、沟道层(CH)、栅极(G)和衬底构成。石墨烯是由碳原子构成的二维材料，由于具有较高的迁移率等独特的物理化学性质而受到广泛关注。然而，作为石墨烯射频电路基本单元的石墨烯场效应晶体管(Graphene Field Effect Transistor,G-FET)目前并未获得人们所期望的高性能，原因之一是石墨烯是一种化学性质稳定、无极性、疏水的材料，其表面难以获得较高质量的电介质，这也是G-FET自对准结构较难实现的原因之一。现有技术中，石墨烯层邻近一衬底设置，种子层设置在石墨烯层背离衬底的表面，栅介质层设置在种子层上，所述种子层设置在石墨烯层上以促进栅介质层更好地生长。然而，当所述种子层为有机物时，由于有机物的的介电常数较小，因此，所述种子层会影响到栅电容的大小，进而影响栅极电场对沟道层的调控作用。当所述种子层为无机物(比如，氧化铝纳米颗粒)时，无机物的介电常数虽然比有机物的介电常数大，但是，后续在种子层上形成栅介质层时，种子层和栅介质层之间形成的界面会存在很多界面缺陷，进而影响G-FET的性能。综上所述，现有技术中G-FET的性能不佳。
发明内容
第一方面，本发明提供了一种场效应晶体管，所述场效应晶体管包括：
衬底，所述衬底包括第一表面；
栅极，所述栅极自所述第一表面嵌设于所述衬底内，且所述栅极的一端面与所述第一表面平齐；
栅介质层，覆盖所述第一表面及所述栅极与所述第一表面平齐的端面；
石墨烯层，设置在所述栅介质层背离所述衬底的表面；
源极，设置在所述石墨烯层背离所述栅介质层的表面；及
漏极，设置在所述石墨烯层背离所述栅介质层的表面，且与所述源极之间设有间隙。
在第一种实施方式中，所述栅极包括第一端面、第二端面及第三端面，与所述第一表面平齐的端面定义为所述第一端面，所述第二端面与所述第三端面相对设置，所述第二端面及所述第三端面分别与所述第一端面相交，且所述第二端面与所述源极面对所述漏极的端面共面，所述第三端面与所述漏极面对所述源极的端面共面。
进一步地，所述衬底的材料包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。
进一步地，所述栅极的材料包括Pt、Au、Al、Cu、Ti、Ag、Sc、Y、Cr、Ni等材料中的任意一种或者多种。
进一步地，所述栅介质层包括HfO2、ZrO2、Al2O3、SiO2、Si3N4等材料中的任意一种或者多种。
进一步地，所述石墨烯层包括单层石墨烯、双层石墨烯或者多层石墨烯中的任意一种。
进一步地，所述源极及所述漏极包括Pt、Au、Al、Ni、Cu、Ag、Ti、Sc、Y等金属材料中的任意一种或者多种，或者所述源极及所述漏极还可以为多层石墨或者氧化铟锡。
在第二种实施方式中，所述衬底为对紫外光的透光率超过预设透光率的绝缘衬底。
在第三种实施方式中，所述石墨烯层包括单层石墨烯、双层石墨烯或者多层石墨烯中的任意一种。
在第四种实施方式中，所述栅极的厚度大于10nm。
相较于现有技术，本发明的场效应晶体管中栅介质层直接形成在所述第一表面上，能够获得高质量的栅介质层。所述石墨烯层设置在栅介质层背离所述衬底的表面，因此，消除了现有技术中在石墨烯层表面设置栅介质层时难以形成栅介质层的技术问题。且本发明的栅介质层上设置石墨烯层相较于现有技术少了一层种子层，因此，本发明的场效应晶体管更薄。进一步地，由于本发明 的场效应晶体管中石墨烯层直接设置在栅介质层上，石墨烯层与栅介质层之间没有种子层，现有技术中引进种子层所带来的种子层影响栅电容的大小以及种子层和栅介质层形成界面缺陷的技术问题得到了解决，从而提升了本发明场效应晶体管的性能。
进一步地，由于本发明的场效应晶体管中的所述栅极自所述第一表面的中部嵌入所述衬底，可以抑制因衬底引起的高频损耗。
此外，由于所述栅极的第二端面与所述源极面对所述漏极的端面共面，所述栅极的第三端面与所述漏极面对所述源极的端面共面，因此，所述栅极与所述源极之间不存在绝缘介质侧墙且所述栅极与所述漏极之间不存在绝缘介质侧墙，从而抑制了所述场效应晶体管中沟道部分可能存在的寄生电阻效应。进一步地，由于所述栅极的第二端面与所述源极面对所述漏极的端面共面，所述栅极的第三端面与所述漏极面对所述源极的端面共面，所述栅极和所述源极没有交叠，所述栅极和所述漏极之间没有交叠，因此，所述栅极和所述源极之间的寄生电容较小，所述栅极和所述漏极之间的寄生电容较小。
更进一步地，本发明中的场效应晶体管中的所述栅极、所述源极及所述漏极可以做得较厚，而不会明显增加寄生电容和。且较厚的栅极、源极及较厚的漏极能够减小这些电极自身的电阻，也能抑制这些电极产生的寄生电阻。
第二方面，本发明提供了一种场效应晶体管的制备方法，所述场效应晶体管的制备方法包括：
步骤S110，提供一衬底，所述衬底包括相对设置的第一表面及第二表面；
步骤S120，形成栅极，所述栅极自所述第一表面嵌设于到所述衬底内，且所述栅极的一端面与所述第一表面平齐；
步骤S130，形成栅介质层，所述栅介质层覆盖所述第一表面及所述栅极与所述第一表面平齐的端面；
步骤S140，形成石墨烯层，所述石墨烯层设置在所述栅介质层背离所述衬底的表面；
步骤S150，形成源极和漏极，所述源极和所述漏极设置在所述石墨烯层背离所述栅介质层的表面，且所述源极及所述漏极之间设有间隙。
在第一种实施方式中，所述步骤S120包括：
步骤S121，在所述第一表面涂布第一光刻胶层；
步骤S122，图案化所述第一光刻胶层，以移除覆盖所述第一表面的部分第一光刻胶层；
步骤S123，以剩余的第一光刻胶层为掩膜对所述第一表面进行等离子蚀刻，以在所述第一表面上形成凹槽；
步骤S124，形成第一金属层，所述第一金属层覆盖所述第一光刻胶层及填充所述凹槽，其中，所述第一金属层的厚度大于或等于所述凹槽的深度；
步骤S125，剥离剩余的所述第一光刻胶层，并将高于所述凹槽的第一金属层部分移除，以使得位于所述凹槽的第一金属层的端面与所述第一表面平齐，位于所述凹槽内且端面与所述第一表面平齐的第一金属层为所述栅极。
在第二种实施方式中，所述步骤S140包括：
步骤S141，提供一基板；
步骤S142，在所述基板的一表面上形成石墨烯层；
步骤S143，将形成有所述石墨烯层的基板转印至所述栅介质层背离所述第一表面的表面，将所述石墨烯层转印至所述栅介质层的表面上，并去除所述基板。
在第三种实施方式中，所述栅极包括第一端面、第二端面及第三端面，与所述第一表面平齐的端面定义为第一端面，所述第二端面与所述第三端面相对设置，所述第二端面及所述第三端面分别与所述第一端面相交，且所述第二端面与所述源极面对所述漏极的端面共面，所述第三端面与所述漏极面对所述源极的端面共面。
结合第三种实施方式，在第四种实施方式中，所述衬底包括第三表面及第四表面，所述第三表面与所述第四表面相对设置，所述第三表面及所述第四表面分别与所述第一表面相交，且所述第三表面相较于所述第四表面邻近所述第二端面设置，所述步骤S150包括：
步骤S151，在所述石墨烯层背离所述栅介质层的表面涂布第二光刻胶层；
步骤S152，图案化所述第二光刻胶层，以保留第一部分、第二部分及第三部分，所述第一部分设置于所述第二部分及所述第三部分之间，且所述第一部分与所述第二部分之间形成第一间隙，所述第一部分与所述第三部分之间形 成第二间隙，所述第一间隙及所述第二间隙用于显露部分石墨烯层，且所述第一部分面对所述第二部分的端面与所述第二端面共面，所述第一部分面对所述第三部分的端面与所述第三端面共面，所述第二部分背离所述第一部分的端面与所述第三表面共面，所述第三部分背离所述第一部分的端面与所述第四表面共面；
步骤S153，形成第二金属层，所述第二金属层覆盖所述第一部分、所述第二部分、所述第三部分，并且通过所述第一间隙及所述第二间隙覆盖显露出的石墨烯层；
步骤S154，剥离所述第一部分、所述第二部分及所述第三部分，通过所述第一间隙设置在所述石墨烯层上的第二金属层为所述源极，通过所述第二间隙设置在所述石墨烯层上的第二金属层为所述漏极。
相较于现有技术，本发明的场效应晶体管的制备方法将所述栅介质层直接形成在所述第一表面上，因此，能够获得高质量的栅介质层。所述石墨烯层设置在所述栅介质层背离所述衬底的表面，因此绕开了现有技术中在石墨烯层表面设置栅介质层时难以形成高质量的栅介质层的技术问题。且本发明的栅介质层上设置石墨烯层相较于现有技术少了一层种子层，因此，本发明的场效应晶体管更薄。进一步地，由于本发明的场效应晶体管中石墨烯层直接设置在栅介质层上，石墨烯层与栅介质层之间没有种子层，现有技术中引进种子层所带来的种子层影响栅电容的大小以及种子层和栅介质层形成界面缺陷的技术问题得到了解决，从而提升了制备的场效应晶体管的性能。
由于所述栅极的第二端面与所述源极面对所述漏极的端面共面，所述栅极的第三端面与所述漏极面对所述源极的端面共面，因此，所述栅极与所述源极之间不存在绝缘介质侧墙且所述栅极与所述漏极之间不存在绝缘介质侧墙，从而抑制了所述场效应晶体管中沟道部分可能存在的寄生电阻效应。进一步地，由于所述栅极的第二端面与所述源极面对所述漏极的端面共面，所述栅极的第三端面与所述漏极面对所述源极的端面共面，所述栅极和所述源极没有交叠，所述栅极和所述漏极之间没有交叠，因此，所述栅极和所述源极之间的寄生电容较小，所述栅极和所述漏极之间的寄生电容较小。
进一步地，本发明中的场效应晶体管的制备方法可以将所述栅极、所述源 极及所述漏极可以做得较厚，而不会明显增加寄生电容。且较厚的栅极、源极及较厚的漏极能够减小这些电极自身的电阻，也能抑制这些电极产生的寄生电阻。
进一步地，本发明的场效应晶体管的制备方法将所述石墨烯层在一基板上制备之后再转印至所述栅介质层上，绕开了在石墨烯层的表面较难形成栅介质层的难题，从而提高了所制备出的场效应晶体管的性能。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的场效应晶体管的剖面结构示意图；
图2为本发明一较佳实施方式的场效应晶体管的制备方法的流程图；
图3～图17为本发明一较佳实施方式的场效应晶体管的制备方法中各制备步骤的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1为本发明一较佳实施方式的场效应晶体管的剖面结构示意图。所述场效应晶体管10包括：
衬底110，所述衬底110包括第一表面110a；所述衬底110还包括与所述第一表面110a相对设置的第二表面110b；
栅极120，所述栅极120自所述第一表面110a嵌设于所述衬底110内，且所述栅极120的一端面与所述第一表面110a平齐；
栅介质层130，覆盖所述第一表面110a及所述栅极120与所述第一表面 110a平齐的端面；
石墨烯层140，设置在所述栅介质层130背离所述衬底110的表面；
源极150，设置在所述石墨烯层140背离所述栅介质层130的表面；及
漏极160，设置在所述石墨烯层140背离所述栅介质层130的表面，且与所述源极150之间设有间隙。
相较于现有技术，本发明的场效应晶体管10中栅介质层130直接形成在所述第一表面110a上，能够获得高质量的栅介质层130。所述石墨烯层140设置在栅介质层130背离所述衬底110的表面，因此，消除了现有技术中在石墨烯层表面设置栅介质层时难以形成栅介质层的技术问题。且本发明的栅介质层130上设置石墨烯层140相较于现有技术少了一层种子层，因此，本发明的场效应晶体管10更薄。进一步地，由于本发明的场效应晶体管10中石墨烯层140直接设置在栅介质层130上，石墨烯层140与栅介质层130之间没有种子层，现有技术中引进种子层所带来的种子层影响栅电容的大小以及种子层和栅介质层形成界面缺陷的技术问题得到了解决，从而提升了本发明场效应晶体管10的性能。
进一步地，由于本发明的场效应晶体管10中的所述栅极120自所述第一表面110a嵌设于所述衬底110内，可以抑制因衬底110引起的高频损耗。所述栅极120包括第一端面121、第二端面122及第三端面123，与所述第一表面110a平齐的端面定义为所述第一端面121，所述第二端面122与所述第三端面123相对设置，所述第二端面122及所述第三端面123分别与所述第一端面121相交，且所述第二端面122与所述源极150面对所述漏极160的端面共面，所述第三端面123与所述漏极160面对所述源极150的端面共面。相应地，所述衬底110还包括第三表面110c及第四表面110d，所述第三表面110c及所述第四表面110d相对设置，所述第三表面110c及所述第四表面110d分别与所述第一表面110a相交，且所述第三表面110c相较于所述第四表面110d邻近所述第二端面122设置。
由于所述栅极120的第二端面122与所述源极150面对所述漏极160的端面共面，所述栅极120的第三端面123与所述漏极160面对所述源极150的端面共面，因此，所述栅极120与所述源极150之间不存在绝缘介质侧墙且所述 栅极120与所述漏极160之间不存在绝缘介质侧墙，从而抑制了所述场效应晶体管10中沟道部分可能存在的寄生电阻效应。进一步地，由于所述栅极120的第二端面122与所述源极150面对所述漏极160的端面共面，所述栅极120的第三端面123与所述漏极160面对所述源极150的端面共面，所述栅极120和所述源极150没有交叠，所述栅极120和所述漏极160之间没有交叠，因此，所述栅极120和所述源极150之间的寄生电容CGS较小，所述栅极120和所述漏极160之间的寄生电容CSD较小。
更进一步地，本发明中的场效应晶体管10中的所述栅极120、所述源极150及所述漏极160可以做得较厚，而不会明显增加寄生电容CGS和CSD。且较厚的栅极120、源极150及较厚的漏极160能够减小这些电极自身的电阻，也能抑制这些电极产生的寄生电阻。
在本实施方式中，所述衬底110为对紫外光的透光率超过预设透光率的绝缘衬底。所述衬底110的材料包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。所述衬底110为绝缘层衬底能够减小所述衬底110的高频损耗。
所述栅极120的材料包括Pt、Au、Al、Cu、Ti、Ag、Sc、Y、Cr、Ni等材料中的任意一种或者多种。所述栅极120的厚度大于10nm。
所述栅介质层130包括HfO2、ZrO2、Al2O3、SiO2、Si3N4等材料中的任意一种或者多种。
所述石墨烯层140包括单层石墨烯、双层石墨烯或者多层石墨烯中的任意一种。
所述源极150及所述漏极160优选为在同一工序中同时形成，所述源极150及所述漏极160包括Pt、Au、Al、Ni、Cu、Ag、Ti、Sc、Y等金属材料中的任意一种或者多种。在另一实施方式中，所述源极150及所述漏极160还可以为多层石墨或者氧化铟锡(Indium Tin Oxide，ITO)。
下面结合图1及前面介绍的场效应晶体管10对场效应晶体管的制备方法进行介绍。请参阅图2，图2为本发明一较佳实施方式的场效应晶体管的制备方法的流程图。所述场效应晶体管10的制备方法包括如下步骤。
步骤S110，提供一衬底110，所述衬底110包括相对设置的第一表面110a 及第二表面110b。请一并参阅图3，在本实施方式中，所述衬底110为对紫外光的透光率超过预设透光率的绝缘衬底。所述衬底110的材料包括石英、云母、氧化铝或者透明塑料等电绝缘材料中的任意一种或者多种。所述衬底110为绝缘层衬底能够减小所述衬底110的高频损耗。
步骤S120，形成栅极120，所述栅极120自所述第一表面110a嵌设于所述衬底110内，且所述栅极120的一端面与所述第一表面110a平齐。所述栅极120的材料包括Pt、Au、Al、Cu、Ti、Ag、Sc、Y、Cr、Ni等材料中的任意一种或者多种。所述栅极120的厚度大于10nm。
所述栅极120包括第一端面121、第二端面122及第三端面123，与所述第一表面110a平齐的端面定义为所述第一端面121，所述第二端面122与所述第三端面123相对设置，所述第二端面122及所述第三端面123分别与所述第一端面121相交，且所述第二端面122与所述源极150面对所述漏极160的端面共面，所述第三端面123与所述漏极160面对所述源极150的端面共面。
在本实施方式中，所述步骤S120包括如下步骤。
步骤S121，在所述第一表面110a涂布第一光刻胶层181，请一并参阅图4。
步骤S122，图案化所述第一光刻胶层181，以移除覆盖所述第一表面110a的部分第一光刻胶层181，请一并参阅图5。
步骤S123，以剩余的第一光刻胶层181为掩膜对所述第一表面110a进行等离子蚀刻，以在所述第一表面110a上形成凹槽111。请一并参阅图6，对所述第一表面110a进行等离子蚀刻的反应气体可以为四氟化碳或者六氟化硫等氟基气体。
步骤S124，形成第一金属层182，所述第一金属层182覆盖所述第一光刻胶层181及填充所述凹槽111，其中，所述第一金属层182的厚度大于或等于所述凹槽111的深度。请一并参阅图7，所述第一金属层182可以通过热蒸发、电子束蒸发或者溅射的方法形成。
步骤S125，剥离剩余的所述第一光刻胶层181，并将高于所述凹槽111的第一金属层182部分移除，以使得位于所述凹槽111的所述第一金属层182的端面与所述第一表面110a平齐，位于所述凹槽111内且与端面与所述第一表 面110a平齐的第一金属层182为所述栅极120。请一并参阅图8，在本实施方式中，可以用丙酮等有机溶剂来剥离剩余的所述第一光刻胶层181，将高于所述凹槽111的第一金属层182部分移除时，可以采用化学机械抛光的方式。由此可见，本发明的场效应晶体管的制备方法与现有CMOS工艺兼容。且本发明的栅极120自所述第一表面110a的中部嵌入所述衬底110，可以抑制因衬底10引起的高频损耗。
步骤S130，形成栅介质层130，所述栅介质层130覆盖所述第一表面110a及所述栅极130与所述第一表面110a平齐的端面。请一并参阅图9，所述栅介质层130包括HfO2、ZrO2、Al2O3、SiO2、Si3N4等材料中的任意一种或者多种。形成所述栅介质层130时，可以采用化学气相沉积、原子层沉积或者物理气相沉积等方法形成所述栅介质层130。
步骤S140，形成石墨烯层140，所述石墨烯层140设置在所述栅介质层130背离所述衬底110的表面。所述石墨烯层140包括单层石墨烯、双层石墨烯或者多层石墨烯中的任意一种。
在本实施方式中，所述步骤S140包括以下步骤。
步骤S141，提供一基板183。请一并参阅图10，所述基板183的材料可以为聚甲基丙烯酸甲酯(Poly methyl methacrylate，PMMA)。
步骤S142，在所述基板183的一表面上形成石墨烯层140，请一并参阅图11。
步骤S143，将形成有所述石墨烯184的基板转印至所述栅介质层130背离所述第一表面110a的表面，将所述石墨烯层140转印至所述栅介质层130的表面上，并去除所述基板183，请一并参阅图12。
步骤S150，形成源极150和漏极160，所述源极150和所述漏极160设置在所述石墨烯层140背离所述栅介质层130的表面，且所述源极150及所述漏极160之间设有间隙。
所述衬底110包括第三表面110c及第四表面110d，所述第三表面110c与所述第四表面110d相对设置，所述第三表面110c及所述第四表面110d分别与所述第一表面110a相交，且所述第三表面110c相较于所述第四表面110d邻近所述第二端面122设置。所述步骤S150包括如下步骤。
步骤S151，在所述石墨烯层140背离所述栅介质层130的表面涂布第二光刻胶层184，请一并参阅图13。
步骤S152，图案化所述第二光刻胶层184，以保留第一部分184a、第二部分184b及第三部分184c，所述第一部分184a设置于所述第二部分184b及所述第三部分184c之间，且所述第一部分184a与所述第二部分184b之间形成第一间隙184d，所述第一部分184a与所述第三部分184c之间形成第二间隙184e，所述第一间隙184d及所述第二间隙184e用于显露部分石墨烯层140，且所述第一部分184a面对所述第二部分184b的端面与所述第二端面122共面，所述第一部分184a面对所述第三部分184c的端面与所述第三端面123共面，所述第二部分184b背离所述第一部分184a的端面与所述第三表面110c共面，所述第三部分184c背离所述第一部分184a的端面与所述第四表面110d共面。
所述衬底110为对紫外光的透光率超过预设透光率的绝缘衬底，所述第二光刻胶层184为紫外光光敏光刻胶层。即，被紫外光照射到的第二光刻胶层184的部分消失，没被紫外光照射的第二光刻胶层184的部分保留。在本实施方式中，所述步骤S152包括如下步骤。
步骤S152a，提供光源186及掩膜板187，所述光源186及所述掩膜板187邻近所述第二表面110b设置，且所述掩膜板186设置于所述光源186及所述第二表面110b之间，所述光源186用于发出紫外光，所述掩膜板187包括第一透光部187a、第二透光部187b及第三透光部187c，所述第一透光部187a对应所述栅极120设置且所述第一透光部187a的长度大于所述栅极120长度，所述第二透光部187b及所述第三透光部187c分别设置于所述第一透光部187a相对的两端，且所述第二透光部187b相较于所述第三透光部187c邻近所述第三表面110c设置，所述第二透光部187b背离所述第一部分184a的端面与所述第三表面110c共面，所述第三透光部187c背离所述第一透光部187a的端面与所述第四表面110d共面，且所述第一透光部187a对所述紫外光的透光率大于或等于第一透光率，所述第二透光部187b及所述第三透光部187c对所述紫外光的透光率小于或等于第二透光率，所述第一透光率大于所述第二透光率。举例而言，所述第一透光率为95％甚至更高，所述第二透光率为5％甚至更小。此时，可认为所述光源186发出的紫外线能够穿透所述第一透光部187a，而 所述光源186发出的紫外光几乎不能够穿透所述第二透光部187b及所述第三透光部187c，请一并参阅图14。
步骤S152b，以所述掩膜板187为掩膜使用所述光源186发出的所述紫外光对所述第二光刻胶层184进行曝光，以形成所述第一部分184a、所述第二部分184b及所述第三部分184c。请一并参阅图15，由于所述光源186发出的紫外光几乎不能够穿透所述第二透光部187b及所述第三透光部187c，因此，所述第二光刻胶层184对应所述第二透光部187b及所述第三透光部187c的部分被保留下来以分别形成所述第二部分184b及所述第三部分184c。而所述栅极120不能够透过紫外线，因此，对应所述栅极120的第二光刻胶层184被保留下来，以形成所述第一部分184a。
步骤S153，形成第二金属层185，所述第二金属层185覆盖所述第一部分184a、所述第二部分184b及所述第三部分184c，并且通过所述第一间隙184d及所述第二间隙184e覆盖显露出的石墨烯层140，请一并参阅图16。
步骤S154，剥离所述第一部分184a、所述第二部分184b及所述第三部分184c，通过所述第一间隙184d设置在所述石墨烯层140上的第二金属层185为所述源极150，通过所述第二间隙184e设置在所述石墨烯层140上的第二金属层185为所述漏极160，请一并参阅图17。
相较于现有技术，本发明的场效应晶体管的制备方法将所述栅介质层130直接形成在所述第一表面110上，因此，能够获得高质量的栅介质层130。所述石墨烯层140设置在所述栅介质层130背离所述衬底110的表面，因此绕开了现有技术中在石墨烯层表面设置栅介质层时难以形成高质量的栅介质层的技术问题。且本发明的栅介质层130上设置石墨烯层140相较于现有技术少了一层种子层，因此，本发明的场效应晶体管10更薄。进一步地，由于本发明的场效应晶体管10中石墨烯层140直接设置在进一步地，由于本发明的场效应晶体管10中石墨烯层140直接设置在栅介质层130上，石墨烯层140与栅介质层130之间没有种子层，现有技术中引进种子层所带来的种子层影响栅电容的大小以及种子层和栅介质层形成界面缺陷的技术问题得到了解决，从而提升了制备的场效应晶体管10的性能。
由于所述栅极120的第二端面122与所述源极150面对所述漏极160的端 面共面，所述栅极120的第三端面123与所述漏极160面对所述源极150的端面共面，因此，所述栅极120与所述源极150之间不存在绝缘介质侧墙且所述栅极120与所述漏极160之间不存在绝缘介质侧墙，从而抑制了所述场效应晶体管10中沟道部分可能存在的寄生电阻效应。进一步地，由于所述栅极120的第二端面122与所述源极150面对所述漏极160的端面共面，所述栅极120的第三端面123与所述漏极160面对所述源极150的端面共面，所述栅极120和所述源极150没有交叠，所述栅极120和所述漏极160之间没有交叠，因此，所述栅极120和所述源极150之间的寄生电容CGS较小，所述栅极120和所述漏极160之间的寄生电容CSD较小。
进一步地，本发明中的场效应晶体管的制备方法可以将所述栅极120、所述源极150及所述漏极160可以做得较厚，而不会明显增加寄生电容CGS和CSD。且较厚的栅极120、源极150及较厚的漏极160能够减小这些电极自身的电阻，也能抑制这些电极产生的寄生电阻。
进一步地，本发明的场效应晶体管的制备方法将所述石墨烯层140在一基板上制备之后再转印至所述栅介质层130上，绕开了在石墨烯层140的表面较难形成栅介质层130的难题，从而提高了制备出的场效应晶体管的性能。
本发明实施例中所使用的技术术语仅用于说明特定实施例而并不旨在限定本发明。在本文中，单数形式“一”、“该”及“所述”用于同时包括复数形式，除非上下文中明确另行说明。进一步地，在说明书中所使用的用于“包括”和/或“包含”是指存在所述特征、整体、步骤、操作、元件和/或构件，但是并不排除存在或增加一个或多个其它特征、整体、步骤、操作、元件和/或构件。
在所附权利要求中对应结构、材料、动作以及所有装置或者步骤以及功能元件的等同形式(如果存在的话)旨在包括结合其他明确要求的元件用于执行该功能的任何结构、材料或动作。本发明的描述出于实施例和描述的目的被给出，但并不旨在是穷举的或者将被发明限制在所公开的形式。在不偏离本发明的范围和精神的情况下，多种修改和变形对于本领域的一般技术人员而言是显而易见的。本发明中所描述的实施例能够更好地揭示本发明的原理与实际应用，并使本领域的一般技术人员可了解本发明。
本发明中所描述的流程图仅仅为一个实施例，在不偏离本发明的精神的情况下对此图示或者本发明中的步骤可以有多种修改变化。比如，可以不同次序的执行这些步骤，或者可以增加、删除或者修改某些步骤。本领域的一般技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (11)

  1. 一种场效应晶体管，其特征在于，所述场效应晶体管包括：
    衬底，所述衬底包括第一表面；
    栅极，所述栅极自所述第一表面嵌设于所述衬底内，且所述栅极的一端面与所述第一表面平齐；
    栅介质层，覆盖所述第一表面及所述栅极与所述第一表面平齐的端面；
    石墨烯层，设置在所述栅介质层背离所述衬底的表面；
    源极，设置在所述石墨烯层背离所述栅介质层的表面；及
    漏极，设置在所述石墨烯层背离所述栅介质层的表面，且与所述源极之间设有间隙。
  2. 如权利要求1所述的场效应晶体管，其特征在于，所述栅极包括第一端面、第二端面及第三端面，与所述第一表面平齐的端面定义为所述第一端面，所述第二端面与所述第三端面相对设置，所述第二端面及所述第三端面分别与所述第一端面相交，且所述第二端面与所述源极面对所述漏极的端面共面，所述第三端面与所述漏极面对所述源极的端面共面。
  3. 如权利要求1所述的场效应晶体管，其特征在于，所述衬底为对紫外光的透光率超过预设透光率的绝缘衬底。
  4. 如权利要求1所述的场效应晶体管，其特征在于，所述石墨烯层包括单层石墨烯、双层石墨烯或者多层石墨烯中的任意一种。
  5. 如权利要求1所述的场效应晶体管，其特征在于，所述栅极的厚度大于10nm。
  6. 一种场效应晶体管的制备方法，其特征在于，所述场效应晶体管的制备 方法包括：
    步骤S110，提供一衬底，所述衬底包括相对设置的第一表面及第二表面；
    步骤S120，形成栅极，所述栅极自所述第一表面嵌设于所述衬底内，且所述栅极的一端面与所述第一表面平齐；
    步骤S130，形成栅介质层，所述栅介质层覆盖所述第一表面及所述栅极与所述第一表面平齐的端面；
    步骤S140，形成石墨烯层，所述石墨烯层设置在所述栅介质层背离所述衬底的表面；
    步骤S150，形成源极和漏极，所述源极和所述漏极设置在所述石墨烯层背离所述栅介质层的表面，且所述源极及所述漏极之间设有间隙。
  7. 如权利要求6所述的场效应晶体管的制备方法，其特征在于，所述步骤S120包括：
    步骤S121，在所述第一表面涂布第一光刻胶层；
    步骤S122，图案化所述第一光刻胶层，以移除覆盖所述第一表面的部分第一光刻胶层；
    步骤S123，以剩余的第一光刻胶层为掩膜对所述第一表面进行等离子蚀刻，以在所述第一表面上形成凹槽；
    步骤S124，形成第一金属层，所述第一金属层覆盖所述第一光刻胶层及填充所述凹槽，其中，所述第一金属层的厚度大于或等于所述凹槽的深度；
    步骤S125，剥离剩余的所述第一光刻胶层，并将高于所述凹槽的第一金属层部分移除，以使得位于所述凹槽的第一金属层的端面与所述第一表面平齐，位于所述凹槽内且端面与所述第一表面平齐的第一金属层为所述栅极。
  8. 如权利要求6所述的场效应晶体管的制备方法，其特征在于，所述步骤S140包括：
    步骤S141，提供一基板；
    步骤S142，在所述基板的一表面上形成石墨烯层；
    步骤S143，将形成有所述石墨烯层的基板转印至所述栅介质层背离所述 第一表面的表面，将所述石墨烯层转印至所述栅介质层的表面上，并去除所述基板。
  9. 如权利要求6所述的场效应晶体管的制备方法，其特征在于，所述栅极包括第一端面、第二端面及第三端面，与所述第一表面平齐的端面定义为第一端面，所述第二端面与所述第三端面相对设置，所述第二端面及所述第三端面分别与所述第一端面相交，且所述第二端面与所述源极面对所述漏极的端面共面，所述第三端面与所述漏极面对所述源极的端面共面。
  10. 如权利要求9所述的场效应晶体管的制备方法，其特征在于，所述衬底包括第三表面及第四表面，所述第三表面与所述第四表面相对设置，所述第三表面及所述第四表面分别与所述第一表面相交，且所述第三表面相较于所述第四表面邻近所述第二端面设置，所述步骤S150包括：
    步骤S151，在所述石墨烯层背离所述栅介质层的表面涂布第二光刻胶层；
    步骤S152，图案化所述第二光刻胶层，以保留第一部分、第二部分及第三部分，所述第一部分设置于所述第二部分及所述第三部分之间，且所述第一部分与所述第二部分之间形成第一间隙，所述第一部分与所述第三部分之间形成第二间隙，所述第一间隙及所述第二间隙用于显露部分石墨烯层，且所述第一部分面对所述第二部分的端面与所述第二端面共面，所述第一部分面对所述第三部分的端面与所述第三端面共面，所述第二部分背离所述第一部分的端面与所述第三表面共面，所述第三部分背离所述第一部分的端面与所述第四表面共面；
    步骤S153，形成第二金属层，所述第二金属层覆盖所述第一部分、所述第二部分、所述第三部分，并且通过所述第一间隙及所述第二间隙覆盖显露出的石墨烯层；
    步骤S154，剥离所述第一部分、所述第二部分及所述第三部分，通过所述第一间隙设置在所述石墨烯层上的第二金属层为所述源极，通过所述第二间隙设置在所述石墨烯层上的第二金属层为所述漏极。
  11. 如权利要求10所述的场效应晶体管的制备方法，其特征在于，所述衬底为对紫外光的透光率超过预设透光率的绝缘衬底，所述第二光刻胶层为紫外光光敏光刻胶层，所述步骤S152包括：
    步骤S152a，提供光源及掩膜板，所述光源及所述掩膜板邻近所述第二表面设置，且所述掩膜板设置于所述光源与所述第二表面之间，所述光源用于发出紫外光，所述掩膜板包括第一透光部第二透光部及第三透光部，所述第一透光部对应所述栅极设置且所述第一透光部的长度大于所述栅极的长度，所述第二透光部及所述第三透光部分别设置于所述第一透光部相对的两端，且所述第二透光部相较于所述第三透光部邻近所述第三表面设置，所述第二透光部背离第一透光部的端面与所述第三表面共面，所述第三透光部背离所述第一透光部的端面与所述第四表面共面，且所述第一透光部对所述紫外光的透光率大于或等于第一透光率，所述第二透光部及所述第三透光部对所述紫外光的透光率小于或等于第二透光率，所述第一透光率大于所述第二透光率；
    步骤S152b，以所述掩膜板为掩膜使用所述光源发出的所述紫外光对所述第二光刻胶层进行曝光，以形成所述第一部分、所述第二部分及所述第三部分。
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