WO2017121089A1 - 显示基板及其制作方法和显示装置 - Google Patents

显示基板及其制作方法和显示装置 Download PDF

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Publication number
WO2017121089A1
WO2017121089A1 PCT/CN2016/091059 CN2016091059W WO2017121089A1 WO 2017121089 A1 WO2017121089 A1 WO 2017121089A1 CN 2016091059 W CN2016091059 W CN 2016091059W WO 2017121089 A1 WO2017121089 A1 WO 2017121089A1
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Prior art keywords
pixel unit
electrode
connection
connection portion
line
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PCT/CN2016/091059
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English (en)
French (fr)
Inventor
汪锐
邱海军
尚飞
金在光
李少茹
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/525,468 priority Critical patent/US10199399B2/en
Publication of WO2017121089A1 publication Critical patent/WO2017121089A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned

Definitions

  • Embodiments of the present invention relate to a display substrate, a display device, and a method of fabricating a display substrate.
  • the display substrate includes a display area including a plurality of pixel units arranged in a matrix form.
  • the ratio of the area of the light-transmitting region of the pixel unit to the area of the entire pixel unit is referred to as an aperture ratio.
  • a display substrate comprising a plurality of pixel units arranged in a matrix.
  • the pixel unit includes: a first electrode; a first connection portion connected to the first electrode; and a first connection line connected to the first connection line through the first via hole; and the pixel unit
  • the first connection line is connected to the first connection line of the pixel unit on the upper side thereof and the first connection line of the pixel unit on the lower side thereof.
  • the pixel unit further includes: a second connection portion and a third connection portion connected to the first electrode; the second connection portion of the pixel unit is connected to the third connection portion of the pixel unit on the left side thereof; and The third connection portion of the pixel unit is connected to the second connection portion of the pixel unit located on the right side thereof.
  • first connection portion, the second connection portion, and the third connection portion are disposed on the same layer.
  • the pixel unit further includes: a substrate on which the first electrode is disposed; and a gate line disposed on the substrate, and the first connection portion, the second connection portion, and the third connection The portion is disposed in the same layer as the gate line.
  • the pixel unit further includes: a source/drain electrode layer, and the first connection line is disposed in the same layer as the source/drain electrode layer.
  • the pixel unit further includes: a second electrode disposed on the source/drain electrode layer, wherein the first connection portion and the first connection line are disposed under the alignment chaotic region of the second electrode.
  • the pixel unit further includes: a passivation layer disposed on the source/drain electrode layer, at a first via hole is disposed in a position corresponding to the first connection portion of the passivation layer for communicating the first connection portion and the first connection line; shielding metal is disposed on the passivation layer Above the position corresponding to the first via.
  • the pixel unit further includes: a gate insulating layer disposed on the gate line, wherein the first via hole is disposed at a position corresponding to the first connection portion in the gate insulating layer, And configured to connect the first connecting portion and the first connecting line.
  • the second connection portion is connected to the left edge of the first electrode
  • the third connection portion is connected to the right edge of the first electrode
  • a display device comprising the display substrate as described above.
  • a method of fabricating a display substrate comprising: forming a first electrode on a substrate; forming a first connection portion connected to the first electrode on the first electrode; above the first connection portion Forming a first connection line, the first connection line being connected to the first connection line of the pixel unit on the upper side thereof and the first connection line of the pixel unit on the lower side thereof, the first connection line passing through the first via hole and the The first connecting portions are connected.
  • the method further includes: forming a second connection portion and a third connection portion connected to the first electrode on the first electrode, wherein the second connection portion is connected to the third connection portion of the pixel unit on the left side thereof The third connection portion is connected to the second connection portion in the pixel unit located on the right side thereof.
  • the second connecting portion and the third connecting portion are formed when the first connecting portion is formed.
  • the method further includes forming a gate line on the substrate, wherein the first connection portion, the second connection portion, and the third connection portion are formed when the gate line is formed.
  • the method further includes forming a source/drain electrode layer over the gate line, wherein the first connection line is formed when the source/drain electrode layer is formed.
  • the method further includes forming a second electrode having an alignment chaotic region over the source-drain electrode layer, the alignment chaotic region being located above the first connection portion and the first connection line.
  • the method further includes: forming a passivation layer over the source/drain electrode layer; forming the first via hole at a position corresponding to the first connection portion in the passivation layer to communicate the first a connecting portion and a first connecting line; a shielding metal is formed at a position corresponding to the first via hole above the passivation layer.
  • the method further includes: forming a gate insulating layer over the gate line; forming the first via hole at a position corresponding to the first connection portion in the gate insulating layer to communicate the first a connecting portion and a first connecting line.
  • 1 to 4 are schematic diagrams showing a manufacturing process of a display substrate according to a technique
  • FIG. 8 are schematic diagrams showing a manufacturing process of a display substrate according to an embodiment of the invention.
  • Figure 9 is a cross-sectional view taken along line I-I of Figure 8.
  • FIG. 10 is a plan view showing a display substrate according to an embodiment of the present invention.
  • Figure 11 is a cross-sectional view taken along line I-I of Figure 10 .
  • FIG. 4 are schematic diagrams showing a manufacturing process of a display substrate according to a technique.
  • the common electrode line 6a extends in the lateral direction to connect the common electrodes 1a disposed in the lateral direction, and the second electrode 12a and the third connecting portion 13a are provided on the common electrode 1a.
  • the second via hole 20a may be formed at the second connection portion 12a and the third via hole 30a may be formed at the third connection portion 13a, and when the pixel electrode 5a is formed, the second via hole may be formed.
  • a second connection line 53a is formed at the hole 20a for connecting the common electrode 1a to the common electrode on the upper side thereof, and a third connection line 54a is formed at the third via hole 30a for the common electrode 1a and the same
  • the common electrodes on the lower side are connected.
  • the display substrate includes a plurality of pixel units arranged in a matrix, the pixel unit including: a first electrode 1; a first connection portion 11 connected to the first electrode 1; and a first connection line 2
  • the first connecting portion 11 is connected through the first via 10
  • the first connection line 2 of the pixel unit is connected to the first connection line of the pixel unit on the upper side thereof and the first connection line of the pixel unit on the lower side thereof.
  • the first connection portion 11 is directly disposed on the first electrode 1 to be in contact with the first electrode 1.
  • an insulating layer is disposed between the first connecting line 2 and the first connecting portion 11, and the first via hole 10 is disposed in the insulating layer.
  • the first connection line 2 of the pixel unit is formed as a continuous straight line with the first connection line of the pixel unit on the upper side thereof and the first connection line of the pixel unit on the lower side thereof.
  • the first electrode when the first electrode is a common electrode, the second electrode is a pixel electrode, and when the second electrode is a pixel electrode, the first electrode is a common electrode.
  • the first electrode when the first electrode is a common electrode, the second electrode is a pixel electrode, the first electrode is a common electrode.
  • an embodiment of the present invention will be described by taking a first electrode as a common electrode and a second electrode as a pixel.
  • the first connecting line 2 is connected to the first connecting portion 11 through the first via hole 10, and is further connected to the common electrode 1.
  • the first connection line 2 is also connected to the first connection line of the pixel unit on the upper side thereof and the first connection line of the pixel unit on the lower side thereof, thereby communicating the common electrode in the pixel unit disposed in the longitudinal direction.
  • the embodiment of the present invention requires only one via hole in relation to the manner in which the common electrodes of the pixel units disposed in the longitudinal direction are communicated by the two via holes 20a and 30a and the two connecting lines 53a and 54a as shown in FIGS. 1 to 4. Therefore, the pixel electrode only needs to reserve less area for the via hole, thereby expanding the effective light-emitting area, thereby increasing the aperture ratio.
  • the pixel unit further includes a second connecting portion 12 and a third connecting portion 13 connected to the first electrode 1.
  • the second connection portion 12 of the pixel unit is connected to the third connection portion of the pixel unit located on the left side thereof; the third connection portion 13 of the pixel unit is connected to the second connection portion of the pixel unit located on the right side thereof.
  • the second connecting portion 12 is connected to the left edge of the first electrode 1
  • the third connecting portion 13 is connected to the right edge of the first electrode 1 to facilitate the common electrode and the right pixel unit in the left pixel unit.
  • the common electrode is connected.
  • the common electrode in the pixel unit disposed in the lateral direction is connected by the second connecting portion 12 and the third connecting portion 13, and is reduced by a common electrode line connection in FIGS. 1 to 4.
  • the wiring area reduces the area of the black matrix (BM) used to shield the wiring, thereby increasing the aperture ratio.
  • the aperture ratio can be increased from 63.6% to 66.7%.
  • first connecting portion 11, the second connecting portion 12, and the third connecting portion 13 are disposed on the same layer. That is, the first connecting portion 11, the second connecting portion 12, and the third connecting portion 13 can be formed in one patterning process, which simplifies the manufacturing process.
  • the pixel unit further includes a thin film transistor including a gate, a gate insulating layer, an active layer, a source and a drain, the gate is connected or integrally formed with the gate line, and the source is connected or integrated with the data line, and the drain is formed.
  • the pole is connected to the pixel electrode.
  • the pixel unit further includes a substrate 100 on which the first electrode 1, the gate line 3, and the gate 31 are disposed.
  • the first electrode 1, the gate line 3, and the gate 31 are all in contact with the substrate 100, and the first electrode 1 is spaced apart from the gate line 3 and the gate 31.
  • the first connection portion 11, the second connection portion 12, and the third connection portion 13 are disposed in the same layer as the gate line 3 and the gate electrode 31. That is, the gate line 3, the gate electrode 31, the first connection portion 11, the second connection portion 12, and the third connection portion 13 can be formed in one patterning process, which facilitates the simplification of the fabrication process.
  • the pixel unit further includes a source/drain electrode layer 4, and the first connection line 2 is disposed in the same layer as the source/drain electrode layer 4.
  • the source-drain electrode layer 4 includes the source 42 of the thin film transistor, the drain electrode 43 of the thin film transistor, and the data line 41.
  • the source 42 and the drain 43 of the thin film transistor, the data line 41, and the first connection line 2 can be formed in one patterning process, which facilitates the simplification of the fabrication process.
  • the pixel unit further includes a second electrode 5 disposed on the source/drain electrode layer 4. It is to be understood that an insulating layer such as the passivation layer 102 is further disposed between the second electrode 5 and the source/drain electrode layer 4.
  • the first connection portion 11 and the first connection line 2 are disposed under the alignment chaotic region 51 of the second electrode 5.
  • the second electrode 5 includes a plurality of domains, adjacent domains have different electrode orientations, and the alignment chaotic region 51 is a boundary region between adjacent domains.
  • the first connection line 2 and the first connection portion 11 are disposed under the alignment chaotic region 51, and the first connection is made through the alignment chaotic region 51.
  • the wire 2 and the first connecting portion 11 partially block, so that the first connecting wire 2 and the first connecting portion 11 have less influence on the transmittance. Further, it is possible to further increase the aperture ratio without occluding the first connection line 2 and the first connection portion 11 by the black matrix.
  • the pixel unit further includes a passivation layer 102 disposed between the source/drain electrode layer 4 and the second electrode 5.
  • a first via hole 10 is provided in the passivation layer 102 at a position corresponding to the first connection portion 11 for communicating the first connection portion 11 and the first connection line 2.
  • the first via hole 10 further penetrates the gate insulating layer 101 between the first electrode 1 and the first connection line 2.
  • the pixel unit further includes a occlusion metal 52 disposed at a position above the passivation layer 102 corresponding to the first via hole 10.
  • the communication of the first connecting line 2 and the first connecting portion 11 can be ensured by the first via 10.
  • the occlusion metal 52 may be in the same layer as the pixel electrode 5.
  • the material of the shielding metal 52 can be provided in the first via 10 to electrically connect the first connecting line 2 and the first connecting portion 11.
  • the first via hole 10 may be formed in the gate insulating layer 101 in this embodiment of the present invention. In this case, the first via hole 10 is not disposed in the passivation layer 102.
  • the first connection line 2 is formed in the same layer as the source/drain electrode layer 4 and is disposed on the gate insulating layer 101. When the first connection line 2 is formed, the material of the first connection line 2 can be disposed in the first via hole 10, thereby The first connection line 2 is electrically connected to the first connection portion 11.
  • the first connection line 2 and the passivation layer 102 can directly block the via hole, so that the shielding metal can be shielded from the via hole without additionally providing an occlusion metal, and the area of the pixel electrode 5 can be further increased, thereby further increasing the aperture ratio.
  • Embodiments of the present invention also provide a display device including the above display substrate.
  • the display device in the embodiment of the present invention may be any product or component having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.
  • the embodiment of the invention further provides a method for manufacturing a display substrate, comprising:
  • first connection line 2 Forming a first connection line 2 over the first connection portion 11, as shown in FIG. 6, the first connection line 2 of the pixel unit and the first connection line of the pixel unit on the upper side thereof and the pixel unit on the lower side thereof
  • the first connecting line is connected, and the first connecting line 2 is connected to the first connecting portion 11 through the first via 10, as shown in FIGS. 7 and 8.
  • the above method further includes:
  • a second connecting portion 12 and a third connecting portion 13 connected to the first electrode 1 are formed on the first electrode.
  • the second connection portion 12 of the pixel unit is connected to the third connection portion of the pixel unit located on the left side thereof; the third connection portion 13 of the pixel unit is connected to the second connection portion of the pixel unit located on the right side thereof.
  • connection portion 13 the second connecting portion 12 and the third portion are formed when the first connecting portion 11 is formed.
  • Connection portion 13 the second connecting portion 12 and the third portion are formed when the first connecting portion 11 is formed.
  • the above method further includes forming the gate lines 3 on the substrate.
  • the first connection portion 11, the second connection portion 12, and the third connection portion 13 are formed when the gate line 3 is formed.
  • the above method further includes forming the source/drain electrode layer 4 over the gate line 3.
  • the first connection line 2 is formed when the source/drain electrode layer 4 is formed.
  • the above method further includes: forming a second electrode 5 having an alignment chaotic region 51 over the source/drain electrode layer 4, the alignment chaotic region 51 being located above the first connection portion 11 and the first connection line 2, as shown in FIG. Show.
  • the above method further includes forming a passivation layer 102 over the source/drain electrode layer 4.
  • the first via hole 10 is formed at a position corresponding to the first connection portion 11 in the passivation layer 102.
  • the above method further includes forming a shielding metal 52 at a position corresponding to the first via 10 above the passivation layer.
  • the above method further includes forming the gate insulating layer 101 over the gate line 3.
  • the first via hole 10 is formed at a position corresponding to the first connection portion 11 in the gate insulating layer 101.
  • the formation process employed in the above process may include, for example, a deposition process such as deposition, sputtering, and the like, and a patterning process such as etching.

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Abstract

一种显示基板及其制作方法和显示装置。显示基板包括排列成矩阵的多个像素单元，像素单元包括：第一电极(1)；与第一电极(1)相连的第一连接部(11)；以及第一连接线(2)，第一连接部(11)通过第一过孔(10)连接至第一连接线(2)。像素单元的第一连接线(2)与位于其上侧的像素单元的第一连接线(2)和位于其下侧的像素单元的第一连接线(2)相连。扩大了有效发光区域，进而提高了开口率。

Description

显示基板及其制作方法和显示装置 技术领域
本发明的实施例涉及显示基板、显示装置和显示基板制作方法。
背景技术
显示基板包括显示区域，显示区域包括以矩阵形式设置的多个像素单元。像素单元的透光区域的面积与整个像素单元的面积之比称为开口率。通过提高开口率，可以提高显示装置的亮度并可以降低背光单元的功耗。
发明内容
根据本发明的实施例，提供一种显示基板，包括排列成矩阵的多个像素单元。所述像素单元包括：第一电极；与第一电极相连的第一连接部；以及第一连接线，所述第一连接部通过第一过孔连接至第一连接线；并且所述像素单元的第一连接线与位于其上侧的像素单元的第一连接线和位于其下侧的像素单元的第一连接线相连。
例如，所述像素单元还包括：与第一电极相连的第二连接部和第三连接部；所述像素单元的第二连接部与位于其左侧的像素单元的第三连接部相连；并且所述像素单元的第三连接部与位于其右侧的像素单元的第二连接部相连。
例如，所述第一连接部、第二连接部和第三连接部设置在同一层。
例如，所述像素单元还包括：基底，第一电极设置在所述基底之上；以及栅线，设置在所述基底之上，并且所述第一连接部、第二连接部和第三连接部与所述栅线同层设置。
例如，所述像素单元还包括：源漏电极层，并且所述第一连接线与所述源漏电极层同层设置。
例如，所述像素单元还包括：第二电极，设置在源漏电极层之上，其中，所述第一连接部和第一连接线设置在第二电极的配向混乱区域之下。
例如，所述像素单元还包括：钝化层，设置在所述源漏电极层之上，在 所述钝化层中与所述第一连接部对应的位置设置有所述第一过孔，用于连通所述第一连接部和第一连接线；遮挡金属，设置在所述钝化层之上与所述第一过孔对应的位置。
例如，所述像素单元还包括：栅绝缘层，设置在所述栅线之上，其中，在所述栅绝缘层中与所述第一连接部对应的位置设置有所述第一过孔，用于连通所述第一连接部和第一连接线。
例如，第二连接部与第一电极的左侧边缘相连，第三连接部与第一电极的右侧边缘相连。
根据本发明的实施例，还提供一种显示装置，包括如上所述的显示基板。
根据本发明的实施例，还提供一种显示基板制作方法，包括：在基底上形成第一电极；在第一电极上形成与第一电极相连的第一连接部；在第一连接部之上形成第一连接线，第一连接线与位于其上侧的像素单元的第一连接线和位于其下侧的像素单元的第一连接线相连，第一连接线通过第一过孔与所述第一连接部相连。
例如，所述方法还包括：在第一电极上形成与第一电极相连的第二连接部和第三连接部，其中，第二连接部与位于其左侧的像素单元的第三连接部相连；第三连接部与位于其右侧的像素单元中的第二连接部相连。
例如，在形成所述第一连接部时形成所述第二连接部和第三连接部。
例如，所述方法还包括：在基底上形成栅线，其中，在形成所述栅线时形成所述第一连接部、第二连接部和第三连接部。
例如，所述方法还包括：在所述栅线之上形成源漏电极层，其中，在形成所述源漏电极层时形成所述第一连接线。
例如，所述方法还包括：在源漏电极层之上形成具有配向混乱区域的第二电极，所述配向混乱区域位于所述第一连接部和第一连接线之上。
例如，所述方法还包括：在源漏电极层之上形成钝化层；在所述钝化层中与所述第一连接部对应的位置形成所述第一过孔，以连通所述第一连接部和第一连接线；在所述钝化层之上与所述第一过孔对应的位置形成遮挡金属。
例如，所述方法还包括：在所述栅线之上形成栅绝缘层；在所述栅绝缘层中与所述第一连接部对应的位置形成所述第一过孔，以连通所述第一连接部和第一连接线。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1至图4示出了根据一种技术的显示基板的制作流程示意图；
图5至图8示出了根据本发明实施例的显示基板的制作流程示意图；
图9为沿图8的I-I线剖取的截面图；
图10为根据本发明实施例的显示基板的平面示意图；以及
图11为沿图10的I-I线剖取的截面图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1至图4为根据一种技术的显示基板的制作流程示意图。如图1至图4所示，公共电极线6a沿横向方向延伸以将沿横向方向设置的公共电极1a连接在一起，在公共电极1a上设置有第二连接部12a和第三连接部13a。在形成源漏电极层4a之后可以在第二连接部12a处形成第二过孔20a并在第三连接部13a处形成第三过孔30a，进而在形成像素电极5a时，可以在第二过孔20a处形成第二连接线53a，用于将公共电极1a与位于其上侧的公共电极相连，并在第三过孔30a处形成第三连接线54a，用于将公共电极1a与位于其下侧的公共电极相连。可见，上述结构需要两个过孔来将公共电极1a和沿纵向方向与其相邻的公共电极连接起来，使得位于公共电极之上的像素电极需要为两个过孔留出空间，导致显示基板的开口率降低。
图5至图8为根据本发明实施例的显示基板的制作流程示意图，并且图9为沿图8的I-I线剖取的截面图。参见图5至图9，该显示基板包括排列成矩阵的多个像素单元，所述像素单元包括：第一电极1；与第一电极1相连的第一连接部11；以及第一连接线2，第一连接部11通过第一过孔10连接 至第一连接线2，所述像素单元的第一连接线2与位于其上侧的像素单元的第一连接线和位于其下侧的像素单元的第一连接线相连。
例如，第一连接部11直接设置在第一电极1上，以与第一电极1接触。
例如，第一连接线2与第一连接部11之间设置有绝缘层，第一过孔10设置在该绝缘层中。
例如，像素单元的第一连接线2与位于其上侧的像素单元的第一连接线和位于其下侧的像素单元的第一连接线形成为连续的直线。
需要说明的是，作为示例附图中仅示出了一个像素单元，多个像素单元中的至少一部分像素单元可以相同或相似地形成。
本发明实施例的显示基板中，在第一电极为公共电极时，第二电极为像素电极，在第二电极为像素电极时，第一电极为公共电极。以下以第一电极为公共电极且第二电极为像素电为例对本发明实施例进行说明。
本发明实施例中，第一连接线2通过第一过孔10与第一连接部11相连，进而与公共电极1相连。第一连接线2还与位于其上侧的像素单元的第一连接线和位于其下侧的像素单元的第一连接线相连，从而连通了沿纵向方向设置的像素单元中的公共电极。相对于图1至图4所示的通过两个过孔20a和30a以及两条连接线53a和54a连通沿纵向方向设置的像素单元的公共电极的方式，本发明实施例只需要一个过孔，从而使得像素电极仅需为过孔预留较少的区域，从而扩大了有效发光区域，进而提高了开口率。
例如，像素单元还包括：与第一电极1相连的第二连接部12和第三连接部13。像素单元的第二连接部12与位于其左侧的像素单元的第三连接部相连；像素单元的第三连接部13与位于其右侧的像素单元的第二连接部相连。例如，第二连接部12与第一电极1的左侧边缘相连，第三连接部13与第一电极1的右侧边缘相连，以方便与左侧像素单元中公共电极和右侧像素单元中公共电极进行连接。
本发明实施例中，通过第二连接部12和第三连接部13连接沿横向方向设置的像素单元中的公共电极，相对于图1至图4中通过一条公共电极线连接的方式，减少了布线面积，从而减少了用于遮挡布线的黑矩阵(BM)的面积，进而提升了开口率。根据本发明实施例，对于28HD的三栅线(Triple Gate)结构的显示基板，可以将开口率从63.6％提升至66.7％。
例如，第一连接部11、第二连接部12和第三连接部13设置在同一层。也就是，可以在一道构图工艺中形成第一连接部11、第二连接部12和第三连接部13，便于简化制作工艺。
例如，像素单元还包括薄膜晶体管，薄膜晶体管包括栅极、栅绝缘层、有源层、源极和漏极，栅极与栅线连接或一体形成，源极与数据线连接或一体形成，漏极与像素电极连接。例如，像素单元还包括基底100，第一电极1、栅线3和栅极31设置在基底之上。例如，第一电极1、栅线3、栅极31均与基底100接触，并且第一电极1与栅线3和栅极31间隔开。例如，第一连接部11、第二连接部12和第三连接部13与栅线3和栅极31同层设置。也就是，可以在一道构图工艺中形成栅线3、栅极31、第一连接部11、第二连接部12和第三连接部13，便于简化制作工艺。
例如，像素单元还包括：源漏电极层4，第一连接线2与源漏电极层4同层设置。例如，源漏电极层4包括薄膜晶体管的源极42、薄膜晶体管的漏极43和数据线41。可以在一道构图工艺中形成薄膜晶体管的源极42和漏极43、数据线41和第一连接线2，便于简化制作工艺。
例如，像素单元还包括：第二电极5，设置在源漏电极层4之上。需要理解的是，在第二电极5和源漏电极层4之间还设置有绝缘层，例如钝化层102。
例如，第一连接部11和第一连接线2设置在第二电极5的配向混乱区域51之下。例如，第二电极5包括多个畴，相邻的畴具有不同的电极取向，配向混乱区域51为相邻畴之间的边界区域。
由于第二电极5的配向混乱区域51本身就对透过率有一定影响，将第一连接线2和第一连接部11设置在配向混乱区域51之下，通过配向混乱区域51对第一连接线2和第一连接部11进行一部分遮挡，使得第一连接线2和第一连接部11对透过率的影响较小。进一步，可以无需通过黑矩阵对第一连接线2和第一连接部11进行遮挡，进一步提高开口率。
例如，像素单元还包括：钝化层102，设置在源漏电极层4和第二电极5之间。在钝化层102中与第一连接部11对应的位置设置有第一过孔10，用于连通第一连接部11和第一连接线2。在此情形下，例如，第一过孔10还进一步穿通位于第一电极1和第一连接线2之间的栅绝缘层101。
例如，像素单元还包括：遮挡金属52，设置在钝化层102之上与第一过孔10对应的位置。
通过第一过孔10可以保证第一连接线2和第一连接部11的连通。例如，遮挡金属52可以与像素电极5位于同一层。通过在第一过孔10处形成遮挡金属52，可以在第一过孔10中设置遮挡金属52的材料，从而将第一连接线2和第一连接部11电连接。另外，通过遮挡金属52可以避免其他结构对第一连接线2和第一连接部11的连接处造成影响。
另外，参见图10和图11，本发明实施例可以将第一过孔10形成在栅绝缘层101中，在此情形下，在钝化层102中不设置第一过孔10。第一连接线2与源漏电极层4同层形成并位于栅绝缘层101之上，在形成第一连接线2时即可在第一过孔10中设置第一连接线2的材料，从而将第一连接线2与第一连接部11电连接。在此情形下，第一连接线2以及钝化层102可以直接遮挡过孔，因此无需额外设置遮挡金属对过孔进行遮挡，可以进一步提高像素电极5的面积，从而进一步提高开口率。
本发明实施例还提出了一种显示装置，包括上述显示基板。
需要说明的是，本发明实施例中的显示装置可以为：电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明实施例还提出了一种显示基板制作方法，包括：
在基底上形成第一电极1；
在第一电极上形成与第一电极相连的第一连接部11，如图5所示；
在第一连接部11之上形成第一连接线2，如图6所示，像素单元的第一连接线2与位于其上侧的像素单元的第一连接线和位于其下侧的像素单元的第一连接线相连，第一连接线2通过第一过孔10与第一连接部11相连，如图7和8所示。
例如，上述方法还包括：
在第一电极上形成与第一电极1相连的第二连接部12和第三连接部13。像素单元的第二连接部12与位于其左侧的像素单元的第三连接部相连；像素单元的第三连接部13与位于其右侧的像素单元的第二连接部相连。
例如，如图5所示，在形成第一连接部11时形成第二连接部12和第三 连接部13。
例如，上述方法还包括：在基底上形成栅线3。例如，如图5所示，在形成栅线3时形成第一连接部11、第二连接部12和第三连接部13。
例如，上述方法还包括：在栅线3之上形成源漏电极层4。例如，如图6所示，在形成源漏电极层4时形成第一连接线2。
例如，上述方法还包括：在源漏电极层4之上形成具有配向混乱区域51的第二电极5，配向混乱区域51位于第一连接部11和第一连接线2之上，如图8所示。
例如，上述方法还包括：在源漏电极层4之上形成钝化层102。如图7所示，在钝化层102中与第一连接部11对应的位置形成第一过孔10。
例如，上述方法还包括：在钝化层之上与第一过孔10对应的位置形成遮挡金属52。
例如，上述方法还包括：在栅线3之上形成栅绝缘层101。如图11所示，在栅绝缘层101中与第一连接部11对应的位置形成第一过孔10。
例如，上述流程所采用的形成工艺例如可包括：沉积、溅射等成膜工艺和刻蚀等构图工艺。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
在本发明中，术语“第一”、“第二”、“第三”和“第四”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2016年1月15日递交的第201610027413.8号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims (18)

  1. 一种显示基板，包括排列成矩阵的多个像素单元，其中
    所述像素单元包括：第一电极；与第一电极相连的第一连接部；以及第一连接线，所述第一连接部通过第一过孔连接至第一连接线；并且
    所述像素单元的第一连接线与位于其上侧的像素单元的第一连接线和位于其下侧的像素单元的第一连接线相连。
  2. 根据权利要求1所述的显示基板，其中，
    所述像素单元还包括：与第一电极相连的第二连接部和第三连接部；
    所述像素单元的第二连接部与位于其左侧的像素单元的第三连接部相连；并且
    所述像素单元的第三连接部与位于其右侧的像素单元的第二连接部相连。
  3. 根据权利要求2所述的显示基板，其中，所述第一连接部、第二连接部和第三连接部设置在同一层。
  4. 根据权利要求3所述的显示基板，其中，
    所述像素单元还包括：基底，第一电极设置在所述基底之上；以及栅线，设置在所述基底之上，并且
    所述第一连接部、第二连接部和第三连接部与所述栅线同层设置。
  5. 根据权利要求1所述的显示基板，其中，
    所述像素单元还包括：源漏电极层，并且
    所述第一连接线与所述源漏电极层同层设置。
  6. 根据权利要求5所述的显示基板，其中，
    所述像素单元还包括：第二电极，设置在源漏电极层之上，
    其中，所述第一连接部和第一连接线设置在第二电极的配向混乱区域之下。
  7. 根据权利要求5所述的显示基板，其中，
    所述像素单元还包括：钝化层，设置在所述源漏电极层之上，
    在所述钝化层中与所述第一连接部对应的位置设置有所述第一过孔，用于连通所述第一连接部和第一连接线；
    遮挡金属，设置在所述钝化层之上与所述第一过孔对应的位置。
  8. 根据权利要求3所述的显示基板，其中，
    所述像素单元还包括：栅绝缘层，设置在所述栅线之上，
    其中，在所述栅绝缘层中与所述第一连接部对应的位置设置有所述第一过孔，用于连通所述第一连接部和第一连接线。
  9. 根据权利要求2所述的显示基板，其中，第二连接部与第一电极的左侧边缘相连，第三连接部与第一电极的右侧边缘相连。
  10. 一种显示装置，包括权利要求1至9中任一项所述的显示基板。
  11. 一种显示基板制作方法，包括：
    在基底上形成第一电极；
    在第一电极上形成与第一电极相连的第一连接部；
    在第一连接部之上形成第一连接线，第一连接线与位于其上侧的像素单元的第一连接线和位于其下侧的像素单元的第一连接线相连，第一连接线通过第一过孔与所述第一连接部相连。
  12. 根据权利要求11所述方法，还包括：
    在第一电极上形成与第一电极相连的第二连接部和第三连接部，
    其中，第二连接部与位于其左侧的像素单元的第三连接部相连；
    第三连接部与位于其右侧的像素单元中的第二连接部相连。
  13. 根据权利要求12所述方法，其中，在形成所述第一连接部时形成所述第二连接部和第三连接部。
  14. 根据权利要求13所述方法，还包括：
    在基底上形成栅线，
    其中，在形成所述栅线时形成所述第一连接部、第二连接部和第三连接部。
  15. 根据权利要求14所述方法，还包括：
    在所述栅线之上形成源漏电极层，
    其中，在形成所述源漏电极层时形成所述第一连接线。
  16. 根据权利要求15所述方法，还包括：
    在源漏电极层之上形成具有配向混乱区域的第二电极，所述配向混乱区域位于所述第一连接部和第一连接线之上。
  17. 根据权利要求15所述方法，还包括：
    在源漏电极层之上形成钝化层；
    在所述钝化层中与所述第一连接部对应的位置形成所述第一过孔，以连通所述第一连接部和第一连接线；
    在所述钝化层之上与所述第一过孔对应的位置形成遮挡金属。
  18. 根据权利要求14所述方法，还包括：
    在所述栅线之上形成栅绝缘层；
    在所述栅绝缘层中与所述第一连接部对应的位置形成所述第一过孔，以连通所述第一连接部和第一连接线。
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