WO2017121012A1 - 一种阵列基板及其制备方法 - Google Patents

一种阵列基板及其制备方法 Download PDF

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Publication number
WO2017121012A1
WO2017121012A1 PCT/CN2016/074527 CN2016074527W WO2017121012A1 WO 2017121012 A1 WO2017121012 A1 WO 2017121012A1 CN 2016074527 W CN2016074527 W CN 2016074527W WO 2017121012 A1 WO2017121012 A1 WO 2017121012A1
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Prior art keywords
pattern
hole
light shielding
source
drain electrode
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English (en)
French (fr)
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张春倩
王超
薛景峰
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/023,379 priority Critical patent/US10304860B2/en
Publication of WO2017121012A1 publication Critical patent/WO2017121012A1/zh
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    • G02F1/1362—Active matrix addressed cells
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates

Definitions

  • the driving ability of the thin film transistor (TFT) in the panel GOA circuit largely affects the charging rate of the pixel electrode capacitance (C pixel ) and the storage capacitor (C st ); improving the driving capability of the TFT can improve the display of the panel performance.
  • one technical solution adopted by the present invention is to provide an array. a substrate and a method of fabricating the same, the array substrate being applied to a GOA circuit, the array substrate comprising a substrate and a buffer layer, a first light shielding pattern, a passivation layer, a first semiconductor pattern, and a gate layer sequentially formed on the substrate An insulating layer, a first gate pattern, an interlayer insulating layer, and two first source/drain electrode patterns;
  • a width of the first light shielding pattern is smaller than a distance between the first through hole and the second through hole, such that projections of the first light shielding pattern and the first through hole on the substrate are mutually Overlapping, and projections of the first light shielding pattern and the second through holes on the substrate are offset from each other;
  • the first semiconductor pattern includes a first channel region and two first heavily doped regions on opposite sides of the first channel region;
  • One of the two first source/drain electrode patterns is electrically connected to one of the two first heavily doped regions through the first via, the two first source/drain electrode patterns The other of the two is electrically connected to the other of the two first heavily doped regions through the second via.
  • the array substrate further includes a second light shielding pattern, a second semiconductor pattern, a second gate pattern, and two second source/drain electrode patterns, wherein the second light shielding pattern is located at the buffer layer and the blunt Between the layers, the second semiconductor pattern is between the passivation layer and the gate insulating layer, and the second gate pattern is between the gate insulating layer and the interlayer insulating layer
  • the two second source/drain electrode patterns are further disposed on the interlayer insulating layer, and the array substrate is further disposed with a third through hole and a fourth through hole, wherein the two second source/drain electrode patterns are respectively Electrically connecting to the second semiconductor pattern through the third through hole and the fourth through hole And electrically insulated from the second light shielding pattern.
  • the second semiconductor pattern includes a second channel region and two second heavily doped regions on opposite sides of the second channel region; wherein the third via and the fourth pass The holes are disposed such that the two second source/drain electrode patterns are in contact with the top walls of the two second heavily doped regions through the third through holes and the fourth through holes, respectively; wherein the second A projection of the light shielding pattern on the substrate covers a projection of the second semiconductor pattern on the substrate.
  • Another technical solution adopted by the present invention is to provide an array substrate, the array substrate including a substrate and a buffer layer, a first light shielding pattern, a passivation layer, a first semiconductor pattern, and a gate insulating layer sequentially formed on the substrate a layer, a first gate pattern, an interlayer insulating layer, and two first source/drain electrode patterns; the array substrate is provided with a first via and a second via, the two first source/drain electrode patterns One of the two first source/drain electrode patterns passes through the second through hole through the first via hole and the first semiconductor pattern and the first light shielding pattern; And electrically connected to the first semiconductor pattern and electrically insulated from the first light shielding pattern.
  • the width of the first light shielding pattern is smaller than the distance between the first through hole and the second through hole, so that the first light shielding pattern and the first through hole are on the substrate.
  • the projections overlap each other, and projections of the first light shielding pattern and the second through holes on the substrate are offset from each other.
  • the first semiconductor pattern includes a first channel region and two first heavily doped regions on opposite sides of the first channel region; wherein the two first source/drain electrode patterns are One of the two first heavily doped regions is electrically connected to one of the two first heavily doped regions through the first via, and the other of the two first source/drain electrode patterns passes through the second via The other of the two first heavily doped regions is electrically connected.
  • first through hole and the second through hole are disposed such that the two first source/drain electrode patterns respectively pass through the first through hole and the second through hole and the two A sidewall of a heavily doped region is in contact, and one of the two first source/drain electrode patterns is in contact with a top wall of the first light shielding pattern through the first via.
  • the array substrate further includes a second light shielding pattern, a second semiconductor pattern, a second gate pattern, and two second source/drain electrode patterns, wherein the second light shielding pattern is located Between the buffer layer and the passivation layer, the second semiconductor pattern is located between the passivation layer and the gate insulating layer, and the second gate pattern is located at the gate insulating layer Between the interlayer insulating layers, the two second source/drain electrode patterns are located on the interlayer insulating layer, and the array substrate is further provided with a third through hole and a fourth through hole, the two The second source/drain electrode pattern is electrically connected to the second semiconductor pattern through the third via hole and the fourth via hole, and is electrically insulated from the second light shielding pattern.
  • the second semiconductor pattern includes a second channel region and two second heavily doped regions on opposite sides of the second channel region; wherein the third via and the fourth pass The holes are disposed such that the two second source/drain electrode patterns are in contact with the top walls of the two second heavily doped regions through the third through holes and the fourth through holes, respectively; wherein the second A projection of the light shielding pattern on the substrate covers a projection of the second semiconductor pattern on the substrate.
  • Another technical solution adopted by the present invention is to provide a method for manufacturing an array substrate, which comprises the following steps:
  • a buffer layer Forming a buffer layer, a first light shielding pattern, a passivation layer, a first semiconductor pattern, a gate insulating layer, a first gate pattern, and an interlayer insulating layer on the substrate;
  • first via hole Forming a first via hole and a second via hole, wherein the first via hole is disposed such that the first semiconductor pattern and the first light shielding pattern portion are exposed, and the second via hole exposes the first semiconductor pattern portion ;
  • first source/drain electrode patterns Forming two first source/drain electrode patterns on the interlayer insulating layer such that one of the two first source/drain electrode patterns passes through the first via and the first semiconductor pattern
  • the first light shielding pattern is electrically connected
  • the other of the first source/drain electrode patterns is electrically connected to the first semiconductor pattern through the second through hole, and is electrically connected to the first light shielding pattern Sexual insulation.
  • the width of the first light shielding pattern is smaller than the distance between the first through hole and the second through hole, so that the first light shielding pattern and the first through hole are on the substrate.
  • the projections overlap each other, and projections of the first light shielding pattern and the second through holes on the substrate are offset from each other.
  • first through hole and the second through hole are disposed such that the two first source/drain electrode patterns respectively pass through the first through hole and the second through hole and the two One weight
  • the sidewalls of the doped regions are in contact, and one of the two first source/drain electrode patterns is in contact with the top wall of the first light shielding pattern through the first via holes.
  • the step of sequentially forming a buffer layer, a first light shielding pattern, a passivation layer, a first semiconductor pattern, a gate insulating layer, a first gate pattern, and an interlayer insulating layer on the substrate further includes:
  • the step of forming the first through hole and the second through hole further includes:
  • the step of forming two first source/drain electrode patterns on the interlayer insulating layer further includes:
  • the semiconductor pattern is electrically connected and electrically insulated from the second light shielding pattern.
  • the beneficial effects of the present invention are: the array substrate provided by the present invention and the manufacturing method thereof, in the top gate structure design, by arranging the light shielding layer above the buffer layer and connecting it with the source/drain electrodes, thereby multiplexing the light shielding
  • the layer mask improves the driving capability of the TFT driving circuit without increasing the process and production cost.
  • Embodiment 1 is a schematic structural view of Embodiment 1 of an array substrate provided by the present invention.
  • Embodiment 2 is a schematic structural view of Embodiment 2 of an array substrate provided by the present invention.
  • Embodiment 3 is a schematic structural view of Embodiment 3 of an array substrate provided by the present invention.
  • FIG. 4 is a flow chart showing a method of manufacturing an array substrate of the present invention.
  • 5a-5g are cross-sectional views of the array substrate in each step of the present invention.
  • FIG. 6 is a flow chart showing another embodiment of a method of manufacturing an array substrate of the present invention.
  • FIG. 7a-7c are cross-sectional views of an array substrate in each step of another embodiment of the present invention.
  • Figure 8 is a flow chart showing still another embodiment of the method for fabricating the array substrate of the present invention.
  • 9a-9c are cross-sectional views of an array substrate in each step of still another embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of Embodiment 1 of an array substrate provided by the present invention.
  • the array substrate includes a substrate 100 and a buffer layer 101 and a first light shielding pattern sequentially formed on the substrate 100 .
  • 102 a passivation layer 103, a first semiconductor pattern 104, a gate insulating layer 105, a first gate pattern 106, an interlayer insulating layer 107, and two first source/drain electrode patterns 108 and 109.
  • the array substrate is provided with a first through hole 110 and a second through hole 111, and one of the two first source/drain electrode patterns 108 and 109 passes through the first through hole 110 and the first semiconductor pattern 104 and the first light shielding pattern
  • the other one of the two first source/drain electrode patterns 108 and 109 is electrically connected to the first semiconductor pattern 104 through the second via 111 and electrically insulated from the first light shielding pattern 102 .
  • the substrate 100 is generally a glass substrate or a plastic substrate, and other transparent materials may also be used.
  • the first light shielding pattern 102 and the first gate pattern 106 are both metallic materials such as molybdenum (Mo), titanium (Ti), copper (Cu), rhodium (Rb) or alloy materials thereof.
  • the width of the first light shielding pattern 102 is smaller than the distance between the first through hole 110 and the second through hole 111, so that the projections of the first light shielding pattern 102 and the first through hole 110 on the substrate 100 overlap each other.
  • the projections of one of the light shielding patterns 102 and the second through holes 111 on the substrate 100 are shifted from each other.
  • the first semiconductor pattern 104 includes a first channel region 1041 and two first heavily doped regions 1042 and 1043 on opposite sides of the first channel region 1041.
  • the first source/drain electrode pattern 108 passes through the first A via 110 is electrically connected to the first heavily doped region 1042 , and the first source/drain electrode pattern 109 is electrically connected to the first heavily doped region 1043 through the second via 111 .
  • the first via hole 110 and the second via hole 111 are disposed such that the two first source/drain electrode patterns 108 and 109 pass through the first via hole 110 and the second via hole 111 and the two first heavily doped layers, respectively.
  • the sidewalls of the hetero regions 1042 and 1043 are in contact, and one of the two first source/drain electrode patterns 108 and 109 is in contact with the top wall of the first light shielding pattern 102 through the first via hole 110.
  • the first semiconductor pattern 104 further includes two first lightly doped regions 1044 and 1045, wherein the first lightly doped region 1044 is located between the first channel region 1041 and the first heavily doped region 1042 and both Adjacently disposed, the first lightly doped region 1045 is located between and adjacent to the first channel region 1041 and the first heavily doped region 1043.
  • the two first lightly doped regions 1044 and 1045 are formed by lightly doping the channel with the first gate pattern 106 as a template after the first gate pattern 106 is formed.
  • the first source/drain electrode pattern 108 is in contact with the sidewall of the first heavily doped region 1042 through the first via hole 110, and the first source/drain electrode pattern 109 passes through the second via hole 111 and the first heavily doped region 1043.
  • the sidewall contact constitutes a carrier transport channel; when the circuit is turned on, the carrier concentration increases, and the turn-on current increases, and the voltage applied to the first light-shielding pattern 102 attracts carriers, thereby
  • the channel position is moved from the contact surface of the gate insulating layer 105 to the first semiconductor pattern 104 to the inside of the first semiconductor pattern 104, thereby avoiding the influence of interface defects on carrier transport and reducing carrier transport during transport. Loss, enhance TFT drive capability.
  • FIG. 2 is a schematic structural diagram of Embodiment 2 of the array substrate provided by the present invention.
  • the array substrate includes a TFT top gate structure of a gate terminal region as shown in FIG. 1, and a TFT top gate structure of an effective display region provided on the substrate 100.
  • the TFT top gate structure of the gate terminal region can be used as a switching element of the GOA, and the TFT top gate structure of the effective display region can be used as a switching element of the display pixel.
  • the array substrate further includes a second light shielding pattern 202, a second semiconductor pattern 204, a second gate pattern 206, and two second source/drain electrode patterns 208 and 209, wherein the second light shielding pattern 202 is located Between the buffer layer 101 and the passivation layer 103, the second semiconductor pattern 204 is located between the passivation layer 103 and the gate insulating layer 105, and the second gate pattern 206 is located between the gate insulating layer 105 and the interlayer insulating layer 107.
  • Two second source/drain electrode patterns 208 and 209 are disposed on the interlayer insulating layer 107.
  • the array substrate is further provided with a third via hole 210 and a fourth via hole 211, and two second source/drain electrode patterns 208 and 209 is electrically connected to the second semiconductor pattern 204 through the third via hole 210 and the fourth via hole 211, respectively, and the second light shielding pattern Case 202 is electrically insulated.
  • the second semiconductor pattern 204 includes a second channel region 2041 and two second heavily doped regions 2042 and 2043 located at two sides of the second channel region.
  • the third via hole 210 and the fourth via hole 211 are formed therein.
  • the two source/drain electrode patterns 208 and 209 are disposed to contact the top walls of the two second heavily doped regions 2042 and 2043 through the third via hole 210 and the fourth via hole 211, respectively;
  • the projection of the pattern 202 on the substrate 100 covers the projection of the second semiconductor pattern 204 on the substrate 100.
  • the second semiconductor pattern 204 further includes two second lightly doped regions 2044 and 2045, wherein the second lightly doped region 2044 is disposed adjacent to the second channel region 2041 and the second heavily doped region 2042, and second The lightly doped region 2045 is disposed adjacent to the second channel region 2041 and the second heavily doped region 2043.
  • the two second lightly doped regions 2044 and 2045 are formed by lightly doping the channel with the second gate pattern 206 as a template after the second gate pattern 206 is formed.
  • the etching depths of the third via hole 210 and the fourth via hole 211 are controlled by controlling the etching selection ratio and the gradient etching method so that the third via hole 210 and the fourth via hole 211 are not in contact with the second light blocking pattern 202.
  • the first light-shielding pattern 102 and the second light-shielding pattern 202 are both metal materials or alloy materials, but the widths of the two are different, and the functions are completely different.
  • the second light-shielding pattern 202 must be sufficient.
  • the first light shielding pattern 102 is for attracting carriers through a voltage applied on the first light shielding pattern 102, thereby ditching the trench
  • the track position is moved from the contact surface of the gate insulating layer 105 to the first semiconductor pattern 104 to the inside of the first semiconductor pattern 104, thereby avoiding the influence of interface defects on carrier transport and reducing the loss of carriers during transport. , enhance TFT drive capability.
  • FIG. 3 is a schematic structural diagram of Embodiment 3 of the array substrate provided by the present invention.
  • the array substrate includes an NTFT top gate structure as shown in FIG. 1, and a PTFT top gate structure disposed on the substrate 100.
  • the NTFT top gate structure and the PTFT top gate structure can be used as the switching elements of the GOA, respectively.
  • the array substrate further includes a third light shielding pattern 302, a third semiconductor pattern 304, a third gate pattern 306, and two third source/drain electrode patterns 308 and 309.
  • the third light-shielding pattern 302 is located between the buffer layer 101 and the passivation layer 103
  • the third semiconductor pattern 304 is located between the passivation layer 103 and the gate insulating layer 105
  • the third gate pattern 306 is located at the gate insulating layer 105.
  • two third source/drain electrode patterns 308 and 309 are disposed on the interlayer insulating layer 107.
  • the array substrate is further provided with a fifth through hole 310 and a sixth through hole 311, and the third source/ The drain electrode pattern 308 is electrically connected to the third semiconductor pattern 304 and the third light shielding pattern 302 through the fifth via 310; the third source/drain electrode pattern 309 is electrically connected to the third semiconductor pattern 304 through the sixth via 311. And maintaining electrical insulation with the third light shielding pattern 302.
  • the third semiconductor pattern 304 includes a third channel region 3041 and two third heavily doped regions 3042 and 3043 located at two sides of the third channel region; wherein the third source/drain electrode pattern 308 passes through the fifth
  • the via 310 is electrically connected to the third heavily doped region 3042
  • the third source/drain electrode pattern 309 is electrically connected to the third heavily doped region 3043 through the sixth via 311 .
  • the fifth via hole 310 and the sixth via hole 311 are disposed such that the two third source/drain electrode patterns 308 and 309 pass through the fifth via hole 310 and the sixth via hole 311 and the two third heavily doped regions, respectively.
  • the sidewalls of 3042 and 3043 are in contact, and one of the two third source/drain electrode patterns 308 and 309 is in contact with the top wall of the third light shielding pattern 302 through the fifth via 310.
  • the array substrate provided in this embodiment is mainly used in a MOS tube type device, and the light shielding layer mask is multiplexed by placing the light shielding layer above the buffer layer and connecting it with the source/drain electrodes, without increasing the process. And under the premise of production costs, improve TFT drive capability.
  • FIG. 4 is a flow chart of a method for fabricating an array substrate of the present invention
  • FIGS. 5a to 5g are cross-sectional views of the array substrate in each step of the present invention.
  • the manufacturing method of the array substrate specifically includes the following steps:
  • a buffer layer 401, a first light blocking pattern 402, a passivation layer 403, a first semiconductor pattern 404, a gate insulating layer 405, a first gate pattern 406, and an interlayer insulating layer 407 are sequentially formed on the substrate 400.
  • the first semiconductor pattern 404 includes a first channel region 4041 and two first heavily doped regions 4042 and 4043 on both sides of the first channel region 4041.
  • the first semiconductor pattern 404 further includes two first light Doped regions 4044 and 4045, wherein the first lightly doped region 4044 is disposed adjacent to the first channel region 4041 and the first heavily doped region 4042, and the first lightly doped region 4045 It is disposed adjacent to the first channel region 4041 and the first heavily doped region 4043.
  • the step specifically includes: sequentially depositing a buffer layer 401 and a first light shielding pattern 402 on the substrate 400 by a chemical vapor deposition method, and the buffer layer 401 is generally a silicon oxide (SiO x ) or silicon nitride (SiN x ) layer.
  • the first light shielding pattern 402 is formed into a predetermined pattern by mask lithography.
  • the first semiconductor pattern 404 is formed by forming an amorphous silicon layer on the buffer layer 401 by chemical vapor deposition, converting the amorphous silicon layer into a polysilicon layer by an annealing process, and forming a predetermined pattern on the polysilicon layer by a mask process. Further, a first semiconductor pattern 404 is formed, see FIG. 5a.
  • a patterning process is performed on the formed first semiconductor pattern 404 to form two first heavily doped regions 4042 and 4043.
  • the patterning process specifically includes: coating a photoresist on the first semiconductor pattern 404, forming a photoresist completely reserved region and a photoresist non-reserved region by using a mask process, and removing the photoresist in the non-retained region, for the first
  • the exposed portions of the semiconductor pattern 404 are doped to form two first heavily doped regions 4042 and 4043, and the photoresist is removed, see Figures 5b-5d.
  • a gate insulating layer 405 is deposited on the surface of the first semiconductor pattern 404, and is deposited and patterned by photolithography to form a first gate pattern 406, wherein the first gate pattern 406 is self-aligned with the first channel region 4041.
  • first gate pattern 406 Forming two first lightly doped regions 4044 and 4045 on both sides of the first channel region 4041 by using a first gate pattern 406 as a template, and the first gate pattern 406 and the first channel region 4041 are The alignment is such that the doping operation results in two first lightly doped regions 4044 and 4045 while blocking dopant ions from entering the first channel region 4041.
  • An interlayer insulating layer 407 is then formed on the upper surface of the first gate pattern 406, see FIG. 5e.
  • the first source/drain electrode patterns 408 and 409 can be prepared by a method such as sputtering or chemical vapor deposition, and patterned by mask lithography.
  • the width of the first light shielding pattern 402 is smaller than the distance between the first through hole 410 and the second through hole 411, so that the projections of the first light shielding pattern 402 and the first through hole 410 on the substrate 400 overlap each other.
  • the projections of one of the light shielding patterns 402 and the second through holes 411 on the substrate 400 are shifted from each other.
  • the first via hole 410 and the second via hole 411 are disposed such that the two first source/drain electrode patterns 408 and 409 pass through the first via hole 410 and the second via hole 411 and the two first heavily doped regions, respectively.
  • the sidewalls of the 4042 and 4043 are in contact with each other, and the first source/drain electrode pattern 408 is in contact with the top wall of the first light shielding pattern 402 through the first via hole 410.
  • FIGS. 7a to 7c are cross-sectional views showing an array substrate in each step of another embodiment of the present invention.
  • the manufacturing method of the array substrate is performed on the basis of the steps of the previous embodiment, and therefore the present embodiment is described on the basis of the previous embodiment.
  • the step of sequentially forming the buffer layer 401, the first light shielding pattern 402, the passivation layer 403, the first semiconductor pattern 404, the gate insulating layer 405, the first gate pattern 406, and the interlayer insulating layer 407 on the substrate 400 further includes:
  • the second semiconductor pattern 504 further includes two second lightly doped regions 5044 and 5045, wherein the second lightly doped region 5044 is disposed adjacent to the second channel region 5041 and the second heavily doped region 5042, and second The lightly doped region 5045 is disposed adjacent to the second channel region 5041 and the second heavily doped region 2043.
  • the two second lightly doped regions 5044 and 5045 are formed by lightly doping the channel with the second gate pattern 506 as a template after the second gate pattern 506 is formed.
  • the step of forming the first through hole 410 and the second through hole 411 further includes:
  • S5 forming a third through hole 510 and a fourth through hole 511.
  • the third via 510 and the fourth via 511 respectively expose a portion 504 of the second semiconductor pattern 504, as shown in FIG. 7b.
  • the step of forming the two first source/drain electrode patterns 408 and 409 on the interlayer insulating layer 407 further includes:
  • Two second source/drain electrode patterns 508 and 509 are formed on the interlayer insulating layer 407.
  • Two second source/drain electrode patterns 508 and 509 are formed on the interlayer insulating layer 407 such that the two second source/drain electrode patterns 508 and 509 pass through the third via 510 and the fourth via 511 and the second, respectively.
  • the semiconductor pattern 504 is electrically connected and electrically insulated from the second light blocking pattern 502. Refer to Figure 7c.
  • FIGS. 9a to 9c are cross-sectional views showing an array substrate in each step of still another embodiment of the present invention.
  • the method of manufacturing the array substrate is performed on the basis of the steps of the first embodiment, and therefore the present embodiment is described on the basis of the first embodiment.
  • This embodiment is an application example in which the array substrate structure of the present invention is designed for a PTFT, and its manufacturing method for a PTFT is further explained.
  • the step of sequentially forming the buffer layer 401, the first light shielding pattern 402, the passivation layer 403, the first semiconductor pattern 404, the gate insulating layer 405, the first gate pattern 406, and the interlayer insulating layer 407 on the substrate 400 further includes:
  • the present embodiment is a preparation step of the PTFT.
  • the preparation method of the PTFT does not need to perform the light doping step in the first embodiment, and the PTFT is only heavily doped. Therefore, the first example in this example
  • the three semiconductor patterns 604 include a third channel region 6041 and two third heavily doped regions 6042 and 6043 located on opposite sides of the third channel region.
  • the step of forming the first through hole 410 and the second through hole 411 further includes:
  • S8 Forming a fifth through hole 610 and a sixth through hole 611.
  • the fifth via hole 610 is disposed such that the third semiconductor pattern 604 and the third light shielding pattern 602 are partially exposed, and the sixth via hole 611 partially exposes the third semiconductor pattern 604; see FIG. 9b.
  • the step of forming the two first source/drain electrode patterns 408 and 409 on the interlayer insulating layer 407 further includes:
  • Two third source/drain electrode patterns 608 and 609 are formed on the interlayer insulating layer 407. Two third source/drain electrode patterns 608 and 609 are formed on the interlayer insulating layer 407 to electrically pass the third source/drain electrode pattern 608 through the fifth via 610 and the third semiconductor pattern 604 and the third light shielding pattern 602. The third source/drain electrode pattern 609 is electrically connected to the third semiconductor pattern 604 through the sixth via 611 and electrically insulated from the third light shielding pattern 602, see FIG. 9c.

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Abstract

提供一种阵列基板及其制备方法。阵列基板包括基板(100)，以及依次形成在基板(100)上的缓冲层(101)、第一遮光图案(102)、钝化层(103)、第一半导体图案(104)、栅极绝缘层(105)、第一栅极图案(106)、层间绝缘层(107)及两个第一源/漏电极图案(108，109)。其中，设置第一通孔(110)穿过层间绝缘层(107)、栅极绝缘层(105)、第一半导体图案(104)以及钝化层(103)，两个第一源/漏电极图案(108，109)中的一个通过第一通孔(110)与第一遮光图案(102)电性连接；设置第二通孔(111)穿过层间绝缘层(107)、栅极绝缘层(105)以及第一半导体图案(104)，两个第一源/漏电极图案(108，109)中的另一个通过第二通孔(111)与第一半导体图案(104)电性连接。该结构和方法复用第一遮光图案光罩，将第一遮光图案（102）与第一源/漏电极图案（108,109）相连，以增强薄膜晶体管的驱动能力。

Description

一种阵列基板及其制备方法 【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种阵列基板及其制备方法。
【背景技术】
在现有技术中，液晶显示器中的驱动方式包括被动式和主动式。被动式驱动是通过在液晶面板外部连接集成电路(Integrated Circuit，IC)来完成的；而阵列基板行驱动(Gate Driver on Array)技术，简称GOA技术，是主动式驱动电路中的一种，其是直接将栅极驱动电路(Gate Driver ICs)制作在阵列基板上，以替代外接硅芯片制作的驱动芯片的一种技术。由于GOA电路可直接制作在面板周围，简化了制程工艺，而且还可降低产品成本，提高液晶面板的集成度，从而使面板趋向于更加薄型化。
面板GOA电路中的提高薄膜晶体管(TFT)的驱动能力在很大程度上影响了像素电极电容(Cpixel)和存储电容(Cst)的充电率；提高TFT的驱动能力，可以改善面板的显示性能。
为了提高TFT的驱动能力，现有技术中，通过在GOA底栅结构中，将栅极电极延伸至源/漏电极下方，同时将沟道位置由栅极氧化层与半导体层接触面移到半导体层内部，避免了界面缺陷对载流子输运的影响。但是由于GOA底栅结构中栅极电极与半导体层不是自对准的，半导体层的轻掺杂区的形成需要额外增加一道光罩，并且栅极电极与半导体层的偏离会造成栅极电极与轻掺杂区的交叠，影响器件的漏电流和安全特性等。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及其制备方法，以提高TFT的驱动能力。
为解决上述技术问题，本发明采用的一个技术方案是提供一种阵列 基板及其制备方法，所述阵列基板应用于GOA电路中，所述阵列基板包括基板以及依次形成在所述基板上的缓冲层、第一遮光图案、钝化层、第一半导体图案、栅极绝缘层、第一栅极图案、层间绝缘层及两个第一源/漏电极图案；
其中，所述阵列基板设置有第一通孔和第二通孔，所述两个第一源/漏电极图案中的一个通过所述第一通孔与所述第一半导体图案和所述第一遮光图案电性连接；
所述两个第一源/漏电极图案中的另一个通过所述第二通孔与所述第一半导体图案电性连接，且与所述第一遮光图案保持电性绝缘；
所述第一遮光图案的宽度小于所述第一通孔与所述第二通孔之间的距离，以使得所述第一遮光图案和所述第一通孔在所述基板上的投影彼此重叠，而所述第一遮光图案和所述第二通孔在所述基板上的投影彼此错开；
所述第一半导体图案包括一个第一沟道区以及位于所述第一沟道区两侧的两个第一重掺杂区；
所述两个第一源/漏电极图案中的一个通过所述第一通孔与所述两个第一重掺杂区中的一个电性连接，所述两个第一源/漏电极图案中的另一个通过所述第二通孔与所述两个第一重掺杂区中的另一个电性连接。
其中，所述第一通孔和所述第二通孔设置成使得所述两个第一源/漏电极图案分别通过所述第一通孔和所述第二通孔与所述两个第一重掺杂区的侧壁接触，所述两个第一源/漏电极图案中的一个通过所述第一通孔与所述第一遮光图案的顶壁接触。
其中，所述阵列基板进一步包括第二遮光图案、第二半导体图案、第二栅极图案以及两个第二源/漏电极图案，其中所述第二遮光图案位于所述缓冲层与所述钝化层之间，所述第二半导体图案位于所述钝化层与所述栅极绝缘层之间，所述第二栅极图案位于所述栅极绝缘层与所述层间绝缘层之间，所述两个第二源/漏电极图案位于所述层间绝缘层上，所述阵列基板进一步设置有第三通孔和第四通孔，所述两个第二源/漏电极图案分别通过所述第三通孔和第四通孔与所述第二半导体图案电性连 接，且与所述第二遮光图案电性绝缘。
其中，所述第二半导体图案包括一个第二沟道区以及位于所述第二沟道区两侧的两个第二重掺杂区；其中，所述第三通孔和所述第四通孔设置成使得所述两个第二源/漏电极图案分别通过所述第三通孔和第四通孔与所述两个第二重掺杂区的顶壁接触；其中，所述第二遮光图案在所述基板上的投影覆盖所述第二半导体图案在所述基板上的投影。
本发明采用的另一个技术方案是提供一种阵列基板，所述阵列基板包括基板以及依次形成在所述基板上的缓冲层、第一遮光图案、钝化层、第一半导体图案、栅极绝缘层、第一栅极图案、层间绝缘层及两个第一源/漏电极图案；所述阵列基板设置有第一通孔和第二通孔，所述两个第一源/漏电极图案中的一个通过所述第一通孔与所述第一半导体图案和所述第一遮光图案电性连接；所述两个第一源/漏电极图案中的另一个通过所述第二通孔与所述第一半导体图案电性连接，且与所述第一遮光图案保持电性绝缘。
其中，所述第一遮光图案的宽度小于所述第一通孔与所述第二通孔之间的距离，以使得所述第一遮光图案和所述第一通孔在所述基板上的投影彼此重叠，而所述第一遮光图案和所述第二通孔在所述基板上的投影彼此错开。
其中，所述第一半导体图案包括一个第一沟道区以及位于所述第一沟道区两侧的两个第一重掺杂区；其中，所述两个第一源/漏电极图案中的一个通过所述第一通孔与所述两个第一重掺杂区中的一个电性连接，所述两个第一源/漏电极图案中的另一个通过所述第二通孔与所述两个第一重掺杂区中的另一个电性连接。
其中，所述第一通孔和所述第二通孔设置成使得所述两个第一源/漏电极图案分别通过所述第一通孔和所述第二通孔与所述两个第一重掺杂区的侧壁接触，所述两个第一源/漏电极图案中的一个通过所述第一通孔与所述第一遮光图案的顶壁接触。
其中，所述阵列基板进一步包括第二遮光图案、第二半导体图案、第二栅极图案以及两个第二源/漏电极图案，其中所述第二遮光图案位于 所述缓冲层与所述钝化层之间，所述第二半导体图案位于所述钝化层与所述栅极绝缘层之间，所述第二栅极图案位于所述栅极绝缘层与所述层间绝缘层之间，所述两个第二源/漏电极图案位于所述层间绝缘层上，所述阵列基板进一步设置有第三通孔和第四通孔，所述两个第二源/漏电极图案分别通过所述第三通孔和第四通孔与所述第二半导体图案电性连接，且与所述第二遮光图案电性绝缘。
其中，所述第二半导体图案包括一个第二沟道区以及位于所述第二沟道区两侧的两个第二重掺杂区；其中，所述第三通孔和所述第四通孔设置成使得所述两个第二源/漏电极图案分别通过所述第三通孔和第四通孔与所述两个第二重掺杂区的顶壁接触；其中，所述第二遮光图案在所述基板上的投影覆盖所述第二半导体图案在所述基板上的投影。
为解决上述技术间题，本发明采用的又一个技术方案是提供一种阵列基板的制造方法，所述制造方法包括以下步骤：
在基板上依次形成缓冲层、第一遮光图案、钝化层、第一半导体图案、栅极绝缘层、第一栅极图案以及层间绝缘层；
形成第一通孔和第二通孔，其中所述第一通孔设置成使得所述第一半导体图案和第一遮光图案部分裸露，所述第二通孔使得所述第一半导体图案部分裸露；
在所述层间绝缘层上形成两个第一源/漏电极图案，以使所述两个第一源/漏电极图案中的一个通过所述第一通孔与所述第一半导体图案和所述第一遮光图案电性连接，所述第一源/漏电极图案中的另一个通过所述第二通孔与所述第一半导体图案电性连接，并与所述第一遮光图案电性绝缘。
其中，所述第一遮光图案的宽度小于所述第一通孔与所述第二通孔之间的距离，以使得所述第一遮光图案和所述第一通孔在所述基板上的投影彼此重叠，而所述第一遮光图案和所述第二通孔在所述基板上的投影彼此错开。
其中，所述第一通孔和所述第二通孔设置成使得所述两个第一源/漏电极图案分别通过所述第一通孔和所述第二通孔与所述两个第一重 掺杂区的侧壁接触，所述两个第一源/漏电极图案中的一个通过所述第一通孔与所述第一遮光图案的顶壁接触。
其中，所述在基板上依次形成缓冲层、第一遮光图案、钝化层、第一半导体图案、栅极绝缘层、第一栅极图案以及层间绝缘层的步骤进一步包括：
在位于所述缓冲层与所述钝化层之间形成第二遮光图案，在所述钝化层与所述栅极绝缘层之间形成第二半导体图案，在所述栅极绝缘层与所述层间绝缘层之间形成第二栅极图案；
所述形成第一通孔和第二通孔的步骤进一步包括：
形成第三通孔和第四通孔，所述第三通孔和第四通孔分别使得所述第二半导体图案部分裸露；
所述在所述层间绝缘层上形成两个第一源/漏电极图案的步骤进一步包括：
在所述层间绝缘层上形成两个第二源/漏电极图案，以使得所述两个第二源/漏电极图案分别通过所述第三通孔和第四通孔与所述第二半导体图案电性连接，且与所述第二遮光图案电性绝缘。
本发明的有益效果是：本发明提供的阵列基板及其制造方法，在顶栅结构设计中，通过将遮光层置于缓冲层上方，并使其与源/漏电极相接，从而复用遮光层光罩，在不增加工序和生产成本的前提下，提高TFT驱动电路的驱动能力。
【附图说明】
图1是本发明提供的阵列基板实施方式一的结构示意图；
图2是本发明提供的阵列基板实施方式二的结构示意图；
图3是本发明提供的阵列基板实施方式三的结构示意图；
图4是本发明阵列基板的制造方法的流程图；
图5a-图5g为本发明各步骤中阵列基板的断面图；
图6是本发明阵列基板的制造方法另一实施例的流程图；
图7a-图7c为本发明另一实施例各步骤中阵列基板的断面图；
图8本发明阵列基板的制造方法又一实施例的流程图；
图9a-图9c为本发明又一实施例各步骤中阵列基板的断面图。
【具体实施方式】
下面结合附图和实施方式对本发明进行详细说明。
请参阅图1，其中图1是本发明提供的阵列基板实施方式一的结构示意图，如图1所示，该阵列基板包括基板100以及依次形成在基板100上的缓冲层101、第一遮光图案102、钝化层103、第一半导体图案104、栅极绝缘层105、第一栅极图案106、层间绝缘层107及两个第一源/漏电极图案108及109。
该阵列基板设置有第一通孔110和第二通孔111，两个第一源/漏电极图案108及109中的一个108通过第一通孔110与第一半导体图案104和第一遮光图案102电性连接；两个第一源/漏电极图案108及109中的另一个109通过第二通孔111与第一半导体图案104电性连接，且与第一遮光图案102保持电性绝缘。
其中基板100一般为玻璃基板或者塑料基板，也可以采用其他透明材料。
第一遮光图案102和第一栅极图案106均为金属材料，如钼(Mo)、钛(Ti)、铜(Cu)、铷(Rb)或其合金材料等。
其中，第一遮光图案102的宽度小于第一通孔110与第二通孔111之间的距离，以使得第一遮光图案102和第一通孔110在基板100上的投影彼此重叠，而第一遮光图案102和第二通孔111在基板100上的投影彼此错开。
其中，第一半导体图案104包括一个第一沟道区1041以及位于第一沟道区1041两侧的两个第一重掺杂区1042及1043；其中，第一源/漏电极图案108通过第一通孔110与第一重掺杂区1042电性连接，第一源/漏电极图案109通过第二通孔111与第一重掺杂区1043电性连接。
其中，第一通孔110和第二通孔111设置成使得两个第一源/漏电极图案108及109分别通过第一通孔110和第二通孔111与两个第一重掺 杂区1042及1043的侧壁接触，两个第一源/漏电极图案108及109中的一个通过第一通孔110与第一遮光图案102的顶壁接触。
其中，第一半导体图案104进一步包括两个第一轻掺杂区1044及1045，其中第一轻掺杂区1044位于第一沟道区1041与第一重掺杂区1042之间且与二者相邻设置，第一轻掺杂区1045位于第一沟道区1041和第一重掺杂区1043之间且与二者相邻设置。两个第一轻掺杂区1044及1045是在第一栅极图案106形成后，以第一栅极图案106为模板进行沟道轻掺杂而形成。
第一源/漏电极图案108通过第一通孔110与第一重掺杂区1042的侧壁接触，第一源/漏电极图案109通过第二通孔111与第一重掺杂区1043的侧壁接触，构成了载流子的输运通道；当在电路导通时，载流子浓度增加，同时开启电流增大，第一遮光图案102上施加的电压会吸引载流子，从而将沟道位置由栅极绝缘层105与第一半导体图案104接触面移到第一半导体图案104内部，避免了界面缺陷对载流子输运的影响，减小载流子在输运过程中的损耗，增强TFT驱动能力。
请参阅图2，其中图2是本发明提供的阵列基板实施方式二的结构示意图。
在本实施例中，阵列基板包括如图1所示的栅极端子区域的TFT顶栅结构，以及设置在基板100上的有效显示区域的TFT顶栅结构。其中，栅极端子区域的TFT顶栅结构可用来作为GOA的开关元件，而有效显示区域的TFT顶栅结构可用来作为显示像素的开关元件。
如图2所示，该阵列基板进一步包括第二遮光图案202、第二半导体图案204、第二栅极图案206以及两个第二源/漏电极图案208及209，其中第二遮光图案202位于缓冲层101与钝化层103之间，第二半导体图案204位于钝化层103与栅极绝缘层105之间，第二栅极图案206位于栅极绝缘层105与层间绝缘层107之间，两个第二源/漏电极图案208及209位于层间绝缘层107上，该阵列基板进一步设置有第三通孔210和第四通孔211，两个第二源/漏电极图案208及209分别通过第三通孔210和第四通孔211与第二半导体图案204电性连接，且与第二遮光图 案202电性绝缘。
其中，第二半导体图案204包括一个第二沟道区2041以及位于第二沟道区两侧的两个第二重掺杂区2042及2043；其中，第三通孔210和第四通孔211设置成使得两个第二源/漏电极图案208及209分别通过第三通孔210和第四通孔211与两个第二重掺杂区2042及2043的顶壁接触；其中，第二遮光图案202在基板100上的投影覆盖第二半导体图案204在基板100上的投影。
其中，第二半导体图案204进一步包括两个第二轻掺杂区2044及2045，其中第二轻掺杂区2044与第二沟道区2041和第二重掺杂区2042相邻设置，第二轻掺杂区2045与第二沟道区2041和第二重掺杂区2043相邻设置。两个第二轻掺杂区2044及2045是在第二栅极图案206形成后，以第二栅极图案206为模板进行沟道轻掺杂而形成。
通过控制刻蚀选择比以及梯度刻蚀的方法控制第三通孔210和第四通孔211的刻蚀深度，使第三通孔210和第四通孔211不与第二遮光图案202接触。在本实施例中，第一遮光图案102与第二遮光图案202均为金属材料或合金材料，但是两者的宽度是不同，所起的作用也是完全不同的，第二遮光图案202是必须足够宽以遮挡第二沟道区2041和两个第二重掺杂区2042及2043；而第一遮光图案102是用于通过第一遮光图案102上施加的电压来吸引载流子，从而将沟道位置由栅极绝缘层105与第一半导体图案104接触面移到第一半导体图案104内部，避免了界面缺陷对载流子输运的影响，减小载流子在输运过程中的损耗，增强TFT驱动能力。
请参阅图3，其中图3是本发明提供的阵列基板实施方式三的结构示意图。
在本实施例中，阵列基板包括如图1所示的NTFT顶栅结构，以及设置在基板100上的PTFT顶栅结构。其中，NTFT顶栅结构和PTFT顶栅结构可分别用来作为GOA的开关元件。
如图3所示，该阵列基板进一步包括第三遮光图案302、第三半导体图案304、第三栅极图案306以及两个第三源/漏电极图案308及309， 其中第三遮光图案302位于缓冲层101与钝化层103之间，第三半导体图案304位于钝化层103与栅极绝缘层105之间，第三栅极图案306位于栅极绝缘层105与层间绝缘层107之间，两个第三源/漏电极图案308及309位于层间绝缘层107上，该阵列基板进一步设置有第五通孔310和第六通孔311，第三源/漏电极图案308通过第五通孔310与第三半导体图案304和第三遮光图案302电性连接；第三源/漏电极图案309通过第六通孔311与第三半导体图案304电性连接，且与第三遮光图案302保持电性绝缘。
其中，第三半导体图案304包括一个第三沟道区3041以及位于第三沟道区两侧的两个第三重掺杂区3042及3043；其中，第三源/漏电极图案308通过第五通孔310与第三重掺杂区3042电性连接，第三源/漏电极图案309通过第六通孔311与第三重掺杂区3043电性连接。
其中，第五通孔310和第六通孔311设置成使得两个第三源/漏电极图案308及309分别通过第五通孔310和第六通孔311与两个第三重掺杂区3042及3043的侧壁接触，两个第三源/漏电极图案308及309中的一个通过第五通孔310与第三遮光图案302的顶壁接触。
本实施例中提供的阵列基板主要用于MOS管类器件中，通过将遮光层置于缓冲层上方，并使其与源/漏电极相接，从而复用遮光层光罩，在不增加工序和生产成本的前提下，提高TFT驱动能力。
本发明还提供一种阵列基板的制造方法，图4为本发明阵列基板的制造方法的流程图；图5a-图5g为本发明各步骤中阵列基板的断面图。如图4和图5所示，该阵列基板的制造方法具体包括如下步骤：
S1：在基板400上依次形成缓冲层401、第一遮光图案402、钝化层403、第一半导体图案404、栅极绝缘层405、第一栅极图案406以及层间绝缘层407。
其中，第一半导体图案404包括一个第一沟道区4041以及位于第一沟道区4041两侧的两个第一重掺杂区4042及4043；第一半导体图案404进一步包括两个第一轻掺杂区4044及4045，其中第一轻掺杂区4044与第一沟道区4041和第一重掺杂区4042相邻设置，第一轻掺杂区4045 与第一沟道区4041和第一重掺杂区4043相邻设置。
其中，该步骤具体包括：在基板400上通过化学气相沉积法依次沉积缓冲层401和第一遮光图案402，缓冲层401一般为氧化硅(SiOx)或氮化硅(SiNx)层。其中第一遮光图案402通过掩膜光刻形成预定图案。
第一半导体图案404是通过化学气相沉积法在缓冲层401上形成非晶硅层，并通过退火工艺将该非晶硅层转化为多晶硅层，并通过光罩制程在该多晶硅层上形成预定图案，进而形成第一半导体图案404，参见图5a。
对形成的第一半导体图案404采用构图工艺形成两个第一重掺杂区4042及4043。该构图工艺具体包括：在第一半导体图案404上涂覆光刻胶，采用掩膜工艺形成光刻胶完全保留区和光刻胶不保留区，去除不保留区的光刻胶，对第一半导体图案404两端暴露出的部分进行掺杂，形成两个第一重掺杂区4042及4043，并去除光刻胶，参见图5b-图5d。
在第一半导体图案404上表面沉积栅极绝缘层405，沉积并掩膜光刻图形化形成第一栅极图案406，其中第一栅极图案406与第一沟道区4041自对准。
以第一栅极图案406为模板，采用掺杂工艺在第一沟道区4041两侧形成两个第一轻掺杂区4044及4045，第一栅极图案406与第一沟道区4041自对准，使得在进行掺杂的操作得到两个第一轻掺杂区4044及4045的同时阻挡了掺杂离子进入第一沟道区4041。然后在第一栅极图案406上表面形成层间绝缘层407，参见图5e。
S2：形成第一通孔410和第二通孔411。其中第一通孔410设置成使得第一半导体图案404和第一遮光图案402部分裸露，第二通孔411使得第一半导体图案404部分裸露；参见图5f。
S3：在层间绝缘层407上形成两个第一源/漏电极图案408及409。在层间绝缘层407上形成两个第一源/漏电极图案408及409，以使两个第一源/漏电极图案408及409中的一个通过第一通孔410与第一半导体图案404和第一遮光图案402电性连接，第一源/漏电极图案408及409 中的另一个通过第二通孔411与第一半导体图案404电性连接，并与第一遮光图案402电性绝缘，参见图5g。
第一源/漏电极图案408及409可采用溅射或化学气相沉积法等方法制备，并通过掩膜光刻图形化而形成。
其中，第一遮光图案402的宽度小于第一通孔410与第二通孔411之间的距离，以使得第一遮光图案402和第一通孔410在基板400上的投影彼此重叠，而第一遮光图案402和第二通孔411在基板400上的投影彼此错开。
其中，第一通孔410和第二通孔411设置成使得两个第一源/漏电极图案408及409分别通过第一通孔410和第二通孔411与两个第一重掺杂区4042及4043的侧壁接触，第一源/漏电极图案408通过第一通孔410与第一遮光图案402的顶壁接触。
图6为本发明阵列基板的制造方法另一实施例的流程图；图7a-图7c为本发明另一实施例各步骤中阵列基板的断面图。该阵列基板的制造方法是在前一实施例的步骤基础上进行的，因此本实施例在前一实施例的基础上进行描述。
在基板400上依次形成缓冲层401、第一遮光图案402、钝化层403、第一半导体图案404、栅极绝缘层405、第一栅极图案406以及层间绝缘层407的步骤进一步包括：
S4：在位于缓冲层401与钝化层403之间形成第二遮光图案502，在钝化层403与栅极绝缘层405之间形成第二半导体图案504，在栅极绝缘层405与层间绝缘层407之间形成第二栅极图案506，参照图7a所示。
其中，第二半导体图案504进一步包括两个第二轻掺杂区5044及5045，其中第二轻掺杂区5044与第二沟道区5041和第二重掺杂区5042相邻设置，第二轻掺杂区5045与第二沟道区5041和第二重掺杂区2043相邻设置。两个第二轻掺杂区5044及5045是在第二栅极图案506形成后，以第二栅极图案506为模板进行沟道轻掺杂而形成。
其中第二重掺杂区和第二轻掺杂区的形成步骤参考前一实施例，不 再赘述。
形成第一通孔410和第二通孔411的步骤进一步包括：
S5：形成第三通孔510和第四通孔511。第三通孔510和第四通孔511分别使得第二半导体图案504部分裸露504，参照图7b所示。
在层间绝缘层407上形成两个第一源/漏电极图案408及409的步骤进一步包括：
S6：在层间绝缘层407上形成两个第二源/漏电极图案508及509。在层间绝缘层407上形成两个第二源/漏电极图案508及509以使得两个第二源/漏电极图案508及509分别通过第三通孔510和第四通孔511与第二半导体图案504电性连接，且与第二遮光图案502电性绝缘。参照图7c所示。
图8为本发明阵列基板的制造方法又一实施例的流程图；图9a-图9c为本发明又一实施例各步骤中阵列基板的断面图。该阵列基板的制造方法第一实施例的步骤基础上进行的，因此本实施例在第一实施例的基础上进行描述。
本实施例是将本发明的阵列基板结构设计用于PTFT的应用例，进而阐述其用于PTFT的制造方法。
在基板400上依次形成缓冲层401、第一遮光图案402、钝化层403、第一半导体图案404、栅极绝缘层405、第一栅极图案406以及层间绝缘层407的步骤进一步包括：
S7：在位于缓冲层401与钝化层403之间形成第三遮光图案602，在钝化层403与栅极绝缘层405之间形成第三半导体图案604，在栅极绝缘层405与层间绝缘层407之间形成第三栅极图案606，参照图9a所示。
这里需要指出的是，本实施例是PTFT的制备步骤，PTFT的制备过程中不需要进行制备方法第一实施例中轻掺杂的步骤，PTFT只进行重掺杂，因此，本实例中的第三半导体图案604包括一个第三沟道区6041以及位于第三沟道区两侧的两个第三重掺杂区6042及6043。
形成第一通孔410和第二通孔411的步骤进一步包括：
S8：形成第五通孔610和第六通孔611。其中第五通孔610设置成使得第三半导体图案604和第三遮光图案602部分裸露，第六通孔611使得第三半导体图案604部分裸露；参见图9b。
在层间绝缘层407上形成两个第一源/漏电极图案408及409的步骤进一步包括：
S9：在层间绝缘层407上形成两个第三源/漏电极图案608及609。层间绝缘层407上形成两个第三源/漏电极图案608及609，以使第三源/漏电极图案608通过第五通孔610与第三半导体图案604和第三遮光图案602电性连接，第三源/漏电极图案609通过第六通孔611与第三半导体图案604电性连接，并与第三遮光图案602电性绝缘，参见图9c。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (14)

  1. 一种阵列基板，其中，所述阵列基板应用于GOA电路中，所述阵列基板包括基板以及依次形成在所述基板上的缓冲层、第一遮光图案、钝化层、第一半导体图案、栅极绝缘层、第一栅极图案、层间绝缘层及两个第一源/漏电极图案；
    其中，所述阵列基板设置有第一通孔和第二通孔，所述两个第一源/漏电极图案中的一个通过所述第一通孔与所述第一半导体图案和所述第一遮光图案电性连接；
    所述两个第一源/漏电极图案中的另一个通过所述第二通孔与所述第一半导体图案电性连接，且与所述第一遮光图案保持电性绝缘；
    所述第一遮光图案的宽度小于所述第一通孔与所述第二通孔之间的距离，以使得所述第一遮光图案和所述第一通孔在所述基板上的投影彼此重叠，而所述第一遮光图案和所述第二通孔在所述基板上的投影彼此错开；
    所述第一半导体图案包括一个第一沟道区以及位于所述第一沟道区两侧的两个第一重掺杂区；
    所述两个第一源/漏电极图案中的一个通过所述第一通孔与所述两个第一重掺杂区中的一个电性连接，所述两个第一源/漏电极图案中的另一个通过所述第二通孔与所述两个第一重掺杂区中的另一个电性连接。
  2. 根据权利要求1所述的阵列基板，其中，所述第一通孔和所述第二通孔设置成使得所述两个第一源/漏电极图案分别通过所述第一通孔和所述第二通孔与所述两个第一重掺杂区的侧壁接触，所述两个第一源/漏电极图案中的一个通过所述第一通孔与所述第一遮光图案的顶壁接触。
  3. 根据权利要求1所述的阵列基板，其中，所述阵列基板进一步包括第二遮光图案、第二半导体图案、第二栅极图案以及两个第二源/漏电极图案，其中所述第二遮光图案位于所述缓冲层与所述钝化层之间，所述第二半导体图案位于所述钝化层与所述栅极绝缘层之间，所述第二栅 极图案位于所述栅极绝缘层与所述层间绝缘层之间，所述两个第二源/漏电极图案位于所述层间绝缘层上，所述阵列基板进一步设置有第三通孔和第四通孔，所述两个第二源/漏电极图案分别通过所述第三通孔和第四通孔与所述第二半导体图案电性连接，且与所述第二遮光图案电性绝缘。
  4. 根据权利要求1所述的阵列基板，其中，所述第二半导体图案包括一个第二沟道区以及位于所述第二沟道区两侧的两个第二重掺杂区；
    其中，所述第三通孔和所述第四通孔设置成使得所述两个第二源/漏电极图案分别通过所述第三通孔和第四通孔与所述两个第二重掺杂区的顶壁接触；
    其中，所述第二遮光图案在所述基板上的投影覆盖所述第二半导体图案在所述基板上的投影。
  5. 一种阵列基板，其中，所述阵列基板包括基板以及依次形成在所述基板上的缓冲层、第一遮光图案、钝化层、第一半导体图案、栅极绝缘层、第一栅极图案、层间绝缘层及两个第一源/漏电极图案；
    其中，所述阵列基板设置有第一通孔和第二通孔，所述两个第一源/漏电极图案中的一个通过所述第一通孔与所述第一半导体图案和所述第一遮光图案电性连接；
    所述两个第一源/漏电极图案中的另一个通过所述第二通孔与所述第一半导体图案电性连接，且与所述第一遮光图案保持电性绝缘。
  6. 根据权利要求5所述的阵列基板，其中，所述第一遮光图案的宽度小于所述第一通孔与所述第二通孔之间的距离，以使得所述第一遮光图案和所述第一通孔在所述基板上的投影彼此重叠，而所述第一遮光图案和所述第二通孔在所述基板上的投影彼此错开。
  7. 根据权利要求5所述的阵列基板，其中，所述第一半导体图案包括一个第一沟道区以及位于所述第一沟道区两侧的两个第一重掺杂区；
    其中，所述两个第一源/漏电极图案中的一个通过所述第一通孔与所述两个第一重掺杂区中的一个电性连接，所述两个第一源/漏电极图案中的另一个通过所述第二通孔与所述两个第一重掺杂区中的另一个电性 连接。
  8. 根据权利要求7所述的阵列基板，其中，所述第一通孔和所述第二通孔设置成使得所述两个第一源/漏电极图案分别通过所述第一通孔和所述第二通孔与所述两个第一重掺杂区的侧壁接触，所述两个第一源/漏电极图案中的一个通过所述第一通孔与所述第一遮光图案的顶壁接触。
  9. 根据权利要求5所述的阵列基板，其中，所述阵列基板进一步包括第二遮光图案、第二半导体图案、第二栅极图案以及两个第二源/漏电极图案，其中所述第二遮光图案位于所述缓冲层与所述钝化层之间，所述第二半导体图案位于所述钝化层与所述栅极绝缘层之间，所述第二栅极图案位于所述栅极绝缘层与所述层间绝缘层之间，所述两个第二源/漏电极图案位于所述层间绝缘层上，所述阵列基板进一步设置有第三通孔和第四通孔，所述两个第二源/漏电极图案分别通过所述第三通孔和第四通孔与所述第二半导体图案电性连接，且与所述第二遮光图案电性绝缘。
  10. 根据权利要求9所述的阵列基板，其中，所述第二半导体图案包括一个第二沟道区以及位于所述第二沟道区两侧的两个第二重掺杂区；
    其中，所述第三通孔和所述第四通孔设置成使得所述两个第二源/漏电极图案分别通过所述第三通孔和第四通孔与所述两个第二重掺杂区的顶壁接触；
    其中，所述第二遮光图案在所述基板上的投影覆盖所述第二半导体图案在所述基板上的投影。
  11. 一种阵列基板的制造方法，其中，所述制造方法包括以下步骤：
    在基板上依次形成缓冲层、第一遮光图案、钝化层、第一半导体图案、栅极绝缘层、第一栅极图案以及层间绝缘层；
    形成第一通孔和第二通孔，其中所述第一通孔设置成使得所述第一半导体图案和第一遮光图案部分裸露，所述第二通孔使得所述第一半导体图案部分裸露；
    在所述层间绝缘层上形成两个第一源/漏电极图案，以使所述两个第 一源/漏电极图案中的一个通过所述第一通孔与所述第一半导体图案和所述第一遮光图案电性连接，所述第一源/漏电极图案中的另一个通过所述第二通孔与所述第一半导体图案电性连接，并与所述第一遮光图案电性绝缘。
  12. 根据权利要求11所述的制造方法，其中，所述第一遮光图案的宽度小于所述第一通孔与所述第二通孔之间的距离，以使得所述第一遮光图案和所述第一通孔在所述基板上的投影彼此重叠，而所述第一遮光图案和所述第二通孔在所述基板上的投影彼此错开。
  13. 根据权利要求11所述的制造方法，其中，所述第一通孔和所述第二通孔设置成使得所述两个第一源/漏电极图案分别通过所述第一通孔和所述第二通孔与所述两个第一重掺杂区的侧壁接触，所述两个第一源/漏电极图案中的一个通过所述第一通孔与所述第一遮光图案的顶壁接触。
  14. 根据权利要求11所述的制造方法，其中，所述在基板上依次形成缓冲层、第一遮光图案、钝化层、第一半导体图案、栅极绝缘层、第一栅极图案以及层间绝缘层的步骤进一步包括：
    在位于所述缓冲层与所述钝化层之间形成第二遮光图案，在所述钝化层与所述栅极绝缘层之间形成第二半导体图案，在所述栅极绝缘层与所述层间绝缘层之间形成第二栅极图案；
    所述形成第一通孔和第二通孔的步骤进一步包括：
    形成第三通孔和第四通孔，所述第三通孔和第四通孔分别使得所述第二半导体图案部分裸露；
    所述在所述层间绝缘层上形成两个第一源/漏电极图案的步骤进一步包括：
    在所述层间绝缘层上形成两个第二源/漏电极图案，以使得所述两个第二源/漏电极图案分别通过所述第三通孔和第四通孔与所述第二半导体图案电性连接，且与所述第二遮光图案电性绝缘。
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