WO2017121010A1 - 用于amoled的薄膜晶体管阵列基板及其制造方法 - Google Patents

用于amoled的薄膜晶体管阵列基板及其制造方法 Download PDF

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WO2017121010A1
WO2017121010A1 PCT/CN2016/074505 CN2016074505W WO2017121010A1 WO 2017121010 A1 WO2017121010 A1 WO 2017121010A1 CN 2016074505 W CN2016074505 W CN 2016074505W WO 2017121010 A1 WO2017121010 A1 WO 2017121010A1
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thin film
film transistor
electrode pattern
gate
insulating layer
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French (fr)
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张合静
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present invention relates to the field of planar display, and more particularly to a thin film transistor array substrate for an AMOLED and a method of fabricating the same.
  • a diode (AMOLED) display device generally includes a substrate and a thin film transistor formed on the substrate (Thin Film) Transistor (TFT) and an organic light emitting diode body formed on the thin film transistor.
  • TFT Thin Film Transistor
  • the active matrix organic light emitting diode display device has a switching thin film transistor and a driving thin film transistor in one pixel.
  • the switching thin film transistor is used to address the pixel voltage, that is, the gate driving voltage
  • the driving thin film transistor is used to control the driving current of the organic light emitting diode body.
  • the gate insulating layer of the driving thin film transistor and the switching thin film transistor (Gate Insulator) is formed at the same time and has the same thickness, which makes the gate capacitances of the driving thin film transistor and the switching thin film transistor equal, and the subthreshold swing of the thin film transistor (sub-threshold) Swing, SS) depends on the size of the gate capacitance, and the size of the gate capacitance depends on the thickness of the gate insulating layer, so when the thicknesses of the gate insulating layers of the driving thin film transistor and the switching thin film transistor are equal, the driving thin film transistor and The subthreshold swings of the switching thin film transistors are also equal.
  • Switched thin film transistors require a small subthreshold swing for fast charge and discharge; driving thin film transistors requires a relatively large subthreshold swing to facilitate gray scale display. Therefore, in the case where the subthreshold swings of the driving thin film transistor and the switching thin film transistor are equal in size, a relatively small subthreshold swing may be disadvantageous for gray scale display of the active matrix organic light emitting diode display device; Large subthreshold swings reduce the charge and discharge rate, which affects the operating speed of the display circuit. It can be seen that there is a contradiction between the subthreshold swing of the driving thin film transistor and the subthreshold swing of the switching thin film transistor.
  • the electrodes of the vertical jumper are prone to short circuit in the case of unstable process, and the parasitic capacitance formed by the insulating layer between the electrodes and the same is disadvantageous for high-order display. .
  • the main object of the present invention is to provide a thin film transistor array substrate for AMOLED, which is structured to facilitate gray scale definition and maintain a better circuit operation speed to solve the subthreshold swing of the driving thin film transistor subthreshold swing and the switching thin film transistor. There are contradictory technical problems between the swings.
  • Another object of the present invention is to provide a method for fabricating a thin film transistor array substrate for an AMOLED, which can effectively increase the subthreshold swing of the driving thin film transistor while keeping the subthreshold swing of the switching thin film transistor small.
  • the gray scale can be well defined without affecting the operating voltage and the operating speed of the circuit, thereby improving the display quality of the panel.
  • the manufacturing method can reduce the short circuit probability of the electrode caused by the instability of the process, and improve the yield. Effectively reduces parasitic capacitance.
  • the present invention provides a thin film transistor array substrate for an AMOLED, comprising: a substrate; a plurality of thin film transistor pixel units disposed on the substrate, each thin film transistor pixel unit including at least one driving thin film transistor And at least one switching thin film transistor; a first electrode pattern layer disposed on the substrate; an insulating layer disposed on the substrate and covering the gates of the driving thin film transistor and the switching thin film transistor and the first An electrode pattern layer; and a second electrode pattern layer disposed on the insulating layer and partially overlapping the first electrode pattern layer, wherein the insulating layer has a large thickness at the overlap, Non-overlapping places have a small thickness.
  • the insulating layer also has a larger thickness at a gate position corresponding to the driving thin film transistor; and has a smaller thickness at a gate position corresponding to the switching thin film transistor.
  • the thickness of the insulating layer at the overlap of the second electrode pattern layer and the first electrode pattern layer is substantially equal to the insulating layer at a gate corresponding to the driving thin film transistor. The thickness of the location.
  • the first electrode pattern layer constitutes a lower electrode of a storage capacitor and a plurality of scan lines; and the second electrode pattern layer constitutes an upper electrode of the storage capacitor and a plurality of data lines.
  • the first electrode pattern layer further comprises a gate of the driving thin film transistor and a gate of the switching thin film transistor; and the second electrode pattern layer further comprises the driving thin film transistor a source and a drain, a source and a drain of the switching thin film transistor.
  • a lower electrode of the storage capacitor is connected to a gate of the driving thin film transistor; an upper electrode of the storage capacitor is connected to a source of the driving thin film transistor.
  • the insulating layer comprises one of a silicon oxide layer, a silicon nitride layer, or a combination thereof.
  • the present invention also provides a method for fabricating a thin film transistor array substrate for an AMOLED, comprising the steps of: providing a substrate in step 1, and forming a first electrode pattern layer and a plurality of driving thin film transistors on the substrate. a gate and a gate of the plurality of switching thin film transistors; and step 3, forming an insulating layer on the substrate to cover the first electrode pattern layer, the gate of the driving thin film transistor, and the switching thin film transistor a step of patterning and partially thinning the insulating layer such that the insulating layer is patterned and has different thicknesses; and step 5, corresponding to the switching thin film transistor on the insulating layer a gate and a gate of the driving thin film transistor form a semiconductor layer; and a step 6, forming a second electrode pattern layer on the insulating layer, a source and a drain of the switching thin film transistor, and a driving thin film transistor a source and a drain, wherein the second electrode pattern layer partially overlaps the first electrode pattern layer, wherein the insul
  • the insulating layer also has a larger thickness at a gate position corresponding to the driving thin film transistor; and has a smaller thickness at a gate position corresponding to the switching thin film transistor.
  • the first electrode pattern layer constitutes a lower electrode of a storage capacitor, a plurality of scan lines, a gate of the driving thin film transistor, and a gate of the switching thin film transistor; a second electrode pattern layer constituting an upper electrode of the storage capacitor, a plurality of data lines, a source and a drain of the driving thin film transistor, a source and a drain of the switching thin film transistor; wherein the insulating layer is on a scan line
  • the intersection with the data lines also has a large thickness.
  • the invention mainly adopts a patterning process to make the insulating layer have a large thickness on the gate of the driving thin film transistor and the overlapping portion of the vertical crossing of the electrode, in addition to reducing the gate capacitance of the driving thin film transistor, thereby increasing the driving.
  • the subthreshold swing of the thin film transistor to facilitate gray scale display while also maintaining a small thickness of the insulating layer on the gate of the switching thin film transistor, so that the subthreshold swing of the switching thin film transistor is kept small to increase circuit operation
  • the speed and the overlapping portion of the vertical line of the electrode have a large thickness and can effectively reduce the parasitic capacitance, so the invention can effectively improve the quality of the AMOLED display device.
  • FIG. 1 is a schematic view showing the structure of a thin film transistor array substrate for an AMOLED of the present invention.
  • FIG. 2 is a schematic view showing an electrode jumper structure of a thin film transistor array substrate for an AMOLED of the present invention.
  • FIG. 3 is a flow chart showing a method of fabricating a thin film transistor array substrate for an AMOLED of the present invention.
  • the thin film transistor array substrate of the present invention is mainly applied to an AMOLED display device, that is, an active matrix organic light emitting diode display device, mainly by providing an organic light emitting diode device on the thin film transistor array substrate, and using the thin film transistor array substrate.
  • the driving circuit independently controls the illumination of the pixels formed by each of the organic light emitting diode devices.
  • a thin film transistor array substrate for an AMOLED provided by the present invention mainly includes a substrate 10 , a plurality of thin film transistor pixel units 11 , a first electrode pattern layer 12 , an insulating layer 13 , and a second electrode pattern layer . 14.
  • the substrate 100 is a transparent substrate, and may be, for example, a glass substrate or a plastic substrate.
  • the thin film transistor pixel units 11 are arranged in a matrix and disposed on the substrate 10.
  • Each thin film transistor pixel unit 11 includes at least one driving thin film transistor 11A and at least one switching thin film transistor 11B, wherein the switching thin film transistor 11A is used.
  • the pixel voltage is addressed, and the driving thin film transistor 11B is used to control the driving current of the organic light emitting diode body.
  • the first electrode pattern layer 12 is disposed on the substrate 10, which may be formed, for example, by depositing a metal layer and patterning it.
  • the first electrode pattern layer 12 constitutes a lower electrode 120 of the storage capacitor Cst and a plurality of scan lines.
  • the first electrode pattern layer 12 also constitutes the gate 110A and the gate of the driving thin film transistor 11A.
  • the gate 110B of the switching thin film transistor 11B; the lower electrode 120 of the storage capacitor Cst is connected to the gate 110A of the driving thin film transistor 11A.
  • the insulating layer 13 is disposed on the substrate 10 and covers the gate electrodes 110A, 110B of the driving thin film transistor 11A and the switching thin film transistor 11B as a gate insulating layer; and covers the first electrode pattern layer 12 .
  • the insulating layer 13 may be including silicon oxide, silicon nitride, or a combination thereof, but is not limited thereto.
  • the second electrode pattern layer 14 is disposed on the insulating layer 13, which may be formed, for example, by depositing a metal layer and patterning it.
  • the second electrode pattern layer 14 partially overlaps with the first electrode pattern layer 12, wherein the insulating layer 13 has a larger thickness at the overlap and a smaller thickness at a non-overlap.
  • the second electrode pattern layer 14 may constitute an upper electrode 140 of the storage capacitor Cst and a plurality of data lines, wherein the data lines vertically cross the scan line formed by the first electrode pattern layer 12, Therefore, as shown in FIG. 2, the vertical line of the scan line and the data line is where the second electrode pattern layer 14 partially overlaps the first electrode pattern layer 12, so the insulating layer 13 is on the scan line.
  • a vertical thickness line with the data line has a larger thickness d1 and a non-vertical line has a smaller thickness d2.
  • the insulating layer 13 has a large thickness at the overlap of the electrode patterns, in particular, the insulating layer 13 at the vertical crossing of the electrode has a large thickness, which not only reduces the probability of short circuit of the electrode due to process instability, but also improves the product. The yield can also effectively reduce the parasitic capacitance at the vertical crossing of the electrode.
  • the second electrode pattern layer 14 may also constitute a source 111A and a drain 112A of the driving thin film transistor 11A, a source 111B and a drain 112B of the switching thin film transistor 11B, wherein
  • the drain 112A of the driving thin film transistor 11A may be connected to an organic light emitting diode device; the drain 111B of the switching thin film transistor 11B is connected to the gate 110A of the driving thin film transistor 11A.
  • the upper electrode 140 of the storage capacitor Cst is connected to the source 111A of the driving thin film transistor 11A.
  • the insulating layer 13 also has a large thickness D1 at a position corresponding to the gate 110A of the driving thin film transistor 11A; and corresponds to a position of the gate 110B of the switching thin film transistor 11B. Having a smaller thickness D2, such that the gate 110A of the driving thin film transistor 11A has a thicker insulating layer, which can lower the gate capacitance of the driving thin film transistor 11A, thereby increasing the subthreshold of the driving thin film transistor 11A.
  • the swing is applied to facilitate gray scale display, while the insulating layer 13 has a small thickness on the gate 110B of the switching thin film transistor 11B, so that the subthreshold swing of the switching thin film transistor 11B is kept small to increase the circuit operation speed.
  • the thickness of the insulating layer 13 at the overlap of the second electrode pattern layer 14 and the first electrode pattern layer 12 is preferably substantially equal to the insulating layer 13 corresponding to the driving thin film transistor 11A.
  • the thickness of the position of the gate 110A for example, the thickness d1 of the insulating layer 13 at the vertical line of the scan line and the data line is substantially equal to the position of the insulating layer 13 corresponding to the gate 110A of the driving thin film transistor 11A. Thickness D1.
  • FIG. 3 is a flowchart of a method of fabricating a thin film transistor array substrate for an AMOLED of the present invention.
  • the manufacturing method of the above thin film transistor array substrate mainly comprises the following steps:
  • Step 1 Provide a substrate 10.
  • Step 2 forming a first electrode pattern layer 12, a plurality of gate electrodes 110A of the driving thin film transistors 11A, and a plurality of gates 110B of the switching thin film transistors 11B on the substrate 10.
  • the first The electrode pattern layer 12 may be formed by depositing a metal layer and patterning it, which may constitute a lower electrode 120 of a storage capacitor Cst, a plurality of scan lines, and simultaneously constitute a gate of the driving thin film transistor 11A. 110A and a gate 110B of the switching thin film transistor 11B.
  • Step 3 forming an insulating layer 13 on the substrate 10 to cover the first electrode pattern layer 12, the gate 110A of the driving thin film transistor 11A, and the gate 110B of the switching thin film transistor 11B.
  • Step 4 patterning and partially thinning the insulating layer 13 so that the insulating layer 13 is patterned and has different thicknesses;
  • the specific yellow light process may be: an unpatterned insulating layer Form a photoresist layer on top and then pass the gray mask (gray Tone mask) or halftone mask The mask is exposed to the photoresist layer so that the photoresist layer is selectively exposed to light and the mask pattern is completely copied onto the photoresist. A portion of the photoresist is then removed by a suitable developer such that the photoresist layer exhibits the desired pattern and thickness.
  • gray mask gray Tone mask
  • halftone mask The mask is exposed to the photoresist layer so that the photoresist layer is selectively exposed to light and the mask pattern is completely copied onto the photoresist.
  • a portion of the photoresist is then removed by a suitable developer such that the photoresist layer exhibits the desired pattern and thickness.
  • Step 5 Form a semiconductor layer 15 on the insulating layer 13 corresponding to the position of the gate 110B of the switching thin film transistor 11B and the gate 110A of the driving thin film transistor 11A.
  • Step 6 Form a second electrode pattern layer 14 on the insulating layer 13, a source 111B and a drain 112B of the switching thin film transistor 11B, and a source 111A and a drain 112A of the driving thin film transistor 11A.
  • the second electrode pattern layer 14 may be formed by depositing and patterning a metal layer, and may constitute an upper electrode of the storage capacitor, a plurality of data lines, a source 111A of the driving thin film transistor 11A, and The drain 112A, the source 111B of the switching thin film transistor 11B, and the drain 112B.
  • the second electrode pattern layer 14 partially overlaps the first electrode pattern layer 12, wherein the insulating layer 13 has a large thickness at the overlap after being patterned by the yellow light process described above, and is non-overlapping It has a small thickness.
  • the insulating layer 13 also has a larger thickness at a position corresponding to the gate 110A of the driving thin film transistor 11A; and has a smaller thickness at a position corresponding to the gate 110B of the switching thin film transistor 11B,
  • the insulating layer 13 also has a large thickness at the vertical crossing of the scanning lines and the data lines.
  • the fabrication of the thin film transistor array substrate of the present invention is completed by the above steps.
  • the manufacturing method of the thin film transistor array substrate of the present invention has a large thickness on the gate of the driving thin film transistor and the overlapping portion of the vertical crossing of the electrode by the patterning process, except that the insulating layer can be reduced.
  • Driving the gate capacitance of the thin film transistor thereby increasing the subthreshold swing of the driving thin film transistor to facilitate gray scale display while maintaining the insulating layer has a small thickness on the gate of the switching thin film transistor, so that the switching thin film transistor
  • the subthreshold swing is kept small to increase the circuit operation speed, and the overlapping portions of the vertical crossing lines of the electrodes have a large thickness and can effectively reduce the parasitic capacitance. Therefore, the present invention can effectively improve the quality of the AMOLED display device.

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  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种用于AMOLED的薄膜晶体管阵列基板及其制造方法，所述薄膜晶体管阵列基板包括：一基板（10）；数个薄膜晶体管像素单元（11），设置在所述基板（10）上，每一薄膜晶体管像素单元（11）包括至少一驱动薄膜晶体管（11A）及至少一开关薄膜晶体管（11B）；一第一电极图案层（12），设置在所述基板（10）上；一绝缘层（13），设置于所述基板（10）上，并覆盖所述驱动薄膜晶体管（11A）及开关薄膜晶体管（11B）的栅极（110A，110B）及所述第一电极图案层（12）；以及一第二电极图案层（14），设置在所述绝缘层（13）上，并与所述第一电极图案层（12）部分重叠，其中所述绝缘层（13）在所述重叠处具有较大的厚度，在非重叠处具有较小的厚度。

Description

用于AMOLED的薄膜晶体管阵列基板及其制造方法 技术领域
本发明涉及平面显示领域，尤其涉及一种用于AMOLED的薄膜晶体管阵列基板及其制造方法。
 背景技术
现有的有源矩阵有机发光二极管（Active-matrix organic light emitting diode，AMOLED）显示装置一般包括：基板、形成于基板上的薄膜晶体管（Thin Film Transistor，TFT）及形成于薄膜晶体管上的有机发光二极管本体。具体地说，所述有源矩阵有机发光二极管显示装置在一个像素中具有开关薄膜晶体管和驱动薄膜晶体管。开关薄膜晶体管用于对像素电压也就是栅极驱动电压寻址，而驱动薄膜晶体管用来控制有机发光二极管本体的驱动电流。
在制备有源矩阵有机发光二极管显示装置时，所述驱动薄膜晶体管和开关薄膜晶体管的栅极绝缘层（Gate Insulator）同时形成，厚度相同，这就使得所述驱动薄膜晶体管和开关薄膜晶体管的栅极电容的大小相等，而薄膜晶体管的亚阈值摆幅（sub-threshold swing，S.S.）取决于栅极电容大小，又栅极电容大小取决于栅极绝缘层的厚度，因此当驱动薄膜晶体管和开关薄膜晶体管的栅极绝缘层的厚度相等时，就导致驱动薄膜晶体管和开关薄膜晶体管的亚阈值摆幅也相等。
开关薄膜晶体管需要有较小的亚阈值摆幅以达到快速充放电的目的；驱动薄膜晶体管需要相对较大一点的亚阈值摆幅以利于灰阶的显示。因此，在所述驱动薄膜晶体管和开关薄膜晶体管的亚阈值摆幅的大小相等的情况下，相对较小的亚阈值摆幅会不利于有源矩阵有机发光二极管显示装置的灰阶显示；相对较大的亚阈值摆幅则会降低充放电速度，从而影响显示电路的操作速度。可见，驱动薄膜晶体管亚阈值摆幅与开关薄膜晶体管的亚阈值摆幅之间存在矛盾。
再者，在所述有源矩阵有机发光二极管显示装置中，垂直跨线的电极在制程不稳定的情况下容易发生短路，且电极与它们之间的绝缘层形成的寄生电容不利于高阶显示。
故，有必要提供一种用于AMOLED的薄膜晶体管阵列基板及其制造方法，以解决现有技术所存在的问题。
 技术问题
本发明的主要目的在于提供一种用于AMOLED的薄膜晶体管阵列基板，其结构有利于灰阶定义并维持较佳的电路操作速度，以解决驱动薄膜晶体管亚阈值摆幅与开关薄膜晶体管的亚阈值摆幅之间存在矛盾的技术问题。
本发明的另一目的在于提供一种用于AMOLED的薄膜晶体管阵列基板的制造方法，能在保持开关薄膜晶体管的亚阈值摆幅较小的前提下有效提高驱动薄膜晶体管的亚阈值摆幅，进而在不影响操作电压及电路操作速度的情况下，可以很好的定义灰阶，从而提升面板的显示品质；同时所述制造方法可以减少制程不稳定导致的电极短路概率，提高良率，还能有效减少寄生电容。
 技术解决方案
为实现上述目的，本发明提供一种用于AMOLED的薄膜晶体管阵列基板，包括：一基板；数个薄膜晶体管像素单元，设置在所述基板上，每一薄膜晶体管像素单元包括至少一驱动薄膜晶体管及至少一开关薄膜晶体管；一第一电极图案层，设置在所述基板上；一绝缘层，设置于所述基板上，并覆盖所述驱动薄膜晶体管及开关薄膜晶体管的栅极及所述第一电极图案层；以及一第二电极图案层，设置在所述绝缘层上，并与所述第一电极图案层部分重叠，其中所述绝缘层在所述重叠处具有较大的厚度，在非重叠处具有较小的厚度。
在本发明的一实施例中，所述绝缘层在对应所述驱动薄膜晶体管的栅极位置也具有较大的厚度；在对应所述开关薄膜晶体管的栅极位置具有较小的厚度。
在本发明的一实施例中，所述绝缘层在所述第二电极图案层与所述第一电极图案层的重叠处的厚度大致等于所述绝缘层在对应所述驱动薄膜晶体管的栅极位置的厚度。
在本发明的一实施例中，所述第一电极图案层构成一储存电容的下电极、数个扫描线；所述第二电极图案层构成所述储存电容的上电极、数个数据线。
在本发明的一实施例中，所述第一电极图案层还构成所述驱动薄膜晶体管的栅极和所述开关薄膜晶体管的栅极；所述第二电极图案层还构成所述驱动薄膜晶体管的源极和漏极、所述开关薄膜晶体管的源极和漏极。
在本发明的一实施例中，所述储存电容的下电极连接所述驱动薄膜晶体管的栅极；所述储存电容的上电极连接所述驱动薄膜晶体管的源极。
在本发明的一实施例中，所述绝缘层包括氧化硅层、氮化硅层之一或其组合。
本发明还提供一种用于AMOLED的薄膜晶体管阵列基板的制造方法，包括以下步骤：步骤1、提供一基板；步骤2、在所述基板上形成一第一电极图案层、数个驱动薄膜晶体管的栅极及数个开关薄膜晶体管的栅极；步骤3、在所述基板上形成一绝缘层，以覆盖所述第一电极图案层、所述驱动薄膜晶体管的栅极和所述开关薄膜晶体管的栅极；步骤4、对所述绝缘层进行图案化及局部薄化处理，使得所述绝缘层被图案化并具有不同的厚度；步骤5、在所述绝缘层上对应所述开关薄膜晶体管的栅极与驱动薄膜晶体管的栅极的位置形成一半导体层；以及步骤6、在所述绝缘层上形成一第二电极图案层、所述开关薄膜晶体管的源极和漏极和驱动薄膜晶体管的源极和漏极，其中所述第二电极图案层与所述第一电极图案层部分重叠，其中所述绝缘层在所述重叠处具有较大的厚度，在非重叠处具有较小的厚度。
在本发明的一实施例中，所述绝缘层在对应所述驱动薄膜晶体管的栅极位置也具有较大的厚度；在对应所述开关薄膜晶体管的栅极位置具有较小的厚度。
在本发明的一实施例中，所述第一电极图案层构成一储存电容的下电极、数个扫描线、所述驱动薄膜晶体管的栅极和所述开关薄膜晶体管的栅极；所述第二电极图案层构成所述储存电容的上电极、数个数据线、所述驱动薄膜晶体管的源极和漏极、所述开关薄膜晶体管的源极和漏极；其中所述绝缘层在扫描线与数据线的交错处也具有较大的厚度。
 有益效果
本发明主要是通过图案化处理使得绝缘层在驱动薄膜晶体管的栅极上以及电极垂直跨线的重叠部位都具有较大的厚度，除了可以降低驱动薄膜晶体管的栅极电容，进而增大了驱动薄膜晶体管的亚阈值摆幅，以利于灰阶显示，同时也保持绝缘层在开关薄膜晶体管的栅极上具有较小的厚度，使得开关薄膜晶体管的亚阈值摆幅保持较小，以增加电路操作速度，电极垂直跨线的重叠部位都具有较大的厚度还可以有效减少寄生电容，故本发明可有效提高AMOLED显示装置的品质。
附图说明
图1是本发明用于AMOLED的薄膜晶体管阵列基板的结构示意图。
图2是本发明用于AMOLED的薄膜晶体管阵列基板的电极跨线结构示意图。
图3是本发明用于AMOLED的薄膜晶体管阵列基板的制造方法的流程图。
 本发明的最佳实施方式
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下。再者，本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
本发明的薄膜晶体管阵列基板主要是应用于AMOLED显示装置，即有源矩阵有机发光二极管显示装置，主要是通过在所述薄膜晶体管阵列基板上设置有机发光二极管器件，利用所述薄膜晶体管阵列基板的驱动电路对每个有机发光二极管器件构成的像素的发光进行独立控制。请参阅图1，本发明提供的用于AMOLED的薄膜晶体管阵列基板主要包括一基板10、数个薄膜晶体管像素单元11、一第一电极图案层12、一绝缘层13及一第二电极图案层14。
所述基板100为一透明基板，可以例如是一玻璃基板或是一塑胶基板。
所述薄膜晶体管像素单元11排列成矩阵而设置在所述基板10上，每一薄膜晶体管像素单元11包括至少一驱动薄膜晶体管11A及至少一开关薄膜晶体管11B，其中所述开关薄膜晶体管11A是用于对像素电压寻址，而所述驱动薄膜晶体管11B用来控制有机发光二极管本体的驱动电流。
所述第一电极图案层12设置在所述基板上10，其可以例如是通过沉积一层金属层并将其图案化后而形成。所述第一电极图案层12构成一储存电容Cst的下电极120、数个扫描线；本实施例中，所述第一电极图案层12还构成所述驱动薄膜晶体管11A的栅极110A和所述开关薄膜晶体管11B的栅极110B；所述储存电容Cst的下电极120连接所述驱动薄膜晶体管11A的栅极110A。
所述绝缘层13设置于所述基板10上，并覆盖所述驱动薄膜晶体管11A及开关薄膜晶体管11B的栅极110A,110B，以作为栅极绝缘层；并覆盖所述第一电极图案层12。所述绝缘层13可以是包括氧化硅、氮化硅或其组合，但不在此限。
所述第二电极图案层14设置在所述绝缘层13上，其可以例如是通过沉积一层金属层并将其图案化后而形成。所述第二电极图案层14并且与所述第一电极图案层12部分重叠，其中所述绝缘层13在所述重叠处具有较大的厚度，在非重叠处具有较小的厚度。具体而言，所述第二电极图案层14可构成所述储存电容Cst的上电极140、数个数据线，其中所述数据线垂直跨过所述第一电极图案层12构成的扫描线，因此，如图2所示，扫描线与数据线的垂直跨线处即为所述第二电极图案层14与所述第一电极图案层12部分重叠处，故所述绝缘层13在扫描线与数据线的垂直跨线处具有较大的厚度d1，在非垂直跨线处则具有较小的厚度d2。所述绝缘层13在电极图案的重叠处具有较大的厚度，特别是让电极垂直跨线处的绝缘层13具有较大的厚度，不仅可以减少由于制程不稳定导致的电极短路概率，提高产品的良率，还能有效减少电极垂直跨线处的寄生电容。
此外，如图1所示，所述第二电极图案层14还可构成所述驱动薄膜晶体管11A的源极111A和漏极112A、所述开关薄膜晶体管11B的源极111B和漏极112B，其中所述驱动薄膜晶体管11A的漏极112A可连接至一有机发光二极管器件；所述开关薄膜晶体管11B的漏极111B则连接所述驱动薄膜晶体管11A的栅极110A。所述储存电容Cst的上电极140连接所述驱动薄膜晶体管11A的源极111A。如图1所示，本实施例中，所述绝缘层13在对应所述驱动薄膜晶体管11A的栅极110A位置也具有较大的厚度D1；在对应所述开关薄膜晶体管11B的栅极110B位置具有较小的厚度D2，如此一来，所述驱动薄膜晶体管11A的栅极110A具有较厚的绝缘层将可以降低驱动薄膜晶体管11A的栅极电容，进而增大了驱动薄膜晶体管11A的亚阈值摆幅，以利于灰阶显示，同时绝缘层13在开关薄膜晶体管11B的栅极110B上具有较小的厚度，可使得开关薄膜晶体管11B的亚阈值摆幅保持较小，以增加电路操作速度。在本实施例中，所述绝缘层13在所述第二电极图案层14与所述第一电极图案层12的重叠处的厚度优选大致等于所述绝缘层13在对应所述驱动薄膜晶体管11A的栅极110A位置的厚度，例如所述绝缘层13在扫描线与数据线的垂直跨线处具有的厚度d1大致等于所述绝缘层13在对应所述驱动薄膜晶体管11A的栅极110A位置的厚度D1。
配合图1并进一步参考图3所示，图3是本发明用于AMOLED的薄膜晶体管阵列基板的制造方法的流程图。上述的薄膜晶体管阵列基板的制造方法主要包含下列步骤：
步骤1、提供一基板10。
步骤2、在所述基板10上形成一第一电极图案层12、数个驱动薄膜晶体管11A的栅极110A及数个开关薄膜晶体管11B的栅极110B，在一实施例中，所述第一电极图案层12可以是通过沉积一层金属层并将其图案化后而形成，其可构成一储存电容Cst的下电极120、数个扫描线，并同时构成所述驱动薄膜晶体管11A的栅极110A和所述开关薄膜晶体管11B的栅极110B。
步骤3、在所述基板10上形成一绝缘层13，以覆盖所述第一电极图案层12、所述驱动薄膜晶体管11A的栅极110A和所述开关薄膜晶体管11B的栅极110B。
步骤4、对所述绝缘层13进行图案化及局部薄化处理，使得所述绝缘层13被图案化并具有不同的厚度；其具体的黄光工艺可为：在未经图案化的绝缘层上先形成一光阻层，然后通过灰色调掩膜(gray tone mask)或半色调掩膜(half-tone mask)对光阻层曝光，使得光阻层受到的曝光程度具有选择性，并同时将掩膜图案完整的复印至光阻上。然后，再通过合适的显影液剂（developer）除去部分光阻，使得光阻层显现所需要的图案及厚度。
步骤5、在所述绝缘层13上对应所述开关薄膜晶体管11B的栅极110B与驱动薄膜晶体管11A的栅极110A的位置形成一半导体层15。
步骤6、在所述绝缘层13上形成一第二电极图案层14、所述开关薄膜晶体管11B的源极111B和漏极112B和驱动薄膜晶体管11A的源极111A和漏极112A，其中所述第二电极图案层14可以是通过沉积一层金属层并将其图案化后而形成，并可构成所述储存电容的上电极、数个数据线、所述驱动薄膜晶体管11A的源极111A和漏极112A、所述开关薄膜晶体管11B的源极111B和漏极112B。所述第二电极图案层14与所述第一电极图案层12部分重叠，其中所述绝缘层13经过上述的黄光工艺图案化后，在所述重叠处具有较大的厚度，在非重叠处具有较小的厚度。优选地，所述绝缘层13在对应所述驱动薄膜晶体管11A的栅极110A位置也具有较大的厚度；在对应所述开关薄膜晶体管11B的栅极110B位置具有较小的厚度，又所述绝缘层13在扫描线与数据线的垂直跨线处也具有较大的厚度。
通过上述步骤便完成了本发明的薄膜晶体管阵列基板的制造。
相较于现有技术，本发明的薄膜晶体管阵列基板的制造方法通过图案化处理使得绝缘层在驱动薄膜晶体管的栅极上以及电极垂直跨线的重叠部位都具有较大的厚度，除了可以降低驱动薄膜晶体管的栅极电容，进而增大了驱动薄膜晶体管的亚阈值摆幅，以利于灰阶显示，同时也保持绝缘层在开关薄膜晶体管的栅极上具有较小的厚度，使得开关薄膜晶体管的亚阈值摆幅保持较小，以增加电路操作速度，电极垂直跨线的重叠部位都具有较大的厚度还可以有效减少寄生电容，故本发明可有效提高AMOLED显示装置的品质。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (14)

  1. 一种用于AMOLED的薄膜晶体管阵列基板，其包括：
    一基板；
    数个薄膜晶体管像素单元，设置在所述基板上，每一薄膜晶体管像素单元包括至少一驱动薄膜晶体管及至少一开关薄膜晶体管；
    一第一电极图案层，设置在所述基板上；
    一绝缘层，设置于所述基板上，并覆盖所述驱动薄膜晶体管及开关薄膜晶体管的栅极及所述第一电极图案层；所述绝缘层在对应所述驱动薄膜晶体管的栅极位置具有较大的厚度；在对应所述开关薄膜晶体管的栅极位置具有较小的厚度；以及
    一第二电极图案层，设置在所述绝缘层上，并与所述第一电极图案层部分重叠，其中所述绝缘层在所述重叠处具有较大的厚度，在非重叠处具有较小的厚度；其中所述第一电极图案层构成一储存电容的下电极、数个扫描线；所述第二电极图案层构成所述储存电容的上电极、数个数据线；其中所述绝缘层在扫描线与数据线的垂直跨线处也具有较大的厚度。
  2. 如权利要求1所述的用于AMOLED的薄膜晶体管阵列基板，其中所述第一电极图案层还构成所述驱动薄膜晶体管的栅极和所述开关薄膜晶体管的栅极；所述第二电极图案层还构成所述驱动薄膜晶体管的源极和漏极、所述开关薄膜晶体管的源极和漏极。
  3. 如权利要求2所述的用于AMOLED的薄膜晶体管阵列基板，其中所述储存电容的下电极连接所述驱动薄膜晶体管的栅极；所述储存电容的上电极连接所述驱动薄膜晶体管的源极。
  4. 如权利要求1所述的用于AMOLED的薄膜晶体管阵列基板，其中所述绝缘层包括氧化硅层、氮化硅层之一或其组合。
  5. 一种用于AMOLED的薄膜晶体管阵列基板，其包括：
    一基板；
    数个薄膜晶体管像素单元，设置在所述基板上，每一薄膜晶体管像素单元包括至少一驱动薄膜晶体管及至少一开关薄膜晶体管；
    一第一电极图案层，设置在所述基板上；
    一绝缘层，设置于所述基板上，并覆盖所述驱动薄膜晶体管及开关薄膜晶体管的栅极及所述第一电极图案层；以及
    一第二电极图案层，设置在所述绝缘层上，并与所述第一电极图案层部分重叠，其中所述绝缘层在所述重叠处具有较大的厚度，在非重叠处具有较小的厚度。
  6. 如权利要求5所述的用于AMOLED的薄膜晶体管阵列基板，其中所述绝缘层在对应所述驱动薄膜晶体管的栅极位置也具有较大的厚度；在对应所述开关薄膜晶体管的栅极位置具有较小的厚度。
  7. 如权利要求6所述的用于AMOLED的薄膜晶体管阵列基板，其中所述绝缘层在所述第二电极图案层与所述第一电极图案层的重叠处的厚度大致等于所述绝缘层在对应所述驱动薄膜晶体管的栅极位置的厚度。
  8. 如权利要求5所述的用于AMOLED的薄膜晶体管阵列基板，其中所述第一电极图案层构成一储存电容的下电极、数个扫描线；所述第二电极图案层构成所述储存电容的上电极、数个数据线；其中所述绝缘层在扫描线与数据线的垂直跨线处也具有较大的厚度。
  9. 如权利要求8所述的用于AMOLED的薄膜晶体管阵列基板，其中所述第一电极图案层还构成所述驱动薄膜晶体管的栅极和所述开关薄膜晶体管的栅极；所述第二电极图案层还构成所述驱动薄膜晶体管的源极和漏极、所述开关薄膜晶体管的源极和漏极。
  10. 如权利要求9所述的用于AMOLED的薄膜晶体管阵列基板，其中所述储存电容的下电极连接所述驱动薄膜晶体管的栅极；所述储存电容的上电极连接所述驱动薄膜晶体管的源极。
  11. 如权利要求5所述的用于AMOLED的薄膜晶体管阵列基板，其中所述绝缘层包括氧化硅层、氮化硅层之一或其组合。
  12. 一种用于AMOLED的薄膜晶体管阵列基板的制造方法，包括以下步骤：
    步骤1、提供一基板；
    步骤2、在所述基板上形成一第一电极图案层、数个驱动薄膜晶体管的栅极及数个开关薄膜晶体管的栅极；
    步骤3、在所述基板上形成一绝缘层，以覆盖所述第一电极图案层、所述驱动薄膜晶体管的栅极和所述开关薄膜晶体管的栅极；
    步骤4、对所述绝缘层进行图案化及局部薄化处理，使得所述绝缘层被图案化并具有不同的厚度；
    步骤5、在所述绝缘层上对应所述开关薄膜晶体管的栅极与驱动薄膜晶体管的栅极的位置形成一半导体层；以及
    步骤6、在所述绝缘层上形成一第二电极图案层、所述开关薄膜晶体管的源极和漏极和驱动薄膜晶体管的源极和漏极，其中所述第二电极图案层与所述第一电极图案层部分重叠，其中所述绝缘层在所述重叠处具有较大的厚度，在非重叠处具有较小的厚度。
  13. 如权利要求12所述的用于AMOLED的薄膜晶体管阵列基板的制造方法，其中所述绝缘层在对应所述驱动薄膜晶体管的栅极位置也具有较大的厚度；在对应所述开关薄膜晶体管的栅极位置具有较小的厚度。
  14. 如权利要求13所述的用于AMOLED的薄膜晶体管阵列基板的制造方法，其中所述第一电极图案层构成一储存电容的下电极、数个扫描线、所述驱动薄膜晶体管的栅极和所述开关薄膜晶体管的栅极；所述第二电极图案层构成所述储存电容的上电极、数个数据线、所述驱动薄膜晶体管的源极和漏极、所述开关薄膜晶体管的源极和漏极；其中所述绝缘层在扫描线与数据线的垂直跨线处也具有较大的厚度。
PCT/CN2016/074505 2016-01-13 2016-02-25 用于amoled的薄膜晶体管阵列基板及其制造方法 Ceased WO2017121010A1 (zh)

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