WO2017107746A1 - Gip电路及其驱动方法和平板显示装置 - Google Patents

Gip电路及其驱动方法和平板显示装置 Download PDF

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Publication number
WO2017107746A1
WO2017107746A1 PCT/CN2016/107829 CN2016107829W WO2017107746A1 WO 2017107746 A1 WO2017107746 A1 WO 2017107746A1 CN 2016107829 W CN2016107829 W CN 2016107829W WO 2017107746 A1 WO2017107746 A1 WO 2017107746A1
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Prior art keywords
clock signal
node
transistor
high level
line
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PCT/CN2016/107829
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English (en)
French (fr)
Inventor
杨楠
朱晖
胡思明
张婷婷
宋艳芹
Original Assignee
昆山工研院新型平板显示技术中心有限公司
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Priority to US15/774,727 priority Critical patent/US10360830B2/en
Priority to KR1020187016743A priority patent/KR102069351B1/ko
Priority to JP2018524225A priority patent/JP6630435B2/ja
Priority to EP16877557.5A priority patent/EP3396657B1/en
Publication of WO2017107746A1 publication Critical patent/WO2017107746A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/03—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays
    • G09G3/035—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays for flexible display surfaces
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
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    • G09G2300/0408—Integration of the drivers onto the display substrate
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display

Definitions

  • the present invention relates to the field of flat panel display technologies, and in particular, to a GIP circuit, a driving method thereof, and a flat panel display device.
  • the flat panel display device has the characteristics of being completely flat, light, thin, and power-saving, and thus has been widely used.
  • GIP Gate in Panel
  • the gate driving circuit includes a plurality of driving units for generating a multi-level GIP signal.
  • FIG. 1 is a partial structural diagram of a prior art flat panel display panel.
  • the conventional flat panel display panel 100 includes a plurality of pixels arranged in a matrix (not shown), a plurality of scanning lines (S1 to Sn), and a GIP circuit 10, and the GIP circuit 10 A plurality of sequentially connected driving units (not shown) for respectively generating and outputting GIP signals are included.
  • the first level GIP signal is supplied to the scanning line of the pixel of the first row
  • the second level GIP signal is supplied to the scanning line of the pixel of the second row
  • the nth stage GIP signal is supplied to the scanning line of the pixel of the nth row.
  • Each pixel of the flat panel display panel 100 is gated according to the GIP signal provided by the scan line, and the normal or non-GIP signal of each level directly affects the display effect of the flat panel display panel.
  • the normal or non-GIP signal of each level directly affects the display effect of the flat panel display panel.
  • the driving unit of the existing GIP circuit 10 generally adopts a 10T3C type circuit structure, which not only has a complicated circuit structure, but also uses a large number of thin film transistors (TFTs), and the GIP signal generated by the driving unit is converted to a high level to When it is low, it cannot be pulled down completely.
  • TFTs thin film transistors
  • FIG. 2 is a simulation diagram of a prior art GIP signal.
  • a certain level of GIP signal is pulled high when the low level is converted to a high level, but is not fully pulled when the high level is converted to a low level, and the GIP signal of the next stage is high.
  • the plane is converted to a low level, it is not completely pulled down. This will cause display ripple problems, which will seriously affect the display effect of the flat panel display device.
  • the object of the present invention is to provide a GIP circuit, a driving method thereof and a flat panel display device, so as to solve the problem that the GIP signal outputted by the GIP circuit in the prior art cannot be completely pulled down when the high level is converted to a low level, and the circuit structure is complicated question.
  • the present invention provides a GIP circuit, the GIP circuit comprising: a plurality of sequentially connected driving units, each driving unit and a driving control line, a first gate line, a second gate line, and a a clock signal line and a second clock signal line are connected;
  • the driving unit includes: first to eighth transistors, a first capacitor and a second capacitor; wherein the first transistor is connected between the driving control line and the first node, and the gate thereof is connected to the first clock signal a second transistor connected between the first clock signal line and the third node, the gate of which is connected to the first node; the third transistor is connected between the second clock signal line and the fourth node, a gate is connected to the third node; the fourth transistor is connected to the second node Between the fourth node and the fourth node, the gate thereof is connected to the second clock signal line; the fifth transistor is connected between the third node and the second gate line, and the gate thereof is connected to the first clock signal line; a sixth transistor is connected between the first gate line and the second node, and a gate thereof is connected to the first node; the seventh transistor is connected between the first gate line and the output end, and the gate is connected to the first a second node; the eighth transistor is connected between the second gate line and the output end, the gate thereof is connected to the first node;
  • the first to eighth transistors are P-type thin film transistors.
  • the first transistor and the fifth transistor are both turned on and off by a first clock signal provided by the first clock signal line, and the fourth transistor is guided. Passing and cutting off a second clock signal provided by the second clock signal line, the on and off of the second transistor and the sixth transistor are both controlled by a potential of the first node, the third transistor Turn-on and turn-off are controlled by the potential of the third node.
  • the turning on and off of the eighth transistor is controlled by a potential of the first node, and the turning on and off of the seventh transistor is a potential of the second node control.
  • the signal provided by the first gate line is a high level
  • the signal provided by the second gate line is a low level
  • the present invention also provides a driving method of a GIP circuit, and the driving method of the GIP circuit includes:
  • the scan period includes a first time period, a second time period, a third time period, a fourth time period, and a fifth time period;
  • the first clock signal provided by the first clock signal line changes from a high level to a low level
  • the second clock signal provided by the second clock signal line is at a high level, which is provided by the driving control line.
  • the control signal is at a high level
  • the first node is changed from a low level to a high level
  • the second node is kept at a high level
  • the seventh transistor and the eighth transistor are turned off, so that the output terminal outputs a low level
  • the first clock signal provided by the first clock signal line is at a high level
  • the second clock signal provided by the second clock signal line is changed from a high level to a low level
  • the control signal provided by the control line is driven. Maintaining a high level, the first node is kept at a high level, and the second node is changed from a high level to a low level, and the seventh transistor is turned on, so that the output terminal outputs a high level;
  • the first clock signal provided by the first clock signal line changes from a high level to a low level, and the second clock signal provided by the second clock signal line is at a high level, driving a control signal provided by the control line Keeping high, pulling the potential of the first node, the second node is kept low, so that the output is kept high;
  • the first clock signal provided by the first clock signal line is at a high level
  • the second clock signal provided by the second clock signal line is changed from a high level to a low level
  • the control signal provided by the control line is driven. From high level to low level, the first node remains high and the second node remains low, causing the output to remain high;
  • the first clock signal provided by the first clock signal line changes from a high level to a low level
  • the second clock signal provided by the second clock signal line is at a high level, driving a control signal provided by the control line Keeping low
  • the first node changes from high level to low level
  • the second node changes from low level to high level, turning on the eighth transistor, so that the output terminal outputs low level.
  • the first gate line, the second time period, the third time period, the fourth time period, and the fifth time period are provided by the first gate line
  • the signal remains high and the signal provided by the second gate line remains low.
  • the present invention also provides a flat panel display device comprising: the GIP circuit as described above.
  • the GIP circuit is disposed in a non-display area of the flat panel display device.
  • the flat panel display device is an organic light emitting display, a liquid crystal display device, a plasma display device, a vacuum fluorescent display device, or a flexible display device.
  • a novel GIP circuit is adopted, which not only has a simple structure, but also generates a GIP signal that can be fully pulled when the high level is converted to a low level. Low, the driving ability is stronger, the problem of displaying ripples can be avoided, and the display effect of the flat panel display device is improved.
  • FIG. 1 is a partial structural schematic view of a prior art flat panel display panel
  • FIG. 3 is a schematic structural diagram of a GIP circuit according to an embodiment of the present invention.
  • FIG. 4 is a timing waveform diagram of a driving method of a GIP circuit according to an embodiment of the present invention.
  • Figure 5 is a simulation diagram of a GIP signal in accordance with an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a GIP circuit according to an embodiment of the present invention.
  • the GIP circuit includes a plurality of sequentially connected driving units 20, each of which has a driving control line IN, a first gate line VGH, a second gate line VGL, and a first clock signal.
  • the driving unit 20 includes: first to eighth transistors M1 to M8, a first capacitor C1 and a second capacitor C2; wherein the first transistor M1 is connected between the driving control line IN and the first node N1, and its gate is connected to the first clock signal line CLK1; the second transistor M2 is connected between the first clock signal line CLK1 and the third node N3, The gate is connected to the first node N1; the third transistor M3 is connected between the second clock signal line CLK1B and the fourth node N4, the gate thereof is connected to the third node N3; the fourth transistor M4 is connected Between the two nodes N2 and the fourth node N4, the gate thereof is connected to the second clock signal line CLK1B; the fifth transistor M5 is connected between the third node N3 and the second gate line VGL, and the gate thereof is connected to a first clock signal line CLK1; the sixth transistor M6 is connected between the first gate line VGH and the second node N2, the
  • the GIP circuit includes a plurality of driving units, and the plurality of driving units are sequentially connected.
  • the output end of the previous driving unit is connected to the input end of the latter driving unit, that is, the output end of the previous driving unit and the latter
  • the drive control line IN of the drive unit is connected.
  • Each of the driving units is also connected to the first gate line VGH, the second gate line VGL, the first clock signal line CLK1, and the second clock signal line CLK1B, respectively.
  • the signal provided by the first gate line VGH is always kept at a high level
  • the signal provided by the second gate line VGL is always kept at a low level.
  • the driving unit 20 is of an 8T2C type structure and includes 8 transistors and 2 capacitors.
  • the seventh transistor M7 and the eighth transistor M8 are connected as a driving tube between the first gate line VGH and the second gate line VGL, and the output end EMOUT is disposed between the seventh transistor M7 and the eighth transistor M8.
  • the first transistor M1 to the sixth transistor M6 each function as a switching transistor.
  • the first to eighth transistors M1 to M8 are all P-type thin film transistors.
  • the first transistor M1 and the fifth transistor M5 are turned on and off by Controlled by the first clock signal provided by the first clock signal line CLK1
  • the on and off of the fourth transistor M4 is controlled by the second clock signal provided by the second clock signal line CLK1B
  • the second transistor M2 the sixth transistor M6 and the eighth
  • the on and off of the transistor M8 are both controlled by the potential of the first node N1
  • the conduction and the off of the third transistor M3 are controlled by the potential of the third node N3
  • the conduction and the cutoff of the seventh transistor M7 are performed by the second node.
  • the potential of N2 is controlled.
  • the driving unit 20 adopts 8 transistors and 2 capacitors. Compared with the prior art, the number of transistors and capacitors is reduced, the structure is simpler, and the GIP signal generated by the driving unit is converted at a high level. When it is low, it can be pulled down completely, the driving ability is stronger, and the driving effect is better.
  • the present invention also provides a driving method of a GIP circuit.
  • the driving method of the GIP circuit includes: the scanning period includes a first time period t1, a second time period t2, a third time period t3, a fourth time period t4, and a fifth time period t5. ;among them,
  • the first clock signal provided by the first clock signal line CLK1 changes from a high level to a low level
  • the second clock signal provided by the second clock signal line CLK1B is at a high level, driving the control line IN
  • the provided control signal is at a high level
  • the first node N1 changes from a low level to a high level
  • the second node N2 remains at a high level, turning off the seventh transistor M7 and the eighth transistor M8, so that the output terminal EMOUT output is low.
  • the first clock signal provided by the first clock signal line CLK1 is at a high level
  • the second clock signal provided by the second clock signal line CLK1B is changed from a high level to a low level to drive the control line IN.
  • the provided control signal is kept at a high level
  • the first node N1 is kept at a high level
  • the second node N2 is changed from a high level to a low level
  • the seventh transistor M7 is turned on, so that the output terminal EMOUT outputs a high level; although FIG. 4
  • the first clock signal provided by the first clock signal line CLK1 is changed from a low level to a high level at the end of the first time period t1.
  • the flat-to-high transition may also occur at the beginning of the second period t2 as long as the first clock signal is made high during the second period t2.
  • the first clock signal provided by the first clock signal line CLK1 changes from a high level to a low level, and the second clock signal provided by the second clock signal line CLK1B is at a high level, driving the control line IN
  • the provided control signal remains high, pulling up the potential of the first node N1, and the second node N2 is held low, so that the output terminal EMOUT remains high; although the second clock signal line CLK1B in the embodiment shown in FIG.
  • the second clock signal is provided to jump from a low level to a high level at the end of the second period t2.
  • the present invention should not be limited thereto, and the low level to high level transition may also occur.
  • the second clock signal may be made to be at a high level during the third time period t3.
  • the first clock signal provided by the first clock signal line CLK1 is at a high level
  • the second clock signal provided by the second clock signal line CLK1B is changed from a high level to a low level to drive the control line IN.
  • the provided control signal changes from a high level to a low level, the first node N1 remains high, and the second node N2 remains low, so that the output terminal EMOUT remains high; although in the embodiment shown in FIG.
  • the first clock signal provided by a clock signal line CLK1 is changed from a low level to a high level at the end of the third time period t3.
  • the low level to the high level The hopping may also occur at the beginning of the fourth time period t4 as long as the first clock signal is made to be at a high level during the fourth time period t4.
  • the first clock signal provided by the first clock signal line CLK1 changes from a high level to a low level
  • the second clock signal provided by the second clock signal line CLK1B is at a high level, driving the control line IN
  • the provided control signal is kept low
  • the first node N1 changes from a high level to a low level
  • the second node N2 changes from a low level to a high level
  • the eighth transistor M8 is turned on, so that the output terminal EMOUT outputs low power. level.
  • the second clock signal provided by the second clock signal line CLK1B in the embodiment shown in FIG. 4 is changed from a low level to a high level at the end of the fourth time period t4, the present invention should not be limited thereto.
  • the low-to-high transition may also occur at the beginning of the fifth period t5 as long as the second clock signal is at a high level during the fifth period t5.
  • the signal provided by the first gate line VGH is one Straight to high level
  • the signal provided by the second gate line VGL is always low.
  • the first transistor M1 and the fifth transistor M5 controlled by the first clock signal are both turned off.
  • the control signal supplied from the driving control line IN is supplied to the first node N1 via the first transistor M1, and the first node N1 is changed from the low level to the high level, so that the sixth transistor M6 and the eighth transistor M8 are both The turn-on is turned off, and the signal supplied from the second gate line VGL cannot be supplied to the output terminal EMOUT via the eighth transistor M8.
  • the sixth transistor M6 Since the sixth transistor M6 is in the on state before, the signal supplied from the first gate line VGH is supplied to the second node N2 via the sixth transistor M6, the second node N2 is at the high level, and the sixth transistor M6 is turned on. After the turn-off, the second node N2 continues to remain at a high level, so the seventh transistor M7 is in an off state, and the signal supplied from the first gate line VGH cannot be supplied to the output terminal EMOUT via the seventh transistor M7.
  • the output EMOUT outputs a low level.
  • the signal provided by the second gate line VGL is supplied to the third node N3 via the fifth transistor M5, the third node N3 is at a low level, and the third transistor M3 controlled by the potential of the third node N3 is cut off. Becomes conductive.
  • the fourth transistor M4 controlled by the second clock signal is turned off by conduction, and the second The second clock signal supplied from the clock signal line CLK1B is supplied to the second node N2 via the third transistor M3 and the fourth transistor M4, and the second node N2 is changed from the high level to the low level, so that the seventh transistor M7 is changed from off to Turning on, the signal supplied from the first gate line VGH is supplied to the output terminal EMOUT via the seventh transistor M7, so the output terminal EMOUT outputs a high level.
  • the first transistor M1 and the fifth transistor M5 controlled by the first clock signal are both turned off.
  • the control signal supplied from the drive control line IN is again supplied to the first node N1 via the first transistor M1, so the first node N1 is at a high level, and thus the sixth transistor M6 and the eighth transistor M8 are both in an off state, the signal supplied from the second gate line VGL cannot be supplied to the output terminal EMOUT via the eighth transistor M8, and the second node N2 continues to remain low.
  • the seventh transistor M7 Since the second node N2 is kept at a low level, the seventh transistor M7 is in an on state, and a signal supplied from the first gate line VGH is supplied to the output terminal EMOUT via the seventh transistor M7. Thus, the output terminal EMOUT continues to output a high level.
  • the signal supplied from the second gate line VGL is again supplied to the third node N3 via the fifth transistor M5, thereby making the third node N3 low, and being controlled by the potential of the third node N3.
  • the transistor M3 is turned on from off.
  • the fourth transistor M4 controlled by the second clock signal is turned off by conduction, and the second The second clock signal provided by the clock signal line CLK1B is supplied to the second node N2 via the third transistor M3 and the fourth transistor M4, and the second node N2 is kept at a low level, so the seventh transistor M7 is in an on state, the first gate The signal supplied from the line VGH is supplied to the output terminal EMOUT via the seventh transistor M7, so the output terminal EMOUT outputs a high level.
  • the first transistor M1 and the fifth transistor M5 controlled by the first clock signal are both turned off.
  • the control signal supplied from the driving control line IN is supplied to the first node N1 via the first transistor M1, and the first node N1 is changed from the high level to the low level, so that the sixth transistor M6 and the eighth transistor M8 are both The turn-off becomes conductive, and the signal supplied from the second gate line VGL is supplied to the output terminal EMOUT via the eighth transistor M8.
  • the output terminal EMOUT outputs a low level.
  • the signal supplied from the first gate line VGH is supplied to the second node N2 via the sixth transistor M6, and the second node N2 is changed from the low level to the high level, so the seventh transistor M7 is in the off state, first The signal supplied from the gate line VGH cannot be supplied to the output terminal EMOUT via the seventh transistor M7.
  • the driving unit 20 when the driving unit 20 outputs a low level, the low level signal provided by the second gate line VGL is supplied to the output terminal EMOUT through the conduction of the eighth transistor M8, and thus is converted to a low level at a high level. Usually can be pulled down completely.
  • FIG. 5 is a simulation diagram of a GIP signal according to an embodiment of the present invention.
  • a certain level of GIP signal is pulled high when the low level is converted to a high level, and can be completely pulled low when the high level is converted to a low level, and the GIP signal of the next stage is converted at a high level. When it is low, it is also pulled down completely.
  • the driving effect obtained by using the GIP circuit and the driving method provided by the embodiment of the invention is better, and the display ripple problem can be avoided, thereby improving the display of the flat panel display device. effect.
  • the present invention also provides a flat panel display device comprising the GIP circuit as described above. Please refer to the above for details, and will not go into details here.
  • the flat panel display device generally includes a display area and a non-display area surrounding the display area, and the GIP circuit is generally disposed in a non-display area of the flat panel display device.
  • the flat panel display device may be a liquid crystal display (LCD) device, a plasma display (PDP) device, a vacuum fluorescent display (VFD) device, an organic light emitting display (OLED) device, a flexible display device, or other types of display devices.
  • LCD liquid crystal display
  • PDP plasma display
  • VFD vacuum fluorescent display
  • OLED organic light emitting display
  • flexible display device or other types of display devices.
  • the specific type is not limited herein.
  • a novel GIP circuit is adopted, which not only has a simple structure, but also generates a GIP signal that can be fully pulled when the high level is converted to a low level. Low, the driving ability is stronger, can avoid the display ripple problem, and improve the display effect of the flat panel display device.

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Abstract

一种GIP电路，GIP电路驱动方法以及使用该GIP电路的平板显示装置，该GIP电路结构简单，其产生的GIP信号在高电平转换为低电平时能够完全拉低，驱动能力更强，能够避免显示波纹问题，提升平板显示装置的显示效果。

Description

GIP电路及其驱动方法和平板显示装置 技术领域
本发明涉及平板显示技术领域，特别涉及一种GIP电路及其驱动方法和平板显示装置。
背景技术
近年来，随着信息技术、无线移动通讯和信息家电的快速发展与应用，人们对电子产品的依赖性与日俱增，更带来各种显示技术及显示装置的蓬勃发展。平板显示装置具有完全平面化、轻、薄、省电等特点，因此得到了广泛的应用。
目前，为了降低平板显示装置的制造成本并藉以实现窄边框的目的，在制造过程中通常采用GIP(Gate in Panel，门面板)技术，直接将栅极驱动电路(即GIP电路)集成于平板显示面板上，所述栅极驱动电路包括多个驱动单元，所述多个驱动单元用于产生多级GIP信号。
请参考图1，其为现有技术的平板显示面板的部分结构示意图。如图1所示，现有的平板显示面板100包括有多个呈矩阵排布的像素(图中未示出)、多条扫描线(S1至Sn)和GIP电路10，所述GIP电路10包括多个依次连接的驱动单元(图中未示出)，所述多个驱动单元用于分别产生并输出GIP信号。其中，第1级GIP信号提供给第1行像素的扫描线，第2级GIP信号提供给第2行像素的扫描线，如此类推，第n级GIP信号提供给第n行像素的扫描线。
所述平板显示面板100的各个像素都是根据扫描线提供的GIP信号进行选通的，各级GIP信号正常与否都会直接影响平板显示面板的显示效果。一旦某一级GIP信号出现异常，就无法选通对应的像素，所述平板显示面 板100就会出现屏体不工作、屏体某一行显示异常或者屏体前一部分图片显示正常而后一部分图片显示异常这些异常情况。
然而，现有的GIP电路10中驱动单元通常采用10T3C型电路结构，不但电路结构复杂，采用的薄膜晶体管(TFT)的数量较多，而且所述驱动单元产生的GIP信号在高电平转换为低电平时不能被完全拉低。
请参考图2，其为现有技术的GIP信号的仿真图。如图2所示，某一级GIP信号在低电平转换为高电平时被拉高，但在高电平转换为低电平时没有完全拉低，而且其下一级的GIP信号在高电平转换为低电平时也没有完全拉低。如此会造成显示波纹问题，严重影响平板显示装置的显示效果。
基此，如何解决现有的GIP电路所输出的GIP信号在高电平转换为低电平时不能被完全拉低，而且电路结构复杂的问题，成了本领域技术人员亟待解决的一个技术问题。
发明内容
本发明的目的在于提供一种GIP电路及其驱动方法和平板显示装置，以解决现有技术中GIP电路所输出的GIP信号在高电平转换为低电平时不能被完全拉低，而且电路结构复杂的问题。
为解决上述问题，本发明提供一种GIP电路，所述GIP电路包括：多个依次连接的驱动单元，每个驱动单元分别与驱动控制线、第一栅极线、第二栅极线、第一时钟信号线以及第二时钟信号线连接；
所述驱动单元包括：第一晶体管至第八晶体管、第一电容以及第二电容；其中，所述第一晶体管连接在驱动控制线与第一节点之间，其栅极连接到第一时钟信号线；所述第二晶体管连接在第一时钟信号线与第三节点之间，其栅极连接到第一节点；所述第三晶体管连接在第二时钟信号线与第四节点之间，其栅极连接到第三节点；所述第四晶体管连接在第二节点 与第四节点之间，其栅极连接到第二时钟信号线；所述第五晶体管连接在第三节点与第二栅极线之间，其栅极连接到第一时钟信号线；所述第六晶体管连接在第一栅极线与第二节点之间，其栅极连接到第一节点；所述第七晶体管连接在第一栅极线与输出端之间，其栅极连接到第二节点；所述第八晶体管连接在第二栅极线与输出端之间，其栅极连接到第一节点；所述第一电容连接在第三节点与第四节点之间；所述第二电容连接在第一节点与输出端之间。
可选的，在所述的GIP电路中，所述第一晶体管至第八晶体管均为P型薄膜晶体管。
可选的，在所述的GIP电路中，所述第一晶体管和第五晶体管的导通和截止均由所述第一时钟信号线提供的第一时钟信号控制，所述第四晶体管的导通和截止由所述第二时钟信号线提供的第二时钟信号控制，所述第二晶体管和第六晶体管的导通和截止均由所述第一节点的电位控制，所述第三晶体管的导通和截止由所述第三节点的电位控制。
可选的，在所述的GIP电路中，所述第八晶体管的导通和截止由所述第一节点的电位控制，所述第七晶体管的导通和截止由所述第二节点的电位控制。
可选的，在所述的GIP电路中，所述第一栅极线提供的信号为高电平，第二栅极线提供的信号为低电平。
相应的，本发明还提供了一种GIP电路的驱动方法，所述GIP电路的驱动方法包括：
扫描周期包括第一时间段、第二时间段、第三时间段、第四时间段以及第五时间段；其中，
在第一时间段，第一时钟信号线提供的第一时钟信号由高电平变为低电平，第二时钟信号线提供的第二时钟信号为高电平，驱动控制线提供的 控制信号为高电平，第一节点由低电平变为高电平，第二节点保持为高电平，关闭第七晶体管和第八晶体管，使得输出端输出低电平；
在第二时间段，第一时钟信号线提供的第一时钟信号为高电平，第二时钟信号线提供的第二时钟信号由高电平变为低电平，驱动控制线提供的控制信号保持高电平，第一节点保持高电平，第二节点由高电平变为低电平，打开第七晶体管，使得输出端输出高电平；
在第三时间段，第一时钟信号线提供的第一时钟信号由高电平变为低电平，第二时钟信号线提供的第二时钟信号为高电平，驱动控制线提供的控制信号保持高电平，拉高第一节点的电位，第二节点保持低电平，使得输出端保持高电平；
在第四时间段，第一时钟信号线提供的第一时钟信号为高电平，第二时钟信号线提供的第二时钟信号由高电平变为低电平，驱动控制线提供的控制信号由高电平变为低电平，第一节点保持高电平，第二节点保持低电平，使得输出端保持高电平；以及
在第五时间段，第一时钟信号线提供的第一时钟信号由高电平变为低电平，第二时钟信号线提供的第二时钟信号为高电平，驱动控制线提供的控制信号保持低电平，第一节点由高电平变为低电平，第二节点由低电平变为高电平，打开第八晶体管，使得输出端输出低电平。
可选的，在所述的GIP电路的驱动方法中，在所述第一时间段、第二时间段、第三时间段、第四时间段以及第五时间段，第一栅极线提供的信号保持高电平，第二栅极线提供的信号保持低电平。
相应的，本发明还提供了一种平板显示装置，所述平板显示装置包括：如上所述的GIP电路。
可选的，在所述的平板显示装置中，所述GIP电路设置于所述平板显示装置的非显示区域。
可选的，在所述的平板显示装置中，所述平板显示装置为有机发光显示器、液晶显示装置、等离子体显示装置、真空荧光显示装置、或柔性显示装置。
综上所述，在本发明提供的GIP电路及其驱动方法和平板显示装置中，采用新型的GIP电路，不但结构简单，而且其产生的GIP信号在高电平转换为低电平时能够完全拉低，驱动能力更强，能够避免显示波纹的问题，提升平板显示装置的显示效果。
附图说明
图1是现有技术的平板显示面板的部分结构示意图；
图2是现有技术的GIP信号的仿真图；
图3是本发明实施例的GIP电路的结构示意图；
图4是本发明实施例的GIP电路的驱动方法的时序波形图；
图5是本发明实施例的GIP信号的仿真图。
具体实施方式
以下结合附图和具体实施例对本发明提出一种GIP电路及其驱动方法和平板显示装置作进一步详细说明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
请参考图3，其为本发明实施例的GIP电路的结构示意图。如图3所示，所述GIP电路包括多个依次连接的驱动单元20，每个驱动单元20分别与驱动控制线IN、第一栅极线VGH、第二栅极线VGL、第一时钟信号线CLK1以及第二时钟信号线CLK1B连接；所述驱动单元20包括：第一晶体管M1至第八晶体管M8、第一电容C1以及第二电容C2；其中，所述第一晶体管 M1连接在驱动控制线IN与第一节点N1之间，其栅极连接到第一时钟信号线CLK1；所述第二晶体管M2连接在第一时钟信号线CLK1与第三节点N3之间，其栅极连接到第一节点N1；所述第三晶体管M3连接在第二时钟信号线CLK1B与第四节点N4之间，其栅极连接到第三节点N3；所述第四晶体管M4连接在第二节点N2与第四节点N4之间，其栅极连接到第二时钟信号线CLK1B；所述第五晶体管M5连接在第三节点N3与第二栅极线VGL之间，其栅极连接到第一时钟信号线CLK1；所述第六晶体管M6连接在第一栅极线VGH与第二节点N2之间，其栅极连接到第一节点N1；所述第七晶体管M7连接在第一栅极线VGH与输出端EMOUT之间，其栅极连接到第二节点N2；所述第八晶体管M8连接在第二栅极线VGL与输出端EMOUT之间，其栅极连接到第一节点N1；所述第一电容C1连接在第三节点N3与第四节点N4之间；所述第二电容C2连接在第一节点N1与输出端EMOUT之间。
具体的，所述GIP电路包括多个驱动单元，所述多个驱动单元依次连接，前一个驱动单元的输出端与后一个驱动单元的输入端连接，即前一个驱动单元的输出端与后一个驱动单元的驱动控制线IN连接。每个驱动单元还分别与第一栅极线VGH、第二栅极线VGL、第一时钟信号线CLK1以及第二时钟信号线CLK1B连接。其中，所述第一栅极线VGH提供的信号一直保持为高电平，第二栅极线VGL提供的信号一直保持为低电平。
所述驱动单元20为8T2C型结构，包括8个晶体管和2个电容。其中，第七晶体管M7和第八晶体管M8作为驱动管连接在第一栅极线VGH与第二栅极线VGL之间，输出端EMOUT设置于所述第七晶体管M7和第八晶体管M8之间，第一晶体管M1至第六晶体管M6均作为开关管。
本实施例中，第一晶体管M1至第八晶体管M8均为P型薄膜晶体管。
请继续参考图3，第一晶体管M1和第五晶体管M5的导通和截止均由 第一时钟信号线CLK1提供的第一时钟信号控制，第四晶体管M4的导通和截止由第二时钟信号线CLK1B提供的第二时钟信号控制，第二晶体管M2、第六晶体管M6和第八晶体管M8的导通和截止均由第一节点N1的电位高低控制，第三晶体管M3的导通和截止由第三节点N3的电位高低控制，第七晶体管M7的导通和截止由第二节点N2的电位高低控制。
在所述GIP电路中驱动单元20采用8个晶体管和2个电容器，相对于现有技术，减少了晶体管和电容器的数量，结构更加简单，而且所述驱动单元产生的GIP信号在高电平转换为低电平时能够完全拉低，驱动能力更强，驱动效果更好。
相应的，本发明还提供一种GIP电路的驱动方法。请结合参考图3和图4，所述GIP电路的驱动方法包括：扫描周期包括第一时间段t1、第二时间段t2、第三时间段t3、第四时间段t4以及第五时间段t5；其中，
在第一时间段t1，第一时钟信号线CLK1提供的第一时钟信号由高电平变为低电平，第二时钟信号线CLK1B提供的第二时钟信号为高电平，驱动控制线IN提供的控制信号为高电平，第一节点N1由低电平变为高电平，第二节点N2保持为高电平，关闭第七晶体管M7和第八晶体管M8，使得输出端EMOUT输出低电平；
在第二时间段t2，第一时钟信号线CLK1提供的第一时钟信号为高电平，第二时钟信号线CLK1B提供的第二时钟信号由高电平变为低电平，驱动控制线IN提供的控制信号保持高电平，第一节点N1保持高电平，第二节点N2由高电平变为低电平，打开第七晶体管M7，使得输出端EMOUT输出高电平；虽然图4所示实施例中第一时钟信号线CLK1提供的第一时钟信号是在第一时间段t1的末尾由低电平跳变为高电平，然而本发明不应以此为限，该低电平到高电平的跳变也可发生在第二时间段t2的起始时刻，只要使得第一时钟信号在第二时间段t2内为高电平即可。
在第三时间段t3，第一时钟信号线CLK1提供的第一时钟信号由高电平变为低电平，第二时钟信号线CLK1B提供的第二时钟信号为高电平，驱动控制线IN提供的控制信号保持高电平，拉高第一节点N1的电位，第二节点N2保持低电平，使得输出端EMOUT保持高电平；虽然图4所示实施例中第二时钟信号线CLK1B提供的第二时钟信号是在第二时间段t2的末尾由低电平跳变为高电平，然而本发明不应以此为限，该低电平到高电平的跳变也可发生在第三时间段t3的起始时刻，只要使得第二时钟信号在第三时间段t3内为高电平即可。
在第四时间段t4，第一时钟信号线CLK1提供的第一时钟信号为高电平，第二时钟信号线CLK1B提供的第二时钟信号由高电平变为低电平，驱动控制线IN提供的控制信号由高电平变为低电平，第一节点N1保持高电平，第二节点N2保持低电平，使得输出端EMOUT保持高电平；虽然图4所示实施例中第一时钟信号线CLK1提供的第一时钟信号是在第三时间段t3的末尾由低电平跳变为高电平，然而本发明不应以此为限，该低电平到高电平的跳变也可发生在第四时间段t4的起始时刻，只要使得第一时钟信号在第四时间段t4内为高电平即可。
在第五时间段t5，第一时钟信号线CLK1提供的第一时钟信号由高电平变为低电平，第二时钟信号线CLK1B提供的第二时钟信号为高电平，驱动控制线IN提供的控制信号保持低电平，第一节点N1由高电平变为低电平，第二节点N2由低电平变为高电平，打开第八晶体管M8，使得输出端EMOUT输出低电平。虽然图4所示实施例中第二时钟信号线CLK1B提供的第二时钟信号是在第四时间段t4的末尾由低电平跳变为高电平，然而本发明不应以此为限，该低电平到高电平的跳变也可发生在第五时间段t5的起始时刻，只要使得第二时钟信号在第五时间段t5内为高电平即可。
具体的，在本发明的驱动方法中，所述第一栅极线VGH提供的信号一 直为高电平，第二栅极线VGL提供的信号一直为低电平。
在第一时间段t1，由于第一时钟信号线CLK1提供的第一时钟信号由高电平变为低电平，受第一时钟信号控制的第一晶体管M1和第五晶体管M5均由截止变为导通，驱动控制线IN提供的控制信号经由第一晶体管M1提供至第一节点N1，第一节点N1由低电平变为高电平，因此第六晶体管M6和第八晶体管M8均由导通变为截止，第二栅极线VGL提供的信号无法经由第八晶体管M8提供至输出端EMOUT。
由于此前第六晶体管M6处于导通状态，第一栅极线VGH提供的信号经由第六晶体管M6提供至第二节点N2，第二节点N2处于高电平，第六晶体管M6由导通变为截止后，第二节点N2继续保持高电平，因此第七晶体管M7处于截止状态，第一栅极线VGH提供的信号无法经由第七晶体管M7提供至输出端EMOUT。
在此阶段，输出端EMOUT输出低电平。与此同时，第二栅极线VGL提供的信号经由第五晶体管M5提供至第三节点N3，第三节点N3为低电平，受第三节点N3的电位高低控制的第三晶体管M3由截止变为导通。
在第二时间段t2，由于第二时钟信号线CLK1B提供的第二时钟信号由高电平变为低电平，受第二时钟信号控制的第四晶体管M4由截止变为导通，第二时钟信号线CLK1B提供的第二时钟信号经由第三晶体管M3和第四晶体管M4提供至第二节点N2，第二节点N2由高电平变为低电平，因此第七晶体管M7由截止变为导通，第一栅极线VGH提供的信号经由第七晶体管M7提供至输出端EMOUT，因此输出端EMOUT输出高电平。
在第三时间段t3，由于第一时钟信号线CLK1提供的第一时钟信号由高电平变为低电平，受第一时钟信号控制的第一晶体管M1和第五晶体管M5均由截止变为导通，驱动控制线IN提供的控制信号再次经由第一晶体管M1提供至第一节点N1，因此第一节点N1为高电平，因此第六晶体管 M6和第八晶体管M8均处于截止状态，第二栅极线VGL提供的信号无法经由第八晶体管M8提供至输出端EMOUT，第二节点N2继续保持低电平。
由于第二节点N2保持低电平，因此第七晶体管M7处于导通状态，第一栅极线VGH提供的信号经由第七晶体管M7提供至输出端EMOUT。由此，输出端EMOUT继续输出高电平。
与此同时，第二栅极线VGL提供的信号再次经由第五晶体管M5提供至第三节点N3，由此使得第三节点N3为低电平，受第三节点N3的电位高低控制的第三晶体管M3由截止变为导通。
在第四时间段t4，由于第二时钟信号线CLK1B提供的第二时钟信号由高电平变为低电平，受第二时钟信号控制的第四晶体管M4由截止变为导通，第二时钟信号线CLK1B提供的第二时钟信号经由第三晶体管M3和第四晶体管M4提供至第二节点N2，第二节点N2保持低电平，因此第七晶体管M7处于导通状态，第一栅极线VGH提供的信号经由第七晶体管M7提供至输出端EMOUT，因此输出端EMOUT输出高电平。
在第五时间段t5，由于第一时钟信号线CLK1提供的第一时钟信号由高电平变为低电平，受第一时钟信号控制的第一晶体管M1和第五晶体管M5均由截止变为导通，驱动控制线IN提供的控制信号经由第一晶体管M1提供至第一节点N1，第一节点N1由高电平变为低电平，因此第六晶体管M6和第八晶体管M8均由截止变为导通，第二栅极线VGL提供的信号经由第八晶体管M8提供至输出端EMOUT。由此，输出端EMOUT输出低电平。
与此同时，第一栅极线VGH提供的信号经由第六晶体管M6提供至第二节点N2，第二节点N2由低电平变为高电平，因此第七晶体管M7处于截止状态，第一栅极线VGH提供的信号无法经由第七晶体管M7提供至输出端EMOUT。
由此可见，当驱动单元20输出低电平时，是通过第八晶体管M8的导通使第二栅极线VGL提供的低电平信号提供至输出端EMOUT，因此在高电平转换为低电平时能够完全拉低。
请参考图5，其为本发明实施例的GIP信号的仿真图。如图5所示，某一级GIP信号在低电平转换为高电平时被拉高，在高电平转换为低电平时能够完全拉低，其下一级的GIP信号在高电平转换为低电平时也完全拉低。
由此可见，与传统的GIP电路及其驱动方法相比，采用本发明实施例提供的GIP电路及其驱动方法所获得的驱动效果更好，能够避免显示波纹问题，从而提升平板显示装置的显示效果。
相应的，本发明还提供一种平板显示装置，所述平板显示装置包括如上所述的GIP电路。具体请参考上文，此处不再赘述。
所述平板显示装置通常包括显示区域和围绕于所述显示区域的非显示区域，所述GIP电路一般设置于所述平板显示装置的非显示区域。
其中，所述平板显示装置可以是液晶显示(LCD)装置、等离子体显示(PDP)装置、真空荧光显示(VFD)装置、有机发光显示(OLED)装置、柔性显示装置或者其他类型的显示装置，具体类型在此不作限制。
综上，在本发明实施例提供的GIP电路及其驱动方法和平板显示装置中，采用新型的GIP电路，不但结构简单，而且其产生的GIP信号在高电平转换为低电平时能够完全拉低，驱动能力更强，能够避免显示波纹问题，提升平板显示装置的显示效果。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (10)

  1. 一种GIP电路，其特征在于，包括：多个依次连接的驱动单元，每个驱动单元分别与驱动控制线、第一栅极线、第二栅极线、第一时钟信号线以及第二时钟信号线连接；
    所述驱动单元包括：第一晶体管至第八晶体管、第一电容以及第二电容；其中，所述第一晶体管连接在驱动控制线与第一节点之间，其栅极连接到第一时钟信号线；所述第二晶体管连接在第一时钟信号线与第三节点之间，其栅极连接到第一节点；所述第三晶体管连接在第二时钟信号线与第四节点之间，其栅极连接到第三节点；所述第四晶体管连接在第二节点与第四节点之间，其栅极连接到第二时钟信号线；所述第五晶体管连接在第三节点与第二栅极线之间，其栅极连接到第一时钟信号线；所述第六晶体管连接在第一栅极线与第二节点之间，其栅极连接到第一节点；所述第七晶体管连接在第一栅极线与输出端之间，其栅极连接到第二节点；所述第八晶体管连接在第二栅极线与输出端之间，其栅极连接到第一节点；所述第一电容连接在第三节点与第四节点之间；所述第二电容连接在第一节点与输出端之间。
  2. 如权利要求1所述的GIP电路，其特征在于，所述第一晶体管至第八晶体管均为P型薄膜晶体管。
  3. 如权利要求1所述的GIP电路，其特征在于，所述第一晶体管和第五晶体管的导通和截止均由所述第一时钟信号线提供的第一时钟信号控制，所述第四晶体管的导通和截止由所述第二时钟信号线提供的第二时钟信号控制，所述第二晶体管和第六晶体管的导通和截止均由所述第一节点的电位控制，所述第三晶体管的导通和截止由所述第三节点的电位控制。
  4. 如权利要求1所述的GIP电路，其特征在于，所述第八晶体管的导 通和截止由所述第一节点的电位控制，所述第七晶体管的导通和截止由所述第二节点的电位控制。
  5. 如权利要求1所述的GIP电路，其特征在于，所述第一栅极线提供的信号为高电平，所述第二栅极线提供的信号为低电平。
  6. 一种如权利要求1至5中任一项所述的GIP电路的驱动方法，其特征在于，包括：
    扫描周期包括第一时间段、第二时间段、第三时间段、第四时间段以及第五时间段；其中，
    在第一时间段，第一时钟信号线提供的第一时钟信号由高电平变为低电平，第二时钟信号线提供的第二时钟信号为高电平，驱动控制线提供的控制信号为高电平，第一节点由低电平变为高电平，第二节点保持为高电平，关闭第七晶体管和第八晶体管，使得输出端输出低电平；
    在第二时间段，第一时钟信号线提供的第一时钟信号为高电平，第二时钟信号线提供的第二时钟信号由高电平变为低电平，驱动控制线提供的控制信号保持高电平，第一节点保持高电平，第二节点由高电平变为低电平，打开第七晶体管，使得输出端输出高电平；
    在第三时间段，第一时钟信号线提供的第一时钟信号由高电平变为低电平，第二时钟信号线提供的第二时钟信号为高电平，驱动控制线提供的控制信号保持高电平，拉高第一节点的电位，第二节点保持低电平，使得输出端保持高电平；
    在第四时间段，第一时钟信号线提供的第一时钟信号为高电平，第二时钟信号线提供的第二时钟信号由高电平变为低电平，驱动控制线提供的控制信号由高电平变为低电平，第一节点保持高电平，第二节点保持低电平，使得输出端保持高电平；以及
    在第五时间段，第一时钟信号线提供的第一时钟信号由高电平变为低 电平，第二时钟信号线提供的第二时钟信号为高电平，驱动控制线提供的控制信号保持低电平，第一节点由高电平变为低电平，第二节点由低电平变为高电平，打开第八晶体管，使得输出端输出低电平。
  7. 如权利要求6所述的GIP电路的驱动方法，其特征在于，在所述第一时间段、第二时间段、第三时间段、第四时间段以及第五时间段，第一栅极线提供的信号保持高电平，第二栅极线提供的信号保持低电平。
  8. 一种平板显示装置，其特征在于，包括：如权利要求1至5中任一项所述的GIP电路。
  9. 如权利要求8所述的平板显示装置，其特征在于，所述GIP电路设置于所述平板显示装置的非显示区域。
  10. 如权利要求8所述的平板显示装置，其特征在于，所述平板显示装置为有机发光显示器、液晶显示装置、等离子体显示装置、真空荧光显示装置、或柔性显示装置。
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US10360830B2 (en) 2019-07-23
JP2019504335A (ja) 2019-02-14
US20180322820A1 (en) 2018-11-08
TWI618043B (zh) 2018-03-11
KR20180084899A (ko) 2018-07-25
KR102069351B1 (ko) 2020-01-22
JP6630435B2 (ja) 2020-01-15
EP3396657B1 (en) 2020-04-22
TW201734993A (zh) 2017-10-01

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