WO2017101302A1 - 一种电流舵数模转换器及电流舵数模转化方法、存储介质 - Google Patents

一种电流舵数模转换器及电流舵数模转化方法、存储介质 Download PDF

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WO2017101302A1
WO2017101302A1 PCT/CN2016/088184 CN2016088184W WO2017101302A1 WO 2017101302 A1 WO2017101302 A1 WO 2017101302A1 CN 2016088184 W CN2016088184 W CN 2016088184W WO 2017101302 A1 WO2017101302 A1 WO 2017101302A1
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current
data
digital
gate
current steering
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PCT/CN2016/088184
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English (en)
French (fr)
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易律凡
赵春河
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深圳市中兴微电子技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0614—Continuously compensating for, or preventing, undesired influence of physical parameters of harmonic distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters

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  • the present invention relates to integrated circuit technology, and in particular, to a current steering digital-to-analog converter, a current steering digital-to-analog conversion method, and a storage medium.
  • the CS DAC has a simple structure consisting of a binary current source or a current source matrix, plus a binary-controlled current switch or a thermometer code controller that is converted by a decoder.
  • the current from the current source can be switched through a switch to a directly grounded resistor (high speed application), as shown in Figure 1, or to a feedback resistor through a buffer (low speed application), as shown in Figure 2.
  • the output uses a differential structure to reduce the interference of common mode noise on the output analog signal.
  • a unit current source array is usually used instead of the binary current source.
  • FIG. 2 shows the structure of a conventionally basic current source cell.
  • Each current source unit includes a positive current composed of a P-type CMOS (Positive Channel Metal Oxide Semiconductor) MP and an MPC, and a NMOS (Negative Channel Metal Oxide Semiconductor) MN and MNC. Negative current.
  • the input digital data of the DAC is converted into current control signals DC and DCB through a decoder under the control of the clock, which controls the opening and closing of the current source.
  • the resulting differential current signals I op and I on are then applied to a current-to-voltage converter (I2V) formed by a buffer's feedback resistor (or directly grounded resistor) to output the corresponding converted differential voltage.
  • I2V current-to-voltage converter
  • Figure 3 shows the associated input and output waveforms of the current source unit of Figure 2.
  • Clk is the input clock of the DAC
  • data is the input digital data
  • DAC current is the corresponding output current I op or I on .
  • the output current of the DAC Due to the finite speed of the circuit, the output current of the DAC has finite rise and fall edges t r and t f .
  • the output current has a rising edge and a falling edge in one clock cycle; when inputting a series of consecutive logic '1's (such as three in Figure 3) The output current also has a rising edge at the beginning of this consecutive '1' and a falling edge at the end, as shown in Figure 3.
  • the energy of the final output signal of the DAC is related to the integration of current with time (i.e., the area contained in the DAC current waveform of Figure 3, such as A 0 , ..., A 3 , etc.).
  • the A0 in Fig. 3 corresponds to 1- ⁇ Ar+ ⁇ Af, where ⁇ Ar is the area lost due to the limited rising edge, and ⁇ Af is due to the decrease.
  • ⁇ Ar ⁇ ⁇ Af and because of changes in temperature and process, it is difficult for the two to be equal.
  • the harmonic distortion of the signal caused by this phenomenon is called inter-symbol interference (ISI).
  • FIG. 4 A common method of eliminating the above-described harmonic distortion of the DAC output signal due to the limited rising/falling edge of the output current is shown in FIG. No longer as the current shown in Figure 3 is to be turned on during the entire clock cycle, the current in Figure 4 only needs to be turned on for part of a clock cycle, such as half a clock cycle as shown. If it is still assumed that an ideal current source corresponds to the input data '1', the current output is 1 in one clock cycle, then the area A 0 , ..., A 3 covered by each output current in Figure 4 is 1/ 2- ⁇ A r + ⁇ A f . This eliminates the correlation error caused by the difference in the amplitude of the input signal, that is, harmonic distortion.
  • a switching method such as that in Fig. 4 in which the current is only required to be turned on for a part of one clock cycle is called a return-to-zero (RZ). In contrast, an implementation like the one in Figure 3 is called non-return-to-zero (NRZ).
  • the RZ switching method of FIG. 4 eliminates the harmonic distortion caused by the above ISI, since it is turned on only for a part of one clock cycle, the efficiency of the circuit portion is lost. Second, since the current opening time is shortened, it The requirement for the speed of the current unit circuit, especially the subsequent I2V buffer, will increase as the switching time is shortened, ie the power consumption of the circuit will increase.
  • an embodiment of the present invention provides a current steering digital-to-analog converter, a current steering digital-to-analog conversion method, and a storage medium.
  • a digital input circuit configured to receive an input of digital data and to transmit the digital data to a row decoder and a column decoder;
  • a shuffling circuit coupled to both the row decoder and the column decoder, configured to generate a switch sequence, and transmit the switch sequence to the row decoder and the column decoder;
  • thermometer code is sent to the current source matrix
  • thermometer code configured to control the opening and closing of the current according to the received thermometer code, and output current data
  • a current to voltage converter coupled to the current source matrix is configured to convert the current data to voltage data.
  • the current steering digital-to-analog converter further includes: a clock selection circuit configured to control a frequency of the clock.
  • the current source matrix is composed of a plurality of current source units; the current source unit includes: a PMOS circuit, an NMOS circuit, a pair of common source common drain switches MPSW1 and MPSW2, and another pair of common sources Very common drain switch MPSW3 and MPSW4; a common source Drain switches MNSW1 and MNSW2, another pair of common source common drain switches MNSW3 and MNSW4.
  • the gate of MPSW1 is connected to DC, the gate of MPSW2 is connected to DCB, and the drain is connected to I OP ;
  • the gate of MPSW3 is connected to DBC, the gate of MPSW4 is connected to DBCB, and the drain is connected to I ON , MPSW1, MPSW2 and
  • the sources of MPSW3 and MPSW4 are connected to a common PMOS bias current source MP and MPC;
  • the gate of MNSW1 is connected to DC, the gate of MNSW2 is connected to DCB, the drain is connected to I ON ;
  • the gate of MNSW3 is connected to DBC, the gate of MNSW4 is connected to DBCB, and the drain is connected to I OP ;
  • I OP and I ON are connected to both ends of the current-to-voltage converter I2V;
  • the switch control signals DC, DCB, DBC, and DBCB are generated by two pieces of digital data.
  • the switch control signals DC, DCB, DBC, and DBCB are respectively:
  • shuffle and shuffleb are the switch sequences, and data and datab are the digital data.
  • each pair of switches is turned on every half clock cycle under the selection of the switch sequence
  • each pair of switches is turned on in half the current clock cycle with the selection of the switch sequence.
  • the current-voltage converter is a feedback resistor formed by using a buffer, or a resistor directly grounded.
  • thermometer codes Combining the switch sequence, converting row data and column data of the digital data into corresponding thermometer codes
  • thermometer code controlling the opening and closing of the current, and outputting the current data
  • the current data is converted to voltage data.
  • the storage medium provided by the embodiment of the present invention stores a computer program configured to execute the current steering digital-to-analog conversion method.
  • the embodiment of the invention utilizes the CS DAC current source unit and the shuffling circuit to realize a current steering DAC that is equally opportunistic, ensuring that the current output of the N consecutive logic '1' and the single logic '1' corresponding to the input digital data is absolutely accurate.
  • the N-fold relationship solves the harmonic distortion problem caused by the rising and falling edges of the non-return-to-zero code DAC, while avoiding the introduction of additional power consumption introduced by the return-to-zero code DAC.
  • the technical solution of the embodiment of the present invention proposes an equal opportunity perturbation (EP, Equal Perturbation) current switch control mode, and the output signal harmonic distortion problem caused by the above ISI of the CS DAC is obtained by increasing the clock frequency and collecting data by double edges.
  • EP Equal Perturbation
  • the two-way current switch alternately implements the NRZ switching mode.
  • This method has the characteristics of limited rising and falling edges of the switching current, so that each logic '1' in the digital data has the same number of rising and falling edges, thus eliminating the harmonic distortion caused by ISI.
  • the embodiment of the present invention does not cause an additional requirement on the power consumption of the circuit because the disturbance of the output signal is small in one clock cycle.
  • Figure 1 is a basic structural diagram of a current steering DAC
  • 2 is a current source unit diagram of a conventional current source matrix
  • Figure 3 is a schematic diagram of a conventional CS DAC input clock and data waveform, and output current waveform and current error;
  • FIG. 4 is a schematic diagram of a conventional improved current output waveform and an ISI cancellation error
  • FIG. 5 is a schematic structural diagram of a current steering digital-to-analog converter according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a current source unit of a current source matrix according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of an output current waveform and an ISI cancellation error using a current switching mode of approximately NRZ according to an embodiment of the present invention
  • Figure 8 is a schematic diagram showing the output current waveform and the elimination of ISI error in the manner in which the two logic switches are turned on and off in turn for the data of the continuous logic '1' according to the embodiment of the present invention
  • FIG. 9 is a schematic flow chart of a current steering digital-to-analog conversion method according to an embodiment of the present invention.
  • the current steering digital-to-analog converter of the embodiment of the present invention is a novel equal-opchanical disturbance CS DAC, which generates two RZ current waveforms in one data cycle by two current switches with a clock frequency twice that of digital data. The results are summed and combined into an approximate NRZ output waveform.
  • a shuffle circuit is introduced in the switch logic control module, and the current output of each logic '1' in the corresponding input data data is introduced into a rising edge by turning on and off the two current switches in turn. With a falling edge, the elimination of harmonic distortion caused by ISI is achieved.
  • FIG. 5 is a schematic structural diagram of a current steering digital-to-analog converter according to an embodiment of the present invention. As shown in FIG. 5, the current steering digital-to-analog converter includes:
  • the digital input circuit 51 is configured to receive an input of digital data, and send the digital data to the row decoder 52 and the column decoder 53;
  • the shuffling circuit 54 connected to the row decoder 52 and the column decoder 53 is configured to generate a switch sequence, and send the switch sequence to the row decoder 52 and the column decoder 53;
  • a row decoder 52 and a column decoder 53 respectively connected to the digital input circuit 51 are configured to convert the row data and the column data of the digital data into corresponding ones in combination with the switch sequence Thermometer code; and the converted thermometer code is sent to the current source matrix 55;
  • the current source matrix 55 is configured to control the opening and closing of the current according to the received thermometer code, and output current data
  • a current to voltage converter (I2V) 56 coupled to the current source matrix 55 is configured to convert the current data into voltage data.
  • the current steering digital-to-analog converter further includes a clock selection circuit 57 configured to control the frequency of the clock.
  • the current source matrix 55 is composed of a plurality of current source units; the current source unit includes: a P-type metal insulator semiconductor PMOS circuit, an N-type metal insulator semiconductor NMOS circuit, and a pair of common source common drain switches MPSW1 and MPSW2 The other pair of common source common drain switches MPSW3 and MPSW4; a pair of common source common drain switches MNSW1 and MNSW2, another pair of common source common drain switches MNSW3 and MNSW4.
  • the gate of MPSW1 is connected to DC, the gate of MPSW2 is connected to DCB, the drain is connected to I OP ;
  • the gate of MPSW3 is connected to DBC, the gate of MPSW4 is connected to DBCB, the drain is connected to I ON , the source of MPSW1, MPSW2 and MPSW3, MPSW4 Connected to a common PMOS bias current source MP and MPC;
  • the gate of MNSW1 is connected to DC, the gate of MNSW2 is connected to DCB, the drain is connected to I ON ;
  • the gate of MNSW3 is connected to DBC, the gate of MNSW4 is connected to DBCB, and the drain is connected to I OP ;
  • I OP and I ON are connected to both ends of the current-to-voltage converter I2V;
  • I OP and I ON are connected to the two ends of I2V. Specifically, I OP and I ON are connected to the two inputs of the analog BUF, simulating the crossover resistance and capacitance of the two input and output terminals of the BUF, and functioning as current and voltage. The function of the I2V, the output of the I2V outputs an analog voltage.
  • the switch control signals DC, DCB, DBC, and DBCB are generated by two pieces of digital data.
  • the switch control signals DC, DCB, DBC, and DBCB are respectively:
  • shuffle and shuffleb are the switch sequences, and data and datab are the digital data.
  • each pair of switches is turned on every half clock cycle under the selection of the switch sequence
  • each pair of switches is turned on in half the current clock cycle with the selection of the switch sequence.
  • the current-to-voltage converter 56 is a feedback resistor formed using a buffer or a resistor directly grounded.
  • the novel current steering digital-to-analog conversion method of the embodiment of the present invention adds a shuffle circuit to the current switch control link, and The selection adds a clock selection circuit.
  • the matrix unit circuit of the power source matrix of the present invention is as shown in FIG.
  • the shuffling circuit produces an orderly interleaved current source switching sequence that is provided to the row decoder and column decoder.
  • the thermometer code after row decoding and column decoding is passed to the current source matrix.
  • the output of the current source matrix is connected to I2V to achieve current-to-voltage conversion.
  • FIG. 6 is a circuit structure diagram of a current source unit according to an embodiment of the present invention, which is divided into a PMOS portion and an NMOS portion, and the switch is superposed by the outputs of two DACs generated by four sets of signals DC, DCB, DBC, and DBCB.
  • MPSW1 and MPSW2 are a pair of common source common drain switches. The gate of MPSW1 is connected to DC, the gate of MPSW2 is connected to DCB, and the drain is connected to I OP .
  • MPSW3 and MPSW4 are another pair of common source common drain switches.
  • the gate of MPSW3 is connected to DBC
  • the gate of MPSW4 is connected to DBCB
  • the drain is connected to I ON
  • the sources of MPSW1, MPSW2, MPSW3, and MPSW4 are connected to a common PMOS bias current source MP and MPC.
  • MNSW1 and MNSW2 are a pair of common source common drain switches.
  • the gate of MNSW1 is connected to DC
  • the gate of MNSW2 is connected to DCB
  • the drain is connected to I ON .
  • MNSW3 and MNSW4 are another pair of common source common drain switches.
  • the gate of MNSW3 is connected to DBC
  • the gate of MNSW4 is connected to DBCB
  • the drain is connected to I OP .
  • I2V can be a feedback resistor through a buffer or a directly grounded resistor.
  • the I2V differential output is the output of the DAC, OUTP and OUTN, which completes the conversion from digital to analog.
  • I OP and I ON are connected to the two ends of I2V. Specifically, I OP and I ON are connected to the two inputs of the analog BUF, simulating the crossover resistance and capacitance of the two input and output terminals of the BUF, and functioning as current and voltage.
  • the function of the I2V, the output of the I2V outputs an analog voltage.
  • the switch control signal DC shuffle ⁇ data
  • DCB shuffleb ⁇ data
  • DBC shuffle ⁇ datab
  • DBCB shuffleb ⁇ datab. So in each data data cycle, the positive and negative currents are determined by the logical value of data which flows to I op and which flows to I on . Which one of each pair of current control switches MPSW1 and MPSW2, MPSW3 and MPSW4, MNSW1 and MNSW2, MNSW3 and MNSW4 flows is determined by the logical value of shuffle.
  • each of the above switches is turned on every half clock cycle under the selection of shuffle; also when the frequency of the divided control clock CLK is half of the data rate, Each pair of switches is also turned on in the current half-clock cycle with the choice of shuffle. Therefore, the shuffle module acts like a shuffle, so that the two switches of each pair of current switches are alternately turned on and off.
  • Figure 7 shows the output current waveform and current error of the current source base unit of Figure 6 when the control clock CLK frequency is the same as the data rate. It can be seen that under the selection of the shuffle module, for example, the switch MPSW1 is turned on first in the first half clock cycle, and the switch MPSW2 is in the off state at this time; in the second half clock cycle, the switch MPSW1 is turned off, and the switch MPSW2 is turned on; During the clock cycle, the switch MPSW1 is turned on again in the first half of the clock cycle, and the switch MPSW2 is turned off.
  • the structure of the equal opportunity perturbation CS DAC proposed by the present invention is two embodiments of the invention of a combination of a clock selection circuit, a shuffle circuit, and a symmetric current source matrix, thereby also diffrable new Embodiments are also encompassed and encompassed by the present invention.
  • FIG. 9 is a schematic flow chart of a current steering digital-to-analog conversion method according to an embodiment of the present invention.
  • the current steering digital-to-analog conversion method in the present example is applied to the current steering digital-to-analog converter. As shown in FIG. 9, the method includes the following. step:
  • Step 901 Receive an input of digital data, and generate a switch sequence.
  • the digital input circuit receives an input of digital data and transmits the digital data to a row decoder and a column decoder.
  • a shuffling circuit coupled to both the row decoder and the column decoder generates a switch sequence and transmits the switch sequence to the row decoder and column decoder.
  • Step 902 Combine the switch sequence to convert row data and column data of the digital data into corresponding thermometer codes.
  • thermometer codes respectively converting row data and column data of the digital data into corresponding thermometer codes; and transmitting the converted thermometer codes to the current source matrix.
  • Step 903 Control the current on and off according to the received thermometer code, and output current data.
  • the current source matrix controls the opening and closing of the current according to the thermometer code received, and outputs current data.
  • Step 904 Convert the current data into voltage data.
  • a current to voltage converter coupled to the current source matrix converts the current data into voltage data.
  • the current source matrix is composed of a plurality of current source units; the current source unit includes: a PMOS circuit, an NMOS circuit, a pair of common source common drain switches MPSW1 and MPSW2, and another pair of common sources. Drain switches MPSW3 and MPSW4; a pair of common source common drain switches MNSW1 and MNSW2, and another pair of common source common drain switches MNSW3 and MNSW4.
  • the gate of MPSW1 is connected to DC, the gate of MPSW2 is connected to DCB, the drain is connected to I OP ;
  • the gate of MPSW3 is connected to DBC, the gate of MPSW4 is connected to DBCB, the drain is connected to I ON , the source of MPSW1, MPSW2 and MPSW3, MPSW4 Connected to a common PMOS bias current source MP and MPC;
  • the gate of MNSW1 is connected to DC, the gate of MNSW2 is connected to DCB, the drain is connected to I ON ;
  • the gate of MNSW3 is connected to DBC, the gate of MNSW4 is connected to DBCB, and the drain is connected to I OP ;
  • the source of MNSW1, MNSW2 and MNSW3, MNSW4 Connected to a common NMOS bias current source MN and MNC; I OP and I ON are connected to both ends of I2V;
  • the switch control signals DC, DCB, DBC, and DBCB are generated by two pieces of digital data.
  • I OP and I ON are connected to both ends of the I2V. Specifically, I OP and I ON are connected to the two inputs of the analog BUF, simulating the crossover resistance and capacitance of the two input and output terminals of the BUF. To the action of the current voltage regulator (I2V), the output of the I2V outputs an analog voltage.
  • I2V current voltage regulator
  • the switch control signals DC, DCB, DBC, and DBCB are respectively:
  • shuffle and shuffleb are the switch sequences, and data and datab are the digital data.
  • each pair of switches is turned on every half clock cycle under the selection of the switch sequence
  • each pair of switches is turned on in half the current clock cycle with the selection of the switch sequence.
  • the embodiment of the invention further describes a storage medium in which a computer program is stored, the computer program being configured to perform the current steering digital-to-analog conversion method of the foregoing embodiments.
  • the disclosed method and smart device may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed.
  • the coupling, or direct coupling, or communication connection of the components shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, and may be electrical, mechanical or other forms. of.
  • the units described above as separate components may or may not be physically separated.
  • the components displayed as the unit may be, or may not be, physical units, that is, may be located in one place, or may be distributed to multiple network units; some or all of the units may be selected according to actual needs to implement the solution of the embodiment. purpose.
  • each functional unit in each embodiment of the present invention may be integrated into one second processing unit, or each unit may be separately used as one unit, or two or more units may be integrated into one unit;
  • the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the invention collects data by double edges by increasing the clock frequency to realize two RZ current switching modes in one data cycle; or does not increase the clock frequency, and alternately realizes the NRZ switching mode by two current switches.
  • This method has the characteristics of limited rising and falling edges of the switching current, so that each logic '1' in the digital data has the same number of rising and falling edges, thus eliminating the harmonic distortion caused by ISI.
  • the present invention does not cause an additional requirement on the power consumption of the circuit because the disturbance of the output signal is small in one clock cycle.

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Abstract

一种电流舵数模转换器及电流舵数模转化方法、存储介质，所述电流舵数模转换器包括：数字输入电路(51)，配置为接收数字数据的输入，并将所述数字数据发送给行译码器(52)和列译码器(53)；与所述行译码器(52)和列译码器(53)均连接的洗牌电路(54)，配置为生成开关序列，并将所述开关序列发送给所述行译码器(52)和列译码器(53)；与所述数字输入电路(51)分别连接的行译码器(52)和列译码器(53)，用于结合所述开关序列，将所述数字数据的行数据和列数据分别转换为相应的温度计码；并将转换的温度计码发送给电流源矩阵(55)；电流源矩阵(55)，配置为根据接收到所述温度计码，控制电流的开与关，输出电流数据；与所述电流源矩阵(55)连接的电流电压转换器(56)，配置为将所述电流数据转换为电压数据。

Description

一种电流舵数模转换器及电流舵数模转化方法、存储介质 技术领域
本发明涉及集成电路技术，尤其涉及一种电流舵数模转换器及电流舵数模转化方法、存储介质。
背景技术
通信技术的发展，对数模转换器(DAC，Digital to Analog Converters)的速度与精度提出了更高的要求，高清视频、高质量通话，都需要高速DAC。电流舵驱动数模转换器(CS DAC，Current Steering Digital to Analog Converters)使这一矛盾得到了有效的缓解。不同于其他结构的DAC，CS DAC结构简单，由二进制电流源或者电流源矩阵，再加上二进制数控制的电流开关或者经过译码器转成的温度计码控制器构成。电流源的电流可以通过开关切换到直接接地的电阻上(高速应用)，如图1，或接到通过一个缓冲器的反馈电阻上(低速应用)，如图2所示。在实际应用中，输出采用差分结构以减小共模噪声对输出模拟信号的干扰。为了提高电流源的匹配特性，通常采用单位电流源阵列代替二进制电流源。
图2显示了传统上基本的电流源单元的结构(current cell)。每一个电流源单元包括一个由P型金属绝缘体半导体(PMOS，Positive Channel Metal Oxide Semiconductor)MP与MPC组成的正电流，以及由N型金属绝缘体半导体(NMOS，Negative Channel Metal Oxide Semiconductor)MN与MNC组成的负电流。DAC的输入数字数据在时钟的控制下通过一解码器转变成电流控制信号DC与DCB，控制着这一路电流源的打开与关闭。由此产生的差分电流信号Iop与Ion然后被加到通过一个缓冲器的反馈电阻(或直接接地的电阻)构成的电流电压转换器(I2V)上，从而输出相应的被转化的差 分电压OUTP与OUTN。
图3显示了图2中的电流源单元的有关输入与输出波形。clk为DAC的输入时钟，data为输入数字数据，DAC current为相应的输出电流Iop或Ion。
由于电路的有限速度，DAC的输出电流有着有限的上升与下降沿tr与tf。当输入数据data是一单个的逻辑‘1’时，输出电流在一个时钟周期有一个上升沿与一个下降沿；当输入时一串连续的逻辑‘1’(例如图3中的三个)时，输出电流也会在这连续的‘1’的起始有一个上升沿，在结尾有一个下降沿，如图3所示。
DAC最终的输出信号的能量与电流对时间的积分(即图3DAC current波形下所包含的面积例如A0，……，A3等)有关。假设一个理想的电流源对应输入数据‘1’的电流输出面积为1的话，图3中A0对应着1-ΔAr+ΔAf，其中ΔAr为由于有限的上升沿而失去的面积，而ΔAf为由于下降沿而增加的面积。通常来说，ΔAr≠ΔAf，并且由于随着温度与工艺的变化，两者很难会作到相等。图3中A1＝1-ΔAr，A2＝1，A3＝1+ΔAf。所以它们之间的比值A1:A0，A2:A0，A3:A0，就不再是1:1的关系了。也就是说，输出信号的能量会产生与输入信号幅度相关的误差，从而引起输出信号的谐波失真。此种现象引起的信号的谐波失真被称为符号间干扰(ISI)。
一种常见的消除上述由于输出电流有限的上升/下降沿而引起的DAC输出信号的谐波失真的方法如图4所示。不再如电流图3中所示电流在要在整个时钟周期内要开通，图4中的电流只需在一个时钟周期的部分时间内开通，例如图中所示的半个时钟周期。如果仍假设一个理想的电流源对应输入数据‘1’的电流输出在一个时钟周期内面积为1，那图4中每一个输出电流所覆盖的面积A0，……,A3都为1/2-ΔAr+ΔAf。这就消除了因输入信号幅度不同而引起的相关误差，即谐波失真。像图4中这种电流只需在一个时钟周期的部分时间内开通的开关方式被称为归零式(RZ)。与之相对 的，像图3中的实现方法被称为不归零式(NRZ)。
图4的RZ开关方式虽消除了上面ISI引起的谐波失真，但因其只在一个时钟周期的部分时间电流开通，所以会丧失电路部分的效率；其次，因电流的开通时间缩短，所以它对电流单元电路，特别是之后的I2V的缓冲器的速度的要求会随开关时间的缩短而增加，即电路的功耗会上升。
发明内容
为解决上述技术问题，本发明实施例提供了一种电流舵数模转换器及电流舵数模转化方法、存储介质。
本发明实施例提供的电流舵数模转换器，包括：
数字输入电路，配置为接收数字数据的输入，并将所述数字数据发送给行译码器和列译码器；
与所述行译码器和列译码器均连接的洗牌电路，配置为生成开关序列，并将所述开关序列发送给所述行译码器和列译码器；
与所述数字输入电路分别连接的行译码器和列译码器，配置为结合所述开关序列，将所述数字数据的行数据和列数据分别转换为相应的温度计码；并将转换的温度计码发送给电流源矩阵；
电流源矩阵，配置为根据接收到所述温度计码，控制电流的开与关，输出电流数据；
与所述电流源矩阵连接的电流电压转换器，配置为将所述电流数据转换为电压数据。
本发明实施例中，所述电流舵数模转换器还包括：时钟选择电路，配置为控制时钟的频率。
本发明实施例中，所述电流源矩阵由多个电流源单元组成；所述电流源单元包括：PMOS电路、NMOS电路、一对共源极共漏极开关MPSW1和MPSW2、另一对共源极共漏极开关MPSW3和MPSW4；一对共源极共 漏极开关MNSW1和MNSW2、另一对共源极共漏极开关MNSW3和MNSW4。
本发明实施例中，MPSW1的栅极接DC，MPSW2的栅极接DCB，漏极接IOP；MPSW3的栅极接DBC，MPSW4的栅极接DBCB，漏极接ION，MPSW1、MPSW2和MPSW3、MPSW4的源极接在共同的PMOS偏置电流源MP和MPC上；
MNSW1的栅极接DC，MNSW2的栅极接DCB，漏极接ION；MNSW3的栅极接DBC，MNSW4的栅极接DBCB，漏极接IOP；MNSW1、MNSW2和MNSW3、MNSW4的源极接在共同的NMOS偏置电流源MN和MNC上；IOP和ION接到电流电压转换器I2V的两端；
其中，开关控制信号DC、DCB、DBC、DBCB由2个数字数据的生成。
本发明实施例中，所述开关控制信号DC、DCB、DBC、DBCB分别为：
DC＝shuffle×data；
DCB＝shuffleb×data；
DBC＝shuffle×datab；
DBCB＝shuffleb×datab；
其中，shuffle和shuffleb为所述开关序列，data和datab为所述数字数据。
本发明实施例中，当时钟频率与数字数据速率相同时，每对开关在所述开关序列的选择下每半个时钟周期轮流开通；
当时钟频率为数字数据速率一半时，每对开关在所述开关序列的选择下以当前时钟的一半周期轮流开通。
本发明实施例中，所述电流电压转换器为利用缓冲器形成的反馈电阻，或者为直接接地的电阻。
本发明实施例提供的电流舵数模转化方法包括：
接收数字数据的输入，以及生成开关序列；
结合所述开关序列，将所述数字数据的行数据和列数据分别转换为相应的温度计码；
根据接收到所述温度计码，控制电流的开与关，输出电流数据；
将所述电流数据转换为电压数据。
本发明实施例提供的存储介质中存储有计算机程序，所述计算机程序配置为执行所述的电流舵数模转化方法。
本发明实施例利用CS DAC电流源单元和洗牌电路，实现了等机会扰动的电流舵DAC，保证对应输入数字数据N个连续逻辑‘1’和单个逻辑‘1’的情形的电流输出绝对准确的N倍关系，从而解决了非归零码DAC的因为上升和下降沿而产生的谐波失真问题，同时又避免引入像归零码DAC引入的额外的功耗。本发明实施例的技术方案提出了等机会扰动的(EP，Equal Perturbation)电流开关控制方式，针对CS DAC的上述ISI引起的输出信号谐波失真问题，通过提高时钟频率，以双沿采集数据，以实现一个数据周期内两次的RZ电流开关方式；或者不提高时钟频率，以两路电流开关交替实现NRZ的开关方式。该方式针对开关电流具有有限上升、下降沿的特点，让数字数据中每一个逻辑‘1’都有相同数目的上升、下降沿，从而消除了ISI引起的谐波失真。另一方面，本发明实施例因在一个时钟周期内对输出信号的扰动小，所以也不会引起对电路功耗的额外要求。
附图说明
图1是电流舵DAC的基本结构图；
图2是传统的电流源矩阵的电流源单元图；
图3是传统CS DAC输入时钟与数据波形，以及输出电流波形与电流误差的示意图；
图4是传统的改进型的电流输出波形与消除ISI误差的示意图；
图5是本发明实施例的电流舵数模转器的结构组成示意图；
图6是本发明实施例的电流源矩阵的电流源单元示意图；
图7是本发明实施例的用近似NRZ的电流开关方式的输出电流波形与消除ISI误差的示意图；
图8是本发明实施例的用对连续的逻辑‘1’的数据引入两路电流开关轮流的开启与关闭的方式的输出电流波形与消除ISI误差的示意图；
图9是本发明实施例的电流舵数模转化方法的流程示意图。
具体实施方式
为了能够更加详尽地了解本发明实施例的特点与技术内容，下面结合附图对本发明实施例的实现进行详细阐述，所附附图仅供参考说明之用，并非用来限定本发明实施例。
本发明实施例的电流舵数模转换器是一种新型的等机会扰动CS DAC，用两倍于数字数据的时钟频率通过两路电流开关在一个数据周期内产生两个RZ电流波形，取其结果相加，拼合成一个近似NRZ输出波形。或者，在开关逻辑控制模块引入一洗牌(shuffle)电路，通过对两路电流开关轮流的开启与关闭，从而在对应输入数据data中的每一个逻辑‘1’的电流输出都引入一个上升沿与一个下降沿，实现对ISI引起的谐波失真的消除。
图5为本发明实施例的电流舵数模转换器的结构组成示意图，如图5所示，所述电流舵数模转换器包括：
数字输入电路51，配置为接收数字数据的输入，并将所述数字数据发送给行译码器52和列译码器53；
与所述行译码器52和列译码器53均连接的洗牌电路54，配置为生成开关序列，并将所述开关序列发送给所述行译码器52和列译码器53；
与所述数字输入电路51分别连接的行译码器52和列译码器53，配置为结合所述开关序列，将所述数字数据的行数据和列数据分别转换为相应 的温度计码；并将转换的温度计码发送给电流源矩阵55；
电流源矩阵55，配置为根据接收到所述温度计码，控制电流的开与关，输出电流数据；
与所述电流源矩阵55连接的电流电压转换器(I2V)56，配置为将所述电流数据转换为电压数据。
所述电流舵数模转换器还包括：时钟选择电路57，配置为控制时钟的频率。
所述电流源矩阵55由多个电流源单元组成；所述电流源单元包括：P型金属绝缘体半导体PMOS电路、N型金属绝缘体半导体NMOS电路、一对共源极共漏极开关MPSW1和MPSW2、另一对共源极共漏极开关MPSW3和MPSW4；一对共源极共漏极开关MNSW1和MNSW2、另一对共源极共漏极开关MNSW3和MNSW4。
MPSW1的栅极接DC，MPSW2的栅极接DCB，漏极接IOP；MPSW3的栅极接DBC，MPSW4的栅极接DBCB，漏极接ION，MPSW1、MPSW2和MPSW3、MPSW4的源极接在共同的PMOS偏置电流源MP和MPC上；
MNSW1的栅极接DC，MNSW2的栅极接DCB，漏极接ION；MNSW3的栅极接DBC，MNSW4的栅极接DBCB，漏极接IOP；MNSW1、MNSW2和MNSW3、MNSW4的源极接在共同的NMOS偏置电流源MN和MNC上；IOP和ION接到电流电压转换器I2V的两端；
IOP和ION接到I2V的两端，具体地，IOP和ION接到模拟BUF的两个输入端，模拟BUF的两个输入端和输出端跨界电阻和电容，起到电流电压化器(I2V)的作用，I2V的输出端输出模拟电压。
其中，开关控制信号DC、DCB、DBC、DBCB由2个数字数据的生成。
所述开关控制信号DC、DCB、DBC、DBCB分别为：
DC＝shuffle×data；
DCB＝shuffleb×data；
DBC＝shuffle×datab；
DBCB＝shuffleb×datab；
其中，shuffle和shuffleb为所述开关序列，data和datab为所述数字数据。
当时钟频率与数字数据速率相同时，每对开关在所述开关序列的选择下每半个时钟周期轮流开通；
当时钟频率为数字数据速率一半时，每对开关在所述开关序列的选择下以当前时钟的一半周期轮流开通。
所述电流电压转换器56为利用缓冲器形成的反馈电阻，或者为直接接地的电阻。
本发明实施例中，参照图5，与传统结构图1相比，本发明实施例的新型的电流舵数模转化方法在电流开关控制链路上增加了一洗牌(shuffle)电路，并且可选择的增加一时钟选择电路。与此相对应，本发明的电源源矩阵的矩阵单元电路如图6所示。洗牌电路产生依次交错的采集电流源开关次序，提供给行译码器和列译码器。经过行译码和列译码过后的温度计码传给电流源矩阵。电流源矩阵的输出端连接I2V实现电流对电压的转换。
如图6，是本发明实施例的电流源单元的电路结构图，分为PMOS部分和NMOS部分，开关由四组信号DC、DCB、DBC、DBCB产生的2个DAC的输出叠加而成。MPSW1和MPSW2是一对共源极共漏极开关。MPSW1的栅极接DC，MPSW2的栅极接DCB，漏极接IOP；MPSW3和MPSW4是另一对共源极共漏极开关。MPSW3的栅极接DBC，MPSW4的栅极接DBCB，漏极接ION，MPSW1、MPSW2和MPSW3、MPSW4的源极接在共同的PMOS偏置电流源MP和MPC上。MNSW1和MNSW2是一 对共源极共漏极开关。MNSW1的栅极接DC，MNSW2的栅极接DCB，漏极接ION；MNSW3和MNSW4是另一对共源极共漏极开关。MNSW3的栅极接DBC，MNSW4的栅极接DBCB，漏极接IOP。MNSW1、MNSW2和MNSW3、MNSW4的源极接在共同的NMOS偏置电流源MN和MNC上。IOP和ION接到I2V的两端。I2V可以是通过一个缓冲器的反馈电阻，也可以是直接接地的电阻。I2V差分输出就是DAC的输出OUTP和OUTN，完成从数字到模拟的转换。IOP和ION接到I2V的两端，具体地，IOP和ION接到模拟BUF的两个输入端，模拟BUF的两个输入端和输出端跨界电阻和电容，起到电流电压化器(I2V)的作用，I2V的输出端输出模拟电压。
在图6的单元线路中，开关控制信号DC＝shuffle×data，DCB＝shuffleb×data，DBC＝shuffle×datab，DBCB＝shuffleb×datab。所以在每一个数据data周期，正负电流由data的逻辑值决定哪个流向Iop，哪个流向Ion。而究竟是流经每对电流控制开关MPSW1和MPSW2、MPSW3和MPSW4、MNSW1和MNSW2、MNSW3和MNSW4的哪一个则由shuffle的逻辑值决定。当被分频的控制时钟CLK频率与data速率相同时，上述每对开关会在shuffle的选择下每半个时钟周期轮流开通；同样当被分频的控制时钟CLK频率为data速率一半时，上述每对开关也会在shuffle的选择下以现在的每半个时钟周期轮流开通。所以shuffle模块就像洗牌的作用一样使得每对电流开关的两个开关不停的循环交替开、关。
图7显示了当控制时钟CLK频率与数据的速率相同时图6的电流源基本单元的输出电流波形与电流误差。可以看到，在shuffle模块的选择下，比如开关MPSW1在上半个时钟周期先打开，而此时开关MPSW2则处于关闭状态；在下半个时钟周期，开关MPSW1关闭，而开关MPSW2打开；下个时钟周期，开关MPSW1在上半个时钟周期又打开，开关MPSW2则关闭。由于每对开关在每个数据周期内的一次开、关交替，每个电流源在一个数 据周期内的覆盖面积(Ai+A’i，i＝0,……,3)均为1-2×ΔAr+2×ΔAf。所以不论data中的数据格式是什么，所有对应‘1’的电流输出都是相等的，即消除了ISI引起的谐波失真。由于在每对开关中间交替时上升沿引起的电流丢失与下降沿引起的电流添加可以部分抵消，所以对电路的扰动较小，对电路功耗也没有明显额外需求。
图8是控制时钟CLK频率为数据的速率一半时的情形。同上述分析相似，在shuffle模块的选择下，每对电流控制开关也是经每半个时钟周期(即一个数据周期)交替的开、关。由图8可看出，每个电流源在一个数据周期内的覆盖面积(Ai+A’i，i＝0,……,3)均为1-ΔAr+ΔAf，同样消除了由于ISI引起的谐波失真。并且此方法对电路引起的最大扰动与图2中传统的方法相同，所以不增加对功耗的额外需求。
应该理解的是，本发明提出的等机会扰动CS DAC的结构，是时钟选择电路、洗牌电路(shuffle)、对称电流源矩阵的结合的发明之两种实施方式，由此也能衍射新的实施方式也是本发明所包括和涵盖的。
图9为本发明实施例的电流舵数模转化方法的流程示意图，本示例中的电流舵数模转化方法应用于上述电流舵数模转换器中，如图9所示，所述方法包括以下步骤：
步骤901：接收数字数据的输入，以及生成开关序列。
具体地，数字输入电路接收数字数据的输入，并将所述数字数据发送给行译码器和列译码器。
与所述行译码器和列译码器均连接的洗牌电路生成开关序列，并将所述开关序列发送给所述行译码器和列译码器。
步骤902：结合所述开关序列，将所述数字数据的行数据和列数据分别转换为相应的温度计码。
与所述数字输入电路分别连接的行译码器和列译码器结合所述开关序 列，将所述数字数据的行数据和列数据分别转换为相应的温度计码；并将转换的温度计码发送给电流源矩阵。
步骤903：根据接收到所述温度计码，控制电流的开与关，输出电流数据。
电流源矩阵根据接收到所述温度计码，控制电流的开与关，输出电流数据。
步骤904：将所述电流数据转换为电压数据。
与所述电流源矩阵连接的电流电压转换器将所述电流数据转换为电压数据。
上述方案中，所述电流源矩阵由多个电流源单元组成；所述电流源单元包括：PMOS电路、NMOS电路、一对共源极共漏极开关MPSW1和MPSW2、另一对共源极共漏极开关MPSW3和MPSW4；一对共源极共漏极开关MNSW1和MNSW2、另一对共源极共漏极开关MNSW3和MNSW4。
MPSW1的栅极接DC，MPSW2的栅极接DCB，漏极接IOP；MPSW3的栅极接DBC，MPSW4的栅极接DBCB，漏极接ION，MPSW1、MPSW2和MPSW3、MPSW4的源极接在共同的PMOS偏置电流源MP和MPC上；
MNSW1的栅极接DC，MNSW2的栅极接DCB，漏极接ION；MNSW3的栅极接DBC，MNSW4的栅极接DBCB，漏极接IOP；MNSW1、MNSW2和MNSW3、MNSW4的源极接在共同的NMOS偏置电流源MN和MNC上；IOP和ION接到I2V的两端；
其中，开关控制信号DC、DCB、DBC、DBCB由2个数字数据的生成。
具体地，IOP和ION接到I2V的两端，具体地，IOP和ION接到模拟BUF的两个输入端，模拟BUF的两个输入端和输出端跨界电阻和电容，起到电流电压化器(I2V)的作用，I2V的输出端输出模拟电压。
所述开关控制信号DC、DCB、DBC、DBCB分别为：
DC＝shuffle×data；
DCB＝shuffleb×data；
DBC＝shuffle×datab；
DBCB＝shuffleb×datab；
其中，shuffle和shuffleb为所述开关序列，data和datab为所述数字数据。
当时钟频率与数字数据速率相同时，每对开关在所述开关序列的选择下每半个时钟周期轮流开通；
当时钟频率为数字数据速率一半时，每对开关在所述开关序列的选择下以当前时钟的一半周期轮流开通。
本领域技术人员应当理解，图9所示的电流舵数模转化方法可参照前述电流舵数模转换器的相关描述而理解。
本发明实施例还记载了一种存储介质，所述存储介质中存储有计算机程序，所述计算机程序配置为执行前述各实施例的电流舵数模转化方法。
本发明实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。
在本发明所提供的几个实施例中，应该理解到，所揭露的方法和智能设备，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的， 作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本发明各实施例中的各功能单元可以全部集成在一个第二处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。
工业实用性
本发明通过提高时钟频率，以双沿采集数据，以实现一个数据周期内两次的RZ电流开关方式；或者不提高时钟频率，以两路电流开关交替实现NRZ的开关方式。该方式针对开关电流具有有限上升、下降沿的特点，让数字数据中每一个逻辑‘1’都有相同数目的上升、下降沿，从而消除了ISI引起的谐波失真。另一方面，本发明因在一个时钟周期内对输出信号的扰动小，所以也不会引起对电路功耗的额外要求。

Claims (9)

  1. 一种电流舵数模转换器，包括：
    数字输入电路，配置为接收数字数据的输入，并将所述数字数据发送给行译码器和列译码器；
    与所述行译码器和列译码器均连接的洗牌电路，配置为生成开关序列，并将所述开关序列发送给所述行译码器和列译码器；
    与所述数字输入电路分别连接的行译码器和列译码器，配置为结合所述开关序列，将所述数字数据的行数据和列数据分别转换为相应的温度计码；并将转换的温度计码发送给电流源矩阵；
    电流源矩阵，配置为接收所述温度计码，根据所述温度计码，控制电流的开与关，输出电流数据；
    与所述电流源矩阵连接的电流电压转换器，配置为将所述电流数据转换为电压数据。
  2. 根据权利要求1所述的电流舵数模转换器，其中，所述电流舵数模转换器还包括：时钟选择电路，配置为控制时钟的频率。
  3. 根据权利要求1所述的电流舵数模转换器，其中，所述电流源矩阵由多个电流源单元组成；所述电流源单元包括：P型金属绝缘体半导体PMOS电路、N型金属绝缘体半导体NMOS电路、一对共源极共漏极开关MPSW1和MPSW2、另一对共源极共漏极开关MPSW3和MPSW4；一对共源极共漏极开关MNSW1和MNSW2、另一对共源极共漏极开关MNSW3和MNSW4。
  4. 根据权利要求3所述的电流舵数模转换器，其中，
    MPSW1的栅极接DC，MPSW2的栅极接DCB，漏极接IOP；MPSW3的栅极接DBC，MPSW4的栅极接DBCB，漏极接ION，MPSW1、MPSW2和MPSW3、MPSW4的源极接在共同的PMOS偏置电流源MP和MPC上；
    MNSW1的栅极接DC，MNSW2的栅极接DCB，漏极接ION；MNSW3的栅极接DBC，MNSW4的栅极接DBCB，漏极接IOP；MNSW1、MNSW2和MNSW3、MNSW4的源极接在共同的NMOS偏置电流源MN和MNC上；IOP和ION接到电流电压转换器I2V的两端；
    其中，开关控制信号DC、DCB、DBC、DBCB由两个数字数据的生成。
  5. 根据权利要求4所述的电流舵数模转换器，其中，所述开关控制信号DC、DCB、DBC、DBCB分别为：
    DC＝shuffle×data；
    DCB＝shuffleb×data；
    DBC＝shuffle×datab；
    DBCB＝shuffleb×datab；
    其中，shuffle和shuffleb为所述开关序列，data和datab为所述数字数据。
  6. 根据权利要求5所述的电流舵数模转换器，其中，
    当时钟频率与数字数据速率相同时，每对开关在所述开关序列的选择下每半个时钟周期轮流开通；
    当时钟频率为数字数据速率一半时，每对开关在所述开关序列的选择下以当前时钟的一半周期轮流开通。
  7. 根据权利要求1所述的电流舵数模转换器，其中，所述电流电压转换器为利用缓冲器形成的反馈电阻，或者为直接接地的电阻。
  8. 一种电流舵数模转化方法，包括：
    接收数字数据的输入，以及生成开关序列；
    结合所述开关序列，将所述数字数据的行数据和列数据分别转换为相应的温度计码；
    根据接收到所述温度计码，控制电流的开与关，输出电流数据；
    将所述电流数据转换为电压数据。
  9. 一种存储介质，所述存储介质中存储有计算机程序，所述计算机程序配置为执行权利要求8所述的电流舵数模转化方法。
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