WO2017101205A1 - 阵列基板的esd检测方法 - Google Patents

阵列基板的esd检测方法 Download PDF

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Publication number
WO2017101205A1
WO2017101205A1 PCT/CN2016/072776 CN2016072776W WO2017101205A1 WO 2017101205 A1 WO2017101205 A1 WO 2017101205A1 CN 2016072776 W CN2016072776 W CN 2016072776W WO 2017101205 A1 WO2017101205 A1 WO 2017101205A1
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Prior art keywords
array substrate
metal layer
test site
esd
wire
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English (en)
French (fr)
Inventor
李亚锋
彭香艺
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/912,924 priority Critical patent/US10126343B2/en
Publication of WO2017101205A1 publication Critical patent/WO2017101205A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/001—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/08—Locating faults in cables, transmission lines, or networks
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an ESD detection method for an array substrate.
  • Liquid crystal display has many advantages such as thin body, power saving, no radiation, etc., and is widely used, such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptops. Screen, etc.
  • liquid crystal display devices which include a casing, a liquid crystal panel disposed in the casing, and a backlight module disposed in the casing.
  • the structure of the conventional liquid crystal panel is composed of a color filter substrate, a thin film transistor array substrate (TFT Array Substrate), and a liquid crystal layer (Liquid Crystal Layer) disposed between the two substrates.
  • TFT Array Substrate thin film transistor array substrate
  • Liquid Crystal Layer Liquid Crystal Layer
  • LTPS Low Temperature Poly-silicon
  • a-Si amorphous silicon
  • ESD is one of the most common process failures in liquid crystal displays.
  • ESD occurs, ESD-related lines are melted by a momentary high current. After cooling, the metals that should be disconnected are connected together, thus exacerbating the damage caused by ESD. Therefore, ESD detection is extremely important and very necessary.
  • Current ESD testing can only be found by looking for ESD lesions under the microscope, which is time consuming and costly.
  • the present invention provides an ESD detection method for an array substrate, comprising the following steps:
  • Step 1 providing an array substrate to be subjected to ESD detection, wherein the array substrate is provided with a first metal layer and a second metal layer, and the first metal layer is connected to the first test site on the surface of the array substrate through the first wire
  • the second metal layer is connected to the second test site on the surface of the array substrate through the second wire;
  • Step 2 providing a resistance detecting device, and measuring, by the resistance detecting device, a resistance value between the first test site and the second test site;
  • the resistance value between the first test site and the second test site is positive infinity, no ESD occurs between the first metal layer and the second metal layer; if the first test site is The resistance value between the second test sites is within a measurable range, and ESD occurs between the first metal layer and the second metal layer; thereby, according to the measured first test site and the second test site The resistance value between them detects the position where ESD occurs on the array substrate.
  • the first metal layer and the second metal layer on the array substrate are located in different layers.
  • An insulating layer is disposed between the first metal layer and the second metal layer.
  • the first metal layer on the array substrate is located in the same layer as the second metal layer.
  • the array substrate is a low temperature polysilicon thin film transistor array substrate.
  • the first metal layer and the second metal layer are a combination of one or more of molybdenum, aluminum, and copper.
  • the material of the insulating layer is silicon nitride, silicon oxide, or a combination of the two.
  • the first wire and the second wire are all metal wires, and the first test site and the second test site are metal blocks.
  • the material of the first wire and the second wire is copper or aluminum.
  • the material of the first test site and the second test site is copper or aluminum.
  • the invention also provides an ESD detection method for an array substrate, comprising the following steps:
  • Step 1 providing an array substrate to be subjected to ESD detection, wherein the array substrate is provided with a first metal layer and a second metal layer, and the first metal layer is connected to the first test site on the surface of the array substrate through the first wire
  • the second metal layer is connected to the second test site on the surface of the array substrate through the second wire;
  • Step 2 providing a resistance detecting device, and measuring, by the resistance detecting device, a resistance value between the first test site and the second test site;
  • the resistance value between the first test site and the second test site is positive infinity, No ESD occurs between the first metal layer and the second metal layer; if the resistance value between the first test site and the second test site is within a measurable range, the first metal layer and the second metal layer ESD occurs between the metal layers; thereby detecting a position at which ESD occurs on the array substrate according to the measured resistance value between the first test site and the second test site;
  • the array substrate is a low temperature polysilicon thin film transistor array substrate
  • first metal layer and the second metal layer are a combination of one or more of molybdenum, aluminum, and copper;
  • the first wire and the second wire are all metal wires, and the first test site and the second test site are all metal blocks.
  • the ESD detecting method of the array substrate of the present invention is performed by drawing a first wire on a first metal layer of the array substrate and connecting to a first test site; and extracting a second metal layer on the array substrate Two wires are connected to the second test site; when an ESD fault occurs in the array substrate, the resistance value between the first test site and the second test site is measured by the resistance detecting device; if the first test bit is The resistance value between the point and the second test site is positive infinity, then no ESD occurs between the first metal layer and the second metal layer; if the first test site is between the first test site and the second test site The resistance value is within the measurable range, and ESD occurs between the first metal layer and the second metal layer; thereby detecting the array according to the measured resistance value between the first test site and the second test site The position of the ESD on the substrate; the ESD detection method of the array substrate of the present invention can detect the position of ESD occurring on the array substrate more quickly and accurately than the method for finding the E
  • FIG. 1 is a schematic flow chart of an ESD detecting method of an array substrate of the present invention
  • FIG. 3 is a schematic diagram of a first metal layer and a second metal layer on the array substrate provided in step 1 of the first embodiment of the ESD detecting method of the array substrate according to the present invention
  • FIG. 4 is a schematic cross-sectional structural view of the first metal layer and the second metal layer of FIG. 3;
  • FIG. 5 is a schematic view of the first metal layer and the second metal layer of FIG. 3 after ESD occurs;
  • FIG. 6 is a schematic cross-sectional structural view of the first metal layer and the second metal layer in FIG. 5;
  • step 7 is a schematic diagram of step 1 of a second embodiment of the ESD detecting method of the array substrate of the present invention.
  • FIG. 8 is a schematic diagram of a first metal layer and a second metal layer on the array substrate provided in step 1 of the second embodiment of the ESD detecting method of the array substrate according to the present invention
  • FIG. 9 is a schematic view of the first metal layer and the second metal layer of FIG. 8 after ESD occurs;
  • step 1 of a third embodiment of the ESD detecting method of the array substrate of the present invention is a schematic diagram of step 1 of a third embodiment of the ESD detecting method of the array substrate of the present invention.
  • FIG. 11 is a schematic diagram of a first metal layer and a second metal layer on the array substrate provided in step 1 of the third embodiment of the ESD detecting method of the array substrate according to the present invention.
  • FIG. 12 is a schematic view of the first metal layer and the second metal layer of FIG. 11 after ESD occurs.
  • a first embodiment of an ESD detecting method for an array substrate according to the present invention includes the following steps:
  • Step 1 an array substrate to be subjected to ESD detection is provided.
  • the array substrate is provided with a first metal layer 11 and a second metal layer 12, and the first metal layer 11 is connected by a first wire 21.
  • the second metal layer 12 is connected to the second test site 32 of the surface of the array substrate by the second wire 22.
  • the first test site 31 and the second test site 32 are both disposed on a surface of a peripheral region of the array substrate.
  • the array substrate is a low temperature polysilicon thin film transistor array substrate.
  • first metal layer 11 and the second metal layer 12 on the array substrate are located in different layers, and the first metal layer 11 and the second metal layer 12 are both block structures.
  • the first metal layer 11 and the second metal layer 12 are a stack combination of one or more of molybdenum (Mo), aluminum (Al), and copper (Cu).
  • an insulating layer 13 is disposed between the first metal layer 11 and the second metal layer 12.
  • the material of the insulating layer 13 is silicon nitride (SiN x ), silicon oxide (SiO x ), or a combination of the two.
  • first wire 21 and the second wire 22 are all metal wires
  • first test site 31 and the second test site 32 are all metal blocks.
  • the material of the first wire 21 and the second wire 22 is copper or aluminum.
  • the material of the first test site 31 and the second test site 32 is copper or aluminum.
  • Step 2 A resistance detecting device (not shown) is provided, and the resistance value between the first test site 31 and the second test site 32 is measured by the resistance detecting device.
  • the resistance value between the first test site 31 and the second test site 32 is positive infinity, the first metal layer 11 and the second metal layer 12 are illustrated. No ESD is caused by the ESD. Therefore, it can be determined that ESD does not occur between the first metal layer 11 and the second metal layer 12; please refer to FIG. 5 to FIG. 6 , if the first test site 31 and the first test site The resistance value between the two test sites 32 is within the measurable range, indicating that the first metal layer 11 and the second metal layer 12 are connected to each other due to ESD, and thus the first metal layer 11 can be judged. ESD occurs between the second metal layer 12; thereby detecting the position at which ESD occurs on the array substrate based on the measured resistance value between the first test site 31 and the second test site 32.
  • the resistance detecting device is a multimeter or a megohm meter, preferably a multimeter.
  • a second embodiment of an ESD detecting method for an array substrate according to the present invention is different from the first embodiment in that a first metal layer on the array substrate to be subjected to ESD detection is used.
  • 11 and the second metal layer 12 are both linear structures, and the rest are the same as the first embodiment, and are not described herein again.
  • a third embodiment of an ESD detecting method for an array substrate according to the present invention is different from the first embodiment in that a first metal layer on an array substrate to be ESD-detected is used.
  • 11 is in the same layer as the second metal layer 12, and is a linear structure, and the rest is the same as the first embodiment, and details are not described herein again.
  • the ESD detection method of the array substrate of the present invention is performed by drawing a first wire on the first metal layer of the array substrate and connecting to the first test site; and drawing a second on the second metal layer of the array substrate.
  • the wire is connected to the second test site; when the array substrate is subjected to an ESD fault, the resistance value between the first test site and the second test site is measured by the resistance detecting device; if the first test site is And the resistance value between the first test layer and the second test site is not between the first metal layer and the second metal layer; The resistance value is within the measurable range, and ESD occurs between the first metal layer and the second metal layer; thereby detecting the array substrate according to the measured resistance value between the first test site and the second test site The position of the ESD occurs on the array substrate.
  • the ESD detection method of the array substrate of the present invention can detect the position of ESD on the array substrate more quickly and accurately than the method for finding the ESD position by the microscope in the prior art, saving time and effort, and simultaneously Can save Test costs.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板的ESD检测方法，通过在阵列基板的第一金属层（11）上引出第一导线（21）并连接至第一测试位点（31）；在阵列基板的第二金属层（12）上引出第二导线（22）并连接至第二测试位点（32）；当阵列基板发生ESD故障时，通过电阻检测装置测量所述第一测试位点（31）与第二测试位点（32）之间的电阻值；若所述第一测试位点（31）与第二测试位点（32）之间的电阻值为正无穷，则所述第一金属层（11）与第二金属层（12）之间未发生ESD；若所述第一测试位点（31）与第二测试位点（32）之间的电阻值在可测范围内，则所述第一金属层（11）与第二金属层（12）之间发生ESD；从而根据所测量的第一测试位点（31）与第二测试位点（32）之间的电阻值检测出阵列基板上发生ESD的位置；可快速准确地检测出阵列基板上发生ESD的位置，省时省力，同时可以节省检测成本。

Description

阵列基板的ESD检测方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板的ESD检测方法。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等。
现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括壳体、设于壳体内的液晶面板及设于壳体内的背光模组(Backlight module)。传统的液晶面板的结构是由一彩色滤光片基板(Color Filter Substrate)、一薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)以及一配置于两基板间的液晶层(Liquid Crystal Layer)所构成，其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转，将背光模组的光线折射出来产生画面。
低温多晶硅(Low Temperature Poly-silicon，LTPS)技术是新一代TFT基板的制造技术，与传统非晶硅(a-Si)技术的最大差异在于，低温多晶硅显示器反应速度较快，且有高亮度、高解析度与低耗电量等优点。
随着低温多晶硅半导体薄膜晶体管的发展，而且由于LTPS半导体本身超高载流子迁移率的特性，相应的面板周边集成电路也成为大家关注的焦点，并且很多人投入到SOP(System on Panel，系统集成于面板)的相关技术研究，并逐步成为现实。但是由于LTPS制程比较复杂，需要的工艺数目比较多，这样发生ESD(Electro-Static Discharge，静电释放)的几率就比较大。
ESD是液晶显示屏中最常见的一种工艺故障，当发生ESD时，ESD相关的线路由于瞬间强电流而熔融，冷却后使本应不相连的金属连接在一起，从而加剧了ESD产生的损害，因此ESD检测是极其重要且非常必要的。当前ESD的检测只能通过在显微镜下寻找ESD损害处去查找，这样不仅费时费力，且成本也高。
因此，有必要提供一种阵列基板的ESD检测方法，以解决上述问题。
发明内容
本发明的目的在于提供一种阵列基板的ESD检测方法，可快速准确地检测出阵列基板上发生ESD的位置。
为实现上述目的，本发明提供一种阵列基板的ESD检测方法，包括如下步骤：
步骤1、提供待进行ESD检测的阵列基板，所述阵列基板上设有第一金属层与第二金属层，所述第一金属层通过第一导线连接至阵列基板表面的第一测试位点，所述第二金属层通过第二导线连接至阵列基板表面的第二测试位点；
步骤2、提供电阻检测装置，通过所述电阻检测装置测量所述第一测试位点与第二测试位点之间的电阻值；
若所述第一测试位点与第二测试位点之间的电阻值为正无穷，则所述第一金属层与第二金属层之间未发生ESD；若所述第一测试位点与第二测试位点之间的电阻值在可测范围内，则所述第一金属层与第二金属层之间发生ESD；从而根据所测量的第一测试位点与第二测试位点之间的电阻值检测出阵列基板上发生ESD的位置。
所述阵列基板上的第一金属层与第二金属层位于不同层。
所述第一金属层与第二金属层之间设有绝缘层。
所述阵列基板上的第一金属层与第二金属层位于同一层。
所述阵列基板为低温多晶硅薄膜晶体管阵列基板。
所述第一金属层与第二金属层为钼、铝、铜中的一种或多种的堆栈组合。
所述绝缘层的材料为氮化硅、氧化硅、或二者的组合。
所述第一导线、第二导线均为金属线，所述第一测试位点、及第二测试位点均为金属块。
所述第一导线与第二导线的材料为铜或铝。
所述第一测试位点与第二测试位点的材料为铜或铝。
本发明还提供一种阵列基板的ESD检测方法，包括如下步骤：
步骤1、提供待进行ESD检测的阵列基板，所述阵列基板上设有第一金属层与第二金属层，所述第一金属层通过第一导线连接至阵列基板表面的第一测试位点，所述第二金属层通过第二导线连接至阵列基板表面的第二测试位点；
步骤2、提供电阻检测装置，通过所述电阻检测装置测量所述第一测试位点与第二测试位点之间的电阻值；
若所述第一测试位点与第二测试位点之间的电阻值为正无穷，则所述 第一金属层与第二金属层之间未发生ESD；若所述第一测试位点与第二测试位点之间的电阻值在可测范围内，则所述第一金属层与第二金属层之间发生ESD；从而根据所测量的第一测试位点与第二测试位点之间的电阻值检测出阵列基板上发生ESD的位置；
其中，所述阵列基板为低温多晶硅薄膜晶体管阵列基板；
其中，所述第一金属层与第二金属层为钼、铝、铜中的一种或多种的堆栈组合；
其中，所述第一导线、第二导线均为金属线，所述第一测试位点、及第二测试位点均为金属块。
本发明的有益效果：本发明的阵列基板的ESD检测方法，通过在阵列基板的第一金属层上引出第一导线并连接至第一测试位点；在阵列基板的第二金属层上引出第二导线并连接至第二测试位点；当阵列基板发生ESD故障时，通过电阻检测装置测量所述第一测试位点与第二测试位点之间的电阻值；若所述第一测试位点与第二测试位点之间的电阻值为正无穷，则所述第一金属层与第二金属层之间未发生ESD；若所述第一测试位点与第二测试位点之间的电阻值在可测范围内，则所述第一金属层与第二金属层之间发生ESD；从而根据所测量的第一测试位点与第二测试位点之间的电阻值检测出阵列基板上发生ESD的位置；本发明的阵列基板的ESD检测方法与现有技术中通过显微镜寻找ESD位置的方法相比，可更加快速准确地检测出阵列基板上发生ESD的位置，省时省力，同时可以节省检测成本。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的阵列基板的ESD检测方法的示意流程图；
图2为本发明的阵列基板的ESD检测方法的第一实施例的步骤1的示意图；
图3为本发明的阵列基板的ESD检测方法的第一实施例的步骤1中提供的阵列基板上的第一金属层与第二金属层在正常情况下的示意图；
图4为图3中的第一金属层与第二金属层的剖面结构示意图；
图5为图3中的第一金属层与第二金属层在发生ESD后的示意图；
图6为图5中的第一金属层与第二金属层的剖面结构示意图；
图7为本发明的阵列基板的ESD检测方法的第二实施例的步骤1的示意图；
图8为本发明的阵列基板的ESD检测方法的第二实施例的步骤1中提供的阵列基板上的第一金属层与第二金属层在正常情况下的示意图；
图9为图8中的第一金属层与第二金属层在发生ESD后的示意图；
图10为本发明的阵列基板的ESD检测方法的第三实施例的步骤1的示意图；
图11为本发明的阵列基板的ESD检测方法的第三实施例的步骤1中提供的阵列基板上的第一金属层与第二金属层在正常情况下的示意图；
图12为图11中的第一金属层与第二金属层在发生ESD后的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，并结合图2至图6，为本发明的一种阵列基板的ESD检测方法的第一实施例，包括如下步骤：
步骤1、如图2所示，提供待进行ESD检测的阵列基板，所述阵列基板上设有第一金属层11与第二金属层12，所述第一金属层11通过第一导线21连接至阵列基板表面的第一测试位点31，所述第二金属层12通过第二导线22连接至阵列基板表面的第二测试位点32。
优选的，所述第一测试位点31与第二测试位点32均设置于所述阵列基板的周边区域的表面。
具体地，所述阵列基板为低温多晶硅薄膜晶体管阵列基板。
具体地，所述阵列基板上的第一金属层11与第二金属层12位于不同层，并且所述第一金属层11与第二金属层12均为块状结构。
具体地，所述第一金属层11与第二金属层12为钼(Mo)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
具体地，所述第一金属层11与第二金属层12之间设有绝缘层13。
具体地，所述绝缘层13的材料为氮化硅(SiNx)、氧化硅(SiOx)、或二者的组合。
具体地，所述第一导线21、第二导线22均为金属线，所述第一测试位点31、及第二测试位点32均为金属块。
具体地，所述第一导线21与第二导线22的材料为铜或铝。
具体地，所述第一测试位点31与第二测试位点32的材料为铜或铝。
步骤2、提供电阻检测装置(未图示)，通过所述电阻检测装置测量所述第一测试位点31与第二测试位点32之间的电阻值。
请参阅图3至图4，若所述第一测试位点31与第二测试位点32之间的电阻值为正无穷，则说明所述第一金属层11与第二金属层12之间并未因ESD而导致相互连接，因此可判断所述第一金属层11与第二金属层12之间未发生ESD；请参阅图5至图6，若所述第一测试位点31与第二测试位点32之间的电阻值在可测范围内，则说明所述第一金属层11与第二金属层12之间因ESD而导致相互连接，因此可判断所述第一金属层11与第二金属层12之间发生ESD；从而根据所测量的第一测试位点31与第二测试位点32之间的电阻值检测出阵列基板上发生ESD的位置。
具体的，所述电阻检测装置为万用表或兆欧表，优选为万用表。
请参阅图7至图9，为本发明的一种阵列基板的ESD检测方法的第二实施例，其与上述第一实施例的区别在于，待进行ESD检测的阵列基板上的第一金属层11与第二金属层12均为线状结构，其余部分均与第一实施例相同，此处不再赘述。
请参阅图10至图12，为本发明的一种阵列基板的ESD检测方法的第三实施例，其与上述第一实施例的区别在于，待进行ESD检测的阵列基板上的第一金属层11与第二金属层12位于同一层，且均为线状结构，其余部分均与第一实施例相同，此处不再赘述。
综上所述，本发明的阵列基板的ESD检测方法，通过在阵列基板的第一金属层上引出第一导线并连接至第一测试位点；在阵列基板的第二金属层上引出第二导线并连接至第二测试位点；当阵列基板发生ESD故障时，通过电阻检测装置测量所述第一测试位点与第二测试位点之间的电阻值；若所述第一测试位点与第二测试位点之间的电阻值为正无穷，则所述第一金属层与第二金属层之间未发生ESD；若所述第一测试位点与第二测试位点之间的电阻值在可测范围内，则所述第一金属层与第二金属层之间发生ESD；从而根据所测量的第一测试位点与第二测试位点之间的电阻值检测出阵列基板上发生ESD的位置；本发明的阵列基板的ESD检测方法与现有技术中通过显微镜寻找ESD位置的方法相比，可更加快速准确地检测出阵列基板上发生ESD的位置，省时省力，同时可以节省检测成本。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (17)

  1. 一种阵列基板的ESD检测方法，包括如下步骤：
    步骤1、提供待进行ESD检测的阵列基板，所述阵列基板上设有第一金属层与第二金属层，所述第一金属层通过第一导线连接至阵列基板表面的第一测试位点，所述第二金属层通过第二导线连接至阵列基板表面的第二测试位点；
    步骤2、提供电阻检测装置，通过所述电阻检测装置测量所述第一测试位点与第二测试位点之间的电阻值；
    若所述第一测试位点与第二测试位点之间的电阻值为正无穷，则所述第一金属层与第二金属层之间未发生ESD；若所述第一测试位点与第二测试位点之间的电阻值在可测范围内，则所述第一金属层与第二金属层之间发生ESD；从而根据所测量的第一测试位点与第二测试位点之间的电阻值检测出阵列基板上发生ESD的位置。
  2. 如权利要求1所述的阵列基板的ESD检测方法，其中，所述阵列基板上的第一金属层与第二金属层位于不同层。
  3. 如权利要求2所述的阵列基板的ESD检测方法，其中，所述第一金属层与第二金属层之间设有绝缘层。
  4. 如权利要求1所述的阵列基板的ESD检测方法，其中，所述阵列基板上的第一金属层与第二金属层位于同一层。
  5. 如权利要求1所述的阵列基板的ESD检测方法，其中，所述阵列基板为低温多晶硅薄膜晶体管阵列基板。
  6. 如权利要求1所述的阵列基板的ESD检测方法，其中，所述第一金属层与第二金属层为钼、铝、铜中的一种或多种的堆栈组合。
  7. 如权利要求3所述的阵列基板的ESD检测方法，其中，所述绝缘层的材料为氮化硅、氧化硅、或二者的组合。
  8. 如权利要求1所述的阵列基板的ESD检测方法，其中，所述第一导线、第二导线均为金属线，所述第一测试位点、及第二测试位点均为金属块。
  9. 如权利要求8所述的阵列基板的ESD检测方法，其中，所述第一导线与第二导线的材料为铜或铝。
  10. 如权利要求8所述的阵列基板的ESD检测方法，其中，所述第一测试位点与第二测试位点的材料为铜或铝。
  11. 一种阵列基板的ESD检测方法，包括如下步骤：
    步骤1、提供待进行ESD检测的阵列基板，所述阵列基板上设有第一金属层与第二金属层，所述第一金属层通过第一导线连接至阵列基板表面的第一测试位点，所述第二金属层通过第二导线连接至阵列基板表面的第二测试位点；
    步骤2、提供电阻检测装置，通过所述电阻检测装置测量所述第一测试位点与第二测试位点之间的电阻值；
    若所述第一测试位点与第二测试位点之间的电阻值为正无穷，则所述第一金属层与第二金属层之间未发生ESD；若所述第一测试位点与第二测试位点之间的电阻值在可测范围内，则所述第一金属层与第二金属层之间发生ESD；从而根据所测量的第一测试位点与第二测试位点之间的电阻值检测出阵列基板上发生ESD的位置；
    其中，所述阵列基板为低温多晶硅薄膜晶体管阵列基板；
    其中，所述第一金属层与第二金属层为钼、铝、铜中的一种或多种的堆栈组合；
    其中，所述第一导线、第二导线均为金属线，所述第一测试位点、及第二测试位点均为金属块。
  12. 如权利要求11所述的阵列基板的ESD检测方法，其中，所述阵列基板上的第一金属层与第二金属层位于不同层。
  13. 如权利要求12所述的阵列基板的ESD检测方法，其中，所述第一金属层与第二金属层之间设有绝缘层。
  14. 如权利要求11所述的阵列基板的ESD检测方法，其中，所述阵列基板上的第一金属层与第二金属层位于同一层。
  15. 如权利要求13所述的阵列基板的ESD检测方法，其中，所述绝缘层的材料为氮化硅、氧化硅、或二者的组合。
  16. 如权利要求11所述的阵列基板的ESD检测方法，其中，所述第一导线与第二导线的材料为铜或铝。
  17. 如权利要求11所述的阵列基板的ESD检测方法，其中，所述第一测试位点与第二测试位点的材料为铜或铝。
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