WO2017101203A1 - 低温多晶硅tft基板及其制作方法 - Google Patents

低温多晶硅tft基板及其制作方法 Download PDF

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WO2017101203A1
WO2017101203A1 PCT/CN2016/072772 CN2016072772W WO2017101203A1 WO 2017101203 A1 WO2017101203 A1 WO 2017101203A1 CN 2016072772 W CN2016072772 W CN 2016072772W WO 2017101203 A1 WO2017101203 A1 WO 2017101203A1
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region
drain
source
lightly doped
metal layer
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陈归
龚强
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a low temperature polysilicon TFT substrate and a method of fabricating the same.
  • Liquid crystal display has many advantages such as thin body, power saving, no radiation, etc., and is widely used, such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptops. Screen, etc.
  • liquid crystal display devices which include a casing, a liquid crystal panel disposed in the casing, and a backlight module disposed in the casing.
  • the structure of the conventional liquid crystal panel is composed of a color filter substrate, a thin film transistor array substrate (TFT Array Substrate), and a liquid crystal layer (Liquid Crystal Layer) disposed between the two substrates.
  • TFT Array Substrate thin film transistor array substrate
  • Liquid Crystal Layer Liquid Crystal Layer
  • Low Temperature Poly-silicon (LTPS) technology is the manufacturing technology of the new generation of TFT substrate.
  • a-Si amorphous silicon
  • the low-temperature polysilicon display has a fast response speed and high brightness. High resolution and low power consumption.
  • the top-gate low-temperature polysilicon TFT substrate is commonly used by major manufacturers.
  • the top-gate low-temperature polysilicon TFT substrate in order to prevent the influence of illumination on leakage current, it is generally in the effective display area (Active Area).
  • AA adds a light-shielding metal layer to the bottom of the TFT device, which increases the process cost of the low-temperature polysilicon TFT substrate. It can be seen that the development of the bottom-gate low-temperature polysilicon TFT substrate process is of great significance for cost saving and increased production capacity.
  • FIG. 1 is a schematic cross-sectional view of a conventional bottom-gate low-temperature polysilicon TFT substrate, including a substrate 100, a gate 200 disposed on the substrate 100, and a substrate 200 and a gate 200.
  • LDD lightly doped drain region
  • the source/drain contact region 410, the channel region 420, The three regions of the lightly doped drain region 430 need to be doped separately, so that at least two masks are required in the process, the process is cumbersome, the production efficiency is low, and the production cost is high.
  • the present invention provides a low temperature polysilicon TFT substrate, comprising a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the substrate and the gate, and the gate insulating layer disposed on the substrate a polysilicon layer on the layer, a source and a drain provided on the gate insulating layer and the polysilicon layer, and a metal layer disposed on the polysilicon layer between the source and the drain;
  • the polysilicon layer includes source/drain contact regions on both sides and respectively in contact with the source and drain, a channel region under the metal layer, and a source/drain contact region A lightly doped drain region between the channel regions.
  • the substrate is a glass substrate.
  • the material of the gate insulating layer is silicon nitride, silicon oxide, or a combination of the two.
  • the material of the gate, the source, the drain, and the metal layer is a stacked combination of one or more of molybdenum, aluminum, and copper.
  • the source/drain contact region is an N-type heavily doped region, the channel region is a P-type heavily doped region, and the lightly doped drain region is an N-type lightly doped region; or the source/drain The pole contact region is a P-type heavily doped region, the channel region is an N-type heavily doped region, and the lightly doped drain region is an N-type lightly doped region.
  • the invention also provides a method for manufacturing a low temperature polysilicon TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to form a gate;
  • Step 2 depositing a gate insulating layer on the substrate and the gate;
  • Step 3 forming a polysilicon layer on the gate insulating layer
  • Step 4 performing ion implantation on both side regions of the polysilicon layer to form a source/drain contact region; performing ion implantation on the intermediate region of the polysilicon layer to form a channel region;
  • Step 5 depositing a second metal layer on the gate insulating layer and the polysilicon layer, and The two metal layers are patterned to form a source, a drain, and a metal layer between the source and the drain;
  • Step 6 The metal layer, and the source and the drain are used as a mask, and the polysilicon layer is ion-implanted to obtain a lightly doped drain region between the source/drain contact region and the channel region.
  • the substrate in the step 1 is a glass substrate.
  • the material of the gate insulating layer in the step 2 is silicon nitride, silicon oxide, or a combination of the two.
  • the material of the gate, the source, the drain, and the metal layer is a stacked combination of one or more of molybdenum, aluminum, and copper.
  • the source/drain contact region is an N-type heavily doped region, the channel region is a P-type heavily doped region, and the lightly doped drain region is an N-type lightly doped region; or the source/drain The pole contact region is a P-type heavily doped region, the channel region is an N-type heavily doped region, and the lightly doped drain region is an N-type lightly doped region.
  • the present invention also provides a low temperature polysilicon TFT substrate, comprising a substrate, a gate disposed on the substrate, a gate insulating layer disposed on the substrate and the gate, and polysilicon disposed on the gate insulating layer a layer, a source and a drain disposed on the gate insulating layer and the polysilicon layer, and a metal layer disposed on the polysilicon layer and located between the source and the drain;
  • the polysilicon layer includes source/drain contact regions on both sides and respectively in contact with the source and drain, a channel region under the metal layer, and a source/drain contact region a lightly doped drain region between the channel regions;
  • the substrate is a glass substrate
  • the material of the gate insulating layer is silicon nitride, silicon oxide, or a combination of the two;
  • the material of the gate, the source, the drain, and the metal layer is a stack combination of one or more of molybdenum, aluminum, and copper;
  • the source/drain contact region is an N-type heavily doped region
  • the channel region is a P-type heavily doped region
  • the lightly doped drain region is an N-type lightly doped region
  • the source The /drain contact region is a P-type heavily doped region
  • the channel region is an N-type heavily doped region
  • the lightly doped drain region is an N-type lightly doped region.
  • the low-temperature polysilicon TFT substrate of the present invention has a metal layer disposed above the channel region, and the metal layer, the source and the drain are used as a photomask, and a lightly doped drain region is formed on the polysilicon layer.
  • the reticle required for forming the lightly doped drain region is separately reduced; and at the same time, by adding a metal layer connected to the channel region of the polysilicon layer, the resistance of the channel region can be effectively reduced, and the on-state current of the TFT is improved.
  • the low-temperature polysilicon TFT substrate of the present invention is formed by forming a metal layer over the channel region while forming a source and a drain, and using the metal layer, the source and the drain as a mask, on the polysilicon layer.
  • the formation of a lightly doped drain region reduces the need for a photomask that is separately required to form a lightly doped drain region, thereby saving production costs and increasing throughput.
  • FIG. 1 is a schematic cross-sectional structural view of a conventional low-temperature polysilicon TFT substrate
  • FIG. 2 is a schematic cross-sectional structural view of a low temperature polysilicon TFT substrate of the present invention
  • FIG. 3 is a schematic flow chart of a method for fabricating a low temperature polysilicon TFT substrate of the present invention.
  • the first low temperature polysilicon TFT substrate comprises a substrate 1, a gate electrode 2 disposed on the substrate 1, and a gate insulating layer 3 disposed on the substrate 1 and the gate 2. a polysilicon layer 4 on the gate insulating layer 3, a source 5 and a drain 6 provided on the gate insulating layer 3 and the polysilicon layer 4, and a polysilicon layer 4 disposed on the polysilicon layer 4 and located at the A metal layer 7 between the source 5 and the drain 6.
  • the polysilicon layer 4 includes source/drain contact regions 41 on both sides and respectively in contact with the source 5 and the drain 6, a channel region 42 under the metal layer 7, and located at the source Lightly doped drain region 43 between drain contact region 41 and channel region 42.
  • the substrate 1 is a glass substrate.
  • the material of the gate insulating layer 3 may be silicon nitride (SiN x ), silicon oxide (SiO x ), or a combination of both.
  • the material of the gate 2, the source 5, the drain 6, and the metal layer 7 is a stacked combination of one or more of molybdenum (Mo), aluminum (Al), and copper (Cu).
  • the source/drain contact region 41 is an N-type heavily doped region
  • the channel region 42 is a P-type heavily doped region
  • the lightly doped drain region 43 is an N-type lightly doped region.
  • the source/drain contact region 41 is a P-type heavily doped region
  • the channel region 42 is an N-type heavily doped region
  • the lightly doped drain region 43 is an N-type lightly doped region.
  • the ions doped in the N-type heavily doped region and the N-type lightly doped region are phosphorus ions or arsenic ions; and the ions doped in the P-type heavily doped region are boron ions or gallium ions.
  • the ion concentration in the N-type heavily doped region or the P-type heavily doped region ranges from 10 19 to 10 21 ions/cm 3
  • the ion concentration of the N-type lightly doped region is doped.
  • the range is 10 16 to 10 17 ions/cm 3 .
  • the low-temperature polysilicon TFT substrate is provided with a metal layer above the channel region, and the metal layer, the source and the drain are used as a mask, and a lightly doped drain region is formed on the polysilicon layer to reduce formation of a lightly doped drain region.
  • the mask is separately required; at the same time, due to the addition of a metal layer connected to the channel region of the polysilicon layer, the resistance of the channel region can be effectively reduced, and the on-state current of the TFT can be improved.
  • the present invention further provides a method for fabricating a low temperature polysilicon TFT substrate, comprising the following steps:
  • Step 1 Providing a substrate 1, depositing a first metal layer on the substrate 1, and patterning the first metal layer to form a gate 2.
  • the substrate 1 in the step 1 is a glass substrate.
  • Step 2 depositing a gate insulating layer 3 on the substrate 1 and the gate 2.
  • the material of the gate insulating layer 3 in the step 2 is silicon nitride, silicon oxide, or a combination of the two.
  • Step 3 Form a polysilicon layer 4 on the gate insulating layer 3.
  • Step 4 ion implantation is performed on both side regions of the polysilicon layer 4 to form a source/drain contact region 41; and an intermediate region of the polysilicon layer 4 is ion implanted to form a channel region 42.
  • Step 5 depositing a second metal layer on the gate insulating layer 3 and the polysilicon layer 4, and patterning the second metal layer to form a source 5, a drain 6, and the source The metal layer 7 between the 5 and the drain 6.
  • the material of the gate 2, the source 5, the drain 6, and the metal layer 7 is a stacked combination of one or more of molybdenum, aluminum, and copper.
  • Step 6 The metal layer 7 and the source and drain electrodes 5 and 6 are used as a photomask, and the polysilicon layer 4 is ion-implanted to obtain the source/drain contact region 41 and the channel region 42. Lightly doped drain region 43.
  • the source/drain contact region 41 is an N-type heavily doped region
  • the channel region 42 is a P-type heavily doped region
  • the lightly doped drain region 43 is an N-type lightly doped region.
  • the source/drain contact region 41 is a P-type heavily doped region
  • the channel region 42 is an N-type heavily doped region
  • the lightly doped drain region 43 is an N-type lightly doped region.
  • the ions doped in the N-type heavily doped region and the N-type lightly doped region are phosphorus ions or arsenic ions; and the ions doped in the P-type heavily doped region are boron ions or gallium ions.
  • the ion concentration in the N-type heavily doped region or the P-type heavily doped region ranges from 10 19 to 10 21 ions/cm 3
  • the ion concentration of the N-type lightly doped region is doped.
  • the range is 10 16 to 10 17 ions/cm 3 .
  • the method for fabricating the low-temperature polysilicon TFT substrate is characterized in that a metal layer is formed over the channel region while forming a source and a drain, and the metal layer, the source and the drain are used as a mask.
  • the formation of a lightly doped drain region on the polysilicon layer reduces the need for a photomask that is separately required to form a lightly doped drain region, thereby saving production costs and increasing throughput.
  • the low-temperature polysilicon TFT substrate of the present invention has a metal layer disposed above the channel region, and the metal layer, the source and the drain are used as a mask, and a lightly doped drain region is formed on the polysilicon layer.
  • the reticle required to form the lightly doped drain region is separately reduced; and at the same time, by adding a metal layer connected to the channel region of the polysilicon layer, the resistance of the channel region can be effectively reduced, and the on-state current of the TFT can be improved.
  • the low-temperature polysilicon TFT substrate of the present invention is formed by forming a metal layer over the channel region while forming a source and a drain, and using the metal layer, the source and the drain as a mask, on the polysilicon layer.
  • the formation of a lightly doped drain region reduces the need for a photomask that is separately required to form a lightly doped drain region, thereby saving production costs and increasing throughput.

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Abstract

提供一种低温多晶硅TFT基板及其制作方法。一种低温多晶硅TFT基板，沟道区（42）上方设有金属层（7），可将所述金属层（7）、及源极（5）与漏极（6）作为光罩，在多晶硅层上形成轻掺杂漏区（43），减少形成轻掺杂漏区（43）所单独需要的光罩；同时由于增加了一层与多晶硅层沟道区相连的金属层（7），可以有效降低沟道区（42）的电阻，提高TFT的开态电流。一种低温多晶硅TFT基板的制作方法，通过在形成源极（5）与漏极（6）的同时，在沟道区（42）上方形成金属层（7），并将金属层（7）、及源极（5）与漏极（6）作为光罩，在多晶硅层上形成轻掺杂漏区（43），减少了形成轻掺杂漏区（43）所单独需要的光罩，从而节省了生产成本，提高了产能。

Description

低温多晶硅TFT基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种低温多晶硅TFT基板及其制作方法。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等。
现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括壳体、设于壳体内的液晶面板及设于壳体内的背光模组(Backlight module)。传统的液晶面板的结构是由一彩色滤光片基板(Color Filter Substrate)、一薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)以及一配置于两基板间的液晶层(Liquid Crystal Layer)所构成，其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转，将背光模组的光线折射出来产生画面。
低温多晶硅(Low Temperature Poly-silicon，LTPS)技术是新一代TFT基板的制造技术，与传统非晶硅(a-Si)技术的最大差异在于，低温多晶硅显示器反应速度较快，且有高亮度、高解析度与低耗电量等优点。低温多晶硅技术中，目前各大厂家较常用的是顶栅型的低温多晶硅TFT基板，但是顶栅型的低温多晶硅TFT基板中为了防止光照对漏电流的影响，一般都会在有效显示区域(Active Area，AA)的TFT器件底部增加遮光金属层，这样就增加了低温多晶硅TFT基板的制程成本。由此可见开发底栅型低温多晶硅TFT基板工艺对于节省成本，增加产能具有重要意义。
请参阅图1，为一种现有的底栅型低温多晶硅TFT基板的剖面结构示意图，包括基板100、设于所述基板100上的栅极200、设于所述基板100与栅极200上的栅极绝缘层300、设于所述栅极绝缘层300上的多晶硅层400、设于所述栅极绝缘层300与多晶硅层400上的源极500与漏极600；所述多晶硅层400包括位于两侧且分别与所述源极500与漏极600相接触的源/漏极接触区410、位于所述多晶硅层400中间的沟道区420、及位于所述源/漏极接触区410与沟道区420之间的轻掺杂漏区(LDD)430。在该低温多晶硅TFT基板的制作方法中，所述源/漏极接触区410、沟道区420、 及轻掺杂漏区430这三个区域都需要单独掺杂，这样在制程中至少需要两道光罩，工艺较为繁琐，生产效率较低，生产成本较高。
因此，有必要提供一种低温多晶硅TFT基板及其制作方法，以解决上述问题。
发明内容
本发明的目的在于提供一种低温多晶硅TFT基板，沟道区上方设有金属层，沟道区的电阻较低，TFT的开态电流较高。
本发明的目的还在于提供一种低温多晶硅TFT基板的制作方法，通过在沟道区上方制作金属层，并将金属层、及源极与漏极作为光罩在多晶硅层上形成轻掺杂漏区，减少形成轻掺杂漏区所单独需要的光罩，节省生产成本，提高产能。
为实现上述目的，本发明提供一种低温多晶硅TFT基板，包括基板、设于所述基板上的栅极、设于所述基板与栅极上的栅极绝缘层、设于所述栅极绝缘层上的多晶硅层、设于所述栅极绝缘层与多晶硅层上的源极与漏极、及设于所述多晶硅层上且位于所述源极与漏极之间的金属层；
所述多晶硅层包括位于两侧且分别与所述源极与漏极相接触的源/漏极接触区、位于所述金属层下方的沟道区、及位于所述源/漏极接触区与沟道区之间的轻掺杂漏区。
所述基板为玻璃基板。
所述栅极绝缘层的材料为氮化硅、氧化硅、或二者的组合。
所述栅极、源极、漏极、及金属层的材料为钼、铝、铜中的一种或多种的堆栈组合。
所述源/漏极接触区为N型重掺杂区，所述沟道区为P型重掺杂区，所述轻掺杂漏区为N型轻掺杂区；或所述源/漏极接触区为P型重掺杂区，所述沟道区为N型重掺杂区，所述轻掺杂漏区为N型轻掺杂区。
本发明还提供一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
步骤2、在所述基板与栅极上沉积栅极绝缘层；
步骤3、在所述栅极绝缘层上形成多晶硅层；
步骤4、对所述多晶硅层的两侧区域进行离子植入，形成源/漏极接触区；对所述多晶硅层的中间区域进行离子植入，形成沟道区；
步骤5、在所述栅极绝缘层与多晶硅层上沉积第二金属层，并对所述第 二金属层进行图案化处理，形成源极、漏极、及位于所述源极与漏极之间的金属层；
步骤6、以所述金属层、及源、漏极为光罩，对所述多晶硅层进行离子植入，得到位于所述源/漏极接触区与沟道区之间的轻掺杂漏区。
所述步骤1中的基板为玻璃基板。
所述步骤2中的栅极绝缘层的材料为氮化硅、氧化硅、或二者的组合。
所述栅极、源极、漏极、及金属层的材料为钼、铝、铜中的一种或多种的堆栈组合。
所述源/漏极接触区为N型重掺杂区，所述沟道区为P型重掺杂区，所述轻掺杂漏区为N型轻掺杂区；或者所述源/漏极接触区为P型重掺杂区，所述沟道区为N型重掺杂区，所述轻掺杂漏区为N型轻掺杂区。
本发明还提供一种低温多晶硅TFT基板，包括基板、设于所述基板上的栅极、设于所述基板与栅极上的栅极绝缘层、设于所述栅极绝缘层上的多晶硅层、设于所述栅极绝缘层与多晶硅层上的源极与漏极、及设于所述多晶硅层上且位于所述源极与漏极之间的金属层；
所述多晶硅层包括位于两侧且分别与所述源极与漏极相接触的源/漏极接触区、位于所述金属层下方的沟道区、及位于所述源/漏极接触区与沟道区之间的轻掺杂漏区；
其中，所述基板为玻璃基板；
其中，所述栅极绝缘层的材料为氮化硅、氧化硅、或二者的组合；
其中，所述栅极、源极、漏极、及金属层的材料为钼、铝、铜中的一种或多种的堆栈组合；
其中，所述源/漏极接触区为N型重掺杂区，所述沟道区为P型重掺杂区，所述轻掺杂漏区为N型轻掺杂区；或者所述源/漏极接触区为P型重掺杂区，所述沟道区为N型重掺杂区，所述轻掺杂漏区为N型轻掺杂区。
本发明的有益效果：本发明的低温多晶硅TFT基板，沟道区上方设有金属层，可将所述金属层、及源极与漏极作为光罩，在多晶硅层上形成轻掺杂漏区，减少形成轻掺杂漏区所单独需要的光罩；同时由于增加了一层与多晶硅层沟道区相连的金属层，可以有效降低沟道区的电阻，提高TFT的开态电流。本发明的低温多晶硅TFT基板的制作方法，通过在形成源极与漏极的同时，在沟道区上方形成金属层，并将金属层、及源极与漏极作为光罩，在多晶硅层上形成轻掺杂漏区，减少了形成轻掺杂漏区所单独需要的光罩，从而节省了生产成本，提高了产能。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的低温多晶硅TFT基板的剖面结构示意图；
图2为本发明的低温多晶硅TFT基板的剖面结构示意图；
图3为本发明的低温多晶硅TFT基板的制作方法的示意流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明首先一种低温多晶硅TFT基板，包括基板1、设于所述基板1上的栅极2、设于所述基板1与栅极2上的栅极绝缘层3、设于所述栅极绝缘层3上的多晶硅层4、设于所述栅极绝缘层3与多晶硅层4上的源极5与漏极6、及设于所述多晶硅层4上且位于所述源极5与漏极6之间的金属层7。
所述多晶硅层4包括位于两侧且分别与所述源极5与漏极6相接触的源/漏极接触区41、位于所述金属层7下方的沟道区42、及位于所述源/漏极接触区41与沟道区42之间的轻掺杂漏区43。
具体地，所述基板1为玻璃基板。
具体地，所述栅极绝缘层3的材料可以是氮化硅(SiNx)、氧化硅(SiOx)、或二者的组合。
具体地，所述栅极2、源极5、漏极6、及金属层7的材料为钼(Mo)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
可选的，所述源/漏极接触区41为N型重掺杂区，所述沟道区42为P型重掺杂区，所述轻掺杂漏区43为N型轻掺杂区；或者所述源/漏极接触区41为P型重掺杂区，所述沟道区42为N型重掺杂区，所述轻掺杂漏区43为N型轻掺杂区。
优选的，所述N型重掺杂区与N型轻掺杂区中掺杂的离子为磷离子或砷离子；所述P型重掺杂区中掺杂的离子为硼离子或镓离子。
具体的，所述N型重掺杂区或P型重掺杂区中掺杂的离子浓度范围为1019～1021ions/cm3，所述N型轻掺杂区中掺杂的离子浓度范围为1016～1017ions/cm3。
上述低温多晶硅TFT基板，沟道区上方设有金属层，可将所述金属层、及源极与漏极作为光罩，在多晶硅层上形成轻掺杂漏区，减少形成轻掺杂漏区所单独需要的光罩；同时由于增加了一层与多晶硅层沟道区相连的金属层，可以有效降低沟道区的电阻，提高TFT的开态电流。
请参阅图3，同时参阅图2，本发明还提供一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、提供基板1，在所述基板1上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极2。
具体地，所述步骤1中的基板1为玻璃基板。
步骤2、在所述基板1与栅极2上沉积栅极绝缘层3。
具体地，所述步骤2中的栅极绝缘层3的材料为氮化硅、氧化硅、或二者的组合。
步骤3、在所述栅极绝缘层3上形成多晶硅层4。
步骤4、对所述多晶硅层4的两侧区域进行离子植入，形成源/漏极接触区41；对所述多晶硅层4的中间区域进行离子植入，形成沟道区42。
步骤5、在所述栅极绝缘层3与多晶硅层4上沉积第二金属层，并对所述第二金属层进行图案化处理，形成源极5、漏极6、及位于所述源极5与漏极6之间的金属层7。
具体地，所述栅极2、源极5、漏极6、及金属层7的材料为钼、铝、铜中的一种或多种的堆栈组合。
步骤6、以所述金属层7、及源、漏极5、6为光罩，对所述多晶硅层4进行离子植入，得到位于所述源/漏极接触区41与沟道区42之间的轻掺杂漏区43。
可选的，所述源/漏极接触区41为N型重掺杂区，所述沟道区42为P型重掺杂区，所述轻掺杂漏区43为N型轻掺杂区；或者所述源/漏极接触区41为P型重掺杂区，所述沟道区42为N型重掺杂区，所述轻掺杂漏区43为N型轻掺杂区。
优选的，所述N型重掺杂区与N型轻掺杂区中掺杂的离子为磷离子或砷离子；所述P型重掺杂区中掺杂的离子为硼离子或镓离子。
具体的，所述N型重掺杂区或P型重掺杂区中掺杂的离子浓度范围为1019～1021ions/cm3，所述N型轻掺杂区中掺杂的离子浓度范围为1016～1017ions/cm3。
上述低温多晶硅TFT基板的制作方法，通过在形成源极与漏极的同时，在沟道区上方形成金属层，并将金属层、及源极与漏极作为光罩，在 多晶硅层上形成轻掺杂漏区，减少了形成轻掺杂漏区所单独需要的光罩，从而节省了生产成本，提高了产能。
综上所述，本发明的低温多晶硅TFT基板，沟道区上方设有金属层，可将所述金属层、及源极与漏极作为光罩，在多晶硅层上形成轻掺杂漏区，减少形成轻掺杂漏区所单独需要的光罩；同时由于增加了一层与多晶硅层沟道区相连的金属层，可以有效降低沟道区的电阻，提高TFT的开态电流。本发明的低温多晶硅TFT基板的制作方法，通过在形成源极与漏极的同时，在沟道区上方形成金属层，并将金属层、及源极与漏极作为光罩，在多晶硅层上形成轻掺杂漏区，减少了形成轻掺杂漏区所单独需要的光罩，从而节省了生产成本，提高了产能。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (11)

  1. 一种低温多晶硅TFT基板，包括基板、设于所述基板上的栅极、设于所述基板与栅极上的栅极绝缘层、设于所述栅极绝缘层上的多晶硅层、设于所述栅极绝缘层与多晶硅层上的源极与漏极、及设于所述多晶硅层上且位于所述源极与漏极之间的金属层；
    所述多晶硅层包括位于两侧且分别与所述源极与漏极相接触的源/漏极接触区、位于所述金属层下方的沟道区、及位于所述源/漏极接触区与沟道区之间的轻掺杂漏区。
  2. 如权利要求1所述的低温多晶硅TFT基板，其中，所述基板为玻璃基板。
  3. 如权利要求1所述的低温多晶硅TFT基板，其中，所述栅极绝缘层的材料为氮化硅、氧化硅、或二者的组合。
  4. 如权利要求1所述的低温多晶硅TFT基板，其中，所述栅极、源极、漏极、及金属层的材料为钼、铝、铜中的一种或多种的堆栈组合。
  5. 如权利要求1所述的低温多晶硅TFT基板，其中，所述源/漏极接触区为N型重掺杂区，所述沟道区为P型重掺杂区，所述轻掺杂漏区为N型轻掺杂区；或者所述源/漏极接触区为P型重掺杂区，所述沟道区为N型重掺杂区，所述轻掺杂漏区为N型轻掺杂区。
  6. 一种低温多晶硅TFT基板的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
    步骤2、在所述基板与栅极上沉积栅极绝缘层；
    步骤3、在所述栅极绝缘层上形成多晶硅层；
    步骤4、对所述多晶硅层的两侧区域进行离子植入，形成源/漏极接触区；对所述多晶硅层的中间区域进行离子植入，形成沟道区；
    步骤5、在所述栅极绝缘层与多晶硅层上沉积第二金属层，并对所述第二金属层进行图案化处理，形成源极、漏极、及位于所述源极与漏极之间的金属层；
    步骤6、以所述金属层、及源、漏极为光罩，对所述多晶硅层进行离子植入，得到位于所述源/漏极接触区与沟道区之间的轻掺杂漏区。
  7. 如权利要求6所述的低温多晶硅TFT基板的制作方法，其中，所述步骤1中的基板为玻璃基板。
  8. 如权利要求6所述的低温多晶硅TFT基板的制作方法，其中，所述步骤2中的栅极绝缘层的材料为氮化硅、氧化硅、或二者的组合。
  9. 如权利要求6所述的低温多晶硅TFT基板的制作方法，其中，所述栅极、源极、漏极、及金属层的材料为钼、铝、铜中的一种或多种的堆栈组合。
  10. 如权利要求6所述的低温多晶硅TFT基板的制作方法，其中，所述源/漏极接触区为N型重掺杂区，所述沟道区为P型重掺杂区，所述轻掺杂漏区为N型轻掺杂区；或者所述源/漏极接触区为P型重掺杂区，所述沟道区为N型重掺杂区，所述轻掺杂漏区为N型轻掺杂区。
  11. 一种低温多晶硅TFT基板，包括基板、设于所述基板上的栅极、设于所述基板与栅极上的栅极绝缘层、设于所述栅极绝缘层上的多晶硅层、设于所述栅极绝缘层与多晶硅层上的源极与漏极、及设于所述多晶硅层上且位于所述源极与漏极之间的金属层；
    所述多晶硅层包括位于两侧且分别与所述源极与漏极相接触的源/漏极接触区、位于所述金属层下方的沟道区、及位于所述源/漏极接触区与沟道区之间的轻掺杂漏区；
    其中，所述基板为玻璃基板；
    其中，所述栅极绝缘层的材料为氮化硅、氧化硅、或二者的组合；
    其中，所述栅极、源极、漏极、及金属层的材料为钼、铝、铜中的一种或多种的堆栈组合；
    其中，所述源/漏极接触区为N型重掺杂区，所述沟道区为P型重掺杂区，所述轻掺杂漏区为N型轻掺杂区；或者所述源/漏极接触区为P型重掺杂区，所述沟道区为N型重掺杂区，所述轻掺杂漏区为N型轻掺杂区。
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