WO2017101178A1 - 栅极驱动电路及其阵列基板 - Google Patents

栅极驱动电路及其阵列基板 Download PDF

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Publication number
WO2017101178A1
WO2017101178A1 PCT/CN2016/070289 CN2016070289W WO2017101178A1 WO 2017101178 A1 WO2017101178 A1 WO 2017101178A1 CN 2016070289 W CN2016070289 W CN 2016070289W WO 2017101178 A1 WO2017101178 A1 WO 2017101178A1
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Prior art keywords
gate
signal
level
driving circuit
gate driving
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PCT/CN2016/070289
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English (en)
French (fr)
Inventor
黄笑宇
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/906,584 priority Critical patent/US20180277050A1/en
Publication of WO2017101178A1 publication Critical patent/WO2017101178A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms

Definitions

  • the present patent application relates to the field of liquid crystal display technologies, and in particular to a gate driving circuit and an array substrate thereof for use in a liquid crystal display.
  • liquid crystal display liquid crystal display, LCD
  • LCD liquid crystal display
  • cathode ray tube, CRT cathode ray tube
  • Thin film transistor liquid crystal display Thin Film Transistor LCD, TFT-LCD is one of the main products of the current flat panel display, and has become an important display platform in modern information technology products (IT) and video products.
  • the main driving principle of TFT-LCD the system board connects the red/green/blue (R/G/B) compression signal, control signal and power through the conductive wire to the connector on the printed circuit board (PCB), PCB Board through the source chip in the film (Source-Chip On Film, S-COF) and gate chip in the film (Gate-Chip on Film, G-COF) is connected to the liquid crystal display area so that the liquid crystal display (LCD) obtains the required power and signals.
  • R/G/B red/green/blue
  • S-COF Source-Chip On Film
  • G-COF gate chip in the film
  • the G-COF realizes the opening and closing control of the gate in the display area by the output gate turn-on voltage (VGH) and the gate turn-off voltage (VGL).
  • VGH output gate turn-on voltage
  • VGL gate turn-off voltage
  • the G-COF needs to adopt a higher-order semiconductor process, which ultimately leads to an increase in cost. Therefore, it is necessary to develop a new type of gate driving circuit to solve the above problems.
  • the purpose of the present patent application is to provide a gate driving circuit and an array substrate thereof, through the gate signal processing module, to realize that the polar chip only needs to output a small control voltage in the film (G-COF), and Outputs a large required gate-on voltage (VGH) and gate-off voltage (VGL) to prevent breakdown inside the G-COF integrated circuit, but G-COF does not require a higher-order semiconductor process, saving production G-COF cost.
  • G-COF gate-on voltage
  • VGL gate-off voltage
  • the first embodiment of the present application provides a gate driving circuit disposed on an array substrate of a liquid crystal panel, the gate driving circuit comprising: a scan driving circuit for outputting a scan control signal
  • the scan control signal has a first level and a second level, the first level is greater than the second level;
  • a gate signal processing module is electrically connected to the scan driving circuit, and is provided with a a switch and a second switch, the gate signal processing module receiving the scan control signal, when the scan control signal received by the gate signal processing module is the first level, the gate The signal processing module turns on the first switch and turns off the second switch, so that the first switch outputs a first gate driving signal to drive a gate of a display area, or when the gate
  • the gate signal processing module turns on the second switch and turns off the first switch, so that the second The converter outputs a second gate driving signal to drive the gate of the display area, wherein a difference between the first level and the second level of the
  • the first switch is a first transistor, and is provided with a first source terminal, a first gate terminal, and a first drain terminal.
  • the first level of the scan control signal triggers the first gate terminal, and the first source terminal receives the first gate drive signal to cause the first drain terminal to output
  • the first gate drive signal is used to drive the gate of the display area.
  • the second switch is a second transistor, and is provided with a second source terminal, a second gate terminal, and a second drain terminal.
  • the second level of the scan control signal triggers the second gate terminal, and the second source terminal receives the second gate drive signal to cause the second drain terminal to output
  • the second gate drive signal is used to drive the gate of the display area.
  • the first transistor and the second transistor have opposite polarities, such that when the first transistor is turned on, the second transistor is turned off, or when the first transistor is turned off, The second transistor is turned on.
  • the first gate driving signal is a gate turn-on voltage
  • the second gate driving signal is a gate turn-off voltage
  • the gate signal processing module is disposed on a circuit of the gate chip in the thin film. structure.
  • the first level and the second level of the scan control signal are both smaller than the first gate driving signal, and the level of the second gate driving signal is smaller than the The level of the first gate drive signal.
  • the second embodiment of the present application provides an array substrate including a gate driving circuit, wherein the gate driving circuit adopts the gate driving circuit described in the first embodiment.
  • the first switch is a first transistor, and is provided with a first source terminal, a first gate terminal, and a first drain terminal.
  • the first level of the scan control signal triggers the first gate terminal, and the first source terminal receives the first gate drive signal to cause the first drain terminal to output
  • the first gate drive signal is used to drive the gate of the display area.
  • the second switch is a second transistor, and is provided with a second source terminal, a second gate terminal, and a second drain terminal.
  • the second level of the scan control signal triggers the second gate terminal, and the second source terminal receives the second gate drive signal to cause the second drain terminal to output
  • the second gate drive signal is used to drive the gate of the display area.
  • the first transistor and the second transistor have opposite polarities, such that when the first transistor is turned on, the second transistor is turned off, or when the first transistor is turned off, The second transistor is turned on.
  • the first gate driving signal is a gate turn-on voltage
  • the second gate driving signal is a gate turn-off voltage
  • the gate signal processing module is disposed on a circuit of the gate chip in the thin film. structure.
  • the first level and the second level of the scan control signal are both smaller than the first gate driving signal, and the level of the second gate driving signal is smaller than the The level of the first gate drive signal.
  • the invention prevents the internal breakdown of the G-COF integrated circuit, but the G-COF does not need to adopt a higher order semiconductor process, saving the cost of manufacturing G-COF.
  • FIG. 1 is a block schematic diagram of a gate driving circuit in accordance with an embodiment of the present patent application.
  • FIG. 2 is an equivalent circuit diagram of a gate signal processing module of a gate driving circuit according to an embodiment of the present patent application.
  • FIG. 3 is a timing diagram of waveform signals of a gate signal processing module in accordance with an embodiment of the present patent application.
  • FIG. 1 is a block schematic diagram of a gate driving circuit in accordance with an embodiment of the present patent application.
  • 2 is an equivalent circuit diagram of a gate signal processing module of a gate driving circuit according to an embodiment of the present patent application.
  • 3 is a timing diagram of waveform signals of a gate signal processing module in accordance with an embodiment of the present patent application.
  • the gate driving circuit includes a scan driving circuit 100 and a gate signal processing module 102, which are disposed on the array substrate of the liquid crystal panel, and the scan driving circuit 100 is electrically connected to the gate signal processing module 102, the gate The signal processing module 102 is electrically connected to the gate (not shown) of the display area 104.
  • the scan driving circuit 100 is configured to output a scan control signal SC having a first level VL1 and a second level VL2, the first level VL1 being greater than the second level VL2.
  • the first level VL1 is a high voltage of 3.3V, but is not limited thereto
  • the second level VL2 is a low voltage of 0V, but is not limited thereto.
  • the gate signal processing module 102 is electrically connected to the scan driving circuit, and the gate signal processing module 102 is provided with a first switch 102a and a second switch 102b, and the gate signal processing module 102 receives the scan control signal SC.
  • the scan control signal SC received by the gate signal processing module 102 is the first level VL1
  • the gate signal processing module 102 turns on the first switch 102a and turns off the second
  • the switch 102b causes the first switch 102a to output a first gate drive signal SGD1 to drive the gate of a display area 104 or the scan control signal SC received by the gate signal processing module 102.
  • the gate signal processing module 102 turns on the second switch 102b and turns off the first switch 102a, so that the second switch 102b outputs a second gate.
  • Driving the signal SGD2 to drive the gate of the display area 104 wherein a level difference between the first level VL1 and the second level VL2 of the scan control signal SC is smaller than the first gate Driving signal SGD1 and the second gate
  • the first gate driving signal SGD1 and the second gate driving signal SGD2 are voltages input to the display panel.
  • the first gate driving signal SGD1 and the second gate driving signal SGD2 are driven by a driving voltage.
  • the driving voltage generating unit is electrically connected to the first switch 102a and the second switch 102b.
  • the first switch 102a is a first transistor 102a1, and is provided with a first source terminal S1, a first gate terminal G1, and a first drain terminal D1.
  • the first level VL1 of the scan control signal SC triggers the first gate terminal G1
  • the first source terminal S1 receives the first gate drive signal SGD1 to enable the first A drain terminal D1 outputs the first gate driving signal SGD1 to drive the gate of the display region 104.
  • the second switch 102b is a second transistor 102b1, and is provided with a second source terminal S2, a second gate terminal G2, and a second drain terminal D2.
  • the second level V12 of the scan control signal SC triggers the second gate terminal G2, and the second source terminal S2 receives the second gate drive signal SGD2 to enable the The second drain terminal D2 outputs the second gate driving signal SGD2 to drive the gate of the display region 104.
  • the first transistor 102a1 and the second transistor 102b1 have opposite polarities, such that when the first transistor 102a1 is turned on, the second transistor 102b1 is turned off, or the first transistor is turned on. When 102a1 is turned off, the second transistor 102b1 is turned on.
  • the first gate driving signal SGD1 is a gate-on voltage (VGH), and the second gate driving signal SGD2 is a gate-off voltage (VGL).
  • the first level VL1 and the second level VL2 of the scan control signal SC are smaller than the first gate driving signal SGD1, and the second gate driving The level of the signal SGD2 is smaller than the level of the first gate driving signal SGD1 to prevent the internal breakdown of the G-COF integrated circuit, but the G-COF does not need to adopt a higher-order semiconductor process, thereby saving manufacturing costs.
  • the second embodiment of the present patent application provides an array substrate including a gate driving circuit, wherein the gate driving circuit includes the above-described gate driving circuit.
  • the gate driving circuit and the array substrate thereof of the patent application pass through the gate signal processing module to realize that the polar chip only needs to output a small control voltage in the thin film (G-COF), and the output requires a larger gate opening.
  • Voltage (VGH) and gate-off voltage (VGL) to prevent breakdown inside the G-COF integrated circuit, but G-COF does not require a higher-order semiconductor process, saving the cost of making G-COF.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种栅极驱动电路及其阵列基板，包括：扫描驱动电路（100）用以输出扫描控制信号（SC），所述扫描控制信号（SC）具有第一电平（VL1）以及第二电平（VL2）；栅极信号处理模块（102）设有第一切换器（102a）以及第二切换器（102b），所述栅极信号处理模块（102）接收所述扫描控制信号（SC），当为所述第一电平（VL1）时，通过所述第一切换器（102a）开启并且关闭所述第二切换器（102b），使所述第一切换器（102a）输出第一栅极驱动信号（SGD1）以驱动一显示区域（104）的栅极，或是当为所述第二电平（VL2）时，通过所述第二切换器（102b）开启并且关闭所述第一切换器（102a），使所述第二切换器（102b）输出第二栅极驱动信号（SGD2）以驱动所述显示区域（104）的栅极。实现栅极芯片在薄膜（G-COF）仅需要输出较小的控制电压，而输出较大的所需栅极开启电压（VGH）以及栅极关闭电压（VGL）。

Description

栅极驱动电路及其阵列基板 技术领域
本专利申请涉及一种液晶显示器技术领域，且特别是涉及一种栅极驱动电路及其阵列基板，用于液晶显示器。
 背景技术
由于液晶显示器(liquid crystal display, LCD)具有低辐射、体积小及低耗能等优点，因此逐渐取代传统的阴极射线管(cathode ray tube, CRT)显示器，广泛地应用在笔记型计算机、个人数字助理(personal digital assistant, PDA)、平面电视，或行动电话等信息产品上。
薄膜晶体管液晶显示器(Thin Film Transistor LCD，TFT-LCD)是当前平板显示的主要产品之一，已经成为了现代信息科技产品(IT)以及视讯产品中重要的显示平台。TFT-LCD主要驱动原理，系统主板将红/绿/蓝(R/G/B)压缩信号、控制信号及动力通过导电线材与印刷电路板(PCB)上的连接器(connector)相连接，PCB板通过源极芯片在薄膜(Source-Chip on Film, S-COF）和栅极芯片在薄膜(Gate-Chip on Film, G-COF）与液晶显示区相连接，从而使得液晶显示器(LCD)获得所需的电源以及信号。
其中，G-COF通过输出栅极开启电压（VGH）以及栅极关闭电压（VGL）实现对显示区域内的栅极的开启关闭控制。随着VGH和VGL的电压差的增大，为防止G-COF集成电路内部被击穿，G-COF需要采取更高阶的半导体制程，最终导致成本的上升。因此需要发展一种新式的栅极驱动电路，以解决上述问题。
 技术问题
有鉴于此，本专利申请的目的在于提供一种栅极驱动电路及其阵列基板，通过栅极信号处理模块，以实现极芯片在薄膜(G-COF)仅需要输出较小的控制电压，而输出较大的所需栅极开启电压（VGH）以及栅极关闭电压(VGL)，以防止G-COF集成电路内部被击穿，但是G-COF不需要采取更高阶的半导体制程，节省制作G-COF成本。
 技术解决方案
为达到上述发明目的，本专利申请第一实施例中提供一种栅极驱动电路，设置于液晶面板的阵列基板上，所述栅极驱动电路包括：一扫描驱动电路，用以输出扫描控制信号，所述扫描控制信号具有第一电平以及第二电平，所述第一电平大于所述第二电平；一栅极信号处理模块，电性连接所述扫描驱动电路，设有第一切换器以及第二切换器，所述栅极信号处理模块接收所述扫描控制信号，当所述栅极信号处理模块接收的所述扫描控制信号为所述第一电平时，所述栅极信号处理模块开启所述第一切换器并且关闭所述第二切换器，使所述第一切换器输出一第一栅极驱动信号以驱动一显示区域的栅极，或是当所述栅极信号处理模块接收的所述扫描控制信号为所述第二电平时，所述栅极信号处理模块开启所述第二切换器并且关闭所述第一切换器，使所述第二切换器输出一第二栅极驱动信号以驱动所述显示区域的栅极，其中所述扫描控制信号的所述第一电平与所述第二电平间的电平差值小于所述第一栅极驱动信号与所述第二栅极驱动信号间的电平差值。
在一实施例中，所述第一切换器为第一晶体管，设有第一源极端、第一栅极端以及第一漏极端。
在一实施例中，所述扫描控制信号的第一电平触发所述第一栅极端，所述第一源极端接收所述第一栅极驱动信号，以使所述第一漏极端输出所述第一栅极驱动信号以驱动所述显示区域的栅极。
在一实施例中，所述第二切换器为第二晶体管，设有第二源极端、第二栅极端以及第二漏极端。
在一实施例中，所述扫描控制信号的第二电平触发所述第二栅极端，所述第二源极端接收所述第二栅极驱动信号，以使所述第二漏极端输出所述第二栅极驱动信号以驱动所述显示区域的栅极。
在一实施例中，所述第一晶体管以及所述第二晶体管的极性相反，使所述第一晶体管开启时，所述第二晶体管关闭，或是使所述第一晶体管关闭时，所述第二晶体管开启。
在一实施例中，所述第一栅极驱动信号为栅极开启电压，所述第二栅极驱动信号为栅极关闭电压，所述栅极信号处理模块设置于栅极芯片在薄膜的电路结构。
在一实施例中，所述扫描控制信号的所述第一电平以及所述第二电平皆小于所述第一栅极驱动信号，所述第二栅极驱动信号的电平小于所述第一栅极驱动信号的电平。
本专利申请第二实施例中提供一种阵列基板，包括栅极驱动电路，其中所述栅极驱动电路采用上述第一实施例所述的栅极驱动电路。
在一实施例中，所述第一切换器为第一晶体管，设有第一源极端、第一栅极端以及第一漏极端。
在一实施例中，所述扫描控制信号的第一电平触发所述第一栅极端，所述第一源极端接收所述第一栅极驱动信号，以使所述第一漏极端输出所述第一栅极驱动信号以驱动所述显示区域的栅极。
在一实施例中，所述第二切换器为第二晶体管，设有第二源极端、第二栅极端以及第二漏极端。
在一实施例中，所述扫描控制信号的第二电平触发所述第二栅极端，所述第二源极端接收所述第二栅极驱动信号，以使所述第二漏极端输出所述第二栅极驱动信号以驱动所述显示区域的栅极。
在一实施例中，所述第一晶体管以及所述第二晶体管的极性相反，使所述第一晶体管开启时，所述第二晶体管关闭，或是使所述第一晶体管关闭时，所述第二晶体管开启。
在一实施例中，所述第一栅极驱动信号为栅极开启电压，所述第二栅极驱动信号为栅极关闭电压，所述栅极信号处理模块设置于栅极芯片在薄膜的电路结构。
在一实施例中，所述扫描控制信号的所述第一电平以及所述第二电平皆小于所述第一栅极驱动信号，所述第二栅极驱动信号的电平小于所述第一栅极驱动信号的电平。
 有益效果
本发明防止G-COF集成电路内部被击穿，但是G-COF不需要采取更高阶的半导体制程，节省制作G-COF成本。
附图说明
图1:为根据本专利申请实施例中栅极驱动电路的方框示意图。
图2:为根据本专利申请实施例中栅极驱动电路的栅极信号处理模块的等效电路示意图。
图3:为根据本专利申请实施例中栅极信号处理模块的波形信号时序图。
 本发明的最佳实施方式
本专利申请说明书提供不同的实施例来说明本专利申请不同实施方式的技术特征。实施例中的各组件的配置是为了清楚说明本专利申请揭示的内容，并非用以限制本专利申请。在不同的图式中，相同的组件符号表示相同或相似的组件。
参考图1至图3，图1为根据本专利申请实施例中栅极驱动电路的方框示意图。图2为根据本专利申请实施例中栅极驱动电路的栅极信号处理模块的等效电路示意图。图3为根据本专利申请实施例中栅极信号处理模块的波形信号时序图。所述栅极驱动电路包括扫描驱动电路100以及栅极信号处理模块102，设置于液晶面板的阵列基板上，所述扫描驱动电路100电性连接所述栅极信号处理模块102，所述栅极信号处理模块102电性连接显示区域104的栅极(未图示)。扫描驱动电路100用以输出扫描控制信号SC，所述扫描控制信号SC具有第一电平VL1以及第二电平VL2，所述第一电平VL1大于所述第二电平VL2。在一实施例中，所述第一电平VL1为高电压3.3V，但不限于此，所述第二电平VL2为低电压0V，但不限于此。
栅极信号处理模块102电性连接所述扫描驱动电路，栅极信号处理模块102设有第一切换器102a以及第二切换器102b，所述栅极信号处理模块102接收所述扫描控制信号SC，当所述栅极信号处理模块102接收的所述扫描控制信号SC为所述第一电平VL1时，所述栅极信号处理模块102开启所述第一切换器102a并且关闭所述第二切换器102b，使所述第一切换器102a输出一第一栅极驱动信号SGD1以驱动一显示区域104的栅极，或是当所述栅极信号处理模块102接收的所述扫描控制信号SC为所述第二电平VL2时，所述栅极信号处理模块102开启所述第二切换器102b并且关闭所述第一切换器102a，使所述第二切换器102b输出一第二栅极驱动信号SGD2以驱动所述显示区域104的栅极，其中所述扫描控制信号SC的所述第一电平VL1与所述第二电平VL2间的电平差值小于所述第一栅极驱动信号SGD1与所述第二栅极驱动信号SGD2间的电平差值。换言之，第一栅极驱动信号SGD1以及第二栅极驱动信号SGD2为输入显示面板的电压，在一实施例中，第一栅极驱动信号SGD1以及第二栅极驱动信号SGD2是由一驱动电压产生单元(未图示)所提供，驱动电压产生单元电性连接第一切换器102a以及第二切换器102b。
在一实施例中，所述第一切换器102a为第一晶体管102a1，设有第一源极端S1、第一栅极端G1以及第一漏极端D1。在一实施例中，所述扫描控制信号SC的第一电平VL1触发所述第一栅极端G1，所述第一源极端S1接收所述第一栅极驱动信号SGD1，以使所述第一漏极端D1输出所述第一栅极驱动信号SGD1以驱动所述显示区域104的栅极。
在一实施例中，所述第二切换器102b为第二晶体管102b1，设有第二源极端S2、第二栅极端G2以及第二漏极端D2。在一实施例中，所述扫描控制信号SC的第二电平Vl2触发所述第二栅极端G2，所述第二源极端S2接收所述第二栅极驱动信号SGD2，以使所述第二漏极端D2输出所述第二栅极驱动信号SGD2以驱动所述显示区域104的栅极。
在一实施例中，所述第一晶体管102a1以及所述第二晶体管102b1的极性相反，使所述第一晶体管102a1开启时，所述第二晶体管102b1关闭，或是使所述第一晶体管102a1关闭时，所述第二晶体管102b1开启。
在一实施例中，所述第一栅极驱动信号SGD1为栅极开启电压（VGH），所述第二栅极驱动信号SGD2为栅极关闭电压（VGL）。
在一相对应的周期T内，所述扫描控制信号SC的所述第一电平VL1以及所述第二电平VL2皆小于所述第一栅极驱动信号SGD1，所述第二栅极驱动信号SGD2的电平小于所述第一栅极驱动信号SGD1的电平，以防止G-COF集成电路内部被击穿，但是G-COF不需要采取更高阶的半导体制程，节省制作成本。
本专利申请第二实施例中提供一种阵列基板，包括栅极驱动电路，其中所述栅极驱动电路包括上述的栅极驱动电路。
本专利申请之栅极驱动电路及其阵列基板，通过栅极信号处理模块，以实现极芯片在薄膜(G-COF)仅需要输出较小的控制电压，而输出较大的所需栅极开启电压（VGH）以及栅极关闭电压(VGL)，以防止G-COF集成电路内部被击穿，但是G-COF不需要采取更高阶的半导体制程，节省制作G-COF成本。
虽然本专利申请已用较佳实施例揭露如上，然其
Figure 5e77
非用以限定本专利申请，本专利申请所属技术领域中具有通常知识者，在不脱离本专利申请的精神和范围内，当可作各种的更动与润饰，因此本专利申请的保护范围当视后附的权利要求范围所界定者为准。

Claims (9)

  1. 一种栅极驱动电路，设置于液晶面板的阵列基板上，其中所述栅极驱动电路包括：
    一扫描驱动电路，用以输出扫描控制信号，所述扫描控制信号具有第一电平以及第二电平，所述第一电平大于所述第二电平；
    一栅极信号处理模块，电性连接所述扫描驱动电路，设有第一切换器以及第二切换器，所述栅极信号处理模块接收所述扫描控制信号，当所述栅极信号处理模块接收的所述扫描控制信号为所述第一电平时，所述栅极信号处理模块开启所述第一切换器并且关闭所述第二切换器，使所述第一切换器输出一第一栅极驱动信号以驱动一显示区域的栅极，或是当所述栅极信号处理模块接收的所述扫描控制信号为所述第二电平时，所述栅极信号处理模块开启所述第二切换器并且关闭所述第一切换器，使所述第二切换器输出一第二栅极驱动信号以驱动所述显示区域的栅极，其中所述扫描控制信号的所述第一电平与所述第二电平间的电平差值小于所述第一栅极驱动信号与所述第二栅极驱动信号间的电平差值。
  2. 根据权利要求1所述的栅极驱动电路，其中所述第一切换器为第一晶体管，设有第一源极端、第一栅极端以及第一漏极端。
  3. 根据权利要求2所述的栅极驱动电路，其中所述扫描控制信号的第一电平触发所述第一栅极端，所述第一源极端接收所述第一栅极驱动信号，以使所述第一漏极端输出所述第一栅极驱动信号以驱动所述显示区域的栅极。
  4. 根据权利要求2所述的栅极驱动电路，其中所述第二切换器为第二晶体管，设有第二源极端、第二栅极端以及第二漏极端。
  5. 根据权利要求4所述的栅极驱动电路，其中所述扫描控制信号的第二电平触发所述第二栅极端，所述第二源极端接收所述第二栅极驱动信号，以使所述第二漏极端输出所述第二栅极驱动信号以驱动所述显示区域的栅极。
  6. 根据权利要求4所述的栅极驱动电路，其中所述第一晶体管以及所述第二晶体管的极性相反，使所述第一晶体管开启时，所述第二晶体管关闭，或是使所述第一晶体管关闭时，所述第二晶体管开启。
  7. 根据权利要求1所述的栅极驱动电路，其中所述第一栅极驱动信号为栅极开启电压，所述第二栅极驱动信号为栅极关闭电压，所述栅极信号处理模块设置于栅极芯片在薄膜的电路结构。
  8. 根据权利要求1所述的栅极驱动电路，其中所述扫描控制信号的所述第一电平以及所述第二电平皆小于所述第一栅极驱动信号，所述第二栅极驱动信号的电平小于所述第一栅极驱动信号的电平。
  9. 一种阵列基板，包括栅极驱动电路，其中所述栅极驱动电路采用权利要求1-8中任意一项所述的栅极驱动电路。
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