WO2017096649A1 - 阵列基板及其制造方法 - Google Patents

阵列基板及其制造方法 Download PDF

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Publication number
WO2017096649A1
WO2017096649A1 PCT/CN2015/098964 CN2015098964W WO2017096649A1 WO 2017096649 A1 WO2017096649 A1 WO 2017096649A1 CN 2015098964 W CN2015098964 W CN 2015098964W WO 2017096649 A1 WO2017096649 A1 WO 2017096649A1
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Prior art keywords
channel
transistor
metal layer
electrode strip
pattern
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French (fr)
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徐洪远
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/20—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising components having an active region that includes an inorganic semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a method of fabricating the same.
  • CMOS ring oscillator composed of a plurality of CMOS (Complementary Metal Oxide Semiconductor) inverters is used to generate a clock signal in a circuit.
  • CMOS Complementary Metal Oxide Semiconductor
  • a CMOS inverter is composed of a P-type MOS transistor and an N-type MOS transistor in series, wherein a P-type MOS transistor is used as a load transistor and an N-type MOS transistor is used as a The input tube and one of the two MOS transistors are always off, so this configuration can significantly reduce power consumption.
  • the CMOS inverter has a low resistance and its processing rate can be improved.
  • IGZO Indium Gallium Zinc Oxide
  • AOS amorphous thin film transistors
  • OSC Organic Semiconductor, organic Semiconductor
  • CMOS ring oscillators are problems that the industry needs to solve when improving LCDs.
  • the present invention provides an array substrate and a method of fabricating the same, which are capable of fabricating a CMOS inverter or a CMOS ring oscillator based on IGZO and OSC.
  • the invention provides a method for manufacturing an array substrate, comprising: sequentially forming a common electrode and an insulating layer staggered along a predetermined direction on a substrate substrate, wherein the first metal layer comprises spacing along a predetermined direction. a first electrode strip and a second electrode strip, each common electrode being located between the adjacent first electrode strip and the second electrode strip, the second metal layer and the insulating layer of the common electrode and the corresponding region forming a capacitor; Forming an IGZO pattern spaced along the predetermined direction on the insulating layer, The IGZO pattern is located above the first electrode strip; a second metal layer is formed on the insulating layer and the IGZO pattern layer, and the second metal layer is formed with a first channel and a second channel staggered in a predetermined direction, the first trench The IGZO pattern of the corresponding region is exposed, the second channel exposes the insulating layer of the corresponding region and is located above the second electrode strip; the OSC pattern is formed in the corresponding region of the second channel
  • the invention provides a method for manufacturing an array substrate, comprising: sequentially forming a first metal layer and an insulating layer on a substrate substrate, wherein the first metal layer comprises first electrode strips and second electrodes arranged at intervals in a predetermined direction And forming an IGZO pattern arranged along the predetermined direction on the insulating layer, the IGZO pattern is located above the first electrode strip; forming a second metal layer on the insulating layer and the IGZO pattern layer, the second metal layer being formed along a predetermined direction a first channel and a second channel staggered, the first channel exposing an IGZO pattern of its corresponding region, the second channel exposing an insulating layer of the corresponding region and located above the second electrode strip; Corresponding regions of the track form an OSC pattern; forming a flat passivation layer on the insulating layer, the second metal layer, the IGZO pattern, and the OSC pattern; wherein, the first electrode strip, the first channel, and the second metal layer of the corresponding region
  • the first electrode strip and the second electrode strip are gates of the thin film transistor of the array substrate, and the second metal layer comprises a source and a drain of the thin film transistor, in a predetermined direction, adjacent to the source and the drain A first channel and a second channel are formed, and the same drain is located between the adjacent first channel and the second channel.
  • the source, the drain, and the IGZO pattern of the first electrode strip, the first channel and the corresponding region thereof form a first transistor, a source, a drain, and an OSC of the second electrode strip, the second channel, and corresponding regions thereof
  • the pattern forms a second transistor
  • the array substrate forms an odd number of CMOS inverters connected end to end.
  • the first transistor is an N-channel MOS transistor
  • the second transistor is a P-channel type MOS transistor.
  • the method further comprises: forming common electrodes staggered in a predetermined direction on the substrate substrate, each common electrode being located adjacent to the first electrode strip Between the second electrode strip and the second metal layer and the insulating layer of the common electrode and its corresponding region form a capacitor.
  • An array substrate provided by the present invention comprises: a substrate substrate; a first metal layer and an insulating layer formed on the substrate substrate, the first metal layer comprising a first electrode strip and a plurality of rows arranged in a predetermined direction a second electrode strip; an IGZO pattern formed on the insulating layer and spaced apart in a predetermined direction, the IGZO pattern being located above the first electrode strip; a second metal layer formed on the insulating layer and the IGZO pattern layer, the second metal layer being formed a first channel and a second channel staggered along a predetermined direction, the first channel exposing an IGZO pattern of its corresponding region, the second channel exposing an insulating layer of the corresponding region and located above the second electrode strip; An OSC pattern formed on a corresponding region of the second channel; a flat passivation layer formed on the insulating layer, the second metal layer, the IGZO pattern, and the OSC pattern; wherein the first electrode strip, the first channel, and the corresponding region thereof
  • the first electrode strip and the second electrode strip are gates of the thin film transistor of the array substrate, and the second metal layer comprises a source and a drain of the thin film transistor, in a predetermined direction, adjacent to the source and the drain A first channel and a second channel are formed therebetween, and the same drain is located between the adjacent first channel and the second channel.
  • the source, the drain, and the IGZO pattern of the first electrode strip, the first channel and the corresponding region thereof form a first transistor, a source, a drain, and an OSC of the second electrode strip, the second channel, and corresponding regions thereof
  • the pattern forms a second transistor, and the array substrate is formed with an odd number of CMOS inverters connected end to end.
  • the first transistor is an N-channel MOS transistor
  • the second transistor is a P-channel MOS transistor.
  • the array substrate further includes a common electrode formed on the substrate substrate and staggered in a predetermined direction, each common electrode being located between the adjacent first electrode strip and the second electrode strip, the common electrode and the corresponding region thereof
  • the second metal layer and the insulating layer form a capacitor.
  • the first transistor of the CMOS inverter formed by the IGZO pattern and its corresponding region, the first channel and the second metal layer are formed by the OSC
  • the second electrode strip, the second channel, and the second metal layer of the pattern and its corresponding region form a second transistor of the CMOS inverter, thereby realizing fabrication of a CMOS inverter or a CMOS ring oscillator based on IGZO and OSC.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for fabricating an array substrate of the present invention
  • FIG. 2 is a schematic view of forming an array substrate according to the method shown in FIG. 1;
  • FIG. 3 is a circuit diagram of an embodiment of a CMOS inverter of the present invention.
  • FIG. 4 is a circuit diagram of a CMOS ring oscillator constructed by the CMOS inverter shown in FIG. 3;
  • FIG. 5 is a schematic diagram of timing signals outputted by the CMOS ring oscillator shown in FIG. 4;
  • Figure 6 is a schematic view showing an embodiment of forming a protective layer on IGZO
  • Figure 7 is a cross-sectional view showing the structure of an embodiment of a liquid crystal display panel of the present invention.
  • Figure 8 is a cross-sectional view showing the structure of an embodiment of a liquid crystal display device of the present invention.
  • Fig. 1 is a flow chart showing an embodiment of a method for fabricating an array substrate of the present invention.
  • the method is for forming a CMOS inverter or a CMOS ring oscillator while forming a TFT.
  • the method includes the following:
  • S11 sequentially forming a first metal layer and an insulating layer on the substrate substrate, the first metal layer comprising first electrode strips and second electrode strips arranged at intervals in a predetermined direction;
  • the substrate substrate 21 is used to form the aforementioned array substrate, and the substrate substrate 21 may be a glass substrate, a transparent plastic substrate or a flexible substrate.
  • the first metal layer 22 can be formed on the substrate substrate 21 by the first mask process and the first yellow light process, that is, the gate of the TFT having the predetermined pattern is formed, wherein the gate of the TFT is included in the figure.
  • the first electrode strip 221 and the second electrode strip 222 are arranged in a predetermined direction D indicated by an arrow (only one first electrode strip 221 and one second electrode strip 222 are shown in the drawing), and the predetermined direction D is The direction in which the gate extends is perpendicular to the horizontal direction.
  • the first metal layer 22 can also be directly formed using only methods such as chemical vapor deposition, vacuum evaporation, plasma chemical vapor deposition, sputtering, or low pressure chemical vapor deposition.
  • the embodiment of the present invention further forms the insulating layer 23, that is, the gate insulating layer, on the first metal layer 22 and the substrate substrate 21 on which the first metal layer 22 is not formed.
  • Gate Insulation Layer, GI Gate Insulation Layer
  • the common electrode 24 staggered in the predetermined direction D may be formed on the substrate substrate 21 (only one common electrode 24 is shown), and each common The electrode 24 is located between the adjacent first electrode strip 221 and the second electrode strip 222.
  • the first metal layer 22 and the common electrode 24 may be formed by the first mask process and the first yellow light process, that is, the common electrode 24 and the first metal layer 22 are processed by the same mask and the same yellow. Light process is made.
  • an IGZO pattern (layer) 25 having a predetermined pattern may be formed on the insulating layer 23 by the second mask process and the second yellow light process, wherein the second yellow light process may utilize, but not limited to, having phosphoric acid, An etchant of nitric acid, acetic acid, and deionized water etches a whole semiconductor pattern layer 24 formed on the insulating layer 23 to obtain the IGZO pattern 25.
  • the second yellow light process may utilize, but not limited to, having phosphoric acid, An etchant of nitric acid, acetic acid, and deionized water etches a whole semiconductor pattern layer 24 formed on the insulating layer 23 to obtain the IGZO pattern 25.
  • other embodiments may employ dry etching.
  • S13 forming a second metal layer on the insulating layer and the IGZO pattern layer, the second metal layer being formed with a first channel and a second channel staggered in a predetermined direction, the first channel exposing an IGZO pattern of the corresponding region thereof The second channel exposes the insulating layer of its corresponding region and is located above the second electrode strip.
  • the second metal layer 26 having a predetermined pattern may be formed on the insulating layer 23 by the third mask process and the third yellow light process, that is, the source/drain electrode layer of the TFT is formed, and the second metal layer 26 includes the source. 261 and drain 262.
  • a first channel 263 and a second channel 264 are formed between adjacent source 261 and drain 262 along a predetermined direction D, and the same drain 262 is located adjacent to the first channel 263 and the second channel Between 264, the first channel 263 is located above the first electrode strip 221, and the second channel 264 is located above the second electrode strip 222.
  • an OSC pattern (layer) 27 may be formed in a corresponding region of the second channel 364 by a fourth mask process and a fourth yellow light process. Referring to FIG. 2, the height of the OSC pattern 27 is high. The degree is greater than the height of the second metal layer 26, and a portion of the OSC pattern 27 that is higher than the second metal layer 26 overlies the source 261 and the drain 262.
  • the planar passivation layer 28 may be formed on the insulating layer 23, the second metal layer 26, the IGZO pattern 25, and the OSC pattern 27 by any combination of chemical vapor deposition, atomic layer epitaxy, coating, sputtering, and evaporation.
  • the flat passivation layer 28 is used to protect the above structural elements on the array substrate from external environmental factors.
  • the materials of the flat passivation layer 28 and the insulating layer 23 may be the same or different.
  • the first electrode strips 221, 263 and the first channel corresponding to a source region 261, the drain of the first transistor M 1 262 and the IGZO pattern 25 is formed, a second electrode strips 222, the The second channel 264 and its corresponding region of the source 261, the drain 262 and the OSC pattern 27 form a second transistor M 2 , the first transistor M 1 is an N-channel MOS transistor, and the second transistor M 2 is a P-channel type
  • the MOS transistor, and the first transistor M 1 and the second transistor M 2 are connected in series to form the CMOS inverter 30 shown in FIG. Further, the common electrode 24 and the drain region 262 corresponding to the insulating layer 23 is formed, and a capacitor C L.
  • first electrode and the second electrode strips 221 bar 222 are a first transistor M 1 and M 2 of the gate of the second transistor, a gate connected to the array substrate of both the input voltage V in; adjacent two source 261 are the source of the first transistor M 1 and the second transistor M 2 respectively , the source of the first transistor M 1 is grounded, and the source of the second transistor M 2 is connected to the power supply voltage V dd of the array substrate (also referred to as VDD);
  • the adjacent two drains 262 are the drains of the first transistor M 1 and the second transistor M 2 , respectively, and the drains of the two are used to output the output voltage V out of the array substrate.
  • the output voltage V out When the input voltage V in is low, the output voltage V out is at a high level; when the input voltage V in is at a high level, the output voltage V out is at a low level.
  • an embodiment of the present invention forms an odd number of end-to-end CMOS inverters 30 on an array substrate.
  • the end-to-end connection means that an input end of each CMOS inverter 30 is connected to a CMOS inverter 30.
  • the output terminal that is, the output voltage V out of each CMOS inverter 30 is used as the input voltage V in of the next CMOS inverter 30, and the odd-numbered CMOS inverters 30 are connected end to end to form the CMOS ring oscillator 40 of the array substrate.
  • the CMOS ring oscillator can output the power supply voltage V dd of the array substrate as a clock signal. Referring to FIG. 5, the clock signal has a period T, and the period T conforms to the following relationship.
  • n is the number of CMOS inverters 30, C L is the size of the capacitor, and V t is the threshold voltage at which the first transistor M 1 and the second transistor M 2 are switched between on and off, ⁇ n , ⁇ p is a correlation parameter of the IGZO pattern 25 and the OSC pattern 27, respectively, which is related to parameters such as electron mobility, width to length ratio of the material.
  • CMOS inverter 30 of the embodiment of the present invention has the same working principle as the CMOS inverter of the prior art, and related parameters in the relationship may be referred to the prior art, and details are not described herein.
  • the embodiment of the present invention manufactures a CMOS inverter 30 or a CMOS ring oscillator based on IGZO and OSC, and the manufacturing materials are IGZO and OSC. Therefore, the prepared array substrate has low static power consumption, strong anti-interference ability, and power utilization rate. Higher advantages.
  • the masks used in the first to fourth mask processes are different.
  • the mask processes and the first to fourth yellow processes can be referred to the prior art, and are not described herein.
  • an embodiment of the present invention can form a protective layer 60, also referred to as a water-oxygen barrier layer or an etch stop layer (ESL), on the IGZO pattern 25 shown in FIG.
  • the protective layer 60 serves to ensure the electrical properties of the IGZO channel, in which case the first channel 263 exposes the protective layer 60 of its corresponding region instead of the IGZO pattern 25.
  • the embodiment of the present invention further provides an array substrate having the structure shown in FIG. 2 which is obtained by the above method, and a manufacturing method of other structures of the array substrate can be referred to the prior art.
  • the embodiment of the present invention further provides a liquid crystal display panel 70 shown in FIG. 7 , which includes an array substrate 71 and a color filter substrate 72 disposed at a relatively spaced interval, and a liquid crystal layer 73 interposed between the array substrate 71 and the color filter substrate 72 .
  • the array substrate 71 can be produced by the above method.
  • the embodiment of the present invention further provides a liquid crystal display device 80 shown in FIG. 8 , which includes the liquid crystal display panel 70 shown in FIG. 7 and other components, such as a backlight module 81 and a front frame assembly 82 .
  • a liquid crystal display device 80 shown in FIG. 8 which includes the liquid crystal display panel 70 shown in FIG. 7 and other components, such as a backlight module 81 and a front frame assembly 82 .
  • other structures refer to the prior art, and details are not described herein again.

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  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
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  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
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Abstract

一种阵列基板及其制造方法，由IGZO图案（25）及其对应区域的第一电极条（221）、第一沟道（263）和第二金属层（26）形成CMOS反相器（30）的第一晶体管（M1）、由OSC图案（27）及其对应区域的第二电极条（222）、第二沟道（264）和第二金属层（26）形成CMOS反相器（30）的第二晶体管（M2），从而实现基于IGZO和OSC制造阵列基板的CMOS反相器（30）或CMOS环形振荡器（40）。

Description

阵列基板及其制造方法 【技术领域】
本发明涉及显示技术领域，具体涉及一种阵列基板及其制造方法。
【背景技术】
在LCD(Liquid Crystal Display，液晶显示器)的结构设计中，由多个CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)反相器构成的CMOS环形振荡器用于产生电路中的时钟信号。与传统的NMOS型反相器和PMOS型反相器相比，CMOS反相器由一个P型MOS晶体管和一个N型MOS晶体管串联组成，其中P型MOS晶体管作为负载管，N型MOS晶体管作为输入管，并且两个MOS晶体管中的一个总是截止的，因此这种配置可以大幅降低功耗。另外，CMOS反相器的电阻较低，其处理速率也能得到很好的提高。
当前，业界普遍采用IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)制备TFT(Thin Film Transistor，薄膜晶体管)的非晶态氧化半导体图案(Amorphous Oxide Semiconductor，AOS)，并且OSC(Organic Semiconductor，有机半导体)是一种由小分子或高分子聚合物组成的有机材料，具有可饶、制程成本低的特点，广泛应用于柔性显示器、电子皮肤等领域，因此如何基于IGZO和OSC制造CMOS反相器或CMOS环形振荡器是业界在改良LCD时需要解决的问题。
【发明内容】
有鉴于此，本发明提供一种阵列基板及其制造方法，能够基于IGZO和OSC制造CMOS反相器或CMOS环形振荡器。
本发明提供的一种阵列基板的制造方法，包括：在衬底基材上依次形成第一金属层沿预定方向交错排布的公共电极和绝缘层，第一金属层包括沿预定方向间隔排布的第一电极条和第二电极条，每一公共电极位于相邻的第一电极条和第二电极条之间，公共电极及其对应区域的第二金属层和绝缘层形成一电容；在绝缘层上形成沿预定方向间隔排布的IGZO图案， IGZO图案位于第一电极条的上方；在绝缘层和IGZO图案层上形成第二金属层，第二金属层形成有沿预定方向交错排布的第一沟道和第二沟道，第一沟道暴露其对应区域的IGZO图案，第二沟道暴露其对应区域的绝缘层且位于第二电极条的上方；在第二沟道的对应区域形成OSC图案；在绝缘层、第二金属层、IGZO图案以及OSC图案上形成一平坦钝化层；其中，第一电极条、第一沟道及其对应区域的第二金属层和IGZO图案形成第一晶体管，第二电极条、第二沟道及其对应区域的第二金属层和所述OSC图案形成第二晶体管，且第一晶体管和第二晶体管串联形成一CMOS反相器，第一电极条和第二电极条均为阵列基板的薄膜晶体管的栅极，第二金属层包括薄膜晶体管的源极和漏极，沿预定方向，在相邻的源极和漏极之间形成第一沟道和第二沟道，且同一漏极位于相邻的第一沟道和第二沟道之间。
本发明提供的一种阵列基板的制造方法，包括：在衬底基材上依次形成第一金属层和绝缘层，第一金属层包括沿预定方向间隔排布的第一电极条和第二电极条；在绝缘层上形成沿预定方向间隔排布的IGZO图案，IGZO图案位于第一电极条的上方；在绝缘层和IGZO图案层上形成第二金属层，第二金属层形成有沿预定方向交错排布的第一沟道和第二沟道，第一沟道暴露其对应区域的IGZO图案，第二沟道暴露其对应区域的绝缘层且位于第二电极条的上方；在第二沟道的对应区域形成OSC图案；在绝缘层、第二金属层、IGZO图案以及OSC图案上形成一平坦钝化层；其中，第一电极条、第一沟道及其对应区域的第二金属层和IGZO图案形成第一晶体管，第二电极条、第二沟道及其对应区域的第二金属层和所述OSC图案形成第二晶体管，且第一晶体管和第二晶体管串联形成一CMOS反相器。
其中，第一电极条和第二电极条均为阵列基板的薄膜晶体管的栅极，第二金属层包括薄膜晶体管的源极和漏极，沿预定方向，在相邻的源极和漏极之间形成第一沟道和第二沟道，且同一漏极位于相邻的第一沟道和第二沟道之间。
其中，第一电极条、第一沟道及其对应区域的源极、漏极和IGZO图案形成第一晶体管，第二电极条、第二沟道及其对应区域的源极、漏极和OSC图案形成第二晶体管，且阵列基板形成奇数个首尾相连的CMOS反相器。
其中，第一晶体管为N沟道型MOS晶体管，第二晶体管为P沟道型 MOS晶体管。
其中，在衬底基材上形成第一金属层之后，所述方法还包括：在衬底基材上形成沿预定方向交错排布的公共电极，每一公共电极位于相邻的第一电极条和第二电极条之间，公共电极及其对应区域的第二金属层和绝缘层形成一电容。
本发明提供的一种阵列基板，包括：衬底基材；形成于衬底基材上的第一金属层和绝缘层，第一金属层包括沿预定方向间隔排布的第一电极条和第二电极条；形成于绝缘层上且沿预定方向间隔排布的IGZO图案，IGZO图案位于第一电极条的上方；形成于绝缘层和IGZO图案层上的第二金属层，第二金属层形成有沿预定方向交错排布的第一沟道和第二沟道，第一沟道暴露其对应区域的IGZO图案，第二沟道暴露其对应区域的绝缘层且位于第二电极条的上方；形成于第二沟道的对应区域的OSC图案；平坦钝化层，形成于绝缘层、第二金属层、IGZO图案以及OSC图案上；其中，第一电极条、第一沟道及其对应区域的第二金属层和IGZO图案形成第一晶体管，第二电极条、第二沟道及其对应区域的第二金属层和OSC图案形成第二晶体管，且第一晶体管和第二晶体管串联形成一CMOS反相器。
其中，第一电极条和第二电极条均为阵列基板的薄膜晶体管的栅极，第二金属层包括薄膜晶体管的源极和漏极，沿预定方向，在相邻的源极和漏极之间形成有第一沟道和第二沟道，且同一漏极位于相邻的第一沟道和第二沟道之间。
其中，第一电极条、第一沟道及其对应区域的源极、漏极和IGZO图案形成第一晶体管，第二电极条、第二沟道及其对应区域的源极、漏极和OSC图案形成第二晶体管，且阵列基板形成有奇数个首尾相连的CMOS反相器。
其中，第一晶体管为N沟道型MOS晶体管，第二晶体管为P沟道型MOS晶体管。
其中，阵列基板还包括形成于衬底基材上且沿预定方向交错排布的公共电极，每一公共电极位于相邻的第一电极条和第二电极条之间，公共电极及其对应区域的第二金属层和绝缘层形成一电容。
本发明的阵列基板及其制造方法，设计由IGZO图案及其对应区域的第一电极条、第一沟道和第二金属层形成CMOS反相器的第一晶体管、由OSC 图案及其对应区域的第二电极条、第二沟道和第二金属层形成CMOS反相器的第二晶体管，从而实现基于IGZO和OSC制造CMOS反相器或CMOS环形振荡器。
【附图说明】
图1是本发明的阵列基板的制造方法一实施例的流程示意图；
图2是根据图1所示方法形成阵列基板的示意图；
图3是本发明的CMOS反相器一实施例的电路示意图；
图4是由图3所示CMOS反相器构成的CMOS环形振荡器的电路示意图；
图5是图4所示CMOS环形振荡器输出的时序信号的示意图；
图6是在IGZO上形成保护层一实施例的示意图；
图7是本发明的液晶显示面板一实施例的结构剖视图；
图8是本发明的液晶显示装置一实施例的结构剖视图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明所提供的示例性的实施例的技术方案进行清楚、完整地描述。
图1是本发明的阵列基板的制造方法一实施例的流程示意图。所述方法用于在形成TFT的同时形成CMOS反相器或CMOS环形振荡器。请参阅图1和图2所示，所述方法包括以下：
S11：在衬底基材上依次形成第一金属层和绝缘层，第一金属层包括沿预定方向间隔排布的第一电极条和第二电极条；
参阅图2所示，衬底基材21用于形成前述阵列基板，所述衬底基材21可以为玻璃基材、透明塑料基材或可挠式基材。
本实施例可通过第一光罩制程以及第一黄光制程在衬底基材21上形成第一金属层22，即形成具有预定图案的TFT的栅极，其中TFT的栅极包括沿图中箭头所示的预定方向D间隔排布的第一电极条221和第二电极条222(图中仅示出一个第一电极条221和一个第二电极条222)，预定方向D为与每一栅极的延伸方向相垂直的水平方向。
当然，还可仅采用例如化学气相沉积、真空蒸镀、等离子化学气相沉积、溅射或低压化学气相沉积等方法直接形成第一金属层22。
由于后续需要形成TFT的源极和漏极，因此本发明实施例进一步在第一金属层22以及未形成第一金属层22的衬底基材21上形成绝缘层23，即栅极绝缘层(Gate Insulation Layer，GI)。
本发明实施例在形成第一金属层22之后，还可以在衬底基材21上形成沿预定方向D交错排布的公共电极24(图中仅示出一个公共电极24)，且每一公共电极24位于相邻的第一电极条221和第二电极条222之间。当然，本发明实施例也可以通过第一光罩制程和第一黄光制程形成第一金属层22和公共电极24，即，公共电极24和第一金属层22由同一光罩制程和同一黄光制程制得。
S12：在绝缘层上形成沿预定方向间隔排布的IGZO图案，所述IGZO图案位于第一电极条的上方；
本发明实施例可通过第二光罩制程和第二黄光制程在绝缘层23上形成具有预定图案的IGZO图案(层)25，其中，第二黄光制程可利用包括但不限于具有磷酸、硝酸、醋酸以及去离子水的蚀刻液对形成于绝缘层23上的一整片半导体图案层24进行蚀刻，从而得到所述IGZO图案25，当然其他实施例也可以采用干法蚀刻。
S13：在绝缘层和IGZO图案层上形成第二金属层，第二金属层形成有沿预定方向交错排布的第一沟道和第二沟道，第一沟道暴露其对应区域的IGZO图案，第二沟道暴露其对应区域的绝缘层且位于第二电极条的上方。
本发明实施例可通过第三光罩制程以及第三黄光制程在绝缘层23上形成具有预定图案的第二金属层26，即形成TFT的源漏电极层，第二金属层26包括源极261和漏极262。沿预定方向D，在相邻的源极261和漏极262之间形成第一沟道263和第二沟道264，且同一漏极262位于相邻的第一沟道263和第二沟道264之间，第一沟道263位于第一电极条221的上方，第二沟道264位于第二电极条222的上方。
S14：在第二沟道的对应区域形成OSC图案；
本发明实施例可通过第四光罩制程以及第四黄光制程在第二沟道364的对应区域形成OSC图案(层)27。参阅图2所示，该OSC图案27的高 度大于第二金属层26的高度，且OSC图案27高出第二金属层26的部分覆盖在源极261和漏极262上。
S15：在绝缘层、第二金属层、IGZO图案以及OSC图案上形成一平坦钝化层。
其中，可以采用化学气相沉积、原子层外延、涂覆、溅射以及蒸镀中的任意组合方式在绝缘层23、第二金属层26、IGZO图案25以及OSC图案27上形成平坦钝化层28，该平坦钝化层28用于保护阵列基板上的上述结构元件免受外界环境因素的破坏。并且，该平坦钝化层28和绝缘层23的材质可以相同也可以不相同。
结合图2和图3所示，第一电极条221、第一沟道263及其对应区域的源极261、漏极262和IGZO图案25形成第一晶体管M1，第二电极条222、第二沟道264及其对应区域的源极261、漏极262和OSC图案27形成第二晶体管M2，第一晶体管M1为N沟道型MOS晶体管，第二晶体管M2为P沟道型MOS晶体管，且第一晶体管M1和第二晶体管M2串联形成图3所示的CMOS反相器30。另外，公共电极24及其对应区域的漏极262和绝缘层23形成一电容CL。
其中，第一电极条221和第二电极条222分别为第一晶体管M1和第二晶体管M2的栅极，两者的栅极连接阵列基板的输入电压Vin；相邻两个源极261分别为第一晶体管M1和第二晶体管M2的源极，第一晶体管M1的源极接地，第二晶体管M2的源极连接阵列基板的电源电压Vdd(又称VDD)；相邻两个漏极262分别为第一晶体管M1和第二晶体管M2的漏极，两者的漏极用于输出阵列基板的输出电压Vout。
当输入电压Vin为低电平时，输出电压Vout为高电平；当输入电压Vin为高电平时，输出电压Vout为低电平。
参阅图4所示，本发明实施例在阵列基板形成奇数个首尾相连的CMOS反相器30，所述首尾相连指的是每一CMOS反相器30的输入端连接上一个CMOS反相器30的输出端，即每一CMOS反相器30的输出电压Vout作为下一个CMOS反相器30的输入电压Vin，该奇数个CMOS反相器30首尾相连构成阵列基板的CMOS环形振荡器40，该CMOS环形振荡器可将阵列基板的电源电压Vdd输出为时钟信号。请参阅图5所示，该时钟信号 具有周期T，且该周期T符合如下关系式，
Figure PCTCN2015098964-appb-000001
其中，n为CMOS反相器30的个数，CL为电容的大小，Vt为第一晶体管M1和第二晶体管M2在导通和截止之间相切换的阈值电压，βn、βp分别为IGZO图案25和OSC图案27的相关参数，该相关参数与材料的电子迁移率、宽长之比等参数有关。应该理解到，本发明实施例的CMOS反相器30与现有技术中的CMOS反相器的工作原理相同，该关系式中的相关参数可参阅现有技术，此处不予赘述。
可知，本发明实施例基于IGZO和OSC制造CMOS反相器30或CMOS环形振荡器，制造材料为IGZO和OSC，因此所制得的阵列基板具有静态功耗低、抗干扰能力强、电源利用率高等优点。
上述第一至第四光罩制程所采用的光罩(mask)不同，各个光罩制程以及第一至第四黄光制程可参阅现有技术，此处不予赘述。
参阅图6所示，本发明实施例可在图2所示的IGZO图案25上形成一保护层60，又称为水氧阻隔层或刻蚀阻挡层(Etch Stop Layer，ESL)。该保护层60用于确保IGZO沟道的电学性能，此时第一沟道263暴露其对应区域的保护层60而非IGZO图案25。
本发明实施例还提供一种采用上述方法制得的具有图2所示结构的阵列基板，该阵列基板的其他结构的制造方法可参阅现有技术。
本发明实施例还提供一种图7所示的液晶显示面板70，其包括相对间隔设置的阵列基板71和彩膜基板72以及夹设于阵列基板71和彩膜基板72之间的液晶层73，该阵列基板71可由上述方法制得。
本发明实施例还提供一种图8所示的液晶显示装置80，其包括上述图7所示的液晶显示面板70以及其他组件，例如背光模组81、前框组件82。而至于其他结构，可参阅现有技术，此处不再赘述。
应理解，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种阵列基板的制造方法，其中，所述方法包括：
    在衬底基材上依次形成第一金属层、沿所述预定方向交错排布的公共电极和绝缘层，所述第一金属层包括沿预定方向间隔排布的第一电极条和第二电极条，每一所述公共电极位于相邻的所述第一电极条和所述第二电极条之间，所述公共电极及对应区域的所述第二金属层和所述绝缘层形成一电容；
    在所述绝缘层上形成沿所述预定方向间隔排布的IGZO图案，所述IGZO图案位于所述第一电极条的上方；
    在所述绝缘层和所述IGZO图案层上形成第二金属层，所述第二金属层形成有沿所述预定方向交错排布的第一沟道和第二沟道，所述第一沟道暴露其对应区域的所述IGZO图案，所述第二沟道暴露其对应区域的所述绝缘层且位于所述第二电极条的上方；
    在所述第二沟道的对应区域形成OSC图案；
    在所述绝缘层、所述第二金属层、所述IGZO图案以及所述OSC图案上形成一平坦钝化层；
    其中，所述第一电极条、所述第一沟道及其对应区域的所述第二金属层和所述IGZO图案形成第一晶体管，所述第二电极条、所述第二沟道及其对应区域的所述第二金属层和所述OSC图案形成第二晶体管，且所述第一晶体管和所述第二晶体管串联形成一CMOS反相器，所述第一电极条和所述第二电极条均为所述阵列基板的薄膜晶体管的栅极，所述第二金属层包括所述薄膜晶体管的源极和漏极，沿所述预定方向，在相邻的所述源极和所述漏极之间形成所述第一沟道和所述第二沟道，且同一所述漏极位于相邻的所述第一沟道和所述第二沟道之间。
  2. 根据权利要求1所述的方法，其中，所述第一电极条、所述第一沟道及其对应区域的所述源极、所述漏极和所述IGZO图案形成所述第一晶体管，所述第二电极条、所述第二沟道及其对应区域的所述源极、所述漏极和所述OSC图案形成所述第二晶体管，且所述阵列基板形成奇数个首尾相连的所述CMOS反相器。
  3. 根据权利要求2所述的方法，其中，所述第一晶体管为N沟道型MOS晶体管，所述第二晶体管为P沟道型MOS晶体管。
  4. 一种阵列基板的制造方法，其中，所述方法包括：
    在衬底基材上依次形成第一金属层和绝缘层，所述第一金属层包括沿预定方向间隔排布的第一电极条和第二电极条；
    在所述绝缘层上形成沿所述预定方向间隔排布的IGZO图案，所述IGZO图案位于所述第一电极条的上方；
    在所述绝缘层和所述IGZO图案层上形成第二金属层，所述第二金属层形成有沿所述预定方向交错排布的第一沟道和第二沟道，所述第一沟道暴露其对应区域的所述IGZO图案，所述第二沟道暴露其对应区域的所述绝缘层且位于所述第二电极条的上方；
    在所述第二沟道的对应区域形成OSC图案；
    在所述绝缘层、所述第二金属层、所述IGZO图案以及所述OSC图案上形成一平坦钝化层；
    其中，所述第一电极条、所述第一沟道及其对应区域的所述第二金属层和所述IGZO图案形成第一晶体管，所述第二电极条、所述第二沟道及其对应区域的所述第二金属层和所述OSC图案形成第二晶体管，且所述第一晶体管和所述第二晶体管串联形成一CMOS反相器。
  5. 根据权利要求4所述的方法，其中，所述第一电极条和所述第二电极条均为所述阵列基板的薄膜晶体管的栅极，所述第二金属层包括所述薄膜晶体管的源极和漏极，沿所述预定方向，在相邻的所述源极和所述漏极之间形成所述第一沟道和所述第二沟道，且同一所述漏极位于相邻的所述第一沟道和所述第二沟道之间。
  6. 根据权利要求5所述的方法，其中，所述第一电极条、所述第一沟道及其对应区域的所述源极、所述漏极和所述IGZO图案形成所述第一晶体管，所述第二电极条、所述第二沟道及其对应区域的所述源极、所述漏极和所述OSC图案形成所述第二晶体管，且所述阵列基板形成奇数个首尾相连的所述CMOS反相器。
  7. 根据权利要求6所述的方法，其中，所述第一晶体管为N沟道型MOS晶体管，所述第二晶体管为P沟道型MOS晶体管。
  8. 根据权利要求4所述的方法，其中，在所述衬底基材上形成所述第一金属层之后，所述方法还包括：
    在所述衬底基材上形成沿所述预定方向交错排布的公共电极，每一所述公共电极位于相邻的所述第一电极条和所述第二电极条之间，所述公共电极及对应区域的所述第二金属层和所述绝缘层形成一电容。
  9. 一种阵列基板，其中，所述阵列基板包括：
    衬底基材；
    形成于所述衬底基材上的第一金属层和绝缘层，所述第一金属层包括沿预定方向间隔排布的第一电极条和第二电极条；
    形成于所述绝缘层上且沿所述预定方向间隔排布的IGZO图案，所述IGZO图案位于所述第一电极条的上方；
    形成于所述绝缘层和所述IGZO图案层上的第二金属层，所述第二金属层形成有沿所述预定方向交错排布的第一沟道和第二沟道，所述第一沟道暴露其对应区域的所述IGZO图案，所述第二沟道暴露其对应区域的所述绝缘层且位于所述第二电极条的上方；
    形成于所述第二沟道的对应区域的OSC图案；
    平坦钝化层，形成于所述绝缘层、所述第二金属层、所述IGZO图案以及所述OSC图案上；
    其中，所述第一电极条、所述第一沟道及其对应区域的所述第二金属层和所述IGZO图案形成第一晶体管，所述第二电极条、所述第二沟道及其对应区域的所述第二金属层和所述OSC图案形成第二晶体管，且所述第一晶体管和所述第二晶体管串联形成一CMOS反相器。
  10. 根据权利要求9所述的阵列基板，其中，所述第一电极条和所述第二电极条均为所述阵列基板的薄膜晶体管的栅极，所述第二金属层包括所述薄膜晶体管的源极和漏极，沿所述预定方向，在相邻的所述源极和所述漏极之间形成有所述第一沟道和所述第二沟道，且同一所述漏极位于相邻的所述第一沟道和所述第二沟道之间。
  11. 根据权利要求10所述的阵列基板，其中，所述第一电极条、所述第一沟道及其对应区域的所述源极、所述漏极和所述IGZO图案形成所述第一晶体管，所述第二电极条、所述第二沟道及其对应区域的所述源极、所 述漏极和所述OSC图案形成所述第二晶体管，且所述阵列基板形成有奇数个首尾相连的所述CMOS反相器。
  12. 根据权利要求11所述的阵列基板，其中，所述第一晶体管为N沟道型MOS晶体管，所述第二晶体管为P沟道型MOS晶体管。
  13. 根据权利要求9所述的阵列基板，其中，所述阵列基板还包括形成于所述衬底基材上且沿所述预定方向交错排布的公共电极，每一所述公共电极位于相邻的所述第一电极条和所述第二电极条之间，所述公共电极及对应区域的所述第二金属层和所述绝缘侧形成一电容。
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