WO2017090455A1 - Dispositif à semi-conducteur et procédé de fabrication - Google Patents

Dispositif à semi-conducteur et procédé de fabrication Download PDF

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Publication number
WO2017090455A1
WO2017090455A1 PCT/JP2016/083465 JP2016083465W WO2017090455A1 WO 2017090455 A1 WO2017090455 A1 WO 2017090455A1 JP 2016083465 W JP2016083465 W JP 2016083465W WO 2017090455 A1 WO2017090455 A1 WO 2017090455A1
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region
impurity diffusion
diffusion region
impurity
concentration
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PCT/JP2016/083465
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English (en)
Japanese (ja)
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進 舍川
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ソニー株式会社
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Priority to US15/773,707 priority Critical patent/US10446596B2/en
Publication of WO2017090455A1 publication Critical patent/WO2017090455A1/fr

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    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14616—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor characterised by the channel of the transistor, e.g. channel having a doping gradient
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    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
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    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present technology relates to a semiconductor device and a manufacturing method. Specifically, the present invention relates to a semiconductor device and a manufacturing method that can suppress generation of noise.
  • a region under a gate electrode is a surface channel type formed by an impurity region having a conductivity type opposite to that of a source / drain region.
  • a channel composed of an inversion layer is formed on the surface of a semiconductor substrate by applying a voltage to a gate electrode, and a current flows between the source and drain.
  • the embedded channel type MOS transistor in which the channel region is formed at a position away from the surface of the semiconductor substrate is not affected by carrier traps existing in the vicinity of the interface between the semiconductor substrate and the gate insulating film.
  • the impurity concentration is reduced due to segregation, pile-up, diffusion, etc. of the impurity on the element isolation region side of the channel region.
  • the noise characteristics deteriorate due to the reduction of the effective gate width.
  • Patent Document 1 in a buried channel MOS transistor, a first impurity diffusion region formed by ion implantation from an oblique direction and a second region formed over the entire region under the gate electrode in a region in contact with the element isolation region side. It has been proposed to form a channel region with the impurity diffusion region. It has been proposed that the formation of the first impurity diffusion region can compensate for the decrease in impurity concentration generated on the element isolation region side of the channel region, enable the effective gate width to be increased, and reduce noise.
  • Some transistors included in the imaging device are configured such that boron is ion-implanted in the element isolation region in order to suppress dark current generated from the element isolation region side of the channel region.
  • Boron ion-implanted at the time of manufacture may wrap around to the channel region due to a subsequent thermal process or the like, and the boron concentration at the end of the channel may be higher than that at the center of the channel. For this reason, there is a possibility that the effective gate width is narrowed and the noise characteristics are deteriorated.
  • the current density on the element isolation region side of the channel region does not increase due to ion implantation conditions that compensate for the decrease in impurity concentration generated on the element isolation region side of the channel region.
  • the interface state deteriorates due to the influence of dry etching or the like when forming the element isolation region.
  • the interface state The noise characteristics may be deteriorated due to the above.
  • the present technology has been made in view of such a situation, and is capable of suppressing deterioration of noise characteristics.
  • a first semiconductor device includes a drain region and a source region provided in a predetermined region of a semiconductor substrate, a channel region provided between the drain region and the source region, A gate electrode formed on the channel region, wherein the channel region is a first impurity diffusion region and an impurity diffusion region having the same conductivity type as the first impurity diffusion region, the first impurity diffusion
  • the region has a different impurity concentration, and includes a second impurity diffusion region formed in a substantially central portion of the first impurity diffusion region.
  • the impurity concentration in the second impurity diffusion region can be higher than the impurity concentration in the first impurity diffusion region.
  • the impurity concentration of the second impurity diffusion region is 1.25 times or more of the impurity concentration of the first impurity diffusion region when the impurity concentration of the first impurity diffusion region is used as a reference. Can be.
  • the impurity concentration of the second impurity diffusion region is smaller than 2.8 times the impurity concentration of the first impurity diffusion region, based on the impurity concentration of the first impurity diffusion region. can do.
  • the second impurity diffusion region may be formed in a strip shape in the gate length direction of the central portion of the first impurity diffusion region.
  • the second impurity diffusion regions may be formed to be scattered in a predetermined shape in the gate length direction or the gate width direction of the central portion of the first impurity diffusion region.
  • the second impurity diffusion region may be formed in a predetermined shape at a central portion of the first impurity diffusion region.
  • a second semiconductor device includes a drain region and a source region provided in a predetermined region of a semiconductor substrate, a channel region provided between the drain region and the source region, A gate electrode formed on the channel region, wherein the channel region is an impurity diffusion region, and the impurity is introduced so that the impurity concentration is highest at a substantially central portion in the channel region. Yes.
  • a manufacturing method includes a drain region and a source region provided in a predetermined region of a semiconductor substrate, a channel region provided between the drain region and the source region, and the channel region. And the channel region is a first impurity diffusion region and an impurity diffusion region of the same conductivity type as the first impurity diffusion region, and is an abbreviation of the first impurity diffusion region.
  • a semiconductor device including a second impurity diffusion region formed in the central portion is manufactured.
  • a mask opened in the channel region is formed, an impurity is introduced to form the first impurity diffusion region, a mask opened in a strip shape in the gate length direction of the channel region is formed, and the impurity is introduced Thus, the second impurity diffusion region can be formed.
  • a mask opened in the channel region is formed, an impurity is introduced to form the first impurity diffusion region, and openings are scattered in a predetermined shape in the gate length direction or the gate width direction of the channel region.
  • the second impurity diffusion region can be formed by forming a mask and introducing impurities.
  • the second impurity diffusion region Forming a mask having an opening in the channel region, introducing the impurity to form the first impurity diffusion region, forming a mask having a predetermined shape in a central portion of the channel region, By introducing the second impurity diffusion region, the second impurity diffusion region can be formed.
  • first impurity diffusion region and the second impurity diffusion region by forming a mask opened in the channel region and introducing impurities from an oblique direction.
  • the impurity concentration of the second impurity diffusion region is 1.25 times or more the impurity concentration of the first impurity diffusion region when the impurity concentration of the first impurity diffusion region is used as a reference.
  • the impurities can be introduced.
  • the impurity concentration in the second impurity diffusion region is smaller than 2.8 times the impurity concentration in the first impurity diffusion region when the impurity concentration in the first impurity diffusion region is used as a reference.
  • the impurities can be introduced.
  • a drain region and a source region provided in a predetermined region of the semiconductor substrate, a channel region provided between the drain region and the source region, and a channel region And a gate electrode formed thereon.
  • the channel region is a first impurity diffusion region and an impurity diffusion region having the same conductivity type as the first impurity diffusion region, and the impurity concentration is different from that of the first impurity diffusion region.
  • the second impurity diffusion region is formed in a substantially central portion.
  • a drain region and a source region provided in a predetermined region of the semiconductor substrate, a channel region provided between the drain region and the source region, and a channel region And a gate electrode formed thereon.
  • the channel region is an impurity diffusion region, and an impurity is introduced so that the impurity concentration becomes the highest at a substantially central portion in the channel region.
  • the first semiconductor device or the second semiconductor device is manufactured.
  • deterioration of noise characteristics can be suppressed.
  • FIG. 1 is a diagram illustrating a configuration of an embodiment of an imaging apparatus to which the present technology is applied.
  • the imaging device 1 according to the present embodiment includes a pixel region 3 composed of a plurality of pixels 2 arranged on a silicon substrate, a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, and an output circuit 7. And a control circuit 8 or the like.
  • the pixel 2 is composed of a photoelectric conversion unit made of a photodiode and a plurality of pixel transistors, and a plurality of pixels 2 are regularly arranged in a two-dimensional array on the substrate.
  • the pixel transistor constituting the pixel 2 may be four MOS transistors constituted by a transfer transistor, a reset transistor, a selection transistor, and an amplifier transistor, or may be three transistors excluding the selection transistor. In this embodiment, an example in which four pixel transistors including a selection transistor are included is used.
  • the pixel area 3 is composed of pixels 2 regularly arranged in a two-dimensional array.
  • the pixel region 3 has an effective pixel region that actually receives light, amplifies the signal charge generated by photoelectric conversion, and reads it to the column signal processing circuit 5, and a black for outputting optical black as a reference for the black level.
  • a reference pixel region (not shown).
  • the black reference pixel region is normally formed on the outer periphery of the effective pixel region.
  • the control circuit 8 generates a clock signal, a control signal, and the like that serve as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do.
  • the clock signal and control signal generated by the control circuit 8 are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.
  • the vertical drive circuit 4 is configured by a shift register, for example, and selectively scans each pixel 2 in the pixel region 3 in the vertical direction sequentially in units of rows. Then, the pixel signal based on the signal charge generated according to the amount of light received in the photodiode of each pixel 2 is supplied to the column signal processing circuit 5 through the vertical signal line.
  • the column signal processing circuit 5 is arranged, for example, for each column of the pixels 2, and a signal output from the pixels 2 for one row is sent to the black reference pixel region (not shown, but around the effective pixel region) for each pixel column. Signal processing such as noise removal and signal amplification.
  • a horizontal selection switch (not shown) is provided between the column signal processing circuit 5 and the horizontal signal line 10.
  • the horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.
  • the output circuit 7 performs signal processing on signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10 and outputs the signals.
  • FIG. 2 is an equivalent circuit diagram of the pixels constituting the imaging device 1.
  • the unit pixel 2 includes a photodiode PD that is a photoelectric conversion element, a transfer transistor Tr1, a reset transistor Tr2, an amplification transistor Tr3, and a selection transistor Tr4.
  • These pixel transistors Tr1 to Tr4 are composed of, for example, n-channel MOS transistors.
  • the amplifying transistor Tr3 is a buried channel type MOS transistor.
  • the transfer transistor Tr1 has a source connected to the cathode side of the photodiode PD and a drain connected to the floating diffusion portion FD.
  • a transfer wiring for supplying a transfer pulse ⁇ TRG is connected to the gate electrode 20 between the source and drain of the transfer transistor Tr1.
  • the signal charges (electrons) photoelectrically converted by the photodiode PD and stored therein are transferred to the floating diffusion portion FD by applying a transfer pulse ⁇ TRG to the gate electrode 20 of the transfer transistor Tr1.
  • the reset transistor Tr2 has a drain connected to the power supply voltage VDD and a source connected to the floating diffusion portion FD.
  • a reset wiring for supplying a reset pulse ⁇ RST is connected to the gate electrode 21 between the source and drain of the reset transistor Tr2.
  • a reset pulse ⁇ RST is applied to the gate electrode 21 of the reset transistor Tr2.
  • the potential of the floating diffusion portion FD is reset to the VDD level by the power supply voltage VDD.
  • the amplifying transistor Tr3 has its drain connected to the power supply voltage VDD and its source connected to the drain of the selection transistor Tr4.
  • the gate electrode 23 between the source and drain of the amplification transistor Tr3 is connected to the floating diffusion portion FD.
  • the amplification transistor Tr3 constitutes a force follower circuit using the power supply voltage VDD as a load, and a pixel signal corresponding to the potential change of the floating diffusion portion FD is output.
  • the drain of the selection transistor Tr4 is connected to the source of the amplification transistor Tr3, and the source is connected to the vertical signal line 9.
  • a selection wiring for supplying a selection pulse ⁇ SEL is connected to the gate electrode 23 between the source and drain of the selection transistor Tr4.
  • the signal charge accumulated in the light receiving part PD is supplied to the floating diffusion part FD by the transfer transistor Tr1 by supplying the transfer pulse ⁇ TRG to the gate electrode 20.
  • the potential of the floating diffusion portion FD is displaced, and the potential change is transmitted to the gate electrode 22.
  • the potential supplied to the gate electrode 22 is amplified by the amplification transistor Tr3, and is selectively output to the vertical signal line 9 by the selection transistor Tr4 as a pixel signal.
  • the signal charge read to the floating diffusion portion FD is reset by the reset transistor Tr2 so as to have the same potential as the potential near the power supply voltage VDD.
  • the pixel signal output to the vertical signal line 9 is then output via the column signal processing circuit 5, the horizontal signal line 10, and the output circuit 7 shown in FIG.
  • FIG. 3 is a plan layout diagram of the unit pixel.
  • the transfer transistor Tr1 is not shown.
  • a photodiode PD is formed in the center of the unit pixel region, and a reset transistor Tr2 and an amplification transistor Tr3 are formed on one side of the region where the photodiode PD is formed.
  • the selection transistors Tr4 are continuously arranged in the horizontal direction.
  • the active region (active region) formed in the semiconductor substrate including the source / drain regions 25 of the pixel transistors Tr2 to Tr4 and the regions under the gate electrodes 21 to 23 is an element isolation made of STI (Shallow Trench Isolation). It is electrically isolated by region 24. Further, each of the pixel transistors Tr1 to Tr4 can be configured by a buried channel type MOS transistor.
  • FIG. 4A shows a cross-sectional configuration along the line AA in FIG. 3
  • FIG. 4B shows a cross-sectional configuration along the line BB in FIG.
  • the amplification transistor Tr3 to which the present technology is applied has regions with different impurity concentrations in the channel region, as will be described later with reference to FIGS.
  • the amplification transistor Tr3 having a region with different impurity concentrations in the channel region and the amplification transistor Tr3 having no region with different impurity concentrations in the channel region, Referring to FIG. 4, the amplification transistor Tr3 that does not have regions with different impurity concentrations in the channel region will be described.
  • a second conductivity type for example, p-type well region 13 to be an element formation region is formed on the surface side of the first conductivity type, for example, n-type semiconductor substrate 12.
  • a pixel transistor (not shown) including the amplification transistor Tr3 and a photodiode PD are formed in the well region 13 serving as an element formation region.
  • the amplification transistor Tr3 includes a source region 25a and a drain region 25b formed on the surface side, and a gate electrode 22 formed on the semiconductor substrate 12 between the source region 25a and the drain region 25b.
  • the source region 25a and the drain region 25b are formed in the well region 13 formed on the surface side of the semiconductor substrate 12, and are constituted by n-type impurity regions.
  • the gate electrode 22 is formed on the semiconductor substrate 12 via a gate insulating film 26 made of, for example, a silicon oxide film, and is made of, for example, polysilicon.
  • a channel region 14 made of a p-type impurity region is formed on the surface side of the semiconductor substrate 12 below the gate electrode 22.
  • the active region including the channel region 14 is a so-called STI composed of a trench portion 27 formed in the semiconductor substrate 12 and a buried film 28 embedded in the trench portion 27.
  • the element isolation region 24 is electrically isolated.
  • the trench portion 27 is formed at a desired depth from the surface of the semiconductor substrate 12.
  • the buried film 28 is made of an insulating material made of, for example, a silicon oxide film.
  • the gate width W of the amplification transistor Tr3 is a distance from one element isolation region 24 to the other element isolation region 24 as shown in FIG. 4B.
  • the gate length L is a distance from the end portion on the source region 25a side under the gate electrode 22 to the end portion on the drain region 25b side as shown in FIG.
  • a region having different impurity concentrations is provided in the channel region 14 (channel region 30 in FIGS. 5 and 6), so that the size of the gate electrode is increased.
  • the effective gate width W can be increased without changing the above, and the influence of the interface state on the element isolation region side can be avoided to reduce noise.
  • FIG. 5 is a plan layout view of the unit pixel as in FIG. 3, but shows a portion of the amplification transistor Tr3 and shows a layer under the gate oxide film 26.
  • FIG. 5 is a plan layout view of the unit pixel as in FIG. 3, but shows a portion of the amplification transistor Tr3 and shows a layer under the gate oxide film 26.
  • FIG. 5 is a plan layout view of the unit pixel as in FIG. 3, but shows a portion of the amplification transistor Tr3 and shows a layer under the gate oxide film 26.
  • FIG. 6A shows a cross-sectional configuration along the line AA in FIG. 3 as in FIG. 4A
  • FIG. 6B shows a cross-section along the line BB in FIG. 3 like B in FIG.
  • the configuration is shown.
  • FIG. 6A shows a cross-sectional configuration along the line AA in FIG. 5
  • FIG. 6B shows a cross-sectional configuration along the line BB in FIG.
  • FIG. 5 shows a cross-sectional configuration along the line CC in FIG. 6B.
  • amplification transistor Tr3 shown in FIGS. 5 and 6 portions having the same configuration as the amplification transistor Tr3 shown in FIGS. 3 and 4 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • the channel region 30 includes a first impurity diffusion region 30a and a second impurity diffusion region 30b.
  • the second impurity diffusion region 30 b is formed in a band shape at the central portion in the channel region 30.
  • a cross-sectional configuration along the line AA in FIG. 5 (a cross-sectional configuration in the gate length L direction of the amplification transistor Tr3), in other words, when cutting at the position of the first impurity diffusion region 30a of the channel region 30, FIG.
  • the channel region 30 is formed of a first impurity diffusion region 30a.
  • the portion shown as the first impurity diffusion region 30a in FIG. 6A is the second impurity diffusion region 30b. It becomes.
  • the cross-sectional configuration along the BB line in FIG. 5 (the cross-sectional configuration in the gate width W direction of the amplification transistor Tr3) is the second impurity diffusion region 30b in the central portion of the channel region 30 as shown in FIG.
  • the first impurity diffusion region 30a is formed at both ends thereof (so as to surround the second impurity diffusion region 30b).
  • an impurity diffusion region 31 made of a p-type impurity for suppressing dark current generated from the element isolation region 24 is formed in the vicinity of the element isolation region 24.
  • the impurity diffusion region 31 made of p-type impurities for suppressing this dark current can be formed by ion implantation of boron into the element isolation region 24.
  • the ion-implanted boron may wrap around to the channel region 14 of the amplification transistor Tr3 due to a subsequent thermal process or the like.
  • the boron concentration at the end of the channel region 14 is higher than the central portion of the channel region 14, and the effective gate width W may be reduced. As a result, noise characteristics may be deteriorated.
  • the channel region 30 is configured by the first impurity diffusion region 30a and the second impurity diffusion region 30b, and the concentration is added to these two regions as described later.
  • the concentration is added to these two regions as described later.
  • the amplification transistor Tr3 to which the present technology is applied has a source region 25a and a drain region 25b made of n-type impurities formed between the source region 25a and the drain region 25b.
  • a gate electrode 22 formed through a gate oxide film 26 is provided on the semiconductor substrate between the provided channel region 30 and the source region 25a and the drain region 25b.
  • the channel region 30 under the gate electrode 22 includes a first impurity diffusion region 30a made of p-type impurities formed immediately below the gate electrode 22, and a first impurity diffusion.
  • a second impurity diffusion region 30b made of a strip-like p-type impurity extending in the direction of the gate length L of the transistor is formed at the center of the region 30a.
  • the second impurity diffusion region 30b can be formed by ion implantation through a resist mask opened in a strip shape in the gate length W direction of the transistor as will be described later. Further, as the impurities contained in the first impurity diffusion region 30a and the second impurity diffusion region 30b, for example, boron, phosphorus, arsenic, antimony, indium, germanium, or the like can be used.
  • FIG. 7 shows the impurity concentration distribution and the current density distribution in the channel region 30 when the amplification transistor Tr3 is configured as shown in FIGS.
  • the graph shown in FIG. 7A is a graph showing the impurity concentration in the cross-sectional direction along the line BB in FIG. 5 (the cross section shown in FIG. 6B).
  • B of FIG. 7 is a graph showing a current density distribution in a cross-sectional direction (cross section shown in B of FIG. 6) along the line BB of FIG.
  • Graphs 1 to 6 shown in FIG. 7 are graphs each having a density difference of 1 to 2.8 times.
  • the concentration difference is a difference (ratio) between the impurity concentration of the first impurity diffusion region 30a and the impurity concentration of the second impurity diffusion region 30b.
  • the concentration difference represents the concentration of the impurity in the second impurity diffusion region 30b when the concentration of the impurity in the first impurity diffusion region 30a is used as a reference.
  • the concentration of impurities in the central portion of the channel region 30 is higher than the concentration of impurities in other regions.
  • the central portion of the channel region 30 corresponds to the second impurity diffusion region 30b, and the other region in the channel region 30 corresponds to the first impurity diffusion region 30a.
  • the impurity concentration of the second impurity diffusion region 30b forming the channel region 30 of the amplification transistor Tr3 is configured to be higher than the impurity concentration of the first impurity diffusion region 30a.
  • the concentration difference in FIG. 7 represents the concentration of the second impurity diffusion region 30b on the basis of the concentration of the first impurity diffusion region 30a. That is, the concentration difference is a value obtained by dividing the concentration of the second impurity diffusion region 30b by the concentration of the first impurity diffusion region 30a. Concentration of second impurity diffusion region 30b / concentration of first impurity diffusion region 30a
  • the graph 1 is a graph with a density difference of 1 time
  • the graph 2 is a graph with a density difference of 1.25 times
  • the graph 3 is a density difference of 1.30 times.
  • the graph 4 is a graph with a density difference of 1.63 times
  • the graph 5 is a graph with a density difference of 2.2 times
  • the graph 6 is a graph with a density difference of 2.8 times. is there.
  • the graph 1 in which the concentration difference is 1 is the impurity concentration and current density distribution in the conventional amplification transistor Tr3 shown for comparison, for example, the amplification transistor Tr3 shown in FIG.
  • the impurity concentration is highest in the second impurity diffusion region 30b disposed in the central portion of the channel region 30, and gradually increases from the peak value.
  • the concentration becomes smaller.
  • the impurity concentration distribution maintains the peak value (concentration b) in the second impurity diffusion region 30b, and in the first impurity diffusion region 30a,
  • the region has a predetermined density (density a) uniformly.
  • the first impurity diffusion region 30a and the second impurity diffusion region 30b are regions that are uniformly formed at predetermined concentrations (concentration a and concentration b), respectively. good. Further, as shown in FIG. 7A, the second impurity diffusion region 30b has the highest concentration, and the concentration gradually decreases from the peak value. In the first impurity diffusion region 30a, A uniform density may be used.
  • the concentration difference is a value obtained by dividing the concentration of the second impurity diffusion region 30b by the concentration of the first impurity diffusion region 30a as described above, but a graph as shown in FIG. 8A is obtained.
  • the concentration b can be a value obtained by dividing the concentration b by the concentration a.
  • the concentration of the first impurity diffusion region 30a is not uniform.
  • the concentration of the first impurity diffusion region 30a when obtaining the concentration difference is set to the lowest concentration value. That is, the lowest concentration value in the first impurity diffusion region 30a and the highest concentration value in the second impurity diffusion region 30b are used as values for calculating the concentration difference.
  • the vertical arrows indicate that the density difference is 1.25 times, 2.2 times, and 2.8 times.
  • the lower side of the arrow indicates the lowest concentration in the first impurity diffusion region 30a, and the upper side of the arrow indicates the highest concentration in the second impurity diffusion region 30b.
  • FIG. 7B the current density distribution of the channel region 30 in which the first impurity diffusion region 30a and the second impurity diffusion region 30b having different impurity concentrations are formed is as shown in FIG. 7B.
  • B of FIG. 7 is a current density distribution obtained when the impurity concentration distribution as shown in A of FIG. 7 is obtained.
  • FIG. 8B an example of the current density distribution obtained when the impurity concentration distribution as shown in FIG. 8A is obtained is shown in FIG. 8B.
  • the current density distribution is A high current density is maintained in the region of the second impurity diffusion region 30b, and the current density gradually decreases as the element isolation region 24 is approached in the region of the first impurity diffusion region 30a.
  • the portion where the current density reaches a peak is widened in the direction of the gate width W of the channel region 30.
  • the current density in the central portion of the channel region 30 is dispersed, so that noise can be reduced.
  • the graph 1 (conventional amplification transistor Tr3) has a peak value in the central portion, but the value gradually decreases as the element isolation region 24 is approached. It can be seen that the current density is not distributed.
  • the peak value of the current density and the position in the channel region 30 corresponding to the peak value differ depending on the concentration difference. For example, comparing the graph 2 with a density difference of 1.25 times and the graph 6 with a density difference of 2.8 times, the density difference of 2.8 times is higher than the density difference of 1.25 times. The peak value of current density is high. However, it can be seen that when the density difference is 2.8 times, the current density near the element isolation region 24 is higher than when the density difference is 1.25 times.
  • the element isolation region 24 side of the channel region 30 tends to deteriorate the interface state due to the influence of dry etching or the like when forming the element isolation region 24, and the current density on the element isolation region 24 side of the channel region 30 is increased. If it is high, the noise characteristics may be deteriorated due to the interface state. Therefore, in order to reduce noise, the current density in the vicinity of the element isolation region 24 in the channel region 30 should not be high.
  • the current density distribution is dispersed in the central portion, the peak value is high, and the concentration difference is set so that the current density in the vicinity of the element isolation region 24 of the channel region 30 does not increase.
  • the density difference is only shown up to 2.8 times, but it can be estimated that if the density difference is further increased, the current density near the element isolation region 24 in the channel region 30 becomes higher. . Therefore, the density difference is not necessarily increased. In this case, it is considered preferable to make the density difference 2.8 times or less.
  • the concentration difference between the first impurity diffusion region 30a and the second impurity diffusion region 30b is 1.25 times or more (greater). Yes, it is possible to form the first impurity diffusion region 30a and the second impurity diffusion region 30b on the basis of 2.8 times or less (smaller) as one criterion.
  • the impurity concentration of the second impurity diffusion region 30b is formed to be higher than the impurity concentration of the first impurity diffusion region 30a in a strip shape in the direction of the gate length L of the amplification transistor Tr3. This can be done by ion implantation through the opened resist mask. Further, the concentration difference between the impurity concentration of the first impurity diffusion region 30a and the impurity concentration of the second impurity diffusion region 30b can be adjusted by setting the dose amount during ion implantation.
  • second impurity diffusion region 30b ⁇ Example of formation of second impurity region> The shape of the second impurity diffusion region 30b will be described. Like the second impurity diffusion region 30b shown in FIG. 5, the second impurity diffusion region 30b described above has a gate length of the transistor in the central portion of the channel region 30 (in the first impurity diffusion region 30a). The case where it is formed as a strip shape extending in the L direction has been described as an example.
  • FIG. 9 shows another shape of the second impurity diffusion region 30b.
  • the second impurity diffusion region 30b shown in FIG. 9 has a predetermined shape and a predetermined size in the direction of the gate length L of the transistor in the central portion in the channel region 30 (in the first impurity diffusion region 30a). A plurality of points are formed.
  • the second impurity diffusion region 30b-1, the second impurity diffusion region 30b-2, and the second impurity diffusion region 30b-3 having a quadrangular (square) shape are formed into the channel region 30.
  • the central portion of the inside (inside the first impurity diffusion region 30a) is arranged.
  • the second impurity diffusion regions 30b may be formed in the middle of the channel region 30 (in the first impurity diffusion region 30a).
  • the second impurity diffusion region 30b has a quadrangular shape, but may have a shape other than a square, such as a rhombus, a polygon, or a circle.
  • the shape of the second impurity diffusion region 30b can be set by the shape of the mask at the time of manufacture.
  • the impurity concentration distribution in the channel region 30 is as shown in FIG.
  • the graph shown in FIG. 10 is a graph showing the impurity concentration in the cross-sectional direction along the line DD in FIG.
  • the second impurity diffusion regions 30b shown in FIG. 10 are formed to be dispersed in three quadrangular shapes, a concentration distribution in which the impurity concentration increases in each of the second impurity diffusion regions 30b is obtained.
  • the current density of the high concentration portion (around that portion) can be improved, and the current density of the central portion of the channel region 30 can be dispersed. Can do. Therefore, noise can be reduced even when the second impurity diffusion region 30b is formed as shown in FIG.
  • the second impurity diffusion region 30b may be provided in a strip shape in the central portion of the channel region 30, or in a predetermined shape in the central portion of the channel region 30 as shown in FIG.
  • the second impurity diffusion regions 30b may be provided in a scattered manner.
  • a second impurity diffusion region 30b may be provided at a central point of the channel region 30 in a predetermined shape.
  • the second impurity diffusion region 30b shown in FIG. 11 is formed in a predetermined shape, that is, a square in FIG. As described above, the second impurity diffusion region 30 b having a high impurity concentration may be provided only in the central portion of the channel region 30.
  • the configuration of one pixel needs to be downsized.
  • the gate width W and the gate length L of the amplification transistor Tr3 may be reduced, and the channel region 30 may be reduced.
  • the channel region 30 is small, the second impurity diffusion region 30b is provided only at the center as shown in FIG. 11, and when the channel region 30 is relatively large, FIG. A configuration in which the second impurity diffusion region 30b is provided in a shape as shown in FIG.
  • the second impurity diffusion region 30b is provided only in the central portion of the channel region 30, the current density in the portion where the impurity is high (or in the vicinity of the portion) is improved.
  • the current density in the central portion of the channel region 30 can be dispersed. Therefore, even when the second impurity diffusion region 30b as shown in FIG. 11 is provided, noise can be reduced.
  • the second impurity diffusion region 30b shown in FIGS. 5, 9, and 11 has been described as an example in which the second impurity diffusion region 30b is provided in the direction of the gate length L.
  • the second impurity diffusion region 30b has a gate width of It can also be configured to be provided in the W direction.
  • FIG. 12 shows an example in which the second impurity diffusion region 30b is provided in the gate width W direction.
  • the second impurity diffusion region 30b shown in FIG. 12 has a predetermined shape (square shape) and a predetermined size in the central portion of the channel region 30 in the same manner as the second impurity diffusion region 30b shown in FIG. This is a case of being formed in a scattered manner, except that the formed direction is the gate width W direction.
  • the center portion of the channel region 30 is formed in a predetermined shape (quadrangle) and scattered in a predetermined size.
  • the second impurity diffusion region 30b shown in FIG. 5 it may be formed in a strip shape in the central portion of the channel region 30.
  • the second impurity diffusion regions 30b shown in FIGS. 9 and 12 may be combined so that the second impurity diffusion regions 30b are formed in the gate width W direction and the gate length L direction, respectively. .
  • the high-concentration portion can be dispersed and the high-concentration portion (or The current density in the vicinity of that portion can be improved. Therefore, the current density in the central portion of the channel region 30 can be dispersed. As a result, even when the second impurity diffusion region 30b as shown in FIG. 12 is provided, noise can be reduced.
  • FIGS. 13 and 14 are diagrams for explaining the manufacture of the amplification transistor Tr3.
  • the case where the second impurity diffusion region 30b shown in FIGS. 5 and 6 is formed in a strip shape in the central portion of the channel region 30 will be described as an example.
  • a trench portion formed at a desired depth from the substrate surface and an element isolation region 24 made of an insulating material embedded in the trench portion are formed on the semiconductor substrate.
  • an n-type semiconductor substrate is prepared, a resist layer is formed on the upper portion of the semiconductor substrate, and exposure / development is performed using a photolithography technique, whereby a resist mask in which a region for forming an element isolation region 24 is opened is patterned. It is formed. Then, by etching the semiconductor substrate, the trench is formed by etching away from the surface side of the semiconductor substrate to a desired depth.
  • the insulating material for forming the element isolation region 24 is filled in the trench using, for example, a CVD (Chemical Vapor Deposition) method, so that the element isolation region 24 is formed on the semiconductor substrate.
  • CVD Chemical Vapor Deposition
  • a resist mask 101 is formed by exposure and development using a photolithography technique, and the dark current generated from the element isolation region 24 side is suppressed via the resist mask 101.
  • An impurity diffusion region 31 made of the p-type impurity is formed.
  • a resist mask 102 is formed by exposure and development using a photolithography technique, and the channel region 30 of the amplification transistor Tr3 is made of p-type impurities through the resist mask 102.
  • a first impurity diffusion region 30a is formed.
  • a resist mask 102 that opens the channel region 30 of the amplification transistor Tr3 is formed, and p-type impurities are ion-implanted through the resist mask 102, whereby the first impurity diffusion region 30a is formed.
  • a strip-like resist mask 103 extending in the gate length L direction of the amplification transistor Tr3 is formed in the central portion of the first impurity diffusion region 30a, and the p-type resist mask 103 is interposed through the resist mask 103.
  • a second impurity diffusion region 30b made of impurities is formed.
  • a resist mask 103 that opens the second impurity diffusion region 30b of the channel region 30 of the amplification transistor Tr3 is formed, and the resist mask 103 is interposed therebetween.
  • a second impurity diffusion region 30b is formed by ion implantation of the p-type impurity.
  • the impurity concentration of the second impurity diffusion region 30b is Impurities are introduced so that the concentration is, for example, 1.25 times or more and less than 2.8 times.
  • the impurity concentration can be increased at the central portion of the channel region 30. That is, by performing ion implantation twice, two regions having different impurity concentrations can be formed. Further, the concentration difference between the impurity concentration of the first impurity diffusion region 30a and the impurity concentration of the second impurity diffusion region 30b can be adjusted by setting the dose amount during ion implantation.
  • boron, phosphorus, arsenic, antimony, indium, germanium, or the like can be used as an ion-implanted impurity when forming the first impurity diffusion region 30a and the second impurity diffusion region 30b. is there.
  • the ion implantation is performed to form the impurity diffusion region.
  • the impurity diffusion region may be formed by introducing impurities into the semiconductor substrate by a method other than ion implantation.
  • the amplification transistor Tr3 having the first impurity diffusion region 30a and the second impurity diffusion region 30b is manufactured.
  • a p-type well region 13 is formed by ion-implanting a p-type impurity such as B (boron) into the surface of the semiconductor substrate in a predetermined process. Is done.
  • the well region 13 is formed in the depth direction from the region where the photodiode PD and the pixel transistors Tr1 to Tr4 (FIGS. 2 and 3) are formed.
  • a step of forming the photodiode PD For example, after the step shown in FIG. 14D, the resist mask 103 is removed, and a resist mask (not shown) that opens a region for forming the photodiode PD is formed.
  • n-type impurities are ion-implanted to a desired depth through the resist mask, thereby forming an n-type semiconductor region that becomes the charge storage layer 15 of the photodiode PD.
  • p-type impurities are ion-implanted at a high concentration on the outermost surface of the semiconductor substrate through a resist mask, thereby forming a p-type semiconductor region serving as the dark current suppression region 16. In this way, the process of forming the photodiode PD is also included.
  • the second impurity diffusion region 30b is formed.
  • the first impurity diffusion region 30a and the second impurity diffusion region 30b are formed by performing ion implantation twice.
  • the first impurity diffusion region 30a and the second impurity diffusion region 30b may be formed by performing ion implantation once.
  • the process shown in FIG. 15 can be replaced with the process shown in FIG. 13C and FIG. 14D.
  • a resist mask 102 that opens the channel region 30 of the amplification transistor Tr3 is formed, and p-type impurities are ion-implanted from the oblique direction through the resist mask 102, so that the first In this step, the impurity diffusion region 30a and the second impurity diffusion region 30b are formed.
  • the second impurity diffusion region 30 b can be formed in the central portion of the channel region 30, and the first impurity diffusion region 30 a can be formed in a region other than the central portion of the channel region 30.
  • the first impurity diffusion region 30a and the second impurity diffusion region 30b may be formed at the same timing by implanting ions from an oblique direction.
  • the amplification transistor Tr3 constituting the pixel 2 is a buried channel type MOS transistor, and the channel region 30 is constituted by the first impurity diffusion region 30a and the second impurity diffusion region 30b.
  • the channel region 14 can be substantially enlarged without changing the size of the gate electrode 22, and noise can be reduced.
  • the case where the two regions of the first impurity diffusion region 30a and the second impurity diffusion region 30b are provided has been described as an example.
  • a plurality of regions having different concentrations, such as regions, may be provided in the channel region 30.
  • a p-channel MOS transistor has been described as an example of the amplifying transistor Tr3.
  • an n-channel MOS transistor may be configured.
  • the first conductivity type may be n-type and the second conductivity type may be p-type.
  • a buried channel type MOS transistor is used as the amplification transistor Tr3.
  • it may be adopted as another pixel transistor, for example, the reset transistor Tr2 or the selection transistor Tr4.
  • the pixel is configured by four pixel transistors including the selection transistor Tr4.
  • the pixel may be configured by three pixel transistors excluding the selection transistor Tr4.
  • the selection transistor Tr4 serves as a switch. Therefore, the amplification transistor Tr3 may be a normally-on (depletion) type FET, or a normally-off type. It is good.
  • the transfer transistor Tr1, the reset transistor Tr2, and the selection transistor Tr4 are also configured as buried channel type MOS transistors. However, only the amplifying transistor Tr3 may be constituted by a buried channel type MOS transistor, and the other pixel transistors may be constituted by surface channel type pixel transistors.
  • the present disclosure is not limited to application to an imaging device that detects the distribution of the incident light quantity of visible light and captures it as an image, but also to an imaging device that captures the distribution of the incident amount of infrared rays, X-rays, or particles as an image Applicable.
  • the present invention can be applied to all solid-state imaging devices (physical quantity distribution detection devices) such as a fingerprint detection sensor that senses other physical quantity distributions such as pressure and capacitance and captures images as images.
  • the present disclosure is not limited to an imaging apparatus that scans each unit pixel of the pixel unit sequentially in units of rows and reads a pixel signal from each unit pixel.
  • the present invention is also applicable to an XY address type imaging apparatus that selects an arbitrary pixel in pixel units and reads out signals from the selected pixels in pixel units.
  • the imaging device may be formed as a single chip, or may be in a module shape having an imaging function in which a pixel portion and a signal processing portion or an optical system are packaged together. .
  • the present disclosure is not limited to application to an imaging device, but can also be applied to a semiconductor device including a buried channel type MOS transistor and other imaging devices.
  • the imaging device refers to a camera system such as a digital still camera or a digital video camera, or an electronic device having an imaging function such as a mobile phone.
  • the above-described module form mounted on an electronic device that is, a camera module may be used as an imaging device.
  • FIG. 13 is a block diagram illustrating a configuration example of an imaging device mounted on an electronic device.
  • the imaging apparatus 201 includes an optical system 202, an imaging element 203, a signal processing circuit 204, a monitor 205, and a memory 206, and can capture still images and moving images.
  • the optical system 202 includes one or more lenses, guides image light (incident light) from a subject to the image sensor 203, and forms an image on a light receiving surface (sensor unit) of the image sensor 203.
  • the imaging device 203 As the imaging device 203, the imaging device 1 of each embodiment described above is applied.
  • the image sensor 203 electrons are accumulated for a certain period according to the image formed on the light receiving surface via the optical system 202. Then, a signal corresponding to the electrons accumulated in the image sensor 203 is supplied to the signal processing circuit 204.
  • the signal processing circuit 204 performs various signal processing on the pixel signal output from the image sensor 203.
  • An image (image data) obtained by performing signal processing by the signal processing circuit 204 is supplied to the monitor 205 and displayed, or supplied to the memory 206 and stored (recorded).
  • an image can be captured at a higher frame rate by increasing the speed of the AD conversion process by applying the imaging apparatus 1 of each of the above-described embodiments. it can.
  • FIG. 17 is a diagram illustrating a usage example in which the above-described imaging device 1 (image sensor) is used.
  • the image sensor described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray as follows.
  • Devices for taking images for viewing such as digital cameras and mobile devices with camera functions
  • Devices used for traffic such as in-vehicle sensors that capture the back, surroundings, and interiors of vehicles, surveillance cameras that monitor traveling vehicles and roads, and ranging sensors that measure distances between vehicles, etc.
  • Equipment used for home appliances such as TVs, refrigerators, air conditioners, etc. to take pictures and operate the equipment according to the gestures ⁇ Endoscopes, equipment that performs blood vessel photography by receiving infrared light, etc.
  • Equipment used for medical and health care ⁇ Security equipment such as security surveillance cameras and personal authentication cameras ⁇ Skin measuring instrument for photographing skin and scalp photography Such as a microscope to do beauty Equipment used for sports-Equipment used for sports such as action cameras and wearable cameras for sports applications-Used for agriculture such as cameras for monitoring the condition of fields and crops apparatus
  • this technique can also take the following structures.
  • a drain region and a source region provided in a predetermined region of the semiconductor substrate;
  • a channel region provided between the drain region and the source region;
  • the channel region is A first impurity diffusion region;
  • the second impurity diffusion region is the same conductivity type as the first impurity diffusion region, has a different impurity concentration from the first impurity diffusion region, and is formed in a substantially central portion of the first impurity diffusion region.
  • a semiconductor device comprising: an impurity diffusion region.
  • the impurity concentration of the second impurity diffusion region is 1.25 times or more of the impurity concentration of the first impurity diffusion region when the impurity concentration of the first impurity diffusion region is used as a reference.
  • the impurity concentration of the second impurity diffusion region is smaller than 2.8 times the impurity concentration of the first impurity diffusion region, based on the impurity concentration of the first impurity diffusion region.
  • the second impurity diffusion region is formed to be scattered in a predetermined shape in the gate length direction or the gate width direction of the central portion of the first impurity diffusion region.
  • Any of (1) to (4) A semiconductor device according to claim 1.
  • a drain region and a source region provided in a predetermined region of the semiconductor substrate; A channel region provided between the drain region and the source region; A gate electrode formed on the channel region, The channel region is an impurity diffusion region;
  • a semiconductor device in which the impurity is introduced so that the concentration of the impurity is highest at a substantially central portion in the channel region.
  • the impurity concentration in the second impurity diffusion region is smaller than 2.8 times the impurity concentration in the first impurity diffusion region when the impurity concentration in the first impurity diffusion region is used as a reference.
  • 1 imaging device 2 pixels, 3 pixel area, 4 vertical drive circuit, 5 column signal processing circuit, 6 horizontal drive circuit, 7 output circuit, 8 control circuit, 9 vertical signal line, 10 horizontal signal line, 12 semiconductor substrate, 13 Well region, 15 charge storage layer, 16 dark current suppression region, 20, 21, 22, 23 gate electrode, 24 element isolation region, 25 source / drain region, 25a source region, 25b drain region, 26 gate insulating film, 27 trench Part, 28 buried film, 30 channel region, 30a first impurity diffusion region, 30b second impurity diffusion region

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  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

La présente invention concerne un dispositif à semi-conducteur et un procédé de fabrication qui permet la réduction du bruit. Un dispositif à semi-conducteur selon la présente invention comprend : une région de drain et une région de source disposées dans une région prescrite d'un substrat semi-conducteur ; une région de canal disposée entre la région de drain et la région de source ; et une électrode de grille formée sur la région de canal. La région de canal est pourvue : d'une première région de diffusion d'impuretés ; et d'une seconde région de diffusion d'impuretés qui est une région de diffusion d'impuretés du même type de conductivité que celui de la première région de diffusion d'impuretés, qui présente une concentration d'impuretés différente de celle de la première région de diffusion d'impuretés, et qui est formée au niveau d'une partie sensiblement centrale de la première région de diffusion d'impuretés. La présente invention est applicable, par exemple, à des transistors constituant un dispositif de capture d'image.
PCT/JP2016/083465 2015-11-25 2016-11-11 Dispositif à semi-conducteur et procédé de fabrication WO2017090455A1 (fr)

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US15/773,707 US10446596B2 (en) 2015-11-25 2016-11-11 Semiconductor device and production method

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JP2015229613A JP2017098424A (ja) 2015-11-25 2015-11-25 半導体装置、製造方法
JP2015-229613 2015-11-25

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Citations (4)

* Cited by examiner, † Cited by third party
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JPH08274330A (ja) * 1994-06-03 1996-10-18 Seiko Instr Inc 半導体装置とその製造方法
JPH098305A (ja) * 1995-06-21 1997-01-10 Commiss Energ Atom トランジスタを製造するための、軽くドープされた領域の間に置かれた高くドープされた領域を有する半導体の形成方法
JPH11274486A (ja) * 1998-03-25 1999-10-08 Toshiba Corp 半導体装置およびその製造方法
JP2015118973A (ja) * 2013-12-17 2015-06-25 シナプティクス・ディスプレイ・デバイス合同会社 半導体装置の製造方法及びその半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498376B1 (en) 1994-06-03 2002-12-24 Seiko Instruments Inc Semiconductor device and manufacturing method thereof
JP4100339B2 (ja) * 2003-12-16 2008-06-11 沖電気工業株式会社 半導体装置の製造方法。
JP4657681B2 (ja) * 2004-06-03 2011-03-23 シャープ株式会社 半導体記憶装置およびその製造方法並びに携帯電子機器
JP4845110B2 (ja) * 2006-08-17 2011-12-28 ルネサスエレクトロニクス株式会社 スプリットゲート型不揮発性メモリとその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08274330A (ja) * 1994-06-03 1996-10-18 Seiko Instr Inc 半導体装置とその製造方法
JPH098305A (ja) * 1995-06-21 1997-01-10 Commiss Energ Atom トランジスタを製造するための、軽くドープされた領域の間に置かれた高くドープされた領域を有する半導体の形成方法
JPH11274486A (ja) * 1998-03-25 1999-10-08 Toshiba Corp 半導体装置およびその製造方法
JP2015118973A (ja) * 2013-12-17 2015-06-25 シナプティクス・ディスプレイ・デバイス合同会社 半導体装置の製造方法及びその半導体装置

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JP2017098424A (ja) 2017-06-01
US10446596B2 (en) 2019-10-15

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