WO2017080013A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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WO2017080013A1
WO2017080013A1 PCT/CN2015/097242 CN2015097242W WO2017080013A1 WO 2017080013 A1 WO2017080013 A1 WO 2017080013A1 CN 2015097242 W CN2015097242 W CN 2015097242W WO 2017080013 A1 WO2017080013 A1 WO 2017080013A1
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active layer
layer
source
array substrate
drain
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French (fr)
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石龙强
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/30—Doping active layers, e.g. electron transporting layers
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • TFT-Active Matrix Organic Light Emitting Diode TFT-AMOLED
  • the source 5 of the TFT is turned on by the pixel electrode 6, and the data signal is transmitted to the pixel electrode 6, so that the display can normally display an image.
  • each pixel unit includes, in order from bottom to top, a gate 1, a gate insulating layer 2, an active layer 3 corresponding to the gate 1, and a layer located in the same layer.
  • the connected source 5 and drain 4 are electrically connected to the pixel electrode 6 of the source 5.
  • the active layer 3 turns on the source 5 and the drain 4 under the driving of the gate 1, so that the data signal accessed by the drain 4 is transmitted to the pixel electrode 6 through the source 5. Therefore, good contact of the source 5 with the pixel electrode 6 is important.
  • a buffer layer 8 may be disposed between the gate electrode 1 and the base substrate 7.
  • the source 5 and the drain 4 are covered with a first insulating layer 10, and the PFA is formed after the first insulating layer 10 is formed.
  • the presence of the PFA facilitates the subsequent process of the array substrate.
  • the common electrode 11 is formed over the PFA, the second insulating layer 12 is formed over the common electrode 11, and finally the pixel electrode 6 is formed.
  • the PFA can react with the metal material of the source 5, a non-conductive material is formed.
  • the via 13 is etched layer by layer, that is, after the first insulating layer 10 is formed, the first insulating layer 10 is etched to form a via 13 and then a PFA is formed.
  • the PFA can contact a part of the source 5 exposed by the via hole 13 to form a non-conducting material on the part of the source 5, which affects the electrical connection between the source 5 and the pixel electrode 6, and reduces the yield of the display.
  • An object of the present invention is to provide an array substrate, a method for fabricating the same, and a display device, which can ensure an effective electrical connection between a source and a pixel electrode.
  • a first aspect of the present invention provides an array substrate including a plurality of arrayed pixel units, each of which is provided with a thin film transistor including a source and a drain in the same layer, An active layer connecting and partially covering the source and the drain, the array substrate further comprising an organic flat layer covering the active layer,
  • the organic flat layer is formed with a first via
  • the active layer is electrically conductive corresponding to a region of the first via, such that a pixel electrode located above the organic flat layer can pass through the first via Electrically connecting the source.
  • the region of the active layer corresponding to the first via is an n-type heavily doped region.
  • the active layer is made of an oxide semiconductor.
  • the region of the active layer corresponding to the first via hole is an n-type heavily doped region by plasma treatment.
  • the plasma is a hydrogen ion.
  • an insulating layer is formed between the active layer and the organic flat layer, the insulating layer is formed with a second via hole, and the first via hole is nested in the second via hole.
  • an embodiment of the present invention provides an array substrate including a plurality of pixel units arranged in an array, and the active layer portion of the pixel unit covers the source and the drain to prevent organic
  • the flat layer contacts the source.
  • the organic flat layer is formed with a first via hole, and the active layer is electrically conductive to the region of the first via hole, which ensures the electrical connection between the pixel electrode and the source, which is beneficial to improving the yield of the array substrate.
  • a second aspect of the present invention provides a display device including the above array substrate.
  • a third aspect of the invention provides a method for preparing an array substrate, the preparation method comprising:
  • Forming an active layer partially covering the drain and the source over the drain and the source;
  • the pixel electrode being electrically connectable to the source through an active layer corresponding to the first via.
  • processing the active layer corresponding to the first via, such that the portion of the active layer is electrically conductive comprises:
  • the region of the active layer corresponding to the first via hole is an n-type heavily doped region by plasma treatment to make the portion of the active layer conductive.
  • the plasma is a hydrogen ion.
  • FIG. 1 is a schematic structural view of an array substrate in the prior art
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic flow chart of a method for preparing an array substrate according to an embodiment of the present invention.
  • 4 to 7 are schematic views showing a process of preparing the array substrate shown in FIG. 2.
  • Embodiments of the present invention provide an array substrate including a plurality of arrayed pixel units, each of which is provided with a thin film transistor.
  • the thin film transistor includes a gate electrode 1 and a gate insulating layer 2 in order from bottom to top.
  • the drain 4 and the source 5 of the layer connect and partially cover the active layer 3 of the drain 4 and the source 5.
  • the thin film transistor is a bottom gate type thin film transistor.
  • the array substrate further includes an insulating layer 14 covering the active layer 3, an organic flat layer 9 over the insulating layer 14, and a pixel electrode 6 over the organic flat layer 9.
  • the organic flat layer 9 is formed with a first via hole 15
  • the insulating layer 14 is formed with a second via hole 16
  • the first via hole 15 is nested in the second via hole 16 .
  • the active layer 3 is electrically conductive to the region of the first via 15 such that the pixel electrode 6 above the organic planar layer 9 can be electrically connected to the source 5 through the first via 15 .
  • the region of the active layer 3 corresponding to the first via 15 can be bombarded by positively charged ions such as hydrogen ions or phosphorus ions by plasma treatment, so that the region is an n-type heavily doped region 17, and the region is raised.
  • the purpose of electrically connecting the pixel electrode 6 to the active layer 3 through the first via 15 is to achieve electrical connection between the pixel electrode 6 and the source 5 under the active layer 3.
  • the active layer 3 isolates the organic flat layer 9 from the source 5 to prevent the organic flat layer 9 from coming into contact with the source 5 to generate a non-conducting material, and the material of the active layer 3 determines that it cannot react with the organic flat layer 9. . Therefore, the pixel electrode 6 can achieve an effective electrical connection with the source 5, ensuring the yield of the display.
  • the active layer 3 can be prepared by using amorphous silicon, low temperature polysilicon or the like.
  • an oxide semiconductor may be used to prepare the active layer 3.
  • the active layer 3 may preferably be made of Indium Gallium Zinc Oxide (IGZO).
  • IGZO is an amorphous oxide containing indium, gallium and zinc.
  • the carrier mobility is 20 to 30 times that of amorphous silicon, which can greatly increase the charge and discharge rate of the pixel electrode 6 and improve the response speed of the pixel. Faster refresh rates and faster response also greatly increase the pixel's line scan rate, making ultra-high resolution possible in displays.
  • the embodiment of the present invention further provides a method for preparing the above array substrate, as shown in FIG. 3, the preparation method includes:
  • Step S101 forming the drain and the source of the same layer through the same patterning process.
  • Step S102 forming an active layer partially covering the drain and the source over the drain and the source.
  • Step S103 forming an organic flat layer, the organic flat layer opening a first via hole, and the first via hole exposes the active layer portion.
  • Step S104 Processing the active layer corresponding to the first via hole, so that the portion of the active layer is electrically conductive.
  • Step S105 forming a pixel electrode, wherein the pixel electrode is electrically connected to the source through the active layer corresponding to the first via.
  • a first metal layer for preparing a gate 1, a gate line or the like is formed on the substrate 18 by physical vapor deposition (PVD), and then exposed by a corresponding mask, developed, wet-etched , stripping and other processes to form the gate 1.
  • PVD physical vapor deposition
  • the substrate 18 may be a substrate substrate or a buffer layer on the substrate substrate.
  • the buffer layer can provide an ideal isolation buffer for the gate 1 and the substrate, and can enhance the adhesion of the gate 1 to the substrate.
  • a gate insulating layer 2 for insulating the gate 1 and the drain 4 and the source 5 is formed by a process such as coating.
  • the gate insulating layer 2 can be made of an insulating material such as silicon nitride (Si x N y ) or silicon oxide (Si x O y ).
  • a second metal layer is formed on the gate insulating layer 2 through a PVD process, and the second metal layer is used to form the drain 4, the source 5, the data line, and the like provided in the same layer. structure.
  • the second metal layer is exposed by a corresponding mask, and a structure such as a drain 4, a source 5, and a data line can be prepared through processes such as development, wet etching, and lift-off.
  • the preparation of the active layer 3 is performed next to obtain an array substrate as shown in FIG.
  • an IGZO layer is formed through PVD, and then exposed by a corresponding mask, and a pattern of the active layer 3 is obtained by a process such as development, wet etching, and lift-off.
  • the active layer 3 has a thickness of 40 to 100 nm and a large contact area with the drain 4 and the source 5, covering most of the drain 4 and the source 5.
  • an insulating layer 14 is formed on the active layer 3 by Plasma Enhanced Chemical Vapor Deposition (PECVD).
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • the insulating layer 14 can also utilize common insulating materials such as silicon nitride and silicon oxide. production. Since the insulating layer 14 is insulated and cannot conduct electricity, in order to make the pixel electrode 6 conductive with the source 5, it is necessary to perform a process of exposure, development, dry etching, etc. on the insulating layer 14 by using a corresponding mask to form a second via. 16, as shown in Figure 5.
  • the second via 16 cannot expose the source 5, but exposes the active layer 3 covering the source 5.
  • a process such as coating is applied over the insulating layer 14 to form an organic flat layer 9.
  • the purpose of forming the organic flat layer 9 over the insulating layer 14 is to increase the aperture ratio of the display. Due to the presence of the organic flat layer 9, the pixel electrode 6 can extend over a portion of the data line, thereby increasing the aperture ratio of the display. This is because the thickness of the organic flat layer 9 is sufficiently thick to avoid excessive parasitic capacitance between the pixel electrode 6 and the data line, which affects the display effect of the display.
  • the insulating layer 14 is provided with the second via hole 16 since the second via hole 16 is to cover the source 5 The active layer 3 is exposed, so that the organic flat layer 9 cannot contact the source 5 through the second via 16 and reacts with the source 5 to form a non-conductive material. Further, since the organic flat layer 9 does not react with the active layer 3 made of IGZO, the characteristics of the active layer 3 are not affected by the organic flat layer 9.
  • the organic flat layer 9 is not electrically conductive, the pixel electrode 6 is disposed over the organic flat layer 9. Therefore, in order to make the pixel electrode 6 electrically connectable to the source 5, the organic flat layer 9 needs to open the first via hole 15, and the first via hole 15 is nested in the second via hole 16, and only the active layer 3 is also Some areas are exposed, as shown in Figure 6.
  • the pixel electrode 6 directly contacting the active layer 3 cannot be electrically connected to the source 5. Therefore, in the embodiment of the present invention, based on the first via 15 opened by the organic flat layer 9, the portion of the active layer 3 exposed to the portion is subjected to hydrogen ion bombardment treatment, so that the portion becomes n-type heavily doped.
  • the region 17, as shown in Fig. 7, is used to improve the conductivity of the active layer 3 of this portion. Thereby, after the pixel electrode 6 contacts the active layer 3 through the first via 15, the good electrical connection with the source 5 can be achieved by the electrically conductive n-type heavily doped region 17.
  • a PVD process is again performed to form an Indium Tin Oxides (ITO) layer for preparing the pixel electrode 6.
  • ITO Indium Tin Oxides
  • the corresponding mask is used for exposure, and the pattern of the pixel electrode 6 is obtained by a process such as development, wet etching, peeling, etc., and an array substrate as shown in FIG. 2 is prepared.
  • an embodiment of the present invention provides an array substrate including a plurality of pixel units arranged in an array, wherein an active layer portion of the pixel unit covers a source and a drain to prevent the organic flat layer from contacting the source.
  • the organic flat layer is formed with a first via hole, and the active layer is electrically conductive to the region of the first via hole, which ensures the electrical connection between the pixel electrode and the source, which is beneficial to improving the yield of the array substrate.
  • the embodiment of the invention further provides a display device, which comprises the above array substrate.
  • the display device can be a device such as a television, a display, a mobile phone, or a tablet computer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板及其制备方法、显示装置，该阵列基板包括多个阵列排布的像素单元，每个像素单元设置有一个薄膜晶体管，该薄膜晶体管包括有源层（3）与有机平坦层（9），该有机平坦层（9）形成有第一过孔（15），该有源层（3）对应第一过孔（15）的区域导电，使得位于有机平坦层（9）之上的像素电极（6）可通过第一过孔（15）电连接薄膜晶体管的源极（5）。

Description

阵列基板及其制备方法、显示装置
相关申请的交叉引用
本申请要求享有2015年11月09日提交的名称为“阵列基板及其制备方法、显示装置”的中国专利申请CN201510755212.5的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体地说，涉及一种阵列基板及其制备方法、显示装置。
背景技术
在薄膜晶体管主动式矩阵液晶显示器(Thin Film Transistor-Active Matrix Liquid Crystal Display，简称TFT-AMLCD)或者薄膜晶体管主动矩阵有机发光二极体显示器(TFT-Active Matrix Organic Light Emitting Diode，简称TFT-AMOLED)中，通过TFT的源极5与像素电极6导通，数据信号得以传输至像素电极6，使得显示器可以正常显示图像。
如图1所示，在TFT-AMLCD中，每一像素单元由下至上依次包括：栅极1、栅极绝缘层2、对应栅极1的有源层3、位于同一层且由有源层3连接的源极5和漏极4、电连接源极5的像素电极6。漏极4接入数据信号之后，有源层3在栅极1的驱动下导通源极5和漏极4，使得漏极4接入的数据信号通过源极5传输至像素电极6。因此，源极5与像素电极6的良好接触十分重要。另外，栅极1和衬底基板7之间还可设置有缓冲层8。
如图1所示，在阵列基板制程中，许多产品加入有机平坦层9(Polymer Film on Array，简称PFA)。具体的，源极5和漏极4之上覆盖有第一绝缘层10，PFA是在形成第一绝缘层10之后形成的，PFA的存在便于阵列基板后续工艺的进行。
在阵列基板的制备过程中，在形成PFA之后，在PFA之上形成公共电极11，在公共电极11之上形成第二绝缘层12，最后形成像素电极6。
为了使得位于最上层的像素电极6可以电连接源极5，需要开设由上至下依次贯穿第二绝缘层12、PFA和第一绝缘层10的过孔13，使得源极5部分暴露在 外、与像素电极6电连接。
由于PFA能够和源极5的金属材料发生反应，形成不导电物。而现有技术中，过孔13是逐层刻蚀的，即在形成第一绝缘层10之后，对第一绝缘层10进行刻蚀工艺，形成过孔13之后再形成PFA。则此时PFA可接触到被过孔13暴露在外的部分源极5，使得这部分源极5之上形成不导电物，影响源极5与像素电极6的电连接，降低显示器的良品率。
发明内容
本发明的目的在于提供一种阵列基板及其制备方法、显示装置，可保证源极与像素电极之间的有效电连接。
本发明第一方面提供了一种阵列基板，该阵列基板包括多个阵列排布的像素单元，每个像素单元设置有一个薄膜晶体管，所述薄膜晶体管包括位于同层的源极和漏极、连接并部分覆盖源极和漏极的有源层，所述阵列基板还包括覆盖所述有源层的有机平坦层，
其中，所述有机平坦层形成有第一过孔，所述有源层对应所述第一过孔的区域导电，使得位于所述有机平坦层之上的像素电极可通过所述第一过孔电连接所述源极。
可选的，所述有源层对应所述第一过孔的区域为n型重掺杂区域。
可选的，所述有源层的材质为氧化物半导体。
可选的，通过等离子处理，使得所述有源层对应所述第一过孔的区域为n型重掺杂区域。
可选的，所述等离子为氢离子。
可选的，所述有源层和所述有机平坦层之间形成有绝缘层，所述绝缘层形成有第二过孔，所述第一过孔嵌套在所述第二过孔内。
本发明带来了以下有益效果：本发明实施例提供了一种阵列基板，该阵列基板包括多个阵列排布的像素单元，像素单元中的有源层部分覆盖源极和漏极，防止有机平坦层接触到源极。同时，有机平坦层形成有第一过孔，有源层对应该第一过孔的区域导电，保证了像素电极与源极的电连接，有利于提高阵列基板的良品率。
本发明第二方面提供了一种显示装置，该显示装置包括上述的阵列基板。
本发明第三方面提供了一种阵列基板的制备方法，该制备方法包括：
通过同一次构图工艺，形成同层设置的漏极和源极；
在所述漏极和所述源极之上，形成部分覆盖所述漏极和所述源极的有源层；
形成有机平坦层，所述有机平坦层开设第一过孔，所述第一过孔将所述有源层部分暴露；
处理所述第一过孔对应的有源层，使得该部分有源层可导电；
形成像素电极，所述像素电极可通过所述第一过孔对应的有源层电连接所述源极。
可选的，处理所述第一过孔对应的有源层，使得该部分有源层导电包括：
通过等离子处理，使得所述有源层对应所述第一过孔的区域为n型重掺杂区域，以使得该部分有源层导电。
可选的，所述等离子为氢离子。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图做简单的介绍：
图1是现有技术中的阵列基板的结构示意图；
图2是本发明实施例提供的阵列基板的结构示意图；
图3是本发明实施例提供的阵列基板的制备方法的流程示意图；
图4至图7是图2所示的阵列基板的制备过程示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
本发明实施例提供了一种阵列基板，该阵列基板包括多个阵列排布的像素单元，每个像素单元设置有一个薄膜晶体管。
如图2所示，薄膜晶体管由下至上依次包括栅极1、栅极绝缘层2、位于同 层的漏极4和源极5、连接并部分覆盖漏极4和源极5的有源层3。显然，该薄膜晶体管为底栅型薄膜晶体管。
进一步的，在薄膜晶体管之上，阵列基板还包括覆盖有源层3的绝缘层14、位于绝缘层14之上的有机平坦层9，以及位于有机平坦层9之上的像素电极6。其中，有机平坦层9形成有第一过孔15，绝缘层14形成有第二过孔16，第一过孔15嵌套在第二过孔16内。有源层3对应第一过孔15的区域导电，使得位于有机平坦层9之上的像素电极6可通过第一过孔15电连接源极5。
具体的，可通过等离子处理，利用氢离子、磷离子等带正电的离子轰击有源层3对应第一过孔15的区域，使得该区域为n型重掺杂区域17，提升该区域的导电能力，从而使得像素电极6通过第一过孔15接触到有源层3，即可实现像素电极6与位于有源层3之下的源极5电连接的目的。
并且，有源层3隔绝开有机平坦层9与源极5，防止有机平坦层9与源极5接触产生不导电物，而有源层3的材质决定了其无法与有机平坦层9发生反应。因此，像素电极6可以实现与源极5的有效电连接，保证了显示器的良品率。
具体的，本发明实施例中，有源层3可采用非晶硅、低温多晶硅等材质制备。但为了提高有源层3的掺杂效率，可选用氧化物半导体来制备有源层3。其中，有源层3可优选由铟镓锌氧化物(Indium Gallium Zinc Oxide，简称IGZO)制得。
IGZO是一种含有铟、镓和锌的非晶氧化物，载流子迁移率是非晶硅的20～30倍，可以大大提高TFT对像素电极6的充放电速率，提高像素的响应速度，实现更快的刷新率，同时更快的响应也大大提高了像素的行扫描速率，使得超高分辨率在显示器中成为可能。
为了制备上述阵列基板，本发明实施例还提供了上述阵列基板的制备方法，如图3所示，该制备方法包括：
步骤S101、通过同一次构图工艺，形成同层设置的漏极和源极。
步骤S102、在漏极和源极之上，形成部分覆盖漏极和源极的有源层。
步骤S103、形成有机平坦层，有机平坦层开设第一过孔，第一过孔将有源层部分暴露。
步骤S104、处理第一过孔对应的有源层，使得该部分有源层可导电。
步骤S105、形成像素电极，所述像素电极可通过第一过孔对应的有源层电连接源极。
本发明实施例提供的阵列基板可具体通过以下制备流程制得：
在衬底18上通过物理气相沉积(Physical Vapor Deposition，简称PVD)形成用于制备栅极1、栅线等结构的第一金属层，之后利用对应的掩膜版进行曝光，经过显影、湿刻、剥离等工艺，形成栅极1。
其中，该衬底18可以是衬底基板，也可是位于衬底基板之上的缓冲层。该缓冲层能对栅极1与衬底基板起到理想的隔离缓冲作用，且能增强栅极1与衬底的附着程度。
之后，在栅极1之上，通过涂覆等工艺，形成用于对栅极1与漏极4、源极5绝缘的栅极绝缘层2。栅极绝缘层2可采用氮化硅(SixNy)、氧化硅(SixOy)等绝缘料制成。栅极绝缘层2形成之后，再次经过PVD工艺，在栅极绝缘层2之上形成第二金属层，该第二金属层用于形成同层设置的漏极4、源极5以及数据线等结构。对第二金属层利用对应的掩膜版进行曝光，经过显影、湿刻、剥离等工艺，可以制备得到漏极4、源极5以及数据线等结构。
在制得漏极4和源极5之后，接下来进行有源层3的制备，得到如图4所示的阵列基板。在漏极4和源极5之上，经过PVD，形成IGZO层，之后利用对应的掩膜版进行曝光，经过显影、湿刻、剥离等工艺得到有源层3的图形。其中，有源层3的厚度为40至100纳米，且与漏极4和源极5的接触面积很大，覆盖绝大部分的漏极4和源极5。如此结构，不仅可以保证有源层3与漏极4、源极5之间的有效接触，还可保护源极5，防止有机平坦层9与源极5接触。
之后，在有源层3之上经过等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，简称PECVD)形成绝缘层14，该绝缘层14同样可以利用氮化硅、氧化硅等常见的绝缘材料制成。由于绝缘层14是绝缘的，无法导电，为了使得像素电极6能够与源极5导电，需要对绝缘层14利用对应的掩膜版，进行曝光、显影、干刻等工艺，形成第二过孔16，如图5所示。
由于本实施例中的有源层3覆盖了大部分的源极5，因此，该第二过孔16无法将源极5暴露在外，而是将覆盖源极5的有源层3暴露在外。
形成第二过孔16之后，在绝缘层14之上经过涂覆等工艺，形成有机平坦层9。本实施例中，在绝缘层14之上形成有机平坦层9的目的是为了提高显示器的开口率。由于有机平坦层9的存在，像素电极6可以延伸覆盖在部分数据线的上方，从而提高显示器的开口率。这是因为有机平坦层9的厚度足够厚，可以避免像素电极6与数据线之间的寄生电容过大，影响显示器的显示效果。
虽然绝缘层14开设有第二过孔16，但由于第二过孔16是将覆盖源极5的 有源层3暴露在外，因此有机平坦层9无法通过第二过孔16接触到源极5，与源极5发生反应形成不导电物。并且，有机平坦层9与由IGZO制成的有源层3无法发生反应，因此有源层3的特性不会受到有机平坦层9的影响。
由于有机平坦层9不导电，而像素电极6是设置在有机平坦层9之上的。因此为了使得像素电极6可以与源极5电连接，有机平坦层9需要开设第一过孔15，该第一过孔15嵌套于第二过孔16内，同样仅将有源层3的部分区域暴露在外，如图6所示。
显然，如果不将有源层3进行一定的处理，由于有源层3未利用导体材质制得，直接接触有源层3的像素电极6还是无法与源极5进行有效的电连接。因此，本发明实施例中，基于有机平坦层9开设的第一过孔15，对该部分被暴露在外的部分有源层3进行氢离子轰击处理，使得这部分区域变为n型重掺杂区域17，如图7所示，以提高这部分有源层3的导电性。从而，像素电极6通过第一过孔15接触到有源层3之后，即可通过导电的n型重掺杂区域17实现与源极5的良好电连接。
最后，在有机平坦层9上，再次经过PVD工艺，形成用于制备像素电极6的氧化铟锡(Indium Tin Oxides，简称ITO)层。之后利用对应的掩膜版进行曝光，经过显影、湿刻、剥离等工艺得到像素电极6的图形，制备得如图2所示的阵列基板。
综上，本发明实施例提供了一种阵列基板，该阵列基板包括多个阵列排布的像素单元，像素单元中的有源层部分覆盖源极和漏极，防止有机平坦层接触到源极。同时，有机平坦层形成有第一过孔，有源层对应该第一过孔的区域导电，保证了像素电极与源极的电连接，有利于提高阵列基板的良品率。
本发明实施例进一步还提供了一种显示装置，该显示装置包括上述的阵列基板。该显示装置可为电视、显示器、手机、平板电脑等装置。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (10)

  1. 一种阵列基板，其中，包括多个阵列排布的像素单元，每个像素单元设置有一个薄膜晶体管，所述薄膜晶体管包括位于同层的源极和漏极、连接并部分覆盖源极和漏极的有源层，所述阵列基板还包括覆盖所述有源层的有机平坦层，
    其中，所述有机平坦层形成有第一过孔，所述有源层对应所述第一过孔的区域导电，使得位于所述有机平坦层之上的像素电极可通过所述第一过孔电连接所述源极。
  2. 根据权利要求1所述的阵列基板，其中，所述有源层对应所述第一过孔的区域为n型重掺杂区域。
  3. 根据权利要求2所述的阵列基板，其中，所述有源层的材质为氧化物半导体。
  4. 根据权利要求3所述的阵列基板，其中，通过等离子处理，使得所述有源层对应所述第一过孔的区域为n型重掺杂区域。
  5. 根据权利要求4所述的阵列基板，其中，所述等离子为氢离子。
  6. 根据权利要求1所述的阵列基板，其中，所述有源层和所述有机平坦层之间形成有绝缘层，所述绝缘层形成有第二过孔，所述第一过孔嵌套在所述第二过孔内。
  7. 一种显示装置，其中，包括阵列基板，所述阵列基板包括多个阵列排布的像素单元，每个像素单元设置有一个薄膜晶体管，所述薄膜晶体管包括位于同层的源极和漏极、连接并部分覆盖源极和漏极的有源层，所述阵列基板还包括覆盖所述有源层的有机平坦层，
    其中，所述有机平坦层形成有第一过孔，所述有源层对应所述第一过孔的区域导电，使得位于所述有机平坦层之上的像素电极可通过所述第一过孔电连接所述源极。
  8. 一种阵列基板的制备方法，其中，包括：
    通过同一次构图工艺，形成同层设置的漏极和源极；
    在所述漏极和所述源极之上，形成部分覆盖所述漏极和所述源极的有源层；
    形成有机平坦层，所述有机平坦层开设第一过孔，所述第一过孔将所述有源层部分暴露；
    处理所述第一过孔对应的有源层，使得该部分有源层导电；
    形成像素电极，所述像素电极可通过所述第一过孔对应的有源层电连接所述源极。
  9. 根据权利要求8所述的制备方法，其中，处理所述第一过孔对应的有源层，使得该部分有源层导电包括：
    通过等离子处理，使得所述有源层对应所述第一过孔的区域为n型重掺杂区域，以使得该部分有源层可导电。
  10. 根据权利要求9所述的制备方法，其中，所述等离子为氢离子。
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