WO2017054595A1 - 具有静电释放保护结构的半导体器件 - Google Patents

具有静电释放保护结构的半导体器件 Download PDF

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WO2017054595A1
WO2017054595A1 PCT/CN2016/096527 CN2016096527W WO2017054595A1 WO 2017054595 A1 WO2017054595 A1 WO 2017054595A1 CN 2016096527 W CN2016096527 W CN 2016096527W WO 2017054595 A1 WO2017054595 A1 WO 2017054595A1
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semiconductor device
protection structure
diode
discharge protection
layer
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PCT/CN2016/096527
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English (en)
French (fr)
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卞铮
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无锡华润上华半导体有限公司
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Priority to US15/764,394 priority Critical patent/US10373945B2/en
Publication of WO2017054595A1 publication Critical patent/WO2017054595A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/866—Zener diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region

Definitions

  • the problem is that due to the high step height in some areas, and in order to ensure the process margin of the subsequent process, the CMP process will have to set a thicker dielectric thickness, thereby sacrificing a part of the performance of the die, and also causing the process itself. stable.
  • a semiconductor device having an electrostatic discharge protection structure being a diode connected between a gate and a source of the semiconductor device, the semiconductor device comprising a substrate, a field oxide layer on the substrate And a gate oxide layer, wherein the diode comprises a diode body and two connection portions respectively connected to the two ends of the diode body for electrically connecting the gate and the source, wherein the substrate is provided There are two insulating mats separated from each other, and a surface of the substrate between the two insulating mats is provided with an insulating layer having a thickness smaller than two of the insulating mats, and the diode main body is disposed on the insulating layer, and two connections are a portion extending from one end of the diode body to the insulating pad on the side; the diode and the two insulating pads are provided with a dielectric layer, the dielectric layer is provided with a metal wire layer, and the metal wire layer comprises an electrical connection a first metal of the gate is taken out and
  • FIG. 1 is a circuit schematic diagram of a semiconductor device having an electrostatic discharge protection structure
  • FIG. 2 is a schematic cross-sectional view of a semiconductor device having an electrostatic discharge protection structure in an embodiment.
  • connection portion 234 extends to the insulating pad 222 on the right side of the diode body 232.
  • a dielectric layer 240 having an insulating function is disposed on the diode 230 and the two insulating pads 222, and a metal wiring layer 260 is disposed on the dielectric layer 240.
  • the metal wire layer 260 includes a first metal extraction 262 electrically connected to the gate and a second metal extraction 264 electrically connected to the source. The first metal extraction 262 and the second metal extraction 264 each pass through a contact hole penetrating the dielectric layer 240.
  • 250 (the filling hole 250 is filled with a conductive material, usually metal) is connected to a connecting portion 234.
  • the insulating pad 222 acts as an etch stop layer for the contact hole 250, preventing the contact hole 250 from being punctured to the substrate due to process fluctuations.
  • the above semiconductor device having an electrostatic discharge protection structure improves the field oxide layer 120 under the existing simple continuous integrated polysilicon 130 to retain the insulating pad 222 only under the extraction hole (contact hole 250), and distinguishes between different process demand regions.
  • the design thus achieves the minimum requirement of the thickness of the insulating layer process in the metal corrosion region and the hole corrosion region, respectively, without using a uniform thickness of the insulating layer in the entire device process region, thereby avoiding waste of deposition thickness.
  • the thickness H2 of the dielectric layer 240 can be made to cover the diode body 232 while being made lower than the prior art.
  • the diode body 232 is made of metal through the contact hole 250 above the connecting portion 234 on both sides, and the connecting portion 234 only functions as an electrical connection, so even if the dielectric layer 240 above it is thin or the connecting portion 234 Damage to the metal does not affect the performance of the device.
  • the dielectric layer 240 is subjected to a chemical mechanical polishing (CMP) process in which a thicker thickness is first deposited and then a portion is polished by a planarization process of CMP to planarize the surface of the device.
  • CMP chemical mechanical polishing
  • the above semiconductor device having an electrostatic discharge protection structure reduces the thickness of the dielectric layer 240 by optimizing the structure, thereby ensuring compatibility with a general CMP process when using a CMP process, and facilitating on-line process control.
  • the production process cost can be significantly reduced, the single process difficulty is reduced, thereby improving the productivity and the yield, and thus it is more suitable for the production process using the CMP process technology, and the CMP technology is more suitable for processing the small line width than the old flattening process.
  • the conductive material filled in the contact hole 250 is tungsten. In other embodiments, other materials such as metals, alloys, and the like which are suitable as contact hole conductive fillers in the art may be used.
  • the semiconductor device is a double diffused metal oxide semiconductor field effect transistor (DMOSFET).
  • DMOSFET double diffused metal oxide semiconductor field effect transistor
  • diode 230 is a Zener diode. In other embodiments, diode 230 can also employ other types of diodes.

Abstract

一种具有静电释放保护结构的半导体器件，包括连接于该半导体器件的栅极和源极之间的二极管(230)，该二极管包括二极管主体(232)和连接于该二极管主体两端、分别用于电性连接该栅极和源极的两个连接部(234)，衬底(210)上设有两个相互分离的绝缘垫(222)，两个该绝缘垫之间的衬底表面设有绝缘层(212)，该二极管主体设于该绝缘层上，两个连接部分别从该二极管主体的一端延伸至该侧的绝缘垫上；该二极管和两个绝缘垫上设有介质层(240)，该介质层上设有金属导线层(260)。

Description

具有静电释放保护结构的半导体器件
【技术领域】
本发明涉及半导体制造技术，特别是涉及一种具有静电释放保护结构的半导体器件。
【背景技术】
目前主流的带ESD（Electro-Static discharge, 静电释放）保护的双扩散金属氧化物半导体场效应管（DMOSFET）器件上的ESD保护结构是通过在多晶硅上制作二极管来实现，其结构如图1所示，在器件的源极和栅极之间并联有二极管。为了将此二极管与其他元胞电路进行电绝缘处理，要求在制造时于晶圆上的二极管下方制作一定厚度的绝缘层，从而导致该区域比其他管芯区域要高。随着半导体工艺进入到更细线宽世代，其介质工艺也进入到相对先进的化学机械抛光（CMP）工艺。带来的问题是由于部分区域台阶高，且为保证后继工艺的工艺余量，CMP工艺将不得不设定较厚的介质厚度，从而牺牲了管芯的一部分性能，同时也造成工艺本身的不稳定。
【发明内容】
基于此，有必要针对传统工艺需要淀积较厚的介质层进行CMP的问题，提供一种具有静电释放保护结构的半导体器件。
一种具有静电释放保护结构的半导体器件，所述静电释放保护结构为连接于所述半导体器件的栅极和源极之间的二极管，所述半导体器件包括衬底、衬底上的场氧化层和栅氧化层，其特征在于，所述二极管包括二极管主体和连接于所述二极管主体两端、分别用于电性连接所述栅极和源极的两个连接部，所述衬底上设有两个相互分离的绝缘垫，两个所述绝缘垫之间的衬底表面设有厚度小于两个所述绝缘垫的绝缘层，所述二极管主体设于所述绝缘层上，两个连接部分别从所述二极管主体的一端延伸至该侧的绝缘垫上；所述二极管和两个绝缘垫上设有介质层，所述介质层上设有金属导线层，所述金属导线层包括电性连接所述栅极的第一金属引出和电性连接所述源极的第二金属引出，所述第一金属引出和第二金属引出各通过一贯穿所述介质层的接触孔连接至一连接部。
上述具有静电释放保护结构的半导体器件，只在接触孔下方保留绝缘垫，对不同工艺需求区域采用区分的设计，由此实现在金属腐蚀区及孔腐蚀区分别满足绝缘层工艺厚度的最低需求，而无需在整个器件工艺区域统一采用一个绝缘层厚度，避免造成淀积厚度的浪费。需要整体淀积的介质层厚度更薄，对于厚介质处接触孔腐蚀的工艺难度也相应降低，在降低成本的同时提高了生产率。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为具有静电释放保护结构的半导体器件的电路原理图；
图2为一实施例中具有静电释放保护结构的半导体器件的剖面示意图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。
图2是一实施例中具有静电释放保护结构的半导体器件的剖面示意图，作为ESD保护结构的二极管230包括二极管主体232，还包括连接于二极管主体232两端、分别用于电性连接栅极（图2中未示）和源极（图2中未示）的两个连接部234。在本实施例中，二极管230的材质为多晶硅，即二极管主体232和连接部234的材质为多晶硅，二极管主体232内掺杂有N型和P型杂质，以形成PN结，在其他实施例中，二极管230也可以采用本领域习知的适合制作二极管的其他材质。半导体器件的衬底210上设有两个相互分离的绝缘垫222，两个绝缘垫222之间的衬底表面设有绝缘层212，绝缘层212的厚度小于两个绝缘垫222的厚度。二极管主体232设于绝缘层212上，两个连接部234分别从二极管主体232的一端延伸至一绝缘垫222上——左边的连接部234延伸至二极管主体232左边的绝缘垫222上，右边的连接部234延伸至二极管主体232右边的绝缘垫222上。二极管230和两个绝缘垫222上设有具绝缘功能的介质层240，介质层240上设有金属导线层260。金属导线层260包括电性连接栅极的第一金属引出262和电性连接源极的第二金属引出264，第一金属引出262和第二金属引出264各通过一贯穿介质层240的接触孔250（接触孔250内填充由导电物质，通常为金属）连接至一连接部234。绝缘垫222作为接触孔250的腐蚀终止层，避免接触孔250因工艺波动刻穿至衬底。
上述具有静电释放保护结构的半导体器件，将现有的简单连续一体的多晶硅130下方的场氧化层120改进为只在引出孔（接触孔250）下方保留绝缘垫222，对不同工艺需求区域采用区分的设计，由此实现在金属腐蚀区及孔腐蚀区分别满足绝缘层工艺厚度的最低需求，而无需在整个器件工艺区域统一采用一个绝缘层厚度，避免造成淀积厚度的浪费。在保持绝缘垫222作为接触孔250的腐蚀终止层的终止厚度T和现有结构一样的前提下，介质层240的厚度H2可以在做得比现有结构更低的同时使得覆盖在二极管主体232上的介质层240厚度比现有结构更厚。故相比现有结构，需要整体淀积的介质层厚度更薄，对于厚介质处接触孔腐蚀的工艺难度也相应降低（因为接触孔的孔深也相应降低），此外，在降低成本的同时提高了生产率。可以在保证后继工艺余量的基础上采用近似基本工艺所采用的CMP工艺，从而降低介质厚度保证工艺稳定性的同时，还可以减少介质工艺预淀积的厚度成本。且在降低H2的同时，可以增加覆盖在二极管主体232上的介质层240的厚度，从而降低了因金属腐蚀的过刻蚀（over etch）造成多晶露出所导致的可靠性风险。
需要指出的是，二极管主体232通过两侧的连接部234上方的接触孔250制作金属引出，连接部234只起到电性连接的作用，因此即使其上方的介质层240很薄或者连接部234被金属刻蚀时损伤也不会影响器件的性能。
在其中一个实施例中，介质层240要经过化学机械抛光（CMP）处理，即先淀积一个较厚的厚度，然后通过CMP的平坦化处理抛光掉一部分，使得器件表面平坦化。
上述具有静电释放保护结构的半导体器件，通过优化结构降低了介质层240的厚度，保证了在使用CMP工艺时能够与一般的CMP工艺兼容，便于在线工艺控制。相比现有结构可以显著降低生产工艺成本，降低单项工艺难度，从而提高生产率和良率，因此更适用于采用CMP工艺技术的生产工艺，而CMP技术相比老式平坦化工艺更加适合加工小线宽产品，有助于提升器件集成度和改善工艺良率。
在图2所示实施例中，两个绝缘垫222之间的绝缘层212为栅氧化层的一部分，即利用半导体器件长栅氧化层时在相应位置形成的二氧化硅作为绝缘层212。绝缘垫222为场氧化层的一部分，即利用半导体器件形成场氧化层时在相应位置形成的二氧化硅作为绝缘垫222（可以先形成一个大块的场氧，再通过刻蚀刻成两个相互分离的绝缘垫222）。利用栅氧化层/场氧化层作为绝缘层212/绝缘垫222，可以节约工序，节省成本、提高生产效率。
在图2所示实施例中，接触孔250内填充的导电物质为钨。在其他实施例中，也可以使用本领域习知的其他适合作为接触孔导电填充物的金属、合金等材质。
在图2所示实施例中，半导体器件为双扩散金属氧化物半导体场效应管（DMOSFET）。
在图2所示实施例中，二极管主体232上的介质层240向下凹陷是为了保证该处金属无残留而对金属导线层260过刻蚀导致的。
在其中一个实施例中，二极管230为齐纳二极管。在其他实施例中，二极管230也可以采用其他类型的二极管。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (8)

  1. 一种具有静电释放保护结构的半导体器件，所述静电释放保护结构为连接于所述半导体器件的栅极和源极之间的二极管，所述半导体器件包括衬底、衬底上的场氧化层和栅氧化层，所述二极管包括二极管主体和连接于所述二极管主体两端、分别用于电性连接所述栅极和源极的两个连接部，所述衬底上设有两个相互分离的绝缘垫，两个所述绝缘垫之间的衬底表面设有厚度小于两个所述绝缘垫的绝缘层，所述二极管主体设于所述绝缘层上，两个连接部分别从所述二极管主体的一端延伸至该侧的绝缘垫上；所述二极管和两个绝缘垫上设有介质层，所述介质层上设有金属导线层，所述金属导线层包括电性连接所述栅极的第一金属引出和电性连接所述源极的第二金属引出，所述第一金属引出和第二金属引出各通过一贯穿所述介质层的接触孔连接至一连接部。
  2. 根据权利要求1所述的具有静电释放保护结构的半导体器件，其特征在于，两个所述绝缘垫为所述场氧化层的一部分。
  3. 根据权利要求1所述的具有静电释放保护结构的半导体器件，其特征在于，所述绝缘层为所述栅氧化层的一部分。
  4. 根据权利要求1所述的具有静电释放保护结构的半导体器件，其特征在于，所述介质层为经过化学机械抛光处理的介质层。
  5. 根据权利要求1所述的具有静电释放保护结构的半导体器件，其特征在于，两个所述接触孔内填充有钨作为导电物质。
  6. 根据权利要求1所述的具有静电释放保护结构的半导体器件，其特征在于，所述半导体器件为双扩散金属氧化物半导体场效应管。
  7. 根据权利要求1所述的具有静电释放保护结构的半导体器件，其特征在于，所述二极管的材质为多晶硅，所述二极管主体内掺杂有N型和P型杂质。
  8. 根据权利要求1所述的具有静电释放保护结构的半导体器件，其特征在于，所述二极管主体上方的介质层表面向下凹陷。
PCT/CN2016/096527 2015-09-30 2016-08-24 具有静电释放保护结构的半导体器件 WO2017054595A1 (zh)

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